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Merge tag 'batadv-next-for-davem-20161027' of git://git.open-mesh.org/linux-merge
[thirdparty/kernel/stable.git] / drivers / net / ethernet / amd / xgbe / xgbe-drv.c
1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/platform_device.h>
118 #include <linux/spinlock.h>
119 #include <linux/tcp.h>
120 #include <linux/if_vlan.h>
121 #include <net/busy_poll.h>
122 #include <linux/clk.h>
123 #include <linux/if_ether.h>
124 #include <linux/net_tstamp.h>
125 #include <linux/phy.h>
126
127 #include "xgbe.h"
128 #include "xgbe-common.h"
129
130 static int xgbe_one_poll(struct napi_struct *, int);
131 static int xgbe_all_poll(struct napi_struct *, int);
132
133 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
134 {
135 struct xgbe_channel *channel_mem, *channel;
136 struct xgbe_ring *tx_ring, *rx_ring;
137 unsigned int count, i;
138 int ret = -ENOMEM;
139
140 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
141
142 channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL);
143 if (!channel_mem)
144 goto err_channel;
145
146 tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring),
147 GFP_KERNEL);
148 if (!tx_ring)
149 goto err_tx_ring;
150
151 rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring),
152 GFP_KERNEL);
153 if (!rx_ring)
154 goto err_rx_ring;
155
156 for (i = 0, channel = channel_mem; i < count; i++, channel++) {
157 snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
158 channel->pdata = pdata;
159 channel->queue_index = i;
160 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
161 (DMA_CH_INC * i);
162
163 if (pdata->per_channel_irq) {
164 /* Get the DMA interrupt (offset 1) */
165 ret = platform_get_irq(pdata->pdev, i + 1);
166 if (ret < 0) {
167 netdev_err(pdata->netdev,
168 "platform_get_irq %u failed\n",
169 i + 1);
170 goto err_irq;
171 }
172
173 channel->dma_irq = ret;
174 }
175
176 if (i < pdata->tx_ring_count) {
177 spin_lock_init(&tx_ring->lock);
178 channel->tx_ring = tx_ring++;
179 }
180
181 if (i < pdata->rx_ring_count) {
182 spin_lock_init(&rx_ring->lock);
183 channel->rx_ring = rx_ring++;
184 }
185
186 netif_dbg(pdata, drv, pdata->netdev,
187 "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
188 channel->name, channel->dma_regs, channel->dma_irq,
189 channel->tx_ring, channel->rx_ring);
190 }
191
192 pdata->channel = channel_mem;
193 pdata->channel_count = count;
194
195 return 0;
196
197 err_irq:
198 kfree(rx_ring);
199
200 err_rx_ring:
201 kfree(tx_ring);
202
203 err_tx_ring:
204 kfree(channel_mem);
205
206 err_channel:
207 return ret;
208 }
209
210 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
211 {
212 if (!pdata->channel)
213 return;
214
215 kfree(pdata->channel->rx_ring);
216 kfree(pdata->channel->tx_ring);
217 kfree(pdata->channel);
218
219 pdata->channel = NULL;
220 pdata->channel_count = 0;
221 }
222
223 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
224 {
225 return (ring->rdesc_count - (ring->cur - ring->dirty));
226 }
227
228 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
229 {
230 return (ring->cur - ring->dirty);
231 }
232
233 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
234 struct xgbe_ring *ring, unsigned int count)
235 {
236 struct xgbe_prv_data *pdata = channel->pdata;
237
238 if (count > xgbe_tx_avail_desc(ring)) {
239 netif_info(pdata, drv, pdata->netdev,
240 "Tx queue stopped, not enough descriptors available\n");
241 netif_stop_subqueue(pdata->netdev, channel->queue_index);
242 ring->tx.queue_stopped = 1;
243
244 /* If we haven't notified the hardware because of xmit_more
245 * support, tell it now
246 */
247 if (ring->tx.xmit_more)
248 pdata->hw_if.tx_start_xmit(channel, ring);
249
250 return NETDEV_TX_BUSY;
251 }
252
253 return 0;
254 }
255
256 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
257 {
258 unsigned int rx_buf_size;
259
260 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
261 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
262
263 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
264 ~(XGBE_RX_BUF_ALIGN - 1);
265
266 return rx_buf_size;
267 }
268
269 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
270 {
271 struct xgbe_hw_if *hw_if = &pdata->hw_if;
272 struct xgbe_channel *channel;
273 enum xgbe_int int_id;
274 unsigned int i;
275
276 channel = pdata->channel;
277 for (i = 0; i < pdata->channel_count; i++, channel++) {
278 if (channel->tx_ring && channel->rx_ring)
279 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
280 else if (channel->tx_ring)
281 int_id = XGMAC_INT_DMA_CH_SR_TI;
282 else if (channel->rx_ring)
283 int_id = XGMAC_INT_DMA_CH_SR_RI;
284 else
285 continue;
286
287 hw_if->enable_int(channel, int_id);
288 }
289 }
290
291 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
292 {
293 struct xgbe_hw_if *hw_if = &pdata->hw_if;
294 struct xgbe_channel *channel;
295 enum xgbe_int int_id;
296 unsigned int i;
297
298 channel = pdata->channel;
299 for (i = 0; i < pdata->channel_count; i++, channel++) {
300 if (channel->tx_ring && channel->rx_ring)
301 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
302 else if (channel->tx_ring)
303 int_id = XGMAC_INT_DMA_CH_SR_TI;
304 else if (channel->rx_ring)
305 int_id = XGMAC_INT_DMA_CH_SR_RI;
306 else
307 continue;
308
309 hw_if->disable_int(channel, int_id);
310 }
311 }
312
313 static irqreturn_t xgbe_isr(int irq, void *data)
314 {
315 struct xgbe_prv_data *pdata = data;
316 struct xgbe_hw_if *hw_if = &pdata->hw_if;
317 struct xgbe_channel *channel;
318 unsigned int dma_isr, dma_ch_isr;
319 unsigned int mac_isr, mac_tssr;
320 unsigned int i;
321
322 /* The DMA interrupt status register also reports MAC and MTL
323 * interrupts. So for polling mode, we just need to check for
324 * this register to be non-zero
325 */
326 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
327 if (!dma_isr)
328 goto isr_done;
329
330 netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
331
332 for (i = 0; i < pdata->channel_count; i++) {
333 if (!(dma_isr & (1 << i)))
334 continue;
335
336 channel = pdata->channel + i;
337
338 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
339 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
340 i, dma_ch_isr);
341
342 /* The TI or RI interrupt bits may still be set even if using
343 * per channel DMA interrupts. Check to be sure those are not
344 * enabled before using the private data napi structure.
345 */
346 if (!pdata->per_channel_irq &&
347 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
348 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
349 if (napi_schedule_prep(&pdata->napi)) {
350 /* Disable Tx and Rx interrupts */
351 xgbe_disable_rx_tx_ints(pdata);
352
353 /* Turn on polling */
354 __napi_schedule_irqoff(&pdata->napi);
355 }
356 }
357
358 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
359 pdata->ext_stats.rx_buffer_unavailable++;
360
361 /* Restart the device on a Fatal Bus Error */
362 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
363 schedule_work(&pdata->restart_work);
364
365 /* Clear all interrupt signals */
366 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
367 }
368
369 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
370 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
371
372 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
373 hw_if->tx_mmc_int(pdata);
374
375 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
376 hw_if->rx_mmc_int(pdata);
377
378 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
379 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
380
381 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
382 /* Read Tx Timestamp to clear interrupt */
383 pdata->tx_tstamp =
384 hw_if->get_tx_tstamp(pdata);
385 queue_work(pdata->dev_workqueue,
386 &pdata->tx_tstamp_work);
387 }
388 }
389 }
390
391 isr_done:
392 return IRQ_HANDLED;
393 }
394
395 static irqreturn_t xgbe_dma_isr(int irq, void *data)
396 {
397 struct xgbe_channel *channel = data;
398
399 /* Per channel DMA interrupts are enabled, so we use the per
400 * channel napi structure and not the private data napi structure
401 */
402 if (napi_schedule_prep(&channel->napi)) {
403 /* Disable Tx and Rx interrupts */
404 disable_irq_nosync(channel->dma_irq);
405
406 /* Turn on polling */
407 __napi_schedule_irqoff(&channel->napi);
408 }
409
410 return IRQ_HANDLED;
411 }
412
413 static void xgbe_tx_timer(unsigned long data)
414 {
415 struct xgbe_channel *channel = (struct xgbe_channel *)data;
416 struct xgbe_prv_data *pdata = channel->pdata;
417 struct napi_struct *napi;
418
419 DBGPR("-->xgbe_tx_timer\n");
420
421 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
422
423 if (napi_schedule_prep(napi)) {
424 /* Disable Tx and Rx interrupts */
425 if (pdata->per_channel_irq)
426 disable_irq_nosync(channel->dma_irq);
427 else
428 xgbe_disable_rx_tx_ints(pdata);
429
430 /* Turn on polling */
431 __napi_schedule(napi);
432 }
433
434 channel->tx_timer_active = 0;
435
436 DBGPR("<--xgbe_tx_timer\n");
437 }
438
439 static void xgbe_service(struct work_struct *work)
440 {
441 struct xgbe_prv_data *pdata = container_of(work,
442 struct xgbe_prv_data,
443 service_work);
444
445 pdata->phy_if.phy_status(pdata);
446 }
447
448 static void xgbe_service_timer(unsigned long data)
449 {
450 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
451
452 queue_work(pdata->dev_workqueue, &pdata->service_work);
453
454 mod_timer(&pdata->service_timer, jiffies + HZ);
455 }
456
457 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
458 {
459 struct xgbe_channel *channel;
460 unsigned int i;
461
462 setup_timer(&pdata->service_timer, xgbe_service_timer,
463 (unsigned long)pdata);
464
465 channel = pdata->channel;
466 for (i = 0; i < pdata->channel_count; i++, channel++) {
467 if (!channel->tx_ring)
468 break;
469
470 setup_timer(&channel->tx_timer, xgbe_tx_timer,
471 (unsigned long)channel);
472 }
473 }
474
475 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
476 {
477 mod_timer(&pdata->service_timer, jiffies + HZ);
478 }
479
480 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
481 {
482 struct xgbe_channel *channel;
483 unsigned int i;
484
485 del_timer_sync(&pdata->service_timer);
486
487 channel = pdata->channel;
488 for (i = 0; i < pdata->channel_count; i++, channel++) {
489 if (!channel->tx_ring)
490 break;
491
492 del_timer_sync(&channel->tx_timer);
493 }
494 }
495
496 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
497 {
498 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
499 struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
500
501 DBGPR("-->xgbe_get_all_hw_features\n");
502
503 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
504 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
505 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
506
507 memset(hw_feat, 0, sizeof(*hw_feat));
508
509 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
510
511 /* Hardware feature register 0 */
512 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
513 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
514 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
515 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
516 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
517 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
518 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
519 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
520 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
521 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
522 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
523 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
524 ADDMACADRSEL);
525 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
526 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
527
528 /* Hardware feature register 1 */
529 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
530 RXFIFOSIZE);
531 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
532 TXFIFOSIZE);
533 hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
534 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
535 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
536 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
537 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
538 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
539 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
540 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
541 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
542 HASHTBLSZ);
543 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
544 L3L4FNUM);
545
546 /* Hardware feature register 2 */
547 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
548 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
549 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
550 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
551 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
552 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
553
554 /* Translate the Hash Table size into actual number */
555 switch (hw_feat->hash_table_size) {
556 case 0:
557 break;
558 case 1:
559 hw_feat->hash_table_size = 64;
560 break;
561 case 2:
562 hw_feat->hash_table_size = 128;
563 break;
564 case 3:
565 hw_feat->hash_table_size = 256;
566 break;
567 }
568
569 /* Translate the address width setting into actual number */
570 switch (hw_feat->dma_width) {
571 case 0:
572 hw_feat->dma_width = 32;
573 break;
574 case 1:
575 hw_feat->dma_width = 40;
576 break;
577 case 2:
578 hw_feat->dma_width = 48;
579 break;
580 default:
581 hw_feat->dma_width = 32;
582 }
583
584 /* The Queue, Channel and TC counts are zero based so increment them
585 * to get the actual number
586 */
587 hw_feat->rx_q_cnt++;
588 hw_feat->tx_q_cnt++;
589 hw_feat->rx_ch_cnt++;
590 hw_feat->tx_ch_cnt++;
591 hw_feat->tc_cnt++;
592
593 DBGPR("<--xgbe_get_all_hw_features\n");
594 }
595
596 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
597 {
598 struct xgbe_channel *channel;
599 unsigned int i;
600
601 if (pdata->per_channel_irq) {
602 channel = pdata->channel;
603 for (i = 0; i < pdata->channel_count; i++, channel++) {
604 if (add)
605 netif_napi_add(pdata->netdev, &channel->napi,
606 xgbe_one_poll, NAPI_POLL_WEIGHT);
607
608 napi_enable(&channel->napi);
609 }
610 } else {
611 if (add)
612 netif_napi_add(pdata->netdev, &pdata->napi,
613 xgbe_all_poll, NAPI_POLL_WEIGHT);
614
615 napi_enable(&pdata->napi);
616 }
617 }
618
619 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
620 {
621 struct xgbe_channel *channel;
622 unsigned int i;
623
624 if (pdata->per_channel_irq) {
625 channel = pdata->channel;
626 for (i = 0; i < pdata->channel_count; i++, channel++) {
627 napi_disable(&channel->napi);
628
629 if (del)
630 netif_napi_del(&channel->napi);
631 }
632 } else {
633 napi_disable(&pdata->napi);
634
635 if (del)
636 netif_napi_del(&pdata->napi);
637 }
638 }
639
640 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
641 {
642 struct xgbe_channel *channel;
643 struct net_device *netdev = pdata->netdev;
644 unsigned int i;
645 int ret;
646
647 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
648 netdev->name, pdata);
649 if (ret) {
650 netdev_alert(netdev, "error requesting irq %d\n",
651 pdata->dev_irq);
652 return ret;
653 }
654
655 if (!pdata->per_channel_irq)
656 return 0;
657
658 channel = pdata->channel;
659 for (i = 0; i < pdata->channel_count; i++, channel++) {
660 snprintf(channel->dma_irq_name,
661 sizeof(channel->dma_irq_name) - 1,
662 "%s-TxRx-%u", netdev_name(netdev),
663 channel->queue_index);
664
665 ret = devm_request_irq(pdata->dev, channel->dma_irq,
666 xgbe_dma_isr, 0,
667 channel->dma_irq_name, channel);
668 if (ret) {
669 netdev_alert(netdev, "error requesting irq %d\n",
670 channel->dma_irq);
671 goto err_irq;
672 }
673 }
674
675 return 0;
676
677 err_irq:
678 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
679 for (i--, channel--; i < pdata->channel_count; i--, channel--)
680 devm_free_irq(pdata->dev, channel->dma_irq, channel);
681
682 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
683
684 return ret;
685 }
686
687 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
688 {
689 struct xgbe_channel *channel;
690 unsigned int i;
691
692 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
693
694 if (!pdata->per_channel_irq)
695 return;
696
697 channel = pdata->channel;
698 for (i = 0; i < pdata->channel_count; i++, channel++)
699 devm_free_irq(pdata->dev, channel->dma_irq, channel);
700 }
701
702 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
703 {
704 struct xgbe_hw_if *hw_if = &pdata->hw_if;
705
706 DBGPR("-->xgbe_init_tx_coalesce\n");
707
708 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
709 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
710
711 hw_if->config_tx_coalesce(pdata);
712
713 DBGPR("<--xgbe_init_tx_coalesce\n");
714 }
715
716 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
717 {
718 struct xgbe_hw_if *hw_if = &pdata->hw_if;
719
720 DBGPR("-->xgbe_init_rx_coalesce\n");
721
722 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
723 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
724 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
725
726 hw_if->config_rx_coalesce(pdata);
727
728 DBGPR("<--xgbe_init_rx_coalesce\n");
729 }
730
731 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
732 {
733 struct xgbe_desc_if *desc_if = &pdata->desc_if;
734 struct xgbe_channel *channel;
735 struct xgbe_ring *ring;
736 struct xgbe_ring_data *rdata;
737 unsigned int i, j;
738
739 DBGPR("-->xgbe_free_tx_data\n");
740
741 channel = pdata->channel;
742 for (i = 0; i < pdata->channel_count; i++, channel++) {
743 ring = channel->tx_ring;
744 if (!ring)
745 break;
746
747 for (j = 0; j < ring->rdesc_count; j++) {
748 rdata = XGBE_GET_DESC_DATA(ring, j);
749 desc_if->unmap_rdata(pdata, rdata);
750 }
751 }
752
753 DBGPR("<--xgbe_free_tx_data\n");
754 }
755
756 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
757 {
758 struct xgbe_desc_if *desc_if = &pdata->desc_if;
759 struct xgbe_channel *channel;
760 struct xgbe_ring *ring;
761 struct xgbe_ring_data *rdata;
762 unsigned int i, j;
763
764 DBGPR("-->xgbe_free_rx_data\n");
765
766 channel = pdata->channel;
767 for (i = 0; i < pdata->channel_count; i++, channel++) {
768 ring = channel->rx_ring;
769 if (!ring)
770 break;
771
772 for (j = 0; j < ring->rdesc_count; j++) {
773 rdata = XGBE_GET_DESC_DATA(ring, j);
774 desc_if->unmap_rdata(pdata, rdata);
775 }
776 }
777
778 DBGPR("<--xgbe_free_rx_data\n");
779 }
780
781 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
782 {
783 pdata->phy_link = -1;
784 pdata->phy_speed = SPEED_UNKNOWN;
785
786 return pdata->phy_if.phy_reset(pdata);
787 }
788
789 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
790 {
791 struct xgbe_prv_data *pdata = netdev_priv(netdev);
792 struct xgbe_hw_if *hw_if = &pdata->hw_if;
793 unsigned long flags;
794
795 DBGPR("-->xgbe_powerdown\n");
796
797 if (!netif_running(netdev) ||
798 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
799 netdev_alert(netdev, "Device is already powered down\n");
800 DBGPR("<--xgbe_powerdown\n");
801 return -EINVAL;
802 }
803
804 spin_lock_irqsave(&pdata->lock, flags);
805
806 if (caller == XGMAC_DRIVER_CONTEXT)
807 netif_device_detach(netdev);
808
809 netif_tx_stop_all_queues(netdev);
810
811 xgbe_stop_timers(pdata);
812 flush_workqueue(pdata->dev_workqueue);
813
814 hw_if->powerdown_tx(pdata);
815 hw_if->powerdown_rx(pdata);
816
817 xgbe_napi_disable(pdata, 0);
818
819 pdata->power_down = 1;
820
821 spin_unlock_irqrestore(&pdata->lock, flags);
822
823 DBGPR("<--xgbe_powerdown\n");
824
825 return 0;
826 }
827
828 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
829 {
830 struct xgbe_prv_data *pdata = netdev_priv(netdev);
831 struct xgbe_hw_if *hw_if = &pdata->hw_if;
832 unsigned long flags;
833
834 DBGPR("-->xgbe_powerup\n");
835
836 if (!netif_running(netdev) ||
837 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
838 netdev_alert(netdev, "Device is already powered up\n");
839 DBGPR("<--xgbe_powerup\n");
840 return -EINVAL;
841 }
842
843 spin_lock_irqsave(&pdata->lock, flags);
844
845 pdata->power_down = 0;
846
847 xgbe_napi_enable(pdata, 0);
848
849 hw_if->powerup_tx(pdata);
850 hw_if->powerup_rx(pdata);
851
852 if (caller == XGMAC_DRIVER_CONTEXT)
853 netif_device_attach(netdev);
854
855 netif_tx_start_all_queues(netdev);
856
857 xgbe_start_timers(pdata);
858
859 spin_unlock_irqrestore(&pdata->lock, flags);
860
861 DBGPR("<--xgbe_powerup\n");
862
863 return 0;
864 }
865
866 static int xgbe_start(struct xgbe_prv_data *pdata)
867 {
868 struct xgbe_hw_if *hw_if = &pdata->hw_if;
869 struct xgbe_phy_if *phy_if = &pdata->phy_if;
870 struct net_device *netdev = pdata->netdev;
871 int ret;
872
873 DBGPR("-->xgbe_start\n");
874
875 hw_if->init(pdata);
876
877 ret = phy_if->phy_start(pdata);
878 if (ret)
879 goto err_phy;
880
881 xgbe_napi_enable(pdata, 1);
882
883 ret = xgbe_request_irqs(pdata);
884 if (ret)
885 goto err_napi;
886
887 hw_if->enable_tx(pdata);
888 hw_if->enable_rx(pdata);
889
890 netif_tx_start_all_queues(netdev);
891
892 xgbe_start_timers(pdata);
893 queue_work(pdata->dev_workqueue, &pdata->service_work);
894
895 DBGPR("<--xgbe_start\n");
896
897 return 0;
898
899 err_napi:
900 xgbe_napi_disable(pdata, 1);
901
902 phy_if->phy_stop(pdata);
903
904 err_phy:
905 hw_if->exit(pdata);
906
907 return ret;
908 }
909
910 static void xgbe_stop(struct xgbe_prv_data *pdata)
911 {
912 struct xgbe_hw_if *hw_if = &pdata->hw_if;
913 struct xgbe_phy_if *phy_if = &pdata->phy_if;
914 struct xgbe_channel *channel;
915 struct net_device *netdev = pdata->netdev;
916 struct netdev_queue *txq;
917 unsigned int i;
918
919 DBGPR("-->xgbe_stop\n");
920
921 netif_tx_stop_all_queues(netdev);
922
923 xgbe_stop_timers(pdata);
924 flush_workqueue(pdata->dev_workqueue);
925
926 hw_if->disable_tx(pdata);
927 hw_if->disable_rx(pdata);
928
929 xgbe_free_irqs(pdata);
930
931 xgbe_napi_disable(pdata, 1);
932
933 phy_if->phy_stop(pdata);
934
935 hw_if->exit(pdata);
936
937 channel = pdata->channel;
938 for (i = 0; i < pdata->channel_count; i++, channel++) {
939 if (!channel->tx_ring)
940 continue;
941
942 txq = netdev_get_tx_queue(netdev, channel->queue_index);
943 netdev_tx_reset_queue(txq);
944 }
945
946 DBGPR("<--xgbe_stop\n");
947 }
948
949 static void xgbe_restart_dev(struct xgbe_prv_data *pdata)
950 {
951 DBGPR("-->xgbe_restart_dev\n");
952
953 /* If not running, "restart" will happen on open */
954 if (!netif_running(pdata->netdev))
955 return;
956
957 xgbe_stop(pdata);
958
959 xgbe_free_tx_data(pdata);
960 xgbe_free_rx_data(pdata);
961
962 xgbe_start(pdata);
963
964 DBGPR("<--xgbe_restart_dev\n");
965 }
966
967 static void xgbe_restart(struct work_struct *work)
968 {
969 struct xgbe_prv_data *pdata = container_of(work,
970 struct xgbe_prv_data,
971 restart_work);
972
973 rtnl_lock();
974
975 xgbe_restart_dev(pdata);
976
977 rtnl_unlock();
978 }
979
980 static void xgbe_tx_tstamp(struct work_struct *work)
981 {
982 struct xgbe_prv_data *pdata = container_of(work,
983 struct xgbe_prv_data,
984 tx_tstamp_work);
985 struct skb_shared_hwtstamps hwtstamps;
986 u64 nsec;
987 unsigned long flags;
988
989 if (pdata->tx_tstamp) {
990 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
991 pdata->tx_tstamp);
992
993 memset(&hwtstamps, 0, sizeof(hwtstamps));
994 hwtstamps.hwtstamp = ns_to_ktime(nsec);
995 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
996 }
997
998 dev_kfree_skb_any(pdata->tx_tstamp_skb);
999
1000 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1001 pdata->tx_tstamp_skb = NULL;
1002 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1003 }
1004
1005 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1006 struct ifreq *ifreq)
1007 {
1008 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1009 sizeof(pdata->tstamp_config)))
1010 return -EFAULT;
1011
1012 return 0;
1013 }
1014
1015 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1016 struct ifreq *ifreq)
1017 {
1018 struct hwtstamp_config config;
1019 unsigned int mac_tscr;
1020
1021 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1022 return -EFAULT;
1023
1024 if (config.flags)
1025 return -EINVAL;
1026
1027 mac_tscr = 0;
1028
1029 switch (config.tx_type) {
1030 case HWTSTAMP_TX_OFF:
1031 break;
1032
1033 case HWTSTAMP_TX_ON:
1034 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1035 break;
1036
1037 default:
1038 return -ERANGE;
1039 }
1040
1041 switch (config.rx_filter) {
1042 case HWTSTAMP_FILTER_NONE:
1043 break;
1044
1045 case HWTSTAMP_FILTER_ALL:
1046 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1047 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1048 break;
1049
1050 /* PTP v2, UDP, any kind of event packet */
1051 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1052 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1053 /* PTP v1, UDP, any kind of event packet */
1054 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1055 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1056 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1057 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1058 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1059 break;
1060
1061 /* PTP v2, UDP, Sync packet */
1062 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1063 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1064 /* PTP v1, UDP, Sync packet */
1065 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1066 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1067 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1068 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1069 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1070 break;
1071
1072 /* PTP v2, UDP, Delay_req packet */
1073 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1074 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1075 /* PTP v1, UDP, Delay_req packet */
1076 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1077 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1078 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1079 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1080 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1081 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1082 break;
1083
1084 /* 802.AS1, Ethernet, any kind of event packet */
1085 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1086 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1087 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1088 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1089 break;
1090
1091 /* 802.AS1, Ethernet, Sync packet */
1092 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1093 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1094 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1095 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1096 break;
1097
1098 /* 802.AS1, Ethernet, Delay_req packet */
1099 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1100 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1101 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1102 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1103 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1104 break;
1105
1106 /* PTP v2/802.AS1, any layer, any kind of event packet */
1107 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1108 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1109 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1110 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1111 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1112 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1113 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1114 break;
1115
1116 /* PTP v2/802.AS1, any layer, Sync packet */
1117 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1118 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1119 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1120 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1121 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1122 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1123 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1124 break;
1125
1126 /* PTP v2/802.AS1, any layer, Delay_req packet */
1127 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1128 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1129 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1130 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1131 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1132 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1133 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1134 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1135 break;
1136
1137 default:
1138 return -ERANGE;
1139 }
1140
1141 pdata->hw_if.config_tstamp(pdata, mac_tscr);
1142
1143 memcpy(&pdata->tstamp_config, &config, sizeof(config));
1144
1145 return 0;
1146 }
1147
1148 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1149 struct sk_buff *skb,
1150 struct xgbe_packet_data *packet)
1151 {
1152 unsigned long flags;
1153
1154 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1155 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1156 if (pdata->tx_tstamp_skb) {
1157 /* Another timestamp in progress, ignore this one */
1158 XGMAC_SET_BITS(packet->attributes,
1159 TX_PACKET_ATTRIBUTES, PTP, 0);
1160 } else {
1161 pdata->tx_tstamp_skb = skb_get(skb);
1162 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1163 }
1164 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1165 }
1166
1167 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1168 skb_tx_timestamp(skb);
1169 }
1170
1171 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1172 {
1173 if (skb_vlan_tag_present(skb))
1174 packet->vlan_ctag = skb_vlan_tag_get(skb);
1175 }
1176
1177 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1178 {
1179 int ret;
1180
1181 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1182 TSO_ENABLE))
1183 return 0;
1184
1185 ret = skb_cow_head(skb, 0);
1186 if (ret)
1187 return ret;
1188
1189 packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1190 packet->tcp_header_len = tcp_hdrlen(skb);
1191 packet->tcp_payload_len = skb->len - packet->header_len;
1192 packet->mss = skb_shinfo(skb)->gso_size;
1193 DBGPR(" packet->header_len=%u\n", packet->header_len);
1194 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1195 packet->tcp_header_len, packet->tcp_payload_len);
1196 DBGPR(" packet->mss=%u\n", packet->mss);
1197
1198 /* Update the number of packets that will ultimately be transmitted
1199 * along with the extra bytes for each extra packet
1200 */
1201 packet->tx_packets = skb_shinfo(skb)->gso_segs;
1202 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1203
1204 return 0;
1205 }
1206
1207 static int xgbe_is_tso(struct sk_buff *skb)
1208 {
1209 if (skb->ip_summed != CHECKSUM_PARTIAL)
1210 return 0;
1211
1212 if (!skb_is_gso(skb))
1213 return 0;
1214
1215 DBGPR(" TSO packet to be processed\n");
1216
1217 return 1;
1218 }
1219
1220 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1221 struct xgbe_ring *ring, struct sk_buff *skb,
1222 struct xgbe_packet_data *packet)
1223 {
1224 struct skb_frag_struct *frag;
1225 unsigned int context_desc;
1226 unsigned int len;
1227 unsigned int i;
1228
1229 packet->skb = skb;
1230
1231 context_desc = 0;
1232 packet->rdesc_count = 0;
1233
1234 packet->tx_packets = 1;
1235 packet->tx_bytes = skb->len;
1236
1237 if (xgbe_is_tso(skb)) {
1238 /* TSO requires an extra descriptor if mss is different */
1239 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1240 context_desc = 1;
1241 packet->rdesc_count++;
1242 }
1243
1244 /* TSO requires an extra descriptor for TSO header */
1245 packet->rdesc_count++;
1246
1247 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1248 TSO_ENABLE, 1);
1249 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1250 CSUM_ENABLE, 1);
1251 } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1252 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1253 CSUM_ENABLE, 1);
1254
1255 if (skb_vlan_tag_present(skb)) {
1256 /* VLAN requires an extra descriptor if tag is different */
1257 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1258 /* We can share with the TSO context descriptor */
1259 if (!context_desc) {
1260 context_desc = 1;
1261 packet->rdesc_count++;
1262 }
1263
1264 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1265 VLAN_CTAG, 1);
1266 }
1267
1268 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1269 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1270 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1271 PTP, 1);
1272
1273 for (len = skb_headlen(skb); len;) {
1274 packet->rdesc_count++;
1275 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1276 }
1277
1278 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1279 frag = &skb_shinfo(skb)->frags[i];
1280 for (len = skb_frag_size(frag); len; ) {
1281 packet->rdesc_count++;
1282 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1283 }
1284 }
1285 }
1286
1287 static int xgbe_open(struct net_device *netdev)
1288 {
1289 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1290 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1291 int ret;
1292
1293 DBGPR("-->xgbe_open\n");
1294
1295 /* Initialize the phy */
1296 ret = xgbe_phy_init(pdata);
1297 if (ret)
1298 return ret;
1299
1300 /* Enable the clocks */
1301 ret = clk_prepare_enable(pdata->sysclk);
1302 if (ret) {
1303 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1304 return ret;
1305 }
1306
1307 ret = clk_prepare_enable(pdata->ptpclk);
1308 if (ret) {
1309 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1310 goto err_sysclk;
1311 }
1312
1313 /* Calculate the Rx buffer size before allocating rings */
1314 ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1315 if (ret < 0)
1316 goto err_ptpclk;
1317 pdata->rx_buf_size = ret;
1318
1319 /* Allocate the channel and ring structures */
1320 ret = xgbe_alloc_channels(pdata);
1321 if (ret)
1322 goto err_ptpclk;
1323
1324 /* Allocate the ring descriptors and buffers */
1325 ret = desc_if->alloc_ring_resources(pdata);
1326 if (ret)
1327 goto err_channels;
1328
1329 INIT_WORK(&pdata->service_work, xgbe_service);
1330 INIT_WORK(&pdata->restart_work, xgbe_restart);
1331 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1332 xgbe_init_timers(pdata);
1333
1334 ret = xgbe_start(pdata);
1335 if (ret)
1336 goto err_rings;
1337
1338 clear_bit(XGBE_DOWN, &pdata->dev_state);
1339
1340 DBGPR("<--xgbe_open\n");
1341
1342 return 0;
1343
1344 err_rings:
1345 desc_if->free_ring_resources(pdata);
1346
1347 err_channels:
1348 xgbe_free_channels(pdata);
1349
1350 err_ptpclk:
1351 clk_disable_unprepare(pdata->ptpclk);
1352
1353 err_sysclk:
1354 clk_disable_unprepare(pdata->sysclk);
1355
1356 return ret;
1357 }
1358
1359 static int xgbe_close(struct net_device *netdev)
1360 {
1361 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1362 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1363
1364 DBGPR("-->xgbe_close\n");
1365
1366 /* Stop the device */
1367 xgbe_stop(pdata);
1368
1369 /* Free the ring descriptors and buffers */
1370 desc_if->free_ring_resources(pdata);
1371
1372 /* Free the channel and ring structures */
1373 xgbe_free_channels(pdata);
1374
1375 /* Disable the clocks */
1376 clk_disable_unprepare(pdata->ptpclk);
1377 clk_disable_unprepare(pdata->sysclk);
1378
1379 set_bit(XGBE_DOWN, &pdata->dev_state);
1380
1381 DBGPR("<--xgbe_close\n");
1382
1383 return 0;
1384 }
1385
1386 static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1387 {
1388 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1389 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1390 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1391 struct xgbe_channel *channel;
1392 struct xgbe_ring *ring;
1393 struct xgbe_packet_data *packet;
1394 struct netdev_queue *txq;
1395 int ret;
1396
1397 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1398
1399 channel = pdata->channel + skb->queue_mapping;
1400 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1401 ring = channel->tx_ring;
1402 packet = &ring->packet_data;
1403
1404 ret = NETDEV_TX_OK;
1405
1406 if (skb->len == 0) {
1407 netif_err(pdata, tx_err, netdev,
1408 "empty skb received from stack\n");
1409 dev_kfree_skb_any(skb);
1410 goto tx_netdev_return;
1411 }
1412
1413 /* Calculate preliminary packet info */
1414 memset(packet, 0, sizeof(*packet));
1415 xgbe_packet_info(pdata, ring, skb, packet);
1416
1417 /* Check that there are enough descriptors available */
1418 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1419 if (ret)
1420 goto tx_netdev_return;
1421
1422 ret = xgbe_prep_tso(skb, packet);
1423 if (ret) {
1424 netif_err(pdata, tx_err, netdev,
1425 "error processing TSO packet\n");
1426 dev_kfree_skb_any(skb);
1427 goto tx_netdev_return;
1428 }
1429 xgbe_prep_vlan(skb, packet);
1430
1431 if (!desc_if->map_tx_skb(channel, skb)) {
1432 dev_kfree_skb_any(skb);
1433 goto tx_netdev_return;
1434 }
1435
1436 xgbe_prep_tx_tstamp(pdata, skb, packet);
1437
1438 /* Report on the actual number of bytes (to be) sent */
1439 netdev_tx_sent_queue(txq, packet->tx_bytes);
1440
1441 /* Configure required descriptor fields for transmission */
1442 hw_if->dev_xmit(channel);
1443
1444 if (netif_msg_pktdata(pdata))
1445 xgbe_print_pkt(netdev, skb, true);
1446
1447 /* Stop the queue in advance if there may not be enough descriptors */
1448 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
1449
1450 ret = NETDEV_TX_OK;
1451
1452 tx_netdev_return:
1453 return ret;
1454 }
1455
1456 static void xgbe_set_rx_mode(struct net_device *netdev)
1457 {
1458 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1459 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1460
1461 DBGPR("-->xgbe_set_rx_mode\n");
1462
1463 hw_if->config_rx_mode(pdata);
1464
1465 DBGPR("<--xgbe_set_rx_mode\n");
1466 }
1467
1468 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
1469 {
1470 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1471 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1472 struct sockaddr *saddr = addr;
1473
1474 DBGPR("-->xgbe_set_mac_address\n");
1475
1476 if (!is_valid_ether_addr(saddr->sa_data))
1477 return -EADDRNOTAVAIL;
1478
1479 memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
1480
1481 hw_if->set_mac_address(pdata, netdev->dev_addr);
1482
1483 DBGPR("<--xgbe_set_mac_address\n");
1484
1485 return 0;
1486 }
1487
1488 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
1489 {
1490 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1491 int ret;
1492
1493 switch (cmd) {
1494 case SIOCGHWTSTAMP:
1495 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
1496 break;
1497
1498 case SIOCSHWTSTAMP:
1499 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
1500 break;
1501
1502 default:
1503 ret = -EOPNOTSUPP;
1504 }
1505
1506 return ret;
1507 }
1508
1509 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
1510 {
1511 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1512 int ret;
1513
1514 DBGPR("-->xgbe_change_mtu\n");
1515
1516 ret = xgbe_calc_rx_buf_size(netdev, mtu);
1517 if (ret < 0)
1518 return ret;
1519
1520 pdata->rx_buf_size = ret;
1521 netdev->mtu = mtu;
1522
1523 xgbe_restart_dev(pdata);
1524
1525 DBGPR("<--xgbe_change_mtu\n");
1526
1527 return 0;
1528 }
1529
1530 static void xgbe_tx_timeout(struct net_device *netdev)
1531 {
1532 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1533
1534 netdev_warn(netdev, "tx timeout, device restarting\n");
1535 schedule_work(&pdata->restart_work);
1536 }
1537
1538 static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev,
1539 struct rtnl_link_stats64 *s)
1540 {
1541 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1542 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
1543
1544 DBGPR("-->%s\n", __func__);
1545
1546 pdata->hw_if.read_mmc_stats(pdata);
1547
1548 s->rx_packets = pstats->rxframecount_gb;
1549 s->rx_bytes = pstats->rxoctetcount_gb;
1550 s->rx_errors = pstats->rxframecount_gb -
1551 pstats->rxbroadcastframes_g -
1552 pstats->rxmulticastframes_g -
1553 pstats->rxunicastframes_g;
1554 s->multicast = pstats->rxmulticastframes_g;
1555 s->rx_length_errors = pstats->rxlengtherror;
1556 s->rx_crc_errors = pstats->rxcrcerror;
1557 s->rx_fifo_errors = pstats->rxfifooverflow;
1558
1559 s->tx_packets = pstats->txframecount_gb;
1560 s->tx_bytes = pstats->txoctetcount_gb;
1561 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
1562 s->tx_dropped = netdev->stats.tx_dropped;
1563
1564 DBGPR("<--%s\n", __func__);
1565
1566 return s;
1567 }
1568
1569 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1570 u16 vid)
1571 {
1572 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1573 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1574
1575 DBGPR("-->%s\n", __func__);
1576
1577 set_bit(vid, pdata->active_vlans);
1578 hw_if->update_vlan_hash_table(pdata);
1579
1580 DBGPR("<--%s\n", __func__);
1581
1582 return 0;
1583 }
1584
1585 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1586 u16 vid)
1587 {
1588 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1589 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1590
1591 DBGPR("-->%s\n", __func__);
1592
1593 clear_bit(vid, pdata->active_vlans);
1594 hw_if->update_vlan_hash_table(pdata);
1595
1596 DBGPR("<--%s\n", __func__);
1597
1598 return 0;
1599 }
1600
1601 #ifdef CONFIG_NET_POLL_CONTROLLER
1602 static void xgbe_poll_controller(struct net_device *netdev)
1603 {
1604 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1605 struct xgbe_channel *channel;
1606 unsigned int i;
1607
1608 DBGPR("-->xgbe_poll_controller\n");
1609
1610 if (pdata->per_channel_irq) {
1611 channel = pdata->channel;
1612 for (i = 0; i < pdata->channel_count; i++, channel++)
1613 xgbe_dma_isr(channel->dma_irq, channel);
1614 } else {
1615 disable_irq(pdata->dev_irq);
1616 xgbe_isr(pdata->dev_irq, pdata);
1617 enable_irq(pdata->dev_irq);
1618 }
1619
1620 DBGPR("<--xgbe_poll_controller\n");
1621 }
1622 #endif /* End CONFIG_NET_POLL_CONTROLLER */
1623
1624 static int xgbe_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
1625 struct tc_to_netdev *tc_to_netdev)
1626 {
1627 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1628 u8 tc;
1629
1630 if (tc_to_netdev->type != TC_SETUP_MQPRIO)
1631 return -EINVAL;
1632
1633 tc = tc_to_netdev->tc;
1634
1635 if (tc > pdata->hw_feat.tc_cnt)
1636 return -EINVAL;
1637
1638 pdata->num_tcs = tc;
1639 pdata->hw_if.config_tc(pdata);
1640
1641 return 0;
1642 }
1643
1644 static int xgbe_set_features(struct net_device *netdev,
1645 netdev_features_t features)
1646 {
1647 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1648 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1649 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
1650 int ret = 0;
1651
1652 rxhash = pdata->netdev_features & NETIF_F_RXHASH;
1653 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
1654 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
1655 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
1656
1657 if ((features & NETIF_F_RXHASH) && !rxhash)
1658 ret = hw_if->enable_rss(pdata);
1659 else if (!(features & NETIF_F_RXHASH) && rxhash)
1660 ret = hw_if->disable_rss(pdata);
1661 if (ret)
1662 return ret;
1663
1664 if ((features & NETIF_F_RXCSUM) && !rxcsum)
1665 hw_if->enable_rx_csum(pdata);
1666 else if (!(features & NETIF_F_RXCSUM) && rxcsum)
1667 hw_if->disable_rx_csum(pdata);
1668
1669 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
1670 hw_if->enable_rx_vlan_stripping(pdata);
1671 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
1672 hw_if->disable_rx_vlan_stripping(pdata);
1673
1674 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
1675 hw_if->enable_rx_vlan_filtering(pdata);
1676 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
1677 hw_if->disable_rx_vlan_filtering(pdata);
1678
1679 pdata->netdev_features = features;
1680
1681 DBGPR("<--xgbe_set_features\n");
1682
1683 return 0;
1684 }
1685
1686 static const struct net_device_ops xgbe_netdev_ops = {
1687 .ndo_open = xgbe_open,
1688 .ndo_stop = xgbe_close,
1689 .ndo_start_xmit = xgbe_xmit,
1690 .ndo_set_rx_mode = xgbe_set_rx_mode,
1691 .ndo_set_mac_address = xgbe_set_mac_address,
1692 .ndo_validate_addr = eth_validate_addr,
1693 .ndo_do_ioctl = xgbe_ioctl,
1694 .ndo_change_mtu = xgbe_change_mtu,
1695 .ndo_tx_timeout = xgbe_tx_timeout,
1696 .ndo_get_stats64 = xgbe_get_stats64,
1697 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid,
1698 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid,
1699 #ifdef CONFIG_NET_POLL_CONTROLLER
1700 .ndo_poll_controller = xgbe_poll_controller,
1701 #endif
1702 .ndo_setup_tc = xgbe_setup_tc,
1703 .ndo_set_features = xgbe_set_features,
1704 };
1705
1706 const struct net_device_ops *xgbe_get_netdev_ops(void)
1707 {
1708 return &xgbe_netdev_ops;
1709 }
1710
1711 static void xgbe_rx_refresh(struct xgbe_channel *channel)
1712 {
1713 struct xgbe_prv_data *pdata = channel->pdata;
1714 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1715 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1716 struct xgbe_ring *ring = channel->rx_ring;
1717 struct xgbe_ring_data *rdata;
1718
1719 while (ring->dirty != ring->cur) {
1720 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
1721
1722 /* Reset rdata values */
1723 desc_if->unmap_rdata(pdata, rdata);
1724
1725 if (desc_if->map_rx_buffer(pdata, ring, rdata))
1726 break;
1727
1728 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
1729
1730 ring->dirty++;
1731 }
1732
1733 /* Make sure everything is written before the register write */
1734 wmb();
1735
1736 /* Update the Rx Tail Pointer Register with address of
1737 * the last cleaned entry */
1738 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
1739 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1740 lower_32_bits(rdata->rdesc_dma));
1741 }
1742
1743 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
1744 struct napi_struct *napi,
1745 struct xgbe_ring_data *rdata,
1746 unsigned int len)
1747 {
1748 struct sk_buff *skb;
1749 u8 *packet;
1750 unsigned int copy_len;
1751
1752 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
1753 if (!skb)
1754 return NULL;
1755
1756 /* Start with the header buffer which may contain just the header
1757 * or the header plus data
1758 */
1759 dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
1760 rdata->rx.hdr.dma_off,
1761 rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
1762
1763 packet = page_address(rdata->rx.hdr.pa.pages) +
1764 rdata->rx.hdr.pa.pages_offset;
1765 copy_len = (rdata->rx.hdr_len) ? rdata->rx.hdr_len : len;
1766 copy_len = min(rdata->rx.hdr.dma_len, copy_len);
1767 skb_copy_to_linear_data(skb, packet, copy_len);
1768 skb_put(skb, copy_len);
1769
1770 len -= copy_len;
1771 if (len) {
1772 /* Add the remaining data as a frag */
1773 dma_sync_single_range_for_cpu(pdata->dev,
1774 rdata->rx.buf.dma_base,
1775 rdata->rx.buf.dma_off,
1776 rdata->rx.buf.dma_len,
1777 DMA_FROM_DEVICE);
1778
1779 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1780 rdata->rx.buf.pa.pages,
1781 rdata->rx.buf.pa.pages_offset,
1782 len, rdata->rx.buf.dma_len);
1783 rdata->rx.buf.pa.pages = NULL;
1784 }
1785
1786 return skb;
1787 }
1788
1789 static int xgbe_tx_poll(struct xgbe_channel *channel)
1790 {
1791 struct xgbe_prv_data *pdata = channel->pdata;
1792 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1793 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1794 struct xgbe_ring *ring = channel->tx_ring;
1795 struct xgbe_ring_data *rdata;
1796 struct xgbe_ring_desc *rdesc;
1797 struct net_device *netdev = pdata->netdev;
1798 struct netdev_queue *txq;
1799 int processed = 0;
1800 unsigned int tx_packets = 0, tx_bytes = 0;
1801 unsigned int cur;
1802
1803 DBGPR("-->xgbe_tx_poll\n");
1804
1805 /* Nothing to do if there isn't a Tx ring for this channel */
1806 if (!ring)
1807 return 0;
1808
1809 cur = ring->cur;
1810
1811 /* Be sure we get ring->cur before accessing descriptor data */
1812 smp_rmb();
1813
1814 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1815
1816 while ((processed < XGBE_TX_DESC_MAX_PROC) &&
1817 (ring->dirty != cur)) {
1818 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
1819 rdesc = rdata->rdesc;
1820
1821 if (!hw_if->tx_complete(rdesc))
1822 break;
1823
1824 /* Make sure descriptor fields are read after reading the OWN
1825 * bit */
1826 dma_rmb();
1827
1828 if (netif_msg_tx_done(pdata))
1829 xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
1830
1831 if (hw_if->is_last_desc(rdesc)) {
1832 tx_packets += rdata->tx.packets;
1833 tx_bytes += rdata->tx.bytes;
1834 }
1835
1836 /* Free the SKB and reset the descriptor for re-use */
1837 desc_if->unmap_rdata(pdata, rdata);
1838 hw_if->tx_desc_reset(rdata);
1839
1840 processed++;
1841 ring->dirty++;
1842 }
1843
1844 if (!processed)
1845 return 0;
1846
1847 netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
1848
1849 if ((ring->tx.queue_stopped == 1) &&
1850 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
1851 ring->tx.queue_stopped = 0;
1852 netif_tx_wake_queue(txq);
1853 }
1854
1855 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
1856
1857 return processed;
1858 }
1859
1860 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
1861 {
1862 struct xgbe_prv_data *pdata = channel->pdata;
1863 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1864 struct xgbe_ring *ring = channel->rx_ring;
1865 struct xgbe_ring_data *rdata;
1866 struct xgbe_packet_data *packet;
1867 struct net_device *netdev = pdata->netdev;
1868 struct napi_struct *napi;
1869 struct sk_buff *skb;
1870 struct skb_shared_hwtstamps *hwtstamps;
1871 unsigned int incomplete, error, context_next, context;
1872 unsigned int len, rdesc_len, max_len;
1873 unsigned int received = 0;
1874 int packet_count = 0;
1875
1876 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
1877
1878 /* Nothing to do if there isn't a Rx ring for this channel */
1879 if (!ring)
1880 return 0;
1881
1882 incomplete = 0;
1883 context_next = 0;
1884
1885 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
1886
1887 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1888 packet = &ring->packet_data;
1889 while (packet_count < budget) {
1890 DBGPR(" cur = %d\n", ring->cur);
1891
1892 /* First time in loop see if we need to restore state */
1893 if (!received && rdata->state_saved) {
1894 skb = rdata->state.skb;
1895 error = rdata->state.error;
1896 len = rdata->state.len;
1897 } else {
1898 memset(packet, 0, sizeof(*packet));
1899 skb = NULL;
1900 error = 0;
1901 len = 0;
1902 }
1903
1904 read_again:
1905 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1906
1907 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
1908 xgbe_rx_refresh(channel);
1909
1910 if (hw_if->dev_read(channel))
1911 break;
1912
1913 received++;
1914 ring->cur++;
1915
1916 incomplete = XGMAC_GET_BITS(packet->attributes,
1917 RX_PACKET_ATTRIBUTES,
1918 INCOMPLETE);
1919 context_next = XGMAC_GET_BITS(packet->attributes,
1920 RX_PACKET_ATTRIBUTES,
1921 CONTEXT_NEXT);
1922 context = XGMAC_GET_BITS(packet->attributes,
1923 RX_PACKET_ATTRIBUTES,
1924 CONTEXT);
1925
1926 /* Earlier error, just drain the remaining data */
1927 if ((incomplete || context_next) && error)
1928 goto read_again;
1929
1930 if (error || packet->errors) {
1931 if (packet->errors)
1932 netif_err(pdata, rx_err, netdev,
1933 "error in received packet\n");
1934 dev_kfree_skb(skb);
1935 goto next_packet;
1936 }
1937
1938 if (!context) {
1939 /* Length is cumulative, get this descriptor's length */
1940 rdesc_len = rdata->rx.len - len;
1941 len += rdesc_len;
1942
1943 if (rdesc_len && !skb) {
1944 skb = xgbe_create_skb(pdata, napi, rdata,
1945 rdesc_len);
1946 if (!skb)
1947 error = 1;
1948 } else if (rdesc_len) {
1949 dma_sync_single_range_for_cpu(pdata->dev,
1950 rdata->rx.buf.dma_base,
1951 rdata->rx.buf.dma_off,
1952 rdata->rx.buf.dma_len,
1953 DMA_FROM_DEVICE);
1954
1955 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1956 rdata->rx.buf.pa.pages,
1957 rdata->rx.buf.pa.pages_offset,
1958 rdesc_len,
1959 rdata->rx.buf.dma_len);
1960 rdata->rx.buf.pa.pages = NULL;
1961 }
1962 }
1963
1964 if (incomplete || context_next)
1965 goto read_again;
1966
1967 if (!skb)
1968 goto next_packet;
1969
1970 /* Be sure we don't exceed the configured MTU */
1971 max_len = netdev->mtu + ETH_HLEN;
1972 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1973 (skb->protocol == htons(ETH_P_8021Q)))
1974 max_len += VLAN_HLEN;
1975
1976 if (skb->len > max_len) {
1977 netif_err(pdata, rx_err, netdev,
1978 "packet length exceeds configured MTU\n");
1979 dev_kfree_skb(skb);
1980 goto next_packet;
1981 }
1982
1983 if (netif_msg_pktdata(pdata))
1984 xgbe_print_pkt(netdev, skb, false);
1985
1986 skb_checksum_none_assert(skb);
1987 if (XGMAC_GET_BITS(packet->attributes,
1988 RX_PACKET_ATTRIBUTES, CSUM_DONE))
1989 skb->ip_summed = CHECKSUM_UNNECESSARY;
1990
1991 if (XGMAC_GET_BITS(packet->attributes,
1992 RX_PACKET_ATTRIBUTES, VLAN_CTAG))
1993 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1994 packet->vlan_ctag);
1995
1996 if (XGMAC_GET_BITS(packet->attributes,
1997 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
1998 u64 nsec;
1999
2000 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2001 packet->rx_tstamp);
2002 hwtstamps = skb_hwtstamps(skb);
2003 hwtstamps->hwtstamp = ns_to_ktime(nsec);
2004 }
2005
2006 if (XGMAC_GET_BITS(packet->attributes,
2007 RX_PACKET_ATTRIBUTES, RSS_HASH))
2008 skb_set_hash(skb, packet->rss_hash,
2009 packet->rss_hash_type);
2010
2011 skb->dev = netdev;
2012 skb->protocol = eth_type_trans(skb, netdev);
2013 skb_record_rx_queue(skb, channel->queue_index);
2014
2015 napi_gro_receive(napi, skb);
2016
2017 next_packet:
2018 packet_count++;
2019 }
2020
2021 /* Check if we need to save state before leaving */
2022 if (received && (incomplete || context_next)) {
2023 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2024 rdata->state_saved = 1;
2025 rdata->state.skb = skb;
2026 rdata->state.len = len;
2027 rdata->state.error = error;
2028 }
2029
2030 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2031
2032 return packet_count;
2033 }
2034
2035 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2036 {
2037 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2038 napi);
2039 int processed = 0;
2040
2041 DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2042
2043 /* Cleanup Tx ring first */
2044 xgbe_tx_poll(channel);
2045
2046 /* Process Rx ring next */
2047 processed = xgbe_rx_poll(channel, budget);
2048
2049 /* If we processed everything, we are done */
2050 if (processed < budget) {
2051 /* Turn off polling */
2052 napi_complete_done(napi, processed);
2053
2054 /* Enable Tx and Rx interrupts */
2055 enable_irq(channel->dma_irq);
2056 }
2057
2058 DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2059
2060 return processed;
2061 }
2062
2063 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2064 {
2065 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2066 napi);
2067 struct xgbe_channel *channel;
2068 int ring_budget;
2069 int processed, last_processed;
2070 unsigned int i;
2071
2072 DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2073
2074 processed = 0;
2075 ring_budget = budget / pdata->rx_ring_count;
2076 do {
2077 last_processed = processed;
2078
2079 channel = pdata->channel;
2080 for (i = 0; i < pdata->channel_count; i++, channel++) {
2081 /* Cleanup Tx ring first */
2082 xgbe_tx_poll(channel);
2083
2084 /* Process Rx ring next */
2085 if (ring_budget > (budget - processed))
2086 ring_budget = budget - processed;
2087 processed += xgbe_rx_poll(channel, ring_budget);
2088 }
2089 } while ((processed < budget) && (processed != last_processed));
2090
2091 /* If we processed everything, we are done */
2092 if (processed < budget) {
2093 /* Turn off polling */
2094 napi_complete_done(napi, processed);
2095
2096 /* Enable Tx and Rx interrupts */
2097 xgbe_enable_rx_tx_ints(pdata);
2098 }
2099
2100 DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2101
2102 return processed;
2103 }
2104
2105 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2106 unsigned int idx, unsigned int count, unsigned int flag)
2107 {
2108 struct xgbe_ring_data *rdata;
2109 struct xgbe_ring_desc *rdesc;
2110
2111 while (count--) {
2112 rdata = XGBE_GET_DESC_DATA(ring, idx);
2113 rdesc = rdata->rdesc;
2114 netdev_dbg(pdata->netdev,
2115 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2116 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2117 le32_to_cpu(rdesc->desc0),
2118 le32_to_cpu(rdesc->desc1),
2119 le32_to_cpu(rdesc->desc2),
2120 le32_to_cpu(rdesc->desc3));
2121 idx++;
2122 }
2123 }
2124
2125 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2126 unsigned int idx)
2127 {
2128 struct xgbe_ring_data *rdata;
2129 struct xgbe_ring_desc *rdesc;
2130
2131 rdata = XGBE_GET_DESC_DATA(ring, idx);
2132 rdesc = rdata->rdesc;
2133 netdev_dbg(pdata->netdev,
2134 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2135 idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2136 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2137 }
2138
2139 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2140 {
2141 struct ethhdr *eth = (struct ethhdr *)skb->data;
2142 unsigned char *buf = skb->data;
2143 unsigned char buffer[128];
2144 unsigned int i, j;
2145
2146 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2147
2148 netdev_dbg(netdev, "%s packet of %d bytes\n",
2149 (tx_rx ? "TX" : "RX"), skb->len);
2150
2151 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2152 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2153 netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
2154
2155 for (i = 0, j = 0; i < skb->len;) {
2156 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx",
2157 buf[i++]);
2158
2159 if ((i % 32) == 0) {
2160 netdev_dbg(netdev, " %#06x: %s\n", i - 32, buffer);
2161 j = 0;
2162 } else if ((i % 16) == 0) {
2163 buffer[j++] = ' ';
2164 buffer[j++] = ' ';
2165 } else if ((i % 4) == 0) {
2166 buffer[j++] = ' ';
2167 }
2168 }
2169 if (i % 32)
2170 netdev_dbg(netdev, " %#06x: %s\n", i - (i % 32), buffer);
2171
2172 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2173 }
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git