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Merge tag 'batadv-next-for-davem-20161108-v2' of git://git.open-mesh.org/linux-merge
[thirdparty/kernel/stable.git] / drivers / net / ethernet / amd / xgbe / xgbe-drv.c
1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/spinlock.h>
118 #include <linux/tcp.h>
119 #include <linux/if_vlan.h>
120 #include <net/busy_poll.h>
121 #include <linux/clk.h>
122 #include <linux/if_ether.h>
123 #include <linux/net_tstamp.h>
124 #include <linux/phy.h>
125
126 #include "xgbe.h"
127 #include "xgbe-common.h"
128
129 static int xgbe_one_poll(struct napi_struct *, int);
130 static int xgbe_all_poll(struct napi_struct *, int);
131
132 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
133 {
134 struct xgbe_channel *channel_mem, *channel;
135 struct xgbe_ring *tx_ring, *rx_ring;
136 unsigned int count, i;
137 int ret = -ENOMEM;
138
139 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
140
141 channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL);
142 if (!channel_mem)
143 goto err_channel;
144
145 tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring),
146 GFP_KERNEL);
147 if (!tx_ring)
148 goto err_tx_ring;
149
150 rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring),
151 GFP_KERNEL);
152 if (!rx_ring)
153 goto err_rx_ring;
154
155 for (i = 0, channel = channel_mem; i < count; i++, channel++) {
156 snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
157 channel->pdata = pdata;
158 channel->queue_index = i;
159 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
160 (DMA_CH_INC * i);
161
162 if (pdata->per_channel_irq)
163 channel->dma_irq = pdata->channel_irq[i];
164
165 if (i < pdata->tx_ring_count) {
166 spin_lock_init(&tx_ring->lock);
167 channel->tx_ring = tx_ring++;
168 }
169
170 if (i < pdata->rx_ring_count) {
171 spin_lock_init(&rx_ring->lock);
172 channel->rx_ring = rx_ring++;
173 }
174
175 netif_dbg(pdata, drv, pdata->netdev,
176 "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
177 channel->name, channel->dma_regs, channel->dma_irq,
178 channel->tx_ring, channel->rx_ring);
179 }
180
181 pdata->channel = channel_mem;
182 pdata->channel_count = count;
183
184 return 0;
185
186 err_rx_ring:
187 kfree(tx_ring);
188
189 err_tx_ring:
190 kfree(channel_mem);
191
192 err_channel:
193 return ret;
194 }
195
196 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
197 {
198 if (!pdata->channel)
199 return;
200
201 kfree(pdata->channel->rx_ring);
202 kfree(pdata->channel->tx_ring);
203 kfree(pdata->channel);
204
205 pdata->channel = NULL;
206 pdata->channel_count = 0;
207 }
208
209 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
210 {
211 return (ring->rdesc_count - (ring->cur - ring->dirty));
212 }
213
214 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
215 {
216 return (ring->cur - ring->dirty);
217 }
218
219 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
220 struct xgbe_ring *ring, unsigned int count)
221 {
222 struct xgbe_prv_data *pdata = channel->pdata;
223
224 if (count > xgbe_tx_avail_desc(ring)) {
225 netif_info(pdata, drv, pdata->netdev,
226 "Tx queue stopped, not enough descriptors available\n");
227 netif_stop_subqueue(pdata->netdev, channel->queue_index);
228 ring->tx.queue_stopped = 1;
229
230 /* If we haven't notified the hardware because of xmit_more
231 * support, tell it now
232 */
233 if (ring->tx.xmit_more)
234 pdata->hw_if.tx_start_xmit(channel, ring);
235
236 return NETDEV_TX_BUSY;
237 }
238
239 return 0;
240 }
241
242 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
243 {
244 unsigned int rx_buf_size;
245
246 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
247 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
248
249 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
250 ~(XGBE_RX_BUF_ALIGN - 1);
251
252 return rx_buf_size;
253 }
254
255 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
256 {
257 struct xgbe_hw_if *hw_if = &pdata->hw_if;
258 struct xgbe_channel *channel;
259 enum xgbe_int int_id;
260 unsigned int i;
261
262 channel = pdata->channel;
263 for (i = 0; i < pdata->channel_count; i++, channel++) {
264 if (channel->tx_ring && channel->rx_ring)
265 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
266 else if (channel->tx_ring)
267 int_id = XGMAC_INT_DMA_CH_SR_TI;
268 else if (channel->rx_ring)
269 int_id = XGMAC_INT_DMA_CH_SR_RI;
270 else
271 continue;
272
273 hw_if->enable_int(channel, int_id);
274 }
275 }
276
277 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
278 {
279 struct xgbe_hw_if *hw_if = &pdata->hw_if;
280 struct xgbe_channel *channel;
281 enum xgbe_int int_id;
282 unsigned int i;
283
284 channel = pdata->channel;
285 for (i = 0; i < pdata->channel_count; i++, channel++) {
286 if (channel->tx_ring && channel->rx_ring)
287 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
288 else if (channel->tx_ring)
289 int_id = XGMAC_INT_DMA_CH_SR_TI;
290 else if (channel->rx_ring)
291 int_id = XGMAC_INT_DMA_CH_SR_RI;
292 else
293 continue;
294
295 hw_if->disable_int(channel, int_id);
296 }
297 }
298
299 static irqreturn_t xgbe_isr(int irq, void *data)
300 {
301 struct xgbe_prv_data *pdata = data;
302 struct xgbe_hw_if *hw_if = &pdata->hw_if;
303 struct xgbe_channel *channel;
304 unsigned int dma_isr, dma_ch_isr;
305 unsigned int mac_isr, mac_tssr;
306 unsigned int i;
307
308 /* The DMA interrupt status register also reports MAC and MTL
309 * interrupts. So for polling mode, we just need to check for
310 * this register to be non-zero
311 */
312 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
313 if (!dma_isr)
314 goto isr_done;
315
316 netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
317
318 for (i = 0; i < pdata->channel_count; i++) {
319 if (!(dma_isr & (1 << i)))
320 continue;
321
322 channel = pdata->channel + i;
323
324 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
325 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
326 i, dma_ch_isr);
327
328 /* The TI or RI interrupt bits may still be set even if using
329 * per channel DMA interrupts. Check to be sure those are not
330 * enabled before using the private data napi structure.
331 */
332 if (!pdata->per_channel_irq &&
333 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
334 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
335 if (napi_schedule_prep(&pdata->napi)) {
336 /* Disable Tx and Rx interrupts */
337 xgbe_disable_rx_tx_ints(pdata);
338
339 /* Turn on polling */
340 __napi_schedule_irqoff(&pdata->napi);
341 }
342 }
343
344 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
345 pdata->ext_stats.rx_buffer_unavailable++;
346
347 /* Restart the device on a Fatal Bus Error */
348 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
349 schedule_work(&pdata->restart_work);
350
351 /* Clear all interrupt signals */
352 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
353 }
354
355 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
356 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
357
358 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
359 hw_if->tx_mmc_int(pdata);
360
361 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
362 hw_if->rx_mmc_int(pdata);
363
364 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
365 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
366
367 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
368 /* Read Tx Timestamp to clear interrupt */
369 pdata->tx_tstamp =
370 hw_if->get_tx_tstamp(pdata);
371 queue_work(pdata->dev_workqueue,
372 &pdata->tx_tstamp_work);
373 }
374 }
375 }
376
377 isr_done:
378 return IRQ_HANDLED;
379 }
380
381 static irqreturn_t xgbe_dma_isr(int irq, void *data)
382 {
383 struct xgbe_channel *channel = data;
384
385 /* Per channel DMA interrupts are enabled, so we use the per
386 * channel napi structure and not the private data napi structure
387 */
388 if (napi_schedule_prep(&channel->napi)) {
389 /* Disable Tx and Rx interrupts */
390 disable_irq_nosync(channel->dma_irq);
391
392 /* Turn on polling */
393 __napi_schedule_irqoff(&channel->napi);
394 }
395
396 return IRQ_HANDLED;
397 }
398
399 static void xgbe_tx_timer(unsigned long data)
400 {
401 struct xgbe_channel *channel = (struct xgbe_channel *)data;
402 struct xgbe_prv_data *pdata = channel->pdata;
403 struct napi_struct *napi;
404
405 DBGPR("-->xgbe_tx_timer\n");
406
407 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
408
409 if (napi_schedule_prep(napi)) {
410 /* Disable Tx and Rx interrupts */
411 if (pdata->per_channel_irq)
412 disable_irq_nosync(channel->dma_irq);
413 else
414 xgbe_disable_rx_tx_ints(pdata);
415
416 /* Turn on polling */
417 __napi_schedule(napi);
418 }
419
420 channel->tx_timer_active = 0;
421
422 DBGPR("<--xgbe_tx_timer\n");
423 }
424
425 static void xgbe_service(struct work_struct *work)
426 {
427 struct xgbe_prv_data *pdata = container_of(work,
428 struct xgbe_prv_data,
429 service_work);
430
431 pdata->phy_if.phy_status(pdata);
432 }
433
434 static void xgbe_service_timer(unsigned long data)
435 {
436 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
437
438 queue_work(pdata->dev_workqueue, &pdata->service_work);
439
440 mod_timer(&pdata->service_timer, jiffies + HZ);
441 }
442
443 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
444 {
445 struct xgbe_channel *channel;
446 unsigned int i;
447
448 setup_timer(&pdata->service_timer, xgbe_service_timer,
449 (unsigned long)pdata);
450
451 channel = pdata->channel;
452 for (i = 0; i < pdata->channel_count; i++, channel++) {
453 if (!channel->tx_ring)
454 break;
455
456 setup_timer(&channel->tx_timer, xgbe_tx_timer,
457 (unsigned long)channel);
458 }
459 }
460
461 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
462 {
463 mod_timer(&pdata->service_timer, jiffies + HZ);
464 }
465
466 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
467 {
468 struct xgbe_channel *channel;
469 unsigned int i;
470
471 del_timer_sync(&pdata->service_timer);
472
473 channel = pdata->channel;
474 for (i = 0; i < pdata->channel_count; i++, channel++) {
475 if (!channel->tx_ring)
476 break;
477
478 del_timer_sync(&channel->tx_timer);
479 }
480 }
481
482 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
483 {
484 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
485 struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
486
487 DBGPR("-->xgbe_get_all_hw_features\n");
488
489 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
490 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
491 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
492
493 memset(hw_feat, 0, sizeof(*hw_feat));
494
495 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
496
497 /* Hardware feature register 0 */
498 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
499 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
500 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
501 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
502 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
503 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
504 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
505 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
506 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
507 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
508 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
509 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
510 ADDMACADRSEL);
511 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
512 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
513
514 /* Hardware feature register 1 */
515 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
516 RXFIFOSIZE);
517 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
518 TXFIFOSIZE);
519 hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
520 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
521 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
522 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
523 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
524 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
525 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
526 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
527 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
528 HASHTBLSZ);
529 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
530 L3L4FNUM);
531
532 /* Hardware feature register 2 */
533 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
534 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
535 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
536 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
537 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
538 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
539
540 /* Translate the Hash Table size into actual number */
541 switch (hw_feat->hash_table_size) {
542 case 0:
543 break;
544 case 1:
545 hw_feat->hash_table_size = 64;
546 break;
547 case 2:
548 hw_feat->hash_table_size = 128;
549 break;
550 case 3:
551 hw_feat->hash_table_size = 256;
552 break;
553 }
554
555 /* Translate the address width setting into actual number */
556 switch (hw_feat->dma_width) {
557 case 0:
558 hw_feat->dma_width = 32;
559 break;
560 case 1:
561 hw_feat->dma_width = 40;
562 break;
563 case 2:
564 hw_feat->dma_width = 48;
565 break;
566 default:
567 hw_feat->dma_width = 32;
568 }
569
570 /* The Queue, Channel and TC counts are zero based so increment them
571 * to get the actual number
572 */
573 hw_feat->rx_q_cnt++;
574 hw_feat->tx_q_cnt++;
575 hw_feat->rx_ch_cnt++;
576 hw_feat->tx_ch_cnt++;
577 hw_feat->tc_cnt++;
578
579 /* Translate the fifo sizes into actual numbers */
580 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
581 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
582
583 DBGPR("<--xgbe_get_all_hw_features\n");
584 }
585
586 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
587 {
588 struct xgbe_channel *channel;
589 unsigned int i;
590
591 if (pdata->per_channel_irq) {
592 channel = pdata->channel;
593 for (i = 0; i < pdata->channel_count; i++, channel++) {
594 if (add)
595 netif_napi_add(pdata->netdev, &channel->napi,
596 xgbe_one_poll, NAPI_POLL_WEIGHT);
597
598 napi_enable(&channel->napi);
599 }
600 } else {
601 if (add)
602 netif_napi_add(pdata->netdev, &pdata->napi,
603 xgbe_all_poll, NAPI_POLL_WEIGHT);
604
605 napi_enable(&pdata->napi);
606 }
607 }
608
609 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
610 {
611 struct xgbe_channel *channel;
612 unsigned int i;
613
614 if (pdata->per_channel_irq) {
615 channel = pdata->channel;
616 for (i = 0; i < pdata->channel_count; i++, channel++) {
617 napi_disable(&channel->napi);
618
619 if (del)
620 netif_napi_del(&channel->napi);
621 }
622 } else {
623 napi_disable(&pdata->napi);
624
625 if (del)
626 netif_napi_del(&pdata->napi);
627 }
628 }
629
630 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
631 {
632 struct xgbe_channel *channel;
633 struct net_device *netdev = pdata->netdev;
634 unsigned int i;
635 int ret;
636
637 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
638 netdev->name, pdata);
639 if (ret) {
640 netdev_alert(netdev, "error requesting irq %d\n",
641 pdata->dev_irq);
642 return ret;
643 }
644
645 if (!pdata->per_channel_irq)
646 return 0;
647
648 channel = pdata->channel;
649 for (i = 0; i < pdata->channel_count; i++, channel++) {
650 snprintf(channel->dma_irq_name,
651 sizeof(channel->dma_irq_name) - 1,
652 "%s-TxRx-%u", netdev_name(netdev),
653 channel->queue_index);
654
655 ret = devm_request_irq(pdata->dev, channel->dma_irq,
656 xgbe_dma_isr, 0,
657 channel->dma_irq_name, channel);
658 if (ret) {
659 netdev_alert(netdev, "error requesting irq %d\n",
660 channel->dma_irq);
661 goto err_irq;
662 }
663 }
664
665 return 0;
666
667 err_irq:
668 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
669 for (i--, channel--; i < pdata->channel_count; i--, channel--)
670 devm_free_irq(pdata->dev, channel->dma_irq, channel);
671
672 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
673
674 return ret;
675 }
676
677 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
678 {
679 struct xgbe_channel *channel;
680 unsigned int i;
681
682 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
683
684 if (!pdata->per_channel_irq)
685 return;
686
687 channel = pdata->channel;
688 for (i = 0; i < pdata->channel_count; i++, channel++)
689 devm_free_irq(pdata->dev, channel->dma_irq, channel);
690 }
691
692 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
693 {
694 struct xgbe_hw_if *hw_if = &pdata->hw_if;
695
696 DBGPR("-->xgbe_init_tx_coalesce\n");
697
698 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
699 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
700
701 hw_if->config_tx_coalesce(pdata);
702
703 DBGPR("<--xgbe_init_tx_coalesce\n");
704 }
705
706 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
707 {
708 struct xgbe_hw_if *hw_if = &pdata->hw_if;
709
710 DBGPR("-->xgbe_init_rx_coalesce\n");
711
712 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
713 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
714 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
715
716 hw_if->config_rx_coalesce(pdata);
717
718 DBGPR("<--xgbe_init_rx_coalesce\n");
719 }
720
721 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
722 {
723 struct xgbe_desc_if *desc_if = &pdata->desc_if;
724 struct xgbe_channel *channel;
725 struct xgbe_ring *ring;
726 struct xgbe_ring_data *rdata;
727 unsigned int i, j;
728
729 DBGPR("-->xgbe_free_tx_data\n");
730
731 channel = pdata->channel;
732 for (i = 0; i < pdata->channel_count; i++, channel++) {
733 ring = channel->tx_ring;
734 if (!ring)
735 break;
736
737 for (j = 0; j < ring->rdesc_count; j++) {
738 rdata = XGBE_GET_DESC_DATA(ring, j);
739 desc_if->unmap_rdata(pdata, rdata);
740 }
741 }
742
743 DBGPR("<--xgbe_free_tx_data\n");
744 }
745
746 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
747 {
748 struct xgbe_desc_if *desc_if = &pdata->desc_if;
749 struct xgbe_channel *channel;
750 struct xgbe_ring *ring;
751 struct xgbe_ring_data *rdata;
752 unsigned int i, j;
753
754 DBGPR("-->xgbe_free_rx_data\n");
755
756 channel = pdata->channel;
757 for (i = 0; i < pdata->channel_count; i++, channel++) {
758 ring = channel->rx_ring;
759 if (!ring)
760 break;
761
762 for (j = 0; j < ring->rdesc_count; j++) {
763 rdata = XGBE_GET_DESC_DATA(ring, j);
764 desc_if->unmap_rdata(pdata, rdata);
765 }
766 }
767
768 DBGPR("<--xgbe_free_rx_data\n");
769 }
770
771 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
772 {
773 pdata->phy_link = -1;
774 pdata->phy_speed = SPEED_UNKNOWN;
775
776 return pdata->phy_if.phy_reset(pdata);
777 }
778
779 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
780 {
781 struct xgbe_prv_data *pdata = netdev_priv(netdev);
782 struct xgbe_hw_if *hw_if = &pdata->hw_if;
783 unsigned long flags;
784
785 DBGPR("-->xgbe_powerdown\n");
786
787 if (!netif_running(netdev) ||
788 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
789 netdev_alert(netdev, "Device is already powered down\n");
790 DBGPR("<--xgbe_powerdown\n");
791 return -EINVAL;
792 }
793
794 spin_lock_irqsave(&pdata->lock, flags);
795
796 if (caller == XGMAC_DRIVER_CONTEXT)
797 netif_device_detach(netdev);
798
799 netif_tx_stop_all_queues(netdev);
800
801 xgbe_stop_timers(pdata);
802 flush_workqueue(pdata->dev_workqueue);
803
804 hw_if->powerdown_tx(pdata);
805 hw_if->powerdown_rx(pdata);
806
807 xgbe_napi_disable(pdata, 0);
808
809 pdata->power_down = 1;
810
811 spin_unlock_irqrestore(&pdata->lock, flags);
812
813 DBGPR("<--xgbe_powerdown\n");
814
815 return 0;
816 }
817
818 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
819 {
820 struct xgbe_prv_data *pdata = netdev_priv(netdev);
821 struct xgbe_hw_if *hw_if = &pdata->hw_if;
822 unsigned long flags;
823
824 DBGPR("-->xgbe_powerup\n");
825
826 if (!netif_running(netdev) ||
827 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
828 netdev_alert(netdev, "Device is already powered up\n");
829 DBGPR("<--xgbe_powerup\n");
830 return -EINVAL;
831 }
832
833 spin_lock_irqsave(&pdata->lock, flags);
834
835 pdata->power_down = 0;
836
837 xgbe_napi_enable(pdata, 0);
838
839 hw_if->powerup_tx(pdata);
840 hw_if->powerup_rx(pdata);
841
842 if (caller == XGMAC_DRIVER_CONTEXT)
843 netif_device_attach(netdev);
844
845 netif_tx_start_all_queues(netdev);
846
847 xgbe_start_timers(pdata);
848
849 spin_unlock_irqrestore(&pdata->lock, flags);
850
851 DBGPR("<--xgbe_powerup\n");
852
853 return 0;
854 }
855
856 static int xgbe_start(struct xgbe_prv_data *pdata)
857 {
858 struct xgbe_hw_if *hw_if = &pdata->hw_if;
859 struct xgbe_phy_if *phy_if = &pdata->phy_if;
860 struct net_device *netdev = pdata->netdev;
861 int ret;
862
863 DBGPR("-->xgbe_start\n");
864
865 hw_if->init(pdata);
866
867 ret = phy_if->phy_start(pdata);
868 if (ret)
869 goto err_phy;
870
871 xgbe_napi_enable(pdata, 1);
872
873 ret = xgbe_request_irqs(pdata);
874 if (ret)
875 goto err_napi;
876
877 hw_if->enable_tx(pdata);
878 hw_if->enable_rx(pdata);
879
880 netif_tx_start_all_queues(netdev);
881
882 xgbe_start_timers(pdata);
883 queue_work(pdata->dev_workqueue, &pdata->service_work);
884
885 DBGPR("<--xgbe_start\n");
886
887 return 0;
888
889 err_napi:
890 xgbe_napi_disable(pdata, 1);
891
892 phy_if->phy_stop(pdata);
893
894 err_phy:
895 hw_if->exit(pdata);
896
897 return ret;
898 }
899
900 static void xgbe_stop(struct xgbe_prv_data *pdata)
901 {
902 struct xgbe_hw_if *hw_if = &pdata->hw_if;
903 struct xgbe_phy_if *phy_if = &pdata->phy_if;
904 struct xgbe_channel *channel;
905 struct net_device *netdev = pdata->netdev;
906 struct netdev_queue *txq;
907 unsigned int i;
908
909 DBGPR("-->xgbe_stop\n");
910
911 netif_tx_stop_all_queues(netdev);
912
913 xgbe_stop_timers(pdata);
914 flush_workqueue(pdata->dev_workqueue);
915
916 hw_if->disable_tx(pdata);
917 hw_if->disable_rx(pdata);
918
919 xgbe_free_irqs(pdata);
920
921 xgbe_napi_disable(pdata, 1);
922
923 phy_if->phy_stop(pdata);
924
925 hw_if->exit(pdata);
926
927 channel = pdata->channel;
928 for (i = 0; i < pdata->channel_count; i++, channel++) {
929 if (!channel->tx_ring)
930 continue;
931
932 txq = netdev_get_tx_queue(netdev, channel->queue_index);
933 netdev_tx_reset_queue(txq);
934 }
935
936 DBGPR("<--xgbe_stop\n");
937 }
938
939 static void xgbe_restart_dev(struct xgbe_prv_data *pdata)
940 {
941 DBGPR("-->xgbe_restart_dev\n");
942
943 /* If not running, "restart" will happen on open */
944 if (!netif_running(pdata->netdev))
945 return;
946
947 xgbe_stop(pdata);
948
949 xgbe_free_tx_data(pdata);
950 xgbe_free_rx_data(pdata);
951
952 xgbe_start(pdata);
953
954 DBGPR("<--xgbe_restart_dev\n");
955 }
956
957 static void xgbe_restart(struct work_struct *work)
958 {
959 struct xgbe_prv_data *pdata = container_of(work,
960 struct xgbe_prv_data,
961 restart_work);
962
963 rtnl_lock();
964
965 xgbe_restart_dev(pdata);
966
967 rtnl_unlock();
968 }
969
970 static void xgbe_tx_tstamp(struct work_struct *work)
971 {
972 struct xgbe_prv_data *pdata = container_of(work,
973 struct xgbe_prv_data,
974 tx_tstamp_work);
975 struct skb_shared_hwtstamps hwtstamps;
976 u64 nsec;
977 unsigned long flags;
978
979 if (pdata->tx_tstamp) {
980 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
981 pdata->tx_tstamp);
982
983 memset(&hwtstamps, 0, sizeof(hwtstamps));
984 hwtstamps.hwtstamp = ns_to_ktime(nsec);
985 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
986 }
987
988 dev_kfree_skb_any(pdata->tx_tstamp_skb);
989
990 spin_lock_irqsave(&pdata->tstamp_lock, flags);
991 pdata->tx_tstamp_skb = NULL;
992 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
993 }
994
995 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
996 struct ifreq *ifreq)
997 {
998 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
999 sizeof(pdata->tstamp_config)))
1000 return -EFAULT;
1001
1002 return 0;
1003 }
1004
1005 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1006 struct ifreq *ifreq)
1007 {
1008 struct hwtstamp_config config;
1009 unsigned int mac_tscr;
1010
1011 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1012 return -EFAULT;
1013
1014 if (config.flags)
1015 return -EINVAL;
1016
1017 mac_tscr = 0;
1018
1019 switch (config.tx_type) {
1020 case HWTSTAMP_TX_OFF:
1021 break;
1022
1023 case HWTSTAMP_TX_ON:
1024 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1025 break;
1026
1027 default:
1028 return -ERANGE;
1029 }
1030
1031 switch (config.rx_filter) {
1032 case HWTSTAMP_FILTER_NONE:
1033 break;
1034
1035 case HWTSTAMP_FILTER_ALL:
1036 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1037 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1038 break;
1039
1040 /* PTP v2, UDP, any kind of event packet */
1041 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1042 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1043 /* PTP v1, UDP, any kind of event packet */
1044 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1045 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1046 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1047 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1048 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1049 break;
1050
1051 /* PTP v2, UDP, Sync packet */
1052 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1053 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1054 /* PTP v1, UDP, Sync packet */
1055 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1056 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1057 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1058 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1059 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1060 break;
1061
1062 /* PTP v2, UDP, Delay_req packet */
1063 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1064 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1065 /* PTP v1, UDP, Delay_req packet */
1066 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1067 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1068 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1069 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1070 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1071 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1072 break;
1073
1074 /* 802.AS1, Ethernet, any kind of event packet */
1075 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1076 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1077 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1078 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1079 break;
1080
1081 /* 802.AS1, Ethernet, Sync packet */
1082 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1083 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1084 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1085 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1086 break;
1087
1088 /* 802.AS1, Ethernet, Delay_req packet */
1089 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1090 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1091 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1092 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1093 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1094 break;
1095
1096 /* PTP v2/802.AS1, any layer, any kind of event packet */
1097 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1098 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1099 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1100 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1101 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1102 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1103 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1104 break;
1105
1106 /* PTP v2/802.AS1, any layer, Sync packet */
1107 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1108 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1109 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1110 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1111 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1112 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1113 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1114 break;
1115
1116 /* PTP v2/802.AS1, any layer, Delay_req packet */
1117 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1118 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1119 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1120 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1121 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1122 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1123 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1124 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1125 break;
1126
1127 default:
1128 return -ERANGE;
1129 }
1130
1131 pdata->hw_if.config_tstamp(pdata, mac_tscr);
1132
1133 memcpy(&pdata->tstamp_config, &config, sizeof(config));
1134
1135 return 0;
1136 }
1137
1138 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1139 struct sk_buff *skb,
1140 struct xgbe_packet_data *packet)
1141 {
1142 unsigned long flags;
1143
1144 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1145 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1146 if (pdata->tx_tstamp_skb) {
1147 /* Another timestamp in progress, ignore this one */
1148 XGMAC_SET_BITS(packet->attributes,
1149 TX_PACKET_ATTRIBUTES, PTP, 0);
1150 } else {
1151 pdata->tx_tstamp_skb = skb_get(skb);
1152 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1153 }
1154 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1155 }
1156
1157 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1158 skb_tx_timestamp(skb);
1159 }
1160
1161 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1162 {
1163 if (skb_vlan_tag_present(skb))
1164 packet->vlan_ctag = skb_vlan_tag_get(skb);
1165 }
1166
1167 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1168 {
1169 int ret;
1170
1171 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1172 TSO_ENABLE))
1173 return 0;
1174
1175 ret = skb_cow_head(skb, 0);
1176 if (ret)
1177 return ret;
1178
1179 packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1180 packet->tcp_header_len = tcp_hdrlen(skb);
1181 packet->tcp_payload_len = skb->len - packet->header_len;
1182 packet->mss = skb_shinfo(skb)->gso_size;
1183 DBGPR(" packet->header_len=%u\n", packet->header_len);
1184 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1185 packet->tcp_header_len, packet->tcp_payload_len);
1186 DBGPR(" packet->mss=%u\n", packet->mss);
1187
1188 /* Update the number of packets that will ultimately be transmitted
1189 * along with the extra bytes for each extra packet
1190 */
1191 packet->tx_packets = skb_shinfo(skb)->gso_segs;
1192 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1193
1194 return 0;
1195 }
1196
1197 static int xgbe_is_tso(struct sk_buff *skb)
1198 {
1199 if (skb->ip_summed != CHECKSUM_PARTIAL)
1200 return 0;
1201
1202 if (!skb_is_gso(skb))
1203 return 0;
1204
1205 DBGPR(" TSO packet to be processed\n");
1206
1207 return 1;
1208 }
1209
1210 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1211 struct xgbe_ring *ring, struct sk_buff *skb,
1212 struct xgbe_packet_data *packet)
1213 {
1214 struct skb_frag_struct *frag;
1215 unsigned int context_desc;
1216 unsigned int len;
1217 unsigned int i;
1218
1219 packet->skb = skb;
1220
1221 context_desc = 0;
1222 packet->rdesc_count = 0;
1223
1224 packet->tx_packets = 1;
1225 packet->tx_bytes = skb->len;
1226
1227 if (xgbe_is_tso(skb)) {
1228 /* TSO requires an extra descriptor if mss is different */
1229 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1230 context_desc = 1;
1231 packet->rdesc_count++;
1232 }
1233
1234 /* TSO requires an extra descriptor for TSO header */
1235 packet->rdesc_count++;
1236
1237 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1238 TSO_ENABLE, 1);
1239 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1240 CSUM_ENABLE, 1);
1241 } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1242 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1243 CSUM_ENABLE, 1);
1244
1245 if (skb_vlan_tag_present(skb)) {
1246 /* VLAN requires an extra descriptor if tag is different */
1247 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1248 /* We can share with the TSO context descriptor */
1249 if (!context_desc) {
1250 context_desc = 1;
1251 packet->rdesc_count++;
1252 }
1253
1254 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1255 VLAN_CTAG, 1);
1256 }
1257
1258 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1259 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1260 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1261 PTP, 1);
1262
1263 for (len = skb_headlen(skb); len;) {
1264 packet->rdesc_count++;
1265 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1266 }
1267
1268 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1269 frag = &skb_shinfo(skb)->frags[i];
1270 for (len = skb_frag_size(frag); len; ) {
1271 packet->rdesc_count++;
1272 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1273 }
1274 }
1275 }
1276
1277 static int xgbe_open(struct net_device *netdev)
1278 {
1279 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1280 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1281 int ret;
1282
1283 DBGPR("-->xgbe_open\n");
1284
1285 /* Reset the phy settings */
1286 ret = xgbe_phy_reset(pdata);
1287 if (ret)
1288 return ret;
1289
1290 /* Enable the clocks */
1291 ret = clk_prepare_enable(pdata->sysclk);
1292 if (ret) {
1293 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1294 return ret;
1295 }
1296
1297 ret = clk_prepare_enable(pdata->ptpclk);
1298 if (ret) {
1299 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1300 goto err_sysclk;
1301 }
1302
1303 /* Calculate the Rx buffer size before allocating rings */
1304 ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1305 if (ret < 0)
1306 goto err_ptpclk;
1307 pdata->rx_buf_size = ret;
1308
1309 /* Allocate the channel and ring structures */
1310 ret = xgbe_alloc_channels(pdata);
1311 if (ret)
1312 goto err_ptpclk;
1313
1314 /* Allocate the ring descriptors and buffers */
1315 ret = desc_if->alloc_ring_resources(pdata);
1316 if (ret)
1317 goto err_channels;
1318
1319 INIT_WORK(&pdata->service_work, xgbe_service);
1320 INIT_WORK(&pdata->restart_work, xgbe_restart);
1321 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1322 xgbe_init_timers(pdata);
1323
1324 ret = xgbe_start(pdata);
1325 if (ret)
1326 goto err_rings;
1327
1328 clear_bit(XGBE_DOWN, &pdata->dev_state);
1329
1330 DBGPR("<--xgbe_open\n");
1331
1332 return 0;
1333
1334 err_rings:
1335 desc_if->free_ring_resources(pdata);
1336
1337 err_channels:
1338 xgbe_free_channels(pdata);
1339
1340 err_ptpclk:
1341 clk_disable_unprepare(pdata->ptpclk);
1342
1343 err_sysclk:
1344 clk_disable_unprepare(pdata->sysclk);
1345
1346 return ret;
1347 }
1348
1349 static int xgbe_close(struct net_device *netdev)
1350 {
1351 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1352 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1353
1354 DBGPR("-->xgbe_close\n");
1355
1356 /* Stop the device */
1357 xgbe_stop(pdata);
1358
1359 /* Free the ring descriptors and buffers */
1360 desc_if->free_ring_resources(pdata);
1361
1362 /* Free the channel and ring structures */
1363 xgbe_free_channels(pdata);
1364
1365 /* Disable the clocks */
1366 clk_disable_unprepare(pdata->ptpclk);
1367 clk_disable_unprepare(pdata->sysclk);
1368
1369 set_bit(XGBE_DOWN, &pdata->dev_state);
1370
1371 DBGPR("<--xgbe_close\n");
1372
1373 return 0;
1374 }
1375
1376 static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1377 {
1378 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1379 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1380 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1381 struct xgbe_channel *channel;
1382 struct xgbe_ring *ring;
1383 struct xgbe_packet_data *packet;
1384 struct netdev_queue *txq;
1385 int ret;
1386
1387 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1388
1389 channel = pdata->channel + skb->queue_mapping;
1390 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1391 ring = channel->tx_ring;
1392 packet = &ring->packet_data;
1393
1394 ret = NETDEV_TX_OK;
1395
1396 if (skb->len == 0) {
1397 netif_err(pdata, tx_err, netdev,
1398 "empty skb received from stack\n");
1399 dev_kfree_skb_any(skb);
1400 goto tx_netdev_return;
1401 }
1402
1403 /* Calculate preliminary packet info */
1404 memset(packet, 0, sizeof(*packet));
1405 xgbe_packet_info(pdata, ring, skb, packet);
1406
1407 /* Check that there are enough descriptors available */
1408 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1409 if (ret)
1410 goto tx_netdev_return;
1411
1412 ret = xgbe_prep_tso(skb, packet);
1413 if (ret) {
1414 netif_err(pdata, tx_err, netdev,
1415 "error processing TSO packet\n");
1416 dev_kfree_skb_any(skb);
1417 goto tx_netdev_return;
1418 }
1419 xgbe_prep_vlan(skb, packet);
1420
1421 if (!desc_if->map_tx_skb(channel, skb)) {
1422 dev_kfree_skb_any(skb);
1423 goto tx_netdev_return;
1424 }
1425
1426 xgbe_prep_tx_tstamp(pdata, skb, packet);
1427
1428 /* Report on the actual number of bytes (to be) sent */
1429 netdev_tx_sent_queue(txq, packet->tx_bytes);
1430
1431 /* Configure required descriptor fields for transmission */
1432 hw_if->dev_xmit(channel);
1433
1434 if (netif_msg_pktdata(pdata))
1435 xgbe_print_pkt(netdev, skb, true);
1436
1437 /* Stop the queue in advance if there may not be enough descriptors */
1438 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
1439
1440 ret = NETDEV_TX_OK;
1441
1442 tx_netdev_return:
1443 return ret;
1444 }
1445
1446 static void xgbe_set_rx_mode(struct net_device *netdev)
1447 {
1448 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1449 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1450
1451 DBGPR("-->xgbe_set_rx_mode\n");
1452
1453 hw_if->config_rx_mode(pdata);
1454
1455 DBGPR("<--xgbe_set_rx_mode\n");
1456 }
1457
1458 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
1459 {
1460 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1461 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1462 struct sockaddr *saddr = addr;
1463
1464 DBGPR("-->xgbe_set_mac_address\n");
1465
1466 if (!is_valid_ether_addr(saddr->sa_data))
1467 return -EADDRNOTAVAIL;
1468
1469 memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
1470
1471 hw_if->set_mac_address(pdata, netdev->dev_addr);
1472
1473 DBGPR("<--xgbe_set_mac_address\n");
1474
1475 return 0;
1476 }
1477
1478 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
1479 {
1480 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1481 int ret;
1482
1483 switch (cmd) {
1484 case SIOCGHWTSTAMP:
1485 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
1486 break;
1487
1488 case SIOCSHWTSTAMP:
1489 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
1490 break;
1491
1492 default:
1493 ret = -EOPNOTSUPP;
1494 }
1495
1496 return ret;
1497 }
1498
1499 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
1500 {
1501 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1502 int ret;
1503
1504 DBGPR("-->xgbe_change_mtu\n");
1505
1506 ret = xgbe_calc_rx_buf_size(netdev, mtu);
1507 if (ret < 0)
1508 return ret;
1509
1510 pdata->rx_buf_size = ret;
1511 netdev->mtu = mtu;
1512
1513 xgbe_restart_dev(pdata);
1514
1515 DBGPR("<--xgbe_change_mtu\n");
1516
1517 return 0;
1518 }
1519
1520 static void xgbe_tx_timeout(struct net_device *netdev)
1521 {
1522 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1523
1524 netdev_warn(netdev, "tx timeout, device restarting\n");
1525 schedule_work(&pdata->restart_work);
1526 }
1527
1528 static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev,
1529 struct rtnl_link_stats64 *s)
1530 {
1531 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1532 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
1533
1534 DBGPR("-->%s\n", __func__);
1535
1536 pdata->hw_if.read_mmc_stats(pdata);
1537
1538 s->rx_packets = pstats->rxframecount_gb;
1539 s->rx_bytes = pstats->rxoctetcount_gb;
1540 s->rx_errors = pstats->rxframecount_gb -
1541 pstats->rxbroadcastframes_g -
1542 pstats->rxmulticastframes_g -
1543 pstats->rxunicastframes_g;
1544 s->multicast = pstats->rxmulticastframes_g;
1545 s->rx_length_errors = pstats->rxlengtherror;
1546 s->rx_crc_errors = pstats->rxcrcerror;
1547 s->rx_fifo_errors = pstats->rxfifooverflow;
1548
1549 s->tx_packets = pstats->txframecount_gb;
1550 s->tx_bytes = pstats->txoctetcount_gb;
1551 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
1552 s->tx_dropped = netdev->stats.tx_dropped;
1553
1554 DBGPR("<--%s\n", __func__);
1555
1556 return s;
1557 }
1558
1559 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1560 u16 vid)
1561 {
1562 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1563 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1564
1565 DBGPR("-->%s\n", __func__);
1566
1567 set_bit(vid, pdata->active_vlans);
1568 hw_if->update_vlan_hash_table(pdata);
1569
1570 DBGPR("<--%s\n", __func__);
1571
1572 return 0;
1573 }
1574
1575 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1576 u16 vid)
1577 {
1578 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1579 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1580
1581 DBGPR("-->%s\n", __func__);
1582
1583 clear_bit(vid, pdata->active_vlans);
1584 hw_if->update_vlan_hash_table(pdata);
1585
1586 DBGPR("<--%s\n", __func__);
1587
1588 return 0;
1589 }
1590
1591 #ifdef CONFIG_NET_POLL_CONTROLLER
1592 static void xgbe_poll_controller(struct net_device *netdev)
1593 {
1594 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1595 struct xgbe_channel *channel;
1596 unsigned int i;
1597
1598 DBGPR("-->xgbe_poll_controller\n");
1599
1600 if (pdata->per_channel_irq) {
1601 channel = pdata->channel;
1602 for (i = 0; i < pdata->channel_count; i++, channel++)
1603 xgbe_dma_isr(channel->dma_irq, channel);
1604 } else {
1605 disable_irq(pdata->dev_irq);
1606 xgbe_isr(pdata->dev_irq, pdata);
1607 enable_irq(pdata->dev_irq);
1608 }
1609
1610 DBGPR("<--xgbe_poll_controller\n");
1611 }
1612 #endif /* End CONFIG_NET_POLL_CONTROLLER */
1613
1614 static int xgbe_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
1615 struct tc_to_netdev *tc_to_netdev)
1616 {
1617 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1618 u8 tc;
1619
1620 if (tc_to_netdev->type != TC_SETUP_MQPRIO)
1621 return -EINVAL;
1622
1623 tc = tc_to_netdev->tc;
1624
1625 if (tc > pdata->hw_feat.tc_cnt)
1626 return -EINVAL;
1627
1628 pdata->num_tcs = tc;
1629 pdata->hw_if.config_tc(pdata);
1630
1631 return 0;
1632 }
1633
1634 static int xgbe_set_features(struct net_device *netdev,
1635 netdev_features_t features)
1636 {
1637 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1638 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1639 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
1640 int ret = 0;
1641
1642 rxhash = pdata->netdev_features & NETIF_F_RXHASH;
1643 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
1644 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
1645 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
1646
1647 if ((features & NETIF_F_RXHASH) && !rxhash)
1648 ret = hw_if->enable_rss(pdata);
1649 else if (!(features & NETIF_F_RXHASH) && rxhash)
1650 ret = hw_if->disable_rss(pdata);
1651 if (ret)
1652 return ret;
1653
1654 if ((features & NETIF_F_RXCSUM) && !rxcsum)
1655 hw_if->enable_rx_csum(pdata);
1656 else if (!(features & NETIF_F_RXCSUM) && rxcsum)
1657 hw_if->disable_rx_csum(pdata);
1658
1659 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
1660 hw_if->enable_rx_vlan_stripping(pdata);
1661 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
1662 hw_if->disable_rx_vlan_stripping(pdata);
1663
1664 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
1665 hw_if->enable_rx_vlan_filtering(pdata);
1666 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
1667 hw_if->disable_rx_vlan_filtering(pdata);
1668
1669 pdata->netdev_features = features;
1670
1671 DBGPR("<--xgbe_set_features\n");
1672
1673 return 0;
1674 }
1675
1676 static const struct net_device_ops xgbe_netdev_ops = {
1677 .ndo_open = xgbe_open,
1678 .ndo_stop = xgbe_close,
1679 .ndo_start_xmit = xgbe_xmit,
1680 .ndo_set_rx_mode = xgbe_set_rx_mode,
1681 .ndo_set_mac_address = xgbe_set_mac_address,
1682 .ndo_validate_addr = eth_validate_addr,
1683 .ndo_do_ioctl = xgbe_ioctl,
1684 .ndo_change_mtu = xgbe_change_mtu,
1685 .ndo_tx_timeout = xgbe_tx_timeout,
1686 .ndo_get_stats64 = xgbe_get_stats64,
1687 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid,
1688 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid,
1689 #ifdef CONFIG_NET_POLL_CONTROLLER
1690 .ndo_poll_controller = xgbe_poll_controller,
1691 #endif
1692 .ndo_setup_tc = xgbe_setup_tc,
1693 .ndo_set_features = xgbe_set_features,
1694 };
1695
1696 const struct net_device_ops *xgbe_get_netdev_ops(void)
1697 {
1698 return &xgbe_netdev_ops;
1699 }
1700
1701 static void xgbe_rx_refresh(struct xgbe_channel *channel)
1702 {
1703 struct xgbe_prv_data *pdata = channel->pdata;
1704 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1705 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1706 struct xgbe_ring *ring = channel->rx_ring;
1707 struct xgbe_ring_data *rdata;
1708
1709 while (ring->dirty != ring->cur) {
1710 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
1711
1712 /* Reset rdata values */
1713 desc_if->unmap_rdata(pdata, rdata);
1714
1715 if (desc_if->map_rx_buffer(pdata, ring, rdata))
1716 break;
1717
1718 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
1719
1720 ring->dirty++;
1721 }
1722
1723 /* Make sure everything is written before the register write */
1724 wmb();
1725
1726 /* Update the Rx Tail Pointer Register with address of
1727 * the last cleaned entry */
1728 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
1729 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1730 lower_32_bits(rdata->rdesc_dma));
1731 }
1732
1733 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
1734 struct napi_struct *napi,
1735 struct xgbe_ring_data *rdata,
1736 unsigned int len)
1737 {
1738 struct sk_buff *skb;
1739 u8 *packet;
1740 unsigned int copy_len;
1741
1742 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
1743 if (!skb)
1744 return NULL;
1745
1746 /* Start with the header buffer which may contain just the header
1747 * or the header plus data
1748 */
1749 dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
1750 rdata->rx.hdr.dma_off,
1751 rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
1752
1753 packet = page_address(rdata->rx.hdr.pa.pages) +
1754 rdata->rx.hdr.pa.pages_offset;
1755 copy_len = (rdata->rx.hdr_len) ? rdata->rx.hdr_len : len;
1756 copy_len = min(rdata->rx.hdr.dma_len, copy_len);
1757 skb_copy_to_linear_data(skb, packet, copy_len);
1758 skb_put(skb, copy_len);
1759
1760 len -= copy_len;
1761 if (len) {
1762 /* Add the remaining data as a frag */
1763 dma_sync_single_range_for_cpu(pdata->dev,
1764 rdata->rx.buf.dma_base,
1765 rdata->rx.buf.dma_off,
1766 rdata->rx.buf.dma_len,
1767 DMA_FROM_DEVICE);
1768
1769 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1770 rdata->rx.buf.pa.pages,
1771 rdata->rx.buf.pa.pages_offset,
1772 len, rdata->rx.buf.dma_len);
1773 rdata->rx.buf.pa.pages = NULL;
1774 }
1775
1776 return skb;
1777 }
1778
1779 static int xgbe_tx_poll(struct xgbe_channel *channel)
1780 {
1781 struct xgbe_prv_data *pdata = channel->pdata;
1782 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1783 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1784 struct xgbe_ring *ring = channel->tx_ring;
1785 struct xgbe_ring_data *rdata;
1786 struct xgbe_ring_desc *rdesc;
1787 struct net_device *netdev = pdata->netdev;
1788 struct netdev_queue *txq;
1789 int processed = 0;
1790 unsigned int tx_packets = 0, tx_bytes = 0;
1791 unsigned int cur;
1792
1793 DBGPR("-->xgbe_tx_poll\n");
1794
1795 /* Nothing to do if there isn't a Tx ring for this channel */
1796 if (!ring)
1797 return 0;
1798
1799 cur = ring->cur;
1800
1801 /* Be sure we get ring->cur before accessing descriptor data */
1802 smp_rmb();
1803
1804 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1805
1806 while ((processed < XGBE_TX_DESC_MAX_PROC) &&
1807 (ring->dirty != cur)) {
1808 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
1809 rdesc = rdata->rdesc;
1810
1811 if (!hw_if->tx_complete(rdesc))
1812 break;
1813
1814 /* Make sure descriptor fields are read after reading the OWN
1815 * bit */
1816 dma_rmb();
1817
1818 if (netif_msg_tx_done(pdata))
1819 xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
1820
1821 if (hw_if->is_last_desc(rdesc)) {
1822 tx_packets += rdata->tx.packets;
1823 tx_bytes += rdata->tx.bytes;
1824 }
1825
1826 /* Free the SKB and reset the descriptor for re-use */
1827 desc_if->unmap_rdata(pdata, rdata);
1828 hw_if->tx_desc_reset(rdata);
1829
1830 processed++;
1831 ring->dirty++;
1832 }
1833
1834 if (!processed)
1835 return 0;
1836
1837 netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
1838
1839 if ((ring->tx.queue_stopped == 1) &&
1840 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
1841 ring->tx.queue_stopped = 0;
1842 netif_tx_wake_queue(txq);
1843 }
1844
1845 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
1846
1847 return processed;
1848 }
1849
1850 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
1851 {
1852 struct xgbe_prv_data *pdata = channel->pdata;
1853 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1854 struct xgbe_ring *ring = channel->rx_ring;
1855 struct xgbe_ring_data *rdata;
1856 struct xgbe_packet_data *packet;
1857 struct net_device *netdev = pdata->netdev;
1858 struct napi_struct *napi;
1859 struct sk_buff *skb;
1860 struct skb_shared_hwtstamps *hwtstamps;
1861 unsigned int incomplete, error, context_next, context;
1862 unsigned int len, rdesc_len, max_len;
1863 unsigned int received = 0;
1864 int packet_count = 0;
1865
1866 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
1867
1868 /* Nothing to do if there isn't a Rx ring for this channel */
1869 if (!ring)
1870 return 0;
1871
1872 incomplete = 0;
1873 context_next = 0;
1874
1875 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
1876
1877 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1878 packet = &ring->packet_data;
1879 while (packet_count < budget) {
1880 DBGPR(" cur = %d\n", ring->cur);
1881
1882 /* First time in loop see if we need to restore state */
1883 if (!received && rdata->state_saved) {
1884 skb = rdata->state.skb;
1885 error = rdata->state.error;
1886 len = rdata->state.len;
1887 } else {
1888 memset(packet, 0, sizeof(*packet));
1889 skb = NULL;
1890 error = 0;
1891 len = 0;
1892 }
1893
1894 read_again:
1895 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1896
1897 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
1898 xgbe_rx_refresh(channel);
1899
1900 if (hw_if->dev_read(channel))
1901 break;
1902
1903 received++;
1904 ring->cur++;
1905
1906 incomplete = XGMAC_GET_BITS(packet->attributes,
1907 RX_PACKET_ATTRIBUTES,
1908 INCOMPLETE);
1909 context_next = XGMAC_GET_BITS(packet->attributes,
1910 RX_PACKET_ATTRIBUTES,
1911 CONTEXT_NEXT);
1912 context = XGMAC_GET_BITS(packet->attributes,
1913 RX_PACKET_ATTRIBUTES,
1914 CONTEXT);
1915
1916 /* Earlier error, just drain the remaining data */
1917 if ((incomplete || context_next) && error)
1918 goto read_again;
1919
1920 if (error || packet->errors) {
1921 if (packet->errors)
1922 netif_err(pdata, rx_err, netdev,
1923 "error in received packet\n");
1924 dev_kfree_skb(skb);
1925 goto next_packet;
1926 }
1927
1928 if (!context) {
1929 /* Length is cumulative, get this descriptor's length */
1930 rdesc_len = rdata->rx.len - len;
1931 len += rdesc_len;
1932
1933 if (rdesc_len && !skb) {
1934 skb = xgbe_create_skb(pdata, napi, rdata,
1935 rdesc_len);
1936 if (!skb)
1937 error = 1;
1938 } else if (rdesc_len) {
1939 dma_sync_single_range_for_cpu(pdata->dev,
1940 rdata->rx.buf.dma_base,
1941 rdata->rx.buf.dma_off,
1942 rdata->rx.buf.dma_len,
1943 DMA_FROM_DEVICE);
1944
1945 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1946 rdata->rx.buf.pa.pages,
1947 rdata->rx.buf.pa.pages_offset,
1948 rdesc_len,
1949 rdata->rx.buf.dma_len);
1950 rdata->rx.buf.pa.pages = NULL;
1951 }
1952 }
1953
1954 if (incomplete || context_next)
1955 goto read_again;
1956
1957 if (!skb)
1958 goto next_packet;
1959
1960 /* Be sure we don't exceed the configured MTU */
1961 max_len = netdev->mtu + ETH_HLEN;
1962 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1963 (skb->protocol == htons(ETH_P_8021Q)))
1964 max_len += VLAN_HLEN;
1965
1966 if (skb->len > max_len) {
1967 netif_err(pdata, rx_err, netdev,
1968 "packet length exceeds configured MTU\n");
1969 dev_kfree_skb(skb);
1970 goto next_packet;
1971 }
1972
1973 if (netif_msg_pktdata(pdata))
1974 xgbe_print_pkt(netdev, skb, false);
1975
1976 skb_checksum_none_assert(skb);
1977 if (XGMAC_GET_BITS(packet->attributes,
1978 RX_PACKET_ATTRIBUTES, CSUM_DONE))
1979 skb->ip_summed = CHECKSUM_UNNECESSARY;
1980
1981 if (XGMAC_GET_BITS(packet->attributes,
1982 RX_PACKET_ATTRIBUTES, VLAN_CTAG))
1983 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1984 packet->vlan_ctag);
1985
1986 if (XGMAC_GET_BITS(packet->attributes,
1987 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
1988 u64 nsec;
1989
1990 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1991 packet->rx_tstamp);
1992 hwtstamps = skb_hwtstamps(skb);
1993 hwtstamps->hwtstamp = ns_to_ktime(nsec);
1994 }
1995
1996 if (XGMAC_GET_BITS(packet->attributes,
1997 RX_PACKET_ATTRIBUTES, RSS_HASH))
1998 skb_set_hash(skb, packet->rss_hash,
1999 packet->rss_hash_type);
2000
2001 skb->dev = netdev;
2002 skb->protocol = eth_type_trans(skb, netdev);
2003 skb_record_rx_queue(skb, channel->queue_index);
2004
2005 napi_gro_receive(napi, skb);
2006
2007 next_packet:
2008 packet_count++;
2009 }
2010
2011 /* Check if we need to save state before leaving */
2012 if (received && (incomplete || context_next)) {
2013 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2014 rdata->state_saved = 1;
2015 rdata->state.skb = skb;
2016 rdata->state.len = len;
2017 rdata->state.error = error;
2018 }
2019
2020 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2021
2022 return packet_count;
2023 }
2024
2025 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2026 {
2027 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2028 napi);
2029 int processed = 0;
2030
2031 DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2032
2033 /* Cleanup Tx ring first */
2034 xgbe_tx_poll(channel);
2035
2036 /* Process Rx ring next */
2037 processed = xgbe_rx_poll(channel, budget);
2038
2039 /* If we processed everything, we are done */
2040 if (processed < budget) {
2041 /* Turn off polling */
2042 napi_complete_done(napi, processed);
2043
2044 /* Enable Tx and Rx interrupts */
2045 enable_irq(channel->dma_irq);
2046 }
2047
2048 DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2049
2050 return processed;
2051 }
2052
2053 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2054 {
2055 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2056 napi);
2057 struct xgbe_channel *channel;
2058 int ring_budget;
2059 int processed, last_processed;
2060 unsigned int i;
2061
2062 DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2063
2064 processed = 0;
2065 ring_budget = budget / pdata->rx_ring_count;
2066 do {
2067 last_processed = processed;
2068
2069 channel = pdata->channel;
2070 for (i = 0; i < pdata->channel_count; i++, channel++) {
2071 /* Cleanup Tx ring first */
2072 xgbe_tx_poll(channel);
2073
2074 /* Process Rx ring next */
2075 if (ring_budget > (budget - processed))
2076 ring_budget = budget - processed;
2077 processed += xgbe_rx_poll(channel, ring_budget);
2078 }
2079 } while ((processed < budget) && (processed != last_processed));
2080
2081 /* If we processed everything, we are done */
2082 if (processed < budget) {
2083 /* Turn off polling */
2084 napi_complete_done(napi, processed);
2085
2086 /* Enable Tx and Rx interrupts */
2087 xgbe_enable_rx_tx_ints(pdata);
2088 }
2089
2090 DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2091
2092 return processed;
2093 }
2094
2095 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2096 unsigned int idx, unsigned int count, unsigned int flag)
2097 {
2098 struct xgbe_ring_data *rdata;
2099 struct xgbe_ring_desc *rdesc;
2100
2101 while (count--) {
2102 rdata = XGBE_GET_DESC_DATA(ring, idx);
2103 rdesc = rdata->rdesc;
2104 netdev_dbg(pdata->netdev,
2105 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2106 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2107 le32_to_cpu(rdesc->desc0),
2108 le32_to_cpu(rdesc->desc1),
2109 le32_to_cpu(rdesc->desc2),
2110 le32_to_cpu(rdesc->desc3));
2111 idx++;
2112 }
2113 }
2114
2115 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2116 unsigned int idx)
2117 {
2118 struct xgbe_ring_data *rdata;
2119 struct xgbe_ring_desc *rdesc;
2120
2121 rdata = XGBE_GET_DESC_DATA(ring, idx);
2122 rdesc = rdata->rdesc;
2123 netdev_dbg(pdata->netdev,
2124 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2125 idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2126 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2127 }
2128
2129 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2130 {
2131 struct ethhdr *eth = (struct ethhdr *)skb->data;
2132 unsigned char *buf = skb->data;
2133 unsigned char buffer[128];
2134 unsigned int i, j;
2135
2136 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2137
2138 netdev_dbg(netdev, "%s packet of %d bytes\n",
2139 (tx_rx ? "TX" : "RX"), skb->len);
2140
2141 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2142 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2143 netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
2144
2145 for (i = 0, j = 0; i < skb->len;) {
2146 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx",
2147 buf[i++]);
2148
2149 if ((i % 32) == 0) {
2150 netdev_dbg(netdev, " %#06x: %s\n", i - 32, buffer);
2151 j = 0;
2152 } else if ((i % 16) == 0) {
2153 buffer[j++] = ' ';
2154 buffer[j++] = ' ';
2155 } else if ((i % 4) == 0) {
2156 buffer[j++] = ' ';
2157 }
2158 }
2159 if (i % 32)
2160 netdev_dbg(netdev, " %#06x: %s\n", i - (i % 32), buffer);
2161
2162 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2163 }
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git