drivers/net/ethernet/amd/xgbe/xgbe-main.c

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #include <linux/module.h>
 118 #include <linux/device.h>
 119 #include <linux/spinlock.h>
 120 #include <linux/netdevice.h>
 121 #include <linux/etherdevice.h>
 122 #include <linux/io.h>
 123
 124 #include "xgbe.h"
 125 #include "xgbe-common.h"
 126
 127 MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
 128 MODULE_LICENSE("Dual BSD/GPL");
 129 MODULE_VERSION(XGBE_DRV_VERSION);
 130 MODULE_DESCRIPTION(XGBE_DRV_DESC);
 131
 132 static int debug = -1;
 133 module_param(debug, int, S_IWUSR | S_IRUGO);
 134 MODULE_PARM_DESC(debug, " Network interface message level setting");
 135
 136 static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
 137                                       NETIF_MSG_IFUP);
 138
 139 static void xgbe_default_config(struct xgbe_prv_data *pdata)
 140 {
 141         DBGPR("-->xgbe_default_config\n");
 142
 143         pdata->pblx8 = DMA_PBL_X8_ENABLE;
 144         pdata->tx_sf_mode = MTL_TSF_ENABLE;
 145         pdata->tx_threshold = MTL_TX_THRESHOLD_64;
 146         pdata->tx_pbl = DMA_PBL_16;
 147         pdata->tx_osp_mode = DMA_OSP_ENABLE;
 148         pdata->rx_sf_mode = MTL_RSF_DISABLE;
 149         pdata->rx_threshold = MTL_RX_THRESHOLD_64;
 150         pdata->rx_pbl = DMA_PBL_16;
 151         pdata->pause_autoneg = 1;
 152         pdata->tx_pause = 1;
 153         pdata->rx_pause = 1;
 154         pdata->phy_speed = SPEED_UNKNOWN;
 155         pdata->power_down = 0;
 156
 157         DBGPR("<--xgbe_default_config\n");
 158 }
 159
 160 static void xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
 161 {
 162         xgbe_init_function_ptrs_dev(&pdata->hw_if);
 163         xgbe_init_function_ptrs_phy(&pdata->phy_if);
 164         xgbe_init_function_ptrs_desc(&pdata->desc_if);
 165
 166         pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
 167 }
 168
 169 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *dev)
 170 {
 171         struct xgbe_prv_data *pdata;
 172         struct net_device *netdev;
 173
 174         netdev = alloc_etherdev_mq(sizeof(struct xgbe_prv_data),
 175                                    XGBE_MAX_DMA_CHANNELS);
 176         if (!netdev) {
 177                 dev_err(dev, "alloc_etherdev_mq failed\n");
 178                 return ERR_PTR(-ENOMEM);
 179         }
 180         SET_NETDEV_DEV(netdev, dev);
 181         pdata = netdev_priv(netdev);
 182         pdata->netdev = netdev;
 183         pdata->dev = dev;
 184
 185         spin_lock_init(&pdata->lock);
 186         spin_lock_init(&pdata->xpcs_lock);
 187         mutex_init(&pdata->rss_mutex);
 188         spin_lock_init(&pdata->tstamp_lock);
 189
 190         pdata->msg_enable = netif_msg_init(debug, default_msg_level);
 191
 192         set_bit(XGBE_DOWN, &pdata->dev_state);
 193
 194         return pdata;
 195 }
 196
 197 void xgbe_free_pdata(struct xgbe_prv_data *pdata)
 198 {
 199         struct net_device *netdev = pdata->netdev;
 200
 201         free_netdev(netdev);
 202 }
 203
 204 void xgbe_set_counts(struct xgbe_prv_data *pdata)
 205 {
 206         /* Set all the function pointers */
 207         xgbe_init_all_fptrs(pdata);
 208
 209         /* Populate the hardware features */
 210         xgbe_get_all_hw_features(pdata);
 211
 212         /* Set default max values if not provided */
 213         if (!pdata->tx_max_channel_count)
 214                 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
 215         if (!pdata->rx_max_channel_count)
 216                 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
 217
 218         if (!pdata->tx_max_q_count)
 219                 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
 220         if (!pdata->rx_max_q_count)
 221                 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
 222
 223         /* Calculate the number of Tx and Rx rings to be created
 224          *  -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
 225          *   the number of Tx queues to the number of Tx channels
 226          *   enabled
 227          *  -Rx (DMA) Channels do not map 1-to-1 so use the actual
 228          *   number of Rx queues or maximum allowed
 229          */
 230         pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
 231                                      pdata->hw_feat.tx_ch_cnt);
 232         pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
 233                                      pdata->tx_max_channel_count);
 234         pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
 235                                      pdata->tx_max_q_count);
 236
 237         pdata->tx_q_count = pdata->tx_ring_count;
 238
 239         pdata->rx_ring_count = min_t(unsigned int,
 240                                      netif_get_num_default_rss_queues(),
 241                                      pdata->hw_feat.rx_ch_cnt);
 242         pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
 243                                      pdata->rx_max_channel_count);
 244
 245         pdata->rx_q_count = min_t(unsigned int, pdata->hw_feat.rx_q_cnt,
 246                                   pdata->rx_max_q_count);
 247
 248         if (netif_msg_probe(pdata)) {
 249                 dev_dbg(pdata->dev, "TX/RX DMA channel count = %u/%u\n",
 250                         pdata->tx_ring_count, pdata->rx_ring_count);
 251                 dev_dbg(pdata->dev, "TX/RX hardware queue count = %u/%u\n",
 252                         pdata->tx_q_count, pdata->rx_q_count);
 253         }
 254 }
 255
 256 int xgbe_config_netdev(struct xgbe_prv_data *pdata)
 257 {
 258         struct net_device *netdev = pdata->netdev;
 259         struct device *dev = pdata->dev;
 260         unsigned int i;
 261         int ret;
 262
 263         netdev->irq = pdata->dev_irq;
 264         netdev->base_addr = (unsigned long)pdata->xgmac_regs;
 265         memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len);
 266
 267         /* Issue software reset to device */
 268         pdata->hw_if.exit(pdata);
 269
 270         /* Set default configuration data */
 271         xgbe_default_config(pdata);
 272
 273         /* Set the DMA mask */
 274         ret = dma_set_mask_and_coherent(dev,
 275                                         DMA_BIT_MASK(pdata->hw_feat.dma_width));
 276         if (ret) {
 277                 dev_err(dev, "dma_set_mask_and_coherent failed\n");
 278                 return ret;
 279         }
 280
 281         /* Set default max values if not provided */
 282         if (!pdata->tx_max_fifo_size)
 283                 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
 284         if (!pdata->rx_max_fifo_size)
 285                 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
 286
 287         /* Set and validate the number of descriptors for a ring */
 288         BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_TX_DESC_CNT);
 289         pdata->tx_desc_count = XGBE_TX_DESC_CNT;
 290
 291         BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_RX_DESC_CNT);
 292         pdata->rx_desc_count = XGBE_RX_DESC_CNT;
 293
 294         /* Adjust the number of queues based on interrupts assigned */
 295         if (pdata->channel_irq_count) {
 296                 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
 297                                              pdata->channel_irq_count);
 298                 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
 299                                              pdata->channel_irq_count);
 300
 301                 if (netif_msg_probe(pdata))
 302                         dev_dbg(pdata->dev,
 303                                 "adjusted TX/RX DMA channel count = %u/%u\n",
 304                                 pdata->tx_ring_count, pdata->rx_ring_count);
 305         }
 306
 307         /* Set the number of queues */
 308         ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
 309         if (ret) {
 310                 dev_err(dev, "error setting real tx queue count\n");
 311                 return ret;
 312         }
 313
 314         ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
 315         if (ret) {
 316                 dev_err(dev, "error setting real rx queue count\n");
 317                 return ret;
 318         }
 319
 320         /* Initialize RSS hash key and lookup table */
 321         netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key));
 322
 323         for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
 324                 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
 325                                i % pdata->rx_ring_count);
 326
 327         XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
 328         XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
 329         XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
 330
 331         /* Call MDIO/PHY initialization routine */
 332         ret = pdata->phy_if.phy_init(pdata);
 333         if (ret)
 334                 return ret;
 335
 336         /* Set device operations */
 337         netdev->netdev_ops = xgbe_get_netdev_ops();
 338         netdev->ethtool_ops = xgbe_get_ethtool_ops();
 339 #ifdef CONFIG_AMD_XGBE_DCB
 340         netdev->dcbnl_ops = xgbe_get_dcbnl_ops();
 341 #endif
 342
 343         /* Set device features */
 344         netdev->hw_features = NETIF_F_SG |
 345                               NETIF_F_IP_CSUM |
 346                               NETIF_F_IPV6_CSUM |
 347                               NETIF_F_RXCSUM |
 348                               NETIF_F_TSO |
 349                               NETIF_F_TSO6 |
 350                               NETIF_F_GRO |
 351                               NETIF_F_HW_VLAN_CTAG_RX |
 352                               NETIF_F_HW_VLAN_CTAG_TX |
 353                               NETIF_F_HW_VLAN_CTAG_FILTER;
 354
 355         if (pdata->hw_feat.rss)
 356                 netdev->hw_features |= NETIF_F_RXHASH;
 357
 358         netdev->vlan_features |= NETIF_F_SG |
 359                                  NETIF_F_IP_CSUM |
 360                                  NETIF_F_IPV6_CSUM |
 361                                  NETIF_F_TSO |
 362                                  NETIF_F_TSO6;
 363
 364         netdev->features |= netdev->hw_features;
 365         pdata->netdev_features = netdev->features;
 366
 367         netdev->priv_flags |= IFF_UNICAST_FLT;
 368         netdev->min_mtu = 0;
 369         netdev->max_mtu = XGMAC_JUMBO_PACKET_MTU;
 370
 371         /* Use default watchdog timeout */
 372         netdev->watchdog_timeo = 0;
 373
 374         xgbe_init_rx_coalesce(pdata);
 375         xgbe_init_tx_coalesce(pdata);
 376
 377         netif_carrier_off(netdev);
 378         ret = register_netdev(netdev);
 379         if (ret) {
 380                 dev_err(dev, "net device registration failed\n");
 381                 return ret;
 382         }
 383
 384         /* Create the PHY/ANEG name based on netdev name */
 385         snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
 386                  netdev_name(netdev));
 387
 388         /* Create workqueues */
 389         pdata->dev_workqueue =
 390                 create_singlethread_workqueue(netdev_name(netdev));
 391         if (!pdata->dev_workqueue) {
 392                 netdev_err(netdev, "device workqueue creation failed\n");
 393                 ret = -ENOMEM;
 394                 goto err_netdev;
 395         }
 396
 397         pdata->an_workqueue =
 398                 create_singlethread_workqueue(pdata->an_name);
 399         if (!pdata->an_workqueue) {
 400                 netdev_err(netdev, "phy workqueue creation failed\n");
 401                 ret = -ENOMEM;
 402                 goto err_wq;
 403         }
 404
 405         xgbe_ptp_register(pdata);
 406
 407         xgbe_debugfs_init(pdata);
 408
 409         netif_dbg(pdata, drv, pdata->netdev, "%u Tx software queues\n",
 410                   pdata->tx_ring_count);
 411         netif_dbg(pdata, drv, pdata->netdev, "%u Rx software queues\n",
 412                   pdata->rx_ring_count);
 413
 414         return 0;
 415
 416 err_wq:
 417         destroy_workqueue(pdata->dev_workqueue);
 418
 419 err_netdev:
 420         unregister_netdev(netdev);
 421
 422         return ret;
 423 }
 424
 425 void xgbe_deconfig_netdev(struct xgbe_prv_data *pdata)
 426 {
 427         struct net_device *netdev = pdata->netdev;
 428
 429         xgbe_debugfs_exit(pdata);
 430
 431         xgbe_ptp_unregister(pdata);
 432
 433         pdata->phy_if.phy_exit(pdata);
 434
 435         flush_workqueue(pdata->an_workqueue);
 436         destroy_workqueue(pdata->an_workqueue);
 437
 438         flush_workqueue(pdata->dev_workqueue);
 439         destroy_workqueue(pdata->dev_workqueue);
 440
 441         unregister_netdev(netdev);
 442 }
 443
 444 static int __init xgbe_mod_init(void)
 445 {
 446         int ret;
 447
 448         ret = xgbe_platform_init();
 449         if (ret)
 450                 return ret;
 451
 452         ret = xgbe_pci_init();
 453         if (ret)
 454                 return ret;
 455
 456         return 0;
 457 }
 458
 459 static void __exit xgbe_mod_exit(void)
 460 {
 461         xgbe_pci_exit();
 462
 463         xgbe_platform_exit();
 464 }
 465
 466 module_init(xgbe_mod_init);
 467 module_exit(xgbe_mod_exit);