2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/module.h>
118 #include <linux/kmod.h>
119 #include <linux/mdio.h>
120 #include <linux/phy.h>
121 #include <linux/of.h>
122 #include <linux/bitops.h>
123 #include <linux/jiffies.h>
126 #include "xgbe-common.h"
128 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data
*pdata
)
132 reg
= XMDIO_READ(pdata
, MDIO_MMD_VEND2
, MDIO_VEND2_AN_STAT
);
133 reg
&= ~XGBE_AN_CL37_INT_MASK
;
134 XMDIO_WRITE(pdata
, MDIO_MMD_VEND2
, MDIO_VEND2_AN_STAT
, reg
);
137 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data
*pdata
)
141 reg
= XMDIO_READ(pdata
, MDIO_MMD_VEND2
, MDIO_VEND2_AN_CTRL
);
142 reg
&= ~XGBE_AN_CL37_INT_MASK
;
143 XMDIO_WRITE(pdata
, MDIO_MMD_VEND2
, MDIO_VEND2_AN_CTRL
, reg
);
145 reg
= XMDIO_READ(pdata
, MDIO_MMD_PCS
, MDIO_PCS_DIG_CTRL
);
146 reg
&= ~XGBE_PCS_CL37_BP
;
147 XMDIO_WRITE(pdata
, MDIO_MMD_PCS
, MDIO_PCS_DIG_CTRL
, reg
);
150 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data
*pdata
)
154 reg
= XMDIO_READ(pdata
, MDIO_MMD_PCS
, MDIO_PCS_DIG_CTRL
);
155 reg
|= XGBE_PCS_CL37_BP
;
156 XMDIO_WRITE(pdata
, MDIO_MMD_PCS
, MDIO_PCS_DIG_CTRL
, reg
);
158 reg
= XMDIO_READ(pdata
, MDIO_MMD_VEND2
, MDIO_VEND2_AN_CTRL
);
159 reg
|= XGBE_AN_CL37_INT_MASK
;
160 XMDIO_WRITE(pdata
, MDIO_MMD_VEND2
, MDIO_VEND2_AN_CTRL
, reg
);
163 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data
*pdata
)
165 XMDIO_WRITE(pdata
, MDIO_MMD_AN
, MDIO_AN_INT
, 0);
168 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data
*pdata
)
170 XMDIO_WRITE(pdata
, MDIO_MMD_AN
, MDIO_AN_INTMASK
, 0);
173 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data
*pdata
)
175 XMDIO_WRITE(pdata
, MDIO_MMD_AN
, MDIO_AN_INTMASK
, XGBE_AN_CL73_INT_MASK
);
178 static void xgbe_an_enable_interrupts(struct xgbe_prv_data
*pdata
)
180 switch (pdata
->an_mode
) {
181 case XGBE_AN_MODE_CL73
:
182 xgbe_an73_enable_interrupts(pdata
);
184 case XGBE_AN_MODE_CL37
:
185 case XGBE_AN_MODE_CL37_SGMII
:
186 xgbe_an37_enable_interrupts(pdata
);
193 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data
*pdata
)
195 xgbe_an73_clear_interrupts(pdata
);
196 xgbe_an37_clear_interrupts(pdata
);
199 static void xgbe_an73_enable_kr_training(struct xgbe_prv_data
*pdata
)
203 reg
= XMDIO_READ(pdata
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_PMD_CTRL
);
205 reg
|= XGBE_KR_TRAINING_ENABLE
;
206 XMDIO_WRITE(pdata
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_PMD_CTRL
, reg
);
209 static void xgbe_an73_disable_kr_training(struct xgbe_prv_data
*pdata
)
213 reg
= XMDIO_READ(pdata
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_PMD_CTRL
);
215 reg
&= ~XGBE_KR_TRAINING_ENABLE
;
216 XMDIO_WRITE(pdata
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_PMD_CTRL
, reg
);
219 static void xgbe_kr_mode(struct xgbe_prv_data
*pdata
)
221 /* Enable KR training */
222 xgbe_an73_enable_kr_training(pdata
);
224 /* Set MAC to 10G speed */
225 pdata
->hw_if
.set_speed(pdata
, SPEED_10000
);
227 /* Call PHY implementation support to complete rate change */
228 pdata
->phy_if
.phy_impl
.set_mode(pdata
, XGBE_MODE_KR
);
231 static void xgbe_kx_2500_mode(struct xgbe_prv_data
*pdata
)
233 /* Disable KR training */
234 xgbe_an73_disable_kr_training(pdata
);
236 /* Set MAC to 2.5G speed */
237 pdata
->hw_if
.set_speed(pdata
, SPEED_2500
);
239 /* Call PHY implementation support to complete rate change */
240 pdata
->phy_if
.phy_impl
.set_mode(pdata
, XGBE_MODE_KX_2500
);
243 static void xgbe_kx_1000_mode(struct xgbe_prv_data
*pdata
)
245 /* Disable KR training */
246 xgbe_an73_disable_kr_training(pdata
);
248 /* Set MAC to 1G speed */
249 pdata
->hw_if
.set_speed(pdata
, SPEED_1000
);
251 /* Call PHY implementation support to complete rate change */
252 pdata
->phy_if
.phy_impl
.set_mode(pdata
, XGBE_MODE_KX_1000
);
255 static enum xgbe_mode
xgbe_cur_mode(struct xgbe_prv_data
*pdata
)
257 return pdata
->phy_if
.phy_impl
.cur_mode(pdata
);
260 static bool xgbe_in_kr_mode(struct xgbe_prv_data
*pdata
)
262 return (xgbe_cur_mode(pdata
) == XGBE_MODE_KR
);
265 static void xgbe_change_mode(struct xgbe_prv_data
*pdata
,
269 case XGBE_MODE_KX_1000
:
270 xgbe_kx_1000_mode(pdata
);
272 case XGBE_MODE_KX_2500
:
273 xgbe_kx_2500_mode(pdata
);
278 case XGBE_MODE_UNKNOWN
:
281 netif_dbg(pdata
, link
, pdata
->netdev
,
282 "invalid operation mode requested (%u)\n", mode
);
286 static void xgbe_switch_mode(struct xgbe_prv_data
*pdata
)
288 xgbe_change_mode(pdata
, pdata
->phy_if
.phy_impl
.switch_mode(pdata
));
291 static void xgbe_set_mode(struct xgbe_prv_data
*pdata
,
294 if (mode
== xgbe_cur_mode(pdata
))
297 xgbe_change_mode(pdata
, mode
);
300 static bool xgbe_use_mode(struct xgbe_prv_data
*pdata
,
303 return pdata
->phy_if
.phy_impl
.use_mode(pdata
, mode
);
306 static void xgbe_an37_set(struct xgbe_prv_data
*pdata
, bool enable
,
311 reg
= XMDIO_READ(pdata
, MDIO_MMD_VEND2
, MDIO_CTRL1
);
312 reg
&= ~MDIO_VEND2_CTRL1_AN_ENABLE
;
315 reg
|= MDIO_VEND2_CTRL1_AN_ENABLE
;
318 reg
|= MDIO_VEND2_CTRL1_AN_RESTART
;
320 XMDIO_WRITE(pdata
, MDIO_MMD_VEND2
, MDIO_CTRL1
, reg
);
323 static void xgbe_an37_restart(struct xgbe_prv_data
*pdata
)
325 xgbe_an37_enable_interrupts(pdata
);
326 xgbe_an37_set(pdata
, true, true);
328 netif_dbg(pdata
, link
, pdata
->netdev
, "CL37 AN enabled/restarted\n");
331 static void xgbe_an37_disable(struct xgbe_prv_data
*pdata
)
333 xgbe_an37_set(pdata
, false, false);
334 xgbe_an37_disable_interrupts(pdata
);
336 netif_dbg(pdata
, link
, pdata
->netdev
, "CL37 AN disabled\n");
339 static void xgbe_an73_set(struct xgbe_prv_data
*pdata
, bool enable
,
344 reg
= XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_CTRL1
);
345 reg
&= ~MDIO_AN_CTRL1_ENABLE
;
348 reg
|= MDIO_AN_CTRL1_ENABLE
;
351 reg
|= MDIO_AN_CTRL1_RESTART
;
353 XMDIO_WRITE(pdata
, MDIO_MMD_AN
, MDIO_CTRL1
, reg
);
356 static void xgbe_an73_restart(struct xgbe_prv_data
*pdata
)
358 xgbe_an73_enable_interrupts(pdata
);
359 xgbe_an73_set(pdata
, true, true);
361 netif_dbg(pdata
, link
, pdata
->netdev
, "CL73 AN enabled/restarted\n");
364 static void xgbe_an73_disable(struct xgbe_prv_data
*pdata
)
366 xgbe_an73_set(pdata
, false, false);
367 xgbe_an73_disable_interrupts(pdata
);
369 netif_dbg(pdata
, link
, pdata
->netdev
, "CL73 AN disabled\n");
372 static void xgbe_an_restart(struct xgbe_prv_data
*pdata
)
374 switch (pdata
->an_mode
) {
375 case XGBE_AN_MODE_CL73
:
376 xgbe_an73_restart(pdata
);
378 case XGBE_AN_MODE_CL37
:
379 case XGBE_AN_MODE_CL37_SGMII
:
380 xgbe_an37_restart(pdata
);
387 static void xgbe_an_disable(struct xgbe_prv_data
*pdata
)
389 switch (pdata
->an_mode
) {
390 case XGBE_AN_MODE_CL73
:
391 xgbe_an73_disable(pdata
);
393 case XGBE_AN_MODE_CL37
:
394 case XGBE_AN_MODE_CL37_SGMII
:
395 xgbe_an37_disable(pdata
);
402 static void xgbe_an_disable_all(struct xgbe_prv_data
*pdata
)
404 xgbe_an73_disable(pdata
);
405 xgbe_an37_disable(pdata
);
408 static enum xgbe_an
xgbe_an73_tx_training(struct xgbe_prv_data
*pdata
,
411 unsigned int ad_reg
, lp_reg
, reg
;
413 *state
= XGBE_RX_COMPLETE
;
415 /* If we're not in KR mode then we're done */
416 if (!xgbe_in_kr_mode(pdata
))
417 return XGBE_AN_PAGE_RECEIVED
;
419 /* Enable/Disable FEC */
420 ad_reg
= XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
+ 2);
421 lp_reg
= XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_LPA
+ 2);
423 reg
= XMDIO_READ(pdata
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_FECCTRL
);
424 reg
&= ~(MDIO_PMA_10GBR_FECABLE_ABLE
| MDIO_PMA_10GBR_FECABLE_ERRABLE
);
425 if ((ad_reg
& 0xc000) && (lp_reg
& 0xc000))
426 reg
|= pdata
->fec_ability
;
428 XMDIO_WRITE(pdata
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_FECCTRL
, reg
);
430 /* Start KR training */
431 reg
= XMDIO_READ(pdata
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_PMD_CTRL
);
432 if (reg
& XGBE_KR_TRAINING_ENABLE
) {
433 if (pdata
->phy_if
.phy_impl
.kr_training_pre
)
434 pdata
->phy_if
.phy_impl
.kr_training_pre(pdata
);
436 reg
|= XGBE_KR_TRAINING_START
;
437 XMDIO_WRITE(pdata
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBR_PMD_CTRL
,
440 if (pdata
->phy_if
.phy_impl
.kr_training_post
)
441 pdata
->phy_if
.phy_impl
.kr_training_post(pdata
);
443 netif_dbg(pdata
, link
, pdata
->netdev
,
444 "KR training initiated\n");
447 return XGBE_AN_PAGE_RECEIVED
;
450 static enum xgbe_an
xgbe_an73_tx_xnp(struct xgbe_prv_data
*pdata
,
455 *state
= XGBE_RX_XNP
;
457 msg
= XGBE_XNP_MCF_NULL_MESSAGE
;
458 msg
|= XGBE_XNP_MP_FORMATTED
;
460 XMDIO_WRITE(pdata
, MDIO_MMD_AN
, MDIO_AN_XNP
+ 2, 0);
461 XMDIO_WRITE(pdata
, MDIO_MMD_AN
, MDIO_AN_XNP
+ 1, 0);
462 XMDIO_WRITE(pdata
, MDIO_MMD_AN
, MDIO_AN_XNP
, msg
);
464 return XGBE_AN_PAGE_RECEIVED
;
467 static enum xgbe_an
xgbe_an73_rx_bpa(struct xgbe_prv_data
*pdata
,
470 unsigned int link_support
;
471 unsigned int reg
, ad_reg
, lp_reg
;
473 /* Read Base Ability register 2 first */
474 reg
= XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_LPA
+ 1);
476 /* Check for a supported mode, otherwise restart in a different one */
477 link_support
= xgbe_in_kr_mode(pdata
) ? 0x80 : 0x20;
478 if (!(reg
& link_support
))
479 return XGBE_AN_INCOMPAT_LINK
;
481 /* Check Extended Next Page support */
482 ad_reg
= XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
);
483 lp_reg
= XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_LPA
);
485 return ((ad_reg
& XGBE_XNP_NP_EXCHANGE
) ||
486 (lp_reg
& XGBE_XNP_NP_EXCHANGE
))
487 ? xgbe_an73_tx_xnp(pdata
, state
)
488 : xgbe_an73_tx_training(pdata
, state
);
491 static enum xgbe_an
xgbe_an73_rx_xnp(struct xgbe_prv_data
*pdata
,
494 unsigned int ad_reg
, lp_reg
;
496 /* Check Extended Next Page support */
497 ad_reg
= XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_XNP
);
498 lp_reg
= XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_LPX
);
500 return ((ad_reg
& XGBE_XNP_NP_EXCHANGE
) ||
501 (lp_reg
& XGBE_XNP_NP_EXCHANGE
))
502 ? xgbe_an73_tx_xnp(pdata
, state
)
503 : xgbe_an73_tx_training(pdata
, state
);
506 static enum xgbe_an
xgbe_an73_page_received(struct xgbe_prv_data
*pdata
)
509 unsigned long an_timeout
;
512 if (!pdata
->an_start
) {
513 pdata
->an_start
= jiffies
;
515 an_timeout
= pdata
->an_start
+
516 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT
);
517 if (time_after(jiffies
, an_timeout
)) {
518 /* Auto-negotiation timed out, reset state */
519 pdata
->kr_state
= XGBE_RX_BPA
;
520 pdata
->kx_state
= XGBE_RX_BPA
;
522 pdata
->an_start
= jiffies
;
524 netif_dbg(pdata
, link
, pdata
->netdev
,
525 "CL73 AN timed out, resetting state\n");
529 state
= xgbe_in_kr_mode(pdata
) ? &pdata
->kr_state
534 ret
= xgbe_an73_rx_bpa(pdata
, state
);
538 ret
= xgbe_an73_rx_xnp(pdata
, state
);
548 static enum xgbe_an
xgbe_an73_incompat_link(struct xgbe_prv_data
*pdata
)
550 /* Be sure we aren't looping trying to negotiate */
551 if (xgbe_in_kr_mode(pdata
)) {
552 pdata
->kr_state
= XGBE_RX_ERROR
;
554 if (!(pdata
->phy
.advertising
& ADVERTISED_1000baseKX_Full
) &&
555 !(pdata
->phy
.advertising
& ADVERTISED_2500baseX_Full
))
556 return XGBE_AN_NO_LINK
;
558 if (pdata
->kx_state
!= XGBE_RX_BPA
)
559 return XGBE_AN_NO_LINK
;
561 pdata
->kx_state
= XGBE_RX_ERROR
;
563 if (!(pdata
->phy
.advertising
& ADVERTISED_10000baseKR_Full
))
564 return XGBE_AN_NO_LINK
;
566 if (pdata
->kr_state
!= XGBE_RX_BPA
)
567 return XGBE_AN_NO_LINK
;
570 xgbe_an73_disable(pdata
);
572 xgbe_switch_mode(pdata
);
574 xgbe_an73_restart(pdata
);
576 return XGBE_AN_INCOMPAT_LINK
;
579 static void xgbe_an37_isr(struct xgbe_prv_data
*pdata
)
583 /* Disable AN interrupts */
584 xgbe_an37_disable_interrupts(pdata
);
586 /* Save the interrupt(s) that fired */
587 reg
= XMDIO_READ(pdata
, MDIO_MMD_VEND2
, MDIO_VEND2_AN_STAT
);
588 pdata
->an_int
= reg
& XGBE_AN_CL37_INT_MASK
;
589 pdata
->an_status
= reg
& ~XGBE_AN_CL37_INT_MASK
;
592 /* Clear the interrupt(s) that fired and process them */
593 reg
&= ~XGBE_AN_CL37_INT_MASK
;
594 XMDIO_WRITE(pdata
, MDIO_MMD_VEND2
, MDIO_VEND2_AN_STAT
, reg
);
596 queue_work(pdata
->an_workqueue
, &pdata
->an_irq_work
);
598 /* Enable AN interrupts */
599 xgbe_an37_enable_interrupts(pdata
);
603 static void xgbe_an73_isr(struct xgbe_prv_data
*pdata
)
605 /* Disable AN interrupts */
606 xgbe_an73_disable_interrupts(pdata
);
608 /* Save the interrupt(s) that fired */
609 pdata
->an_int
= XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_INT
);
612 /* Clear the interrupt(s) that fired and process them */
613 XMDIO_WRITE(pdata
, MDIO_MMD_AN
, MDIO_AN_INT
, ~pdata
->an_int
);
615 queue_work(pdata
->an_workqueue
, &pdata
->an_irq_work
);
617 /* Enable AN interrupts */
618 xgbe_an73_enable_interrupts(pdata
);
622 static irqreturn_t
xgbe_an_isr(int irq
, void *data
)
624 struct xgbe_prv_data
*pdata
= (struct xgbe_prv_data
*)data
;
626 netif_dbg(pdata
, intr
, pdata
->netdev
, "AN interrupt received\n");
628 switch (pdata
->an_mode
) {
629 case XGBE_AN_MODE_CL73
:
630 xgbe_an73_isr(pdata
);
632 case XGBE_AN_MODE_CL37
:
633 case XGBE_AN_MODE_CL37_SGMII
:
634 xgbe_an37_isr(pdata
);
643 static irqreturn_t
xgbe_an_combined_isr(int irq
, struct xgbe_prv_data
*pdata
)
645 return xgbe_an_isr(irq
, pdata
);
648 static void xgbe_an_irq_work(struct work_struct
*work
)
650 struct xgbe_prv_data
*pdata
= container_of(work
,
651 struct xgbe_prv_data
,
654 /* Avoid a race between enabling the IRQ and exiting the work by
655 * waiting for the work to finish and then queueing it
657 flush_work(&pdata
->an_work
);
658 queue_work(pdata
->an_workqueue
, &pdata
->an_work
);
661 static const char *xgbe_state_as_string(enum xgbe_an state
)
666 case XGBE_AN_PAGE_RECEIVED
:
667 return "Page-Received";
668 case XGBE_AN_INCOMPAT_LINK
:
669 return "Incompatible-Link";
670 case XGBE_AN_COMPLETE
:
672 case XGBE_AN_NO_LINK
:
681 static void xgbe_an37_state_machine(struct xgbe_prv_data
*pdata
)
683 enum xgbe_an cur_state
= pdata
->an_state
;
688 if (pdata
->an_int
& XGBE_AN_CL37_INT_CMPLT
) {
689 pdata
->an_state
= XGBE_AN_COMPLETE
;
690 pdata
->an_int
&= ~XGBE_AN_CL37_INT_CMPLT
;
692 /* If SGMII is enabled, check the link status */
693 if ((pdata
->an_mode
== XGBE_AN_MODE_CL37_SGMII
) &&
694 !(pdata
->an_status
& XGBE_SGMII_AN_LINK_STATUS
))
695 pdata
->an_state
= XGBE_AN_NO_LINK
;
698 netif_dbg(pdata
, link
, pdata
->netdev
, "CL37 AN %s\n",
699 xgbe_state_as_string(pdata
->an_state
));
701 cur_state
= pdata
->an_state
;
703 switch (pdata
->an_state
) {
707 case XGBE_AN_COMPLETE
:
708 netif_dbg(pdata
, link
, pdata
->netdev
,
709 "Auto negotiation successful\n");
712 case XGBE_AN_NO_LINK
:
716 pdata
->an_state
= XGBE_AN_ERROR
;
719 if (pdata
->an_state
== XGBE_AN_ERROR
) {
720 netdev_err(pdata
->netdev
,
721 "error during auto-negotiation, state=%u\n",
725 xgbe_an37_clear_interrupts(pdata
);
728 if (pdata
->an_state
>= XGBE_AN_COMPLETE
) {
729 pdata
->an_result
= pdata
->an_state
;
730 pdata
->an_state
= XGBE_AN_READY
;
732 netif_dbg(pdata
, link
, pdata
->netdev
, "CL37 AN result: %s\n",
733 xgbe_state_as_string(pdata
->an_result
));
736 xgbe_an37_enable_interrupts(pdata
);
739 static void xgbe_an73_state_machine(struct xgbe_prv_data
*pdata
)
741 enum xgbe_an cur_state
= pdata
->an_state
;
747 if (pdata
->an_int
& XGBE_AN_CL73_PG_RCV
) {
748 pdata
->an_state
= XGBE_AN_PAGE_RECEIVED
;
749 pdata
->an_int
&= ~XGBE_AN_CL73_PG_RCV
;
750 } else if (pdata
->an_int
& XGBE_AN_CL73_INC_LINK
) {
751 pdata
->an_state
= XGBE_AN_INCOMPAT_LINK
;
752 pdata
->an_int
&= ~XGBE_AN_CL73_INC_LINK
;
753 } else if (pdata
->an_int
& XGBE_AN_CL73_INT_CMPLT
) {
754 pdata
->an_state
= XGBE_AN_COMPLETE
;
755 pdata
->an_int
&= ~XGBE_AN_CL73_INT_CMPLT
;
757 pdata
->an_state
= XGBE_AN_ERROR
;
761 netif_dbg(pdata
, link
, pdata
->netdev
, "CL73 AN %s\n",
762 xgbe_state_as_string(pdata
->an_state
));
764 cur_state
= pdata
->an_state
;
766 switch (pdata
->an_state
) {
768 pdata
->an_supported
= 0;
771 case XGBE_AN_PAGE_RECEIVED
:
772 pdata
->an_state
= xgbe_an73_page_received(pdata
);
773 pdata
->an_supported
++;
776 case XGBE_AN_INCOMPAT_LINK
:
777 pdata
->an_supported
= 0;
778 pdata
->parallel_detect
= 0;
779 pdata
->an_state
= xgbe_an73_incompat_link(pdata
);
782 case XGBE_AN_COMPLETE
:
783 pdata
->parallel_detect
= pdata
->an_supported
? 0 : 1;
784 netif_dbg(pdata
, link
, pdata
->netdev
, "%s successful\n",
785 pdata
->an_supported
? "Auto negotiation"
786 : "Parallel detection");
789 case XGBE_AN_NO_LINK
:
793 pdata
->an_state
= XGBE_AN_ERROR
;
796 if (pdata
->an_state
== XGBE_AN_NO_LINK
) {
798 xgbe_an73_clear_interrupts(pdata
);
799 } else if (pdata
->an_state
== XGBE_AN_ERROR
) {
800 netdev_err(pdata
->netdev
,
801 "error during auto-negotiation, state=%u\n",
805 xgbe_an73_clear_interrupts(pdata
);
808 if (pdata
->an_state
>= XGBE_AN_COMPLETE
) {
809 pdata
->an_result
= pdata
->an_state
;
810 pdata
->an_state
= XGBE_AN_READY
;
811 pdata
->kr_state
= XGBE_RX_BPA
;
812 pdata
->kx_state
= XGBE_RX_BPA
;
815 netif_dbg(pdata
, link
, pdata
->netdev
, "CL73 AN result: %s\n",
816 xgbe_state_as_string(pdata
->an_result
));
819 if (cur_state
!= pdata
->an_state
)
825 xgbe_an73_enable_interrupts(pdata
);
828 static void xgbe_an_state_machine(struct work_struct
*work
)
830 struct xgbe_prv_data
*pdata
= container_of(work
,
831 struct xgbe_prv_data
,
834 mutex_lock(&pdata
->an_mutex
);
836 switch (pdata
->an_mode
) {
837 case XGBE_AN_MODE_CL73
:
838 xgbe_an73_state_machine(pdata
);
840 case XGBE_AN_MODE_CL37
:
841 case XGBE_AN_MODE_CL37_SGMII
:
842 xgbe_an37_state_machine(pdata
);
848 mutex_unlock(&pdata
->an_mutex
);
851 static void xgbe_an37_init(struct xgbe_prv_data
*pdata
)
855 /* Set up Advertisement register */
856 reg
= XMDIO_READ(pdata
, MDIO_MMD_VEND2
, MDIO_VEND2_AN_ADVERTISE
);
857 if (pdata
->phy
.advertising
& ADVERTISED_Pause
)
862 if (pdata
->phy
.advertising
& ADVERTISED_Asym_Pause
)
867 /* Full duplex, but not half */
868 reg
|= XGBE_AN_CL37_FD_MASK
;
869 reg
&= ~XGBE_AN_CL37_HD_MASK
;
871 XMDIO_WRITE(pdata
, MDIO_MMD_VEND2
, MDIO_VEND2_AN_ADVERTISE
, reg
);
873 /* Set up the Control register */
874 reg
= XMDIO_READ(pdata
, MDIO_MMD_VEND2
, MDIO_VEND2_AN_CTRL
);
875 reg
&= XGBE_AN_CL37_TX_CONFIG_MASK
;
876 reg
&= XGBE_AN_CL37_PCS_MODE_MASK
;
878 switch (pdata
->an_mode
) {
879 case XGBE_AN_MODE_CL37
:
880 reg
|= XGBE_AN_CL37_PCS_MODE_BASEX
;
882 case XGBE_AN_MODE_CL37_SGMII
:
883 reg
|= XGBE_AN_CL37_PCS_MODE_SGMII
;
889 XMDIO_WRITE(pdata
, MDIO_MMD_VEND2
, MDIO_VEND2_AN_CTRL
, reg
);
891 netif_dbg(pdata
, link
, pdata
->netdev
, "CL37 AN (%s) initialized\n",
892 (pdata
->an_mode
== XGBE_AN_MODE_CL37
) ? "BaseX" : "SGMII");
895 static void xgbe_an73_init(struct xgbe_prv_data
*pdata
)
899 /* Set up Advertisement register 3 first */
900 reg
= XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
+ 2);
901 if (pdata
->phy
.advertising
& ADVERTISED_10000baseR_FEC
)
906 XMDIO_WRITE(pdata
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
+ 2, reg
);
908 /* Set up Advertisement register 2 next */
909 reg
= XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
+ 1);
910 if (pdata
->phy
.advertising
& ADVERTISED_10000baseKR_Full
)
915 if ((pdata
->phy
.advertising
& ADVERTISED_1000baseKX_Full
) ||
916 (pdata
->phy
.advertising
& ADVERTISED_2500baseX_Full
))
921 XMDIO_WRITE(pdata
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
+ 1, reg
);
923 /* Set up Advertisement register 1 last */
924 reg
= XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
);
925 if (pdata
->phy
.advertising
& ADVERTISED_Pause
)
930 if (pdata
->phy
.advertising
& ADVERTISED_Asym_Pause
)
935 /* We don't intend to perform XNP */
936 reg
&= ~XGBE_XNP_NP_EXCHANGE
;
938 XMDIO_WRITE(pdata
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
, reg
);
940 netif_dbg(pdata
, link
, pdata
->netdev
, "CL73 AN initialized\n");
943 static void xgbe_an_init(struct xgbe_prv_data
*pdata
)
945 /* Set up advertisement registers based on current settings */
946 pdata
->an_mode
= pdata
->phy_if
.phy_impl
.an_mode(pdata
);
947 switch (pdata
->an_mode
) {
948 case XGBE_AN_MODE_CL73
:
949 xgbe_an73_init(pdata
);
951 case XGBE_AN_MODE_CL37
:
952 case XGBE_AN_MODE_CL37_SGMII
:
953 xgbe_an37_init(pdata
);
960 static const char *xgbe_phy_fc_string(struct xgbe_prv_data
*pdata
)
962 if (pdata
->tx_pause
&& pdata
->rx_pause
)
964 else if (pdata
->rx_pause
)
966 else if (pdata
->tx_pause
)
972 static const char *xgbe_phy_speed_string(int speed
)
984 return "Unsupported";
988 static void xgbe_phy_print_status(struct xgbe_prv_data
*pdata
)
991 netdev_info(pdata
->netdev
,
992 "Link is Up - %s/%s - flow control %s\n",
993 xgbe_phy_speed_string(pdata
->phy
.speed
),
994 pdata
->phy
.duplex
== DUPLEX_FULL
? "Full" : "Half",
995 xgbe_phy_fc_string(pdata
));
997 netdev_info(pdata
->netdev
, "Link is Down\n");
1000 static void xgbe_phy_adjust_link(struct xgbe_prv_data
*pdata
)
1004 if (pdata
->phy
.link
) {
1005 /* Flow control support */
1006 pdata
->pause_autoneg
= pdata
->phy
.pause_autoneg
;
1008 if (pdata
->tx_pause
!= pdata
->phy
.tx_pause
) {
1010 pdata
->hw_if
.config_tx_flow_control(pdata
);
1011 pdata
->tx_pause
= pdata
->phy
.tx_pause
;
1014 if (pdata
->rx_pause
!= pdata
->phy
.rx_pause
) {
1016 pdata
->hw_if
.config_rx_flow_control(pdata
);
1017 pdata
->rx_pause
= pdata
->phy
.rx_pause
;
1021 if (pdata
->phy_speed
!= pdata
->phy
.speed
) {
1023 pdata
->phy_speed
= pdata
->phy
.speed
;
1026 if (pdata
->phy_link
!= pdata
->phy
.link
) {
1028 pdata
->phy_link
= pdata
->phy
.link
;
1030 } else if (pdata
->phy_link
) {
1032 pdata
->phy_link
= 0;
1033 pdata
->phy_speed
= SPEED_UNKNOWN
;
1036 if (new_state
&& netif_msg_link(pdata
))
1037 xgbe_phy_print_status(pdata
);
1040 static bool xgbe_phy_valid_speed(struct xgbe_prv_data
*pdata
, int speed
)
1042 return pdata
->phy_if
.phy_impl
.valid_speed(pdata
, speed
);
1045 static int xgbe_phy_config_fixed(struct xgbe_prv_data
*pdata
)
1047 enum xgbe_mode mode
;
1049 netif_dbg(pdata
, link
, pdata
->netdev
, "fixed PHY configuration\n");
1051 /* Disable auto-negotiation */
1052 xgbe_an_disable(pdata
);
1054 /* Set specified mode for specified speed */
1055 mode
= pdata
->phy_if
.phy_impl
.get_mode(pdata
, pdata
->phy
.speed
);
1057 case XGBE_MODE_KX_1000
:
1058 case XGBE_MODE_KX_2500
:
1061 case XGBE_MODE_UNKNOWN
:
1066 /* Validate duplex mode */
1067 if (pdata
->phy
.duplex
!= DUPLEX_FULL
)
1070 xgbe_set_mode(pdata
, mode
);
1075 static int __xgbe_phy_config_aneg(struct xgbe_prv_data
*pdata
)
1077 set_bit(XGBE_LINK_INIT
, &pdata
->dev_state
);
1078 pdata
->link_check
= jiffies
;
1080 if (pdata
->phy
.autoneg
!= AUTONEG_ENABLE
)
1081 return xgbe_phy_config_fixed(pdata
);
1083 netif_dbg(pdata
, link
, pdata
->netdev
, "AN PHY configuration\n");
1085 /* Disable auto-negotiation interrupt */
1086 disable_irq(pdata
->an_irq
);
1088 /* Start auto-negotiation in a supported mode */
1089 if (xgbe_use_mode(pdata
, XGBE_MODE_KR
)) {
1090 xgbe_set_mode(pdata
, XGBE_MODE_KR
);
1091 } else if (xgbe_use_mode(pdata
, XGBE_MODE_KX_2500
)) {
1092 xgbe_set_mode(pdata
, XGBE_MODE_KX_2500
);
1093 } else if (xgbe_use_mode(pdata
, XGBE_MODE_KX_1000
)) {
1094 xgbe_set_mode(pdata
, XGBE_MODE_KX_1000
);
1096 enable_irq(pdata
->an_irq
);
1100 /* Disable and stop any in progress auto-negotiation */
1101 xgbe_an_disable_all(pdata
);
1103 /* Clear any auto-negotitation interrupts */
1104 xgbe_an_clear_interrupts_all(pdata
);
1106 pdata
->an_result
= XGBE_AN_READY
;
1107 pdata
->an_state
= XGBE_AN_READY
;
1108 pdata
->kr_state
= XGBE_RX_BPA
;
1109 pdata
->kx_state
= XGBE_RX_BPA
;
1111 /* Re-enable auto-negotiation interrupt */
1112 enable_irq(pdata
->an_irq
);
1114 xgbe_an_init(pdata
);
1115 xgbe_an_restart(pdata
);
1120 static int xgbe_phy_config_aneg(struct xgbe_prv_data
*pdata
)
1124 mutex_lock(&pdata
->an_mutex
);
1126 ret
= __xgbe_phy_config_aneg(pdata
);
1128 set_bit(XGBE_LINK_ERR
, &pdata
->dev_state
);
1130 clear_bit(XGBE_LINK_ERR
, &pdata
->dev_state
);
1132 mutex_unlock(&pdata
->an_mutex
);
1137 static bool xgbe_phy_aneg_done(struct xgbe_prv_data
*pdata
)
1139 return (pdata
->an_result
== XGBE_AN_COMPLETE
);
1142 static void xgbe_check_link_timeout(struct xgbe_prv_data
*pdata
)
1144 unsigned long link_timeout
;
1146 link_timeout
= pdata
->link_check
+ (XGBE_LINK_TIMEOUT
* HZ
);
1147 if (time_after(jiffies
, link_timeout
)) {
1148 netif_dbg(pdata
, link
, pdata
->netdev
, "AN link timeout\n");
1149 xgbe_phy_config_aneg(pdata
);
1153 static enum xgbe_mode
xgbe_phy_status_aneg(struct xgbe_prv_data
*pdata
)
1155 return pdata
->phy_if
.phy_impl
.an_outcome(pdata
);
1158 static void xgbe_phy_status_result(struct xgbe_prv_data
*pdata
)
1160 enum xgbe_mode mode
;
1162 pdata
->phy
.lp_advertising
= 0;
1164 if ((pdata
->phy
.autoneg
!= AUTONEG_ENABLE
) || pdata
->parallel_detect
)
1165 mode
= xgbe_cur_mode(pdata
);
1167 mode
= xgbe_phy_status_aneg(pdata
);
1170 case XGBE_MODE_KX_1000
:
1171 pdata
->phy
.speed
= SPEED_1000
;
1173 case XGBE_MODE_KX_2500
:
1174 pdata
->phy
.speed
= SPEED_2500
;
1177 pdata
->phy
.speed
= SPEED_10000
;
1179 case XGBE_MODE_UNKNOWN
:
1181 pdata
->phy
.speed
= SPEED_UNKNOWN
;
1184 pdata
->phy
.duplex
= DUPLEX_FULL
;
1186 xgbe_set_mode(pdata
, mode
);
1189 static void xgbe_phy_status(struct xgbe_prv_data
*pdata
)
1191 unsigned int link_aneg
;
1193 if (test_bit(XGBE_LINK_ERR
, &pdata
->dev_state
)) {
1194 netif_carrier_off(pdata
->netdev
);
1196 pdata
->phy
.link
= 0;
1200 link_aneg
= (pdata
->phy
.autoneg
== AUTONEG_ENABLE
);
1202 pdata
->phy
.link
= pdata
->phy_if
.phy_impl
.link_status(pdata
);
1203 if (pdata
->phy
.link
) {
1204 if (link_aneg
&& !xgbe_phy_aneg_done(pdata
)) {
1205 xgbe_check_link_timeout(pdata
);
1209 xgbe_phy_status_result(pdata
);
1211 if (test_bit(XGBE_LINK_INIT
, &pdata
->dev_state
))
1212 clear_bit(XGBE_LINK_INIT
, &pdata
->dev_state
);
1214 netif_carrier_on(pdata
->netdev
);
1216 if (test_bit(XGBE_LINK_INIT
, &pdata
->dev_state
)) {
1217 xgbe_check_link_timeout(pdata
);
1223 xgbe_phy_status_result(pdata
);
1225 netif_carrier_off(pdata
->netdev
);
1229 xgbe_phy_adjust_link(pdata
);
1232 static void xgbe_phy_stop(struct xgbe_prv_data
*pdata
)
1234 netif_dbg(pdata
, link
, pdata
->netdev
, "stopping PHY\n");
1236 if (!pdata
->phy_started
)
1239 /* Indicate the PHY is down */
1240 pdata
->phy_started
= 0;
1242 /* Disable auto-negotiation */
1243 xgbe_an_disable_all(pdata
);
1245 if (pdata
->dev_irq
!= pdata
->an_irq
)
1246 devm_free_irq(pdata
->dev
, pdata
->an_irq
, pdata
);
1248 pdata
->phy_if
.phy_impl
.stop(pdata
);
1250 pdata
->phy
.link
= 0;
1251 netif_carrier_off(pdata
->netdev
);
1253 xgbe_phy_adjust_link(pdata
);
1256 static int xgbe_phy_start(struct xgbe_prv_data
*pdata
)
1258 struct net_device
*netdev
= pdata
->netdev
;
1261 netif_dbg(pdata
, link
, pdata
->netdev
, "starting PHY\n");
1263 ret
= pdata
->phy_if
.phy_impl
.start(pdata
);
1267 /* If we have a separate AN irq, enable it */
1268 if (pdata
->dev_irq
!= pdata
->an_irq
) {
1269 ret
= devm_request_irq(pdata
->dev
, pdata
->an_irq
,
1270 xgbe_an_isr
, 0, pdata
->an_name
,
1273 netdev_err(netdev
, "phy irq request failed\n");
1278 /* Set initial mode - call the mode setting routines
1279 * directly to insure we are properly configured
1281 if (xgbe_use_mode(pdata
, XGBE_MODE_KR
)) {
1282 xgbe_kr_mode(pdata
);
1283 } else if (xgbe_use_mode(pdata
, XGBE_MODE_KX_2500
)) {
1284 xgbe_kx_2500_mode(pdata
);
1285 } else if (xgbe_use_mode(pdata
, XGBE_MODE_KX_1000
)) {
1286 xgbe_kx_1000_mode(pdata
);
1292 /* Indicate the PHY is up and running */
1293 pdata
->phy_started
= 1;
1295 xgbe_an_init(pdata
);
1296 xgbe_an_enable_interrupts(pdata
);
1298 return xgbe_phy_config_aneg(pdata
);
1301 if (pdata
->dev_irq
!= pdata
->an_irq
)
1302 devm_free_irq(pdata
->dev
, pdata
->an_irq
, pdata
);
1305 pdata
->phy_if
.phy_impl
.stop(pdata
);
1310 static int xgbe_phy_reset(struct xgbe_prv_data
*pdata
)
1314 ret
= pdata
->phy_if
.phy_impl
.reset(pdata
);
1318 /* Disable auto-negotiation for now */
1319 xgbe_an_disable_all(pdata
);
1321 /* Clear auto-negotiation interrupts */
1322 xgbe_an_clear_interrupts_all(pdata
);
1327 static void xgbe_dump_phy_registers(struct xgbe_prv_data
*pdata
)
1329 struct device
*dev
= pdata
->dev
;
1331 dev_dbg(dev
, "\n************* PHY Reg dump **********************\n");
1333 dev_dbg(dev
, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1
,
1334 XMDIO_READ(pdata
, MDIO_MMD_PCS
, MDIO_CTRL1
));
1335 dev_dbg(dev
, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1
,
1336 XMDIO_READ(pdata
, MDIO_MMD_PCS
, MDIO_STAT1
));
1337 dev_dbg(dev
, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1
,
1338 XMDIO_READ(pdata
, MDIO_MMD_PCS
, MDIO_DEVID1
));
1339 dev_dbg(dev
, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2
,
1340 XMDIO_READ(pdata
, MDIO_MMD_PCS
, MDIO_DEVID2
));
1341 dev_dbg(dev
, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1
,
1342 XMDIO_READ(pdata
, MDIO_MMD_PCS
, MDIO_DEVS1
));
1343 dev_dbg(dev
, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2
,
1344 XMDIO_READ(pdata
, MDIO_MMD_PCS
, MDIO_DEVS2
));
1346 dev_dbg(dev
, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1
,
1347 XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_CTRL1
));
1348 dev_dbg(dev
, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1
,
1349 XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_STAT1
));
1350 dev_dbg(dev
, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
1352 XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
));
1353 dev_dbg(dev
, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
1354 MDIO_AN_ADVERTISE
+ 1,
1355 XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
+ 1));
1356 dev_dbg(dev
, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
1357 MDIO_AN_ADVERTISE
+ 2,
1358 XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_ADVERTISE
+ 2));
1359 dev_dbg(dev
, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
1361 XMDIO_READ(pdata
, MDIO_MMD_AN
, MDIO_AN_COMP_STAT
));
1363 dev_dbg(dev
, "\n*************************************************\n");
1366 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data
*pdata
)
1368 if (pdata
->phy
.advertising
& ADVERTISED_10000baseKR_Full
)
1370 else if (pdata
->phy
.advertising
& ADVERTISED_2500baseX_Full
)
1372 else if (pdata
->phy
.advertising
& ADVERTISED_1000baseKX_Full
)
1375 return SPEED_UNKNOWN
;
1378 static void xgbe_phy_exit(struct xgbe_prv_data
*pdata
)
1380 xgbe_phy_stop(pdata
);
1382 pdata
->phy_if
.phy_impl
.exit(pdata
);
1385 static int xgbe_phy_init(struct xgbe_prv_data
*pdata
)
1389 mutex_init(&pdata
->an_mutex
);
1390 INIT_WORK(&pdata
->an_irq_work
, xgbe_an_irq_work
);
1391 INIT_WORK(&pdata
->an_work
, xgbe_an_state_machine
);
1392 pdata
->mdio_mmd
= MDIO_MMD_PCS
;
1394 /* Check for FEC support */
1395 pdata
->fec_ability
= XMDIO_READ(pdata
, MDIO_MMD_PMAPMD
,
1396 MDIO_PMA_10GBR_FECABLE
);
1397 pdata
->fec_ability
&= (MDIO_PMA_10GBR_FECABLE_ABLE
|
1398 MDIO_PMA_10GBR_FECABLE_ERRABLE
);
1400 /* Setup the phy (including supported features) */
1401 ret
= pdata
->phy_if
.phy_impl
.init(pdata
);
1404 pdata
->phy
.advertising
= pdata
->phy
.supported
;
1406 pdata
->phy
.address
= 0;
1408 if (pdata
->phy
.advertising
& ADVERTISED_Autoneg
) {
1409 pdata
->phy
.autoneg
= AUTONEG_ENABLE
;
1410 pdata
->phy
.speed
= SPEED_UNKNOWN
;
1411 pdata
->phy
.duplex
= DUPLEX_UNKNOWN
;
1413 pdata
->phy
.autoneg
= AUTONEG_DISABLE
;
1414 pdata
->phy
.speed
= xgbe_phy_best_advertised_speed(pdata
);
1415 pdata
->phy
.duplex
= DUPLEX_FULL
;
1418 pdata
->phy
.link
= 0;
1420 pdata
->phy
.pause_autoneg
= pdata
->pause_autoneg
;
1421 pdata
->phy
.tx_pause
= pdata
->tx_pause
;
1422 pdata
->phy
.rx_pause
= pdata
->rx_pause
;
1424 /* Fix up Flow Control advertising */
1425 pdata
->phy
.advertising
&= ~ADVERTISED_Pause
;
1426 pdata
->phy
.advertising
&= ~ADVERTISED_Asym_Pause
;
1428 if (pdata
->rx_pause
) {
1429 pdata
->phy
.advertising
|= ADVERTISED_Pause
;
1430 pdata
->phy
.advertising
|= ADVERTISED_Asym_Pause
;
1433 if (pdata
->tx_pause
)
1434 pdata
->phy
.advertising
^= ADVERTISED_Asym_Pause
;
1436 if (netif_msg_drv(pdata
))
1437 xgbe_dump_phy_registers(pdata
);
1442 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if
*phy_if
)
1444 phy_if
->phy_init
= xgbe_phy_init
;
1445 phy_if
->phy_exit
= xgbe_phy_exit
;
1447 phy_if
->phy_reset
= xgbe_phy_reset
;
1448 phy_if
->phy_start
= xgbe_phy_start
;
1449 phy_if
->phy_stop
= xgbe_phy_stop
;
1451 phy_if
->phy_status
= xgbe_phy_status
;
1452 phy_if
->phy_config_aneg
= xgbe_phy_config_aneg
;
1454 phy_if
->phy_valid_speed
= xgbe_phy_valid_speed
;
1456 phy_if
->an_isr
= xgbe_an_combined_isr
;