drivers/net/ethernet/amd/xgbe/xgbe.h

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #ifndef __XGBE_H__
 118 #define __XGBE_H__
 119
 120 #include <linux/dma-mapping.h>
 121 #include <linux/netdevice.h>
 122 #include <linux/workqueue.h>
 123 #include <linux/phy.h>
 124 #include <linux/if_vlan.h>
 125 #include <linux/bitops.h>
 126 #include <linux/ptp_clock_kernel.h>
 127 #include <linux/timecounter.h>
 128 #include <linux/net_tstamp.h>
 129 #include <net/dcbnl.h>
 130
 131 #define XGBE_DRV_NAME           "amd-xgbe"
 132 #define XGBE_DRV_VERSION        "1.0.3"
 133 #define XGBE_DRV_DESC           "AMD 10 Gigabit Ethernet Driver"
 134
 135 /* Descriptor related defines */
 136 #define XGBE_TX_DESC_CNT        512
 137 #define XGBE_TX_DESC_MIN_FREE   (XGBE_TX_DESC_CNT >> 3)
 138 #define XGBE_TX_DESC_MAX_PROC   (XGBE_TX_DESC_CNT >> 1)
 139 #define XGBE_RX_DESC_CNT        512
 140
 141 #define XGBE_TX_MAX_BUF_SIZE    (0x3fff & ~(64 - 1))
 142
 143 /* Descriptors required for maximum contiguous TSO/GSO packet */
 144 #define XGBE_TX_MAX_SPLIT       ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
 145
 146 /* Maximum possible descriptors needed for an SKB:
 147  * - Maximum number of SKB frags
 148  * - Maximum descriptors for contiguous TSO/GSO packet
 149  * - Possible context descriptor
 150  * - Possible TSO header descriptor
 151  */
 152 #define XGBE_TX_MAX_DESCS       (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
 153
 154 #define XGBE_RX_MIN_BUF_SIZE    (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
 155 #define XGBE_RX_BUF_ALIGN       64
 156 #define XGBE_SKB_ALLOC_SIZE     256
 157 #define XGBE_SPH_HDSMS_SIZE     2       /* Keep in sync with SKB_ALLOC_SIZE */
 158
 159 #define XGBE_MAX_DMA_CHANNELS   16
 160 #define XGBE_MAX_QUEUES         16
 161 #define XGBE_PRIORITY_QUEUES    8
 162 #define XGBE_DMA_STOP_TIMEOUT   5
 163
 164 /* DMA cache settings - Outer sharable, write-back, write-allocate */
 165 #define XGBE_DMA_OS_AXDOMAIN    0x2
 166 #define XGBE_DMA_OS_ARCACHE     0xb
 167 #define XGBE_DMA_OS_AWCACHE     0xf
 168
 169 /* DMA cache settings - System, no caches used */
 170 #define XGBE_DMA_SYS_AXDOMAIN   0x3
 171 #define XGBE_DMA_SYS_ARCACHE    0x0
 172 #define XGBE_DMA_SYS_AWCACHE    0x0
 173
 174 #define XGBE_DMA_INTERRUPT_MASK 0x31c7
 175
 176 #define XGMAC_MIN_PACKET        60
 177 #define XGMAC_STD_PACKET_MTU    1500
 178 #define XGMAC_MAX_STD_PACKET    1518
 179 #define XGMAC_JUMBO_PACKET_MTU  9000
 180 #define XGMAC_MAX_JUMBO_PACKET  9018
 181 #define XGMAC_ETH_PREAMBLE      (12 + 8)        /* Inter-frame gap + preamble */
 182
 183 #define XGMAC_PFC_DATA_LEN      46
 184 #define XGMAC_PFC_DELAYS        14000
 185
 186 #define XGMAC_PRIO_QUEUES(_cnt)                                 \
 187         min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt))
 188
 189 /* Common property names */
 190 #define XGBE_MAC_ADDR_PROPERTY  "mac-address"
 191 #define XGBE_PHY_MODE_PROPERTY  "phy-mode"
 192 #define XGBE_DMA_IRQS_PROPERTY  "amd,per-channel-interrupt"
 193 #define XGBE_SPEEDSET_PROPERTY  "amd,speed-set"
 194
 195 /* Device-tree clock names */
 196 #define XGBE_DMA_CLOCK          "dma_clk"
 197 #define XGBE_PTP_CLOCK          "ptp_clk"
 198
 199 /* ACPI property names */
 200 #define XGBE_ACPI_DMA_FREQ      "amd,dma-freq"
 201 #define XGBE_ACPI_PTP_FREQ      "amd,ptp-freq"
 202
 203 /* Timestamp support - values based on 50MHz PTP clock
 204  *   50MHz => 20 nsec
 205  */
 206 #define XGBE_TSTAMP_SSINC       20
 207 #define XGBE_TSTAMP_SNSINC      0
 208
 209 /* Driver PMT macros */
 210 #define XGMAC_DRIVER_CONTEXT    1
 211 #define XGMAC_IOCTL_CONTEXT     2
 212
 213 #define XGMAC_FIFO_RX_MAX       81920
 214 #define XGMAC_FIFO_TX_MAX       81920
 215 #define XGMAC_FIFO_MIN_ALLOC    2048
 216 #define XGMAC_FIFO_UNIT         256
 217 #define XGMAC_FIFO_ALIGN(_x)                            \
 218         (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
 219 #define XGMAC_FIFO_FC_OFF       2048
 220 #define XGMAC_FIFO_FC_MIN       4096
 221
 222 #define XGBE_TC_MIN_QUANTUM     10
 223
 224 /* Helper macro for descriptor handling
 225  *  Always use XGBE_GET_DESC_DATA to access the descriptor data
 226  *  since the index is free-running and needs to be and-ed
 227  *  with the descriptor count value of the ring to index to
 228  *  the proper descriptor data.
 229  */
 230 #define XGBE_GET_DESC_DATA(_ring, _idx)                         \
 231         ((_ring)->rdata +                                       \
 232          ((_idx) & ((_ring)->rdesc_count - 1)))
 233
 234 /* Default coalescing parameters */
 235 #define XGMAC_INIT_DMA_TX_USECS         1000
 236 #define XGMAC_INIT_DMA_TX_FRAMES        25
 237
 238 #define XGMAC_MAX_DMA_RIWT              0xff
 239 #define XGMAC_INIT_DMA_RX_USECS         30
 240 #define XGMAC_INIT_DMA_RX_FRAMES        25
 241
 242 /* Flow control queue count */
 243 #define XGMAC_MAX_FLOW_CONTROL_QUEUES   8
 244
 245 /* Flow control threshold units */
 246 #define XGMAC_FLOW_CONTROL_UNIT         512
 247 #define XGMAC_FLOW_CONTROL_ALIGN(_x)                            \
 248         (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1))
 249 #define XGMAC_FLOW_CONTROL_VALUE(_x)                            \
 250         (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2)
 251 #define XGMAC_FLOW_CONTROL_MAX          33280
 252
 253 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
 254 #define XGBE_MAC_HASH_TABLE_SIZE        8
 255
 256 /* Receive Side Scaling */
 257 #define XGBE_RSS_HASH_KEY_SIZE          40
 258 #define XGBE_RSS_MAX_TABLE_SIZE         256
 259 #define XGBE_RSS_LOOKUP_TABLE_TYPE      0
 260 #define XGBE_RSS_HASH_KEY_TYPE          1
 261
 262 /* Auto-negotiation */
 263 #define XGBE_AN_MS_TIMEOUT              500
 264 #define XGBE_LINK_TIMEOUT               5
 265
 266 #define XGBE_SGMII_AN_LINK_STATUS       BIT(1)
 267 #define XGBE_SGMII_AN_LINK_SPEED        (BIT(2) | BIT(3))
 268 #define XGBE_SGMII_AN_LINK_SPEED_100    0x04
 269 #define XGBE_SGMII_AN_LINK_SPEED_1000   0x08
 270 #define XGBE_SGMII_AN_LINK_DUPLEX       BIT(4)
 271
 272 struct xgbe_prv_data;
 273
 274 struct xgbe_packet_data {
 275         struct sk_buff *skb;
 276
 277         unsigned int attributes;
 278
 279         unsigned int errors;
 280
 281         unsigned int rdesc_count;
 282         unsigned int length;
 283
 284         unsigned int header_len;
 285         unsigned int tcp_header_len;
 286         unsigned int tcp_payload_len;
 287         unsigned short mss;
 288
 289         unsigned short vlan_ctag;
 290
 291         u64 rx_tstamp;
 292
 293         u32 rss_hash;
 294         enum pkt_hash_types rss_hash_type;
 295
 296         unsigned int tx_packets;
 297         unsigned int tx_bytes;
 298 };
 299
 300 /* Common Rx and Tx descriptor mapping */
 301 struct xgbe_ring_desc {
 302         __le32 desc0;
 303         __le32 desc1;
 304         __le32 desc2;
 305         __le32 desc3;
 306 };
 307
 308 /* Page allocation related values */
 309 struct xgbe_page_alloc {
 310         struct page *pages;
 311         unsigned int pages_len;
 312         unsigned int pages_offset;
 313
 314         dma_addr_t pages_dma;
 315 };
 316
 317 /* Ring entry buffer data */
 318 struct xgbe_buffer_data {
 319         struct xgbe_page_alloc pa;
 320         struct xgbe_page_alloc pa_unmap;
 321
 322         dma_addr_t dma_base;
 323         unsigned long dma_off;
 324         unsigned int dma_len;
 325 };
 326
 327 /* Tx-related ring data */
 328 struct xgbe_tx_ring_data {
 329         unsigned int packets;           /* BQL packet count */
 330         unsigned int bytes;             /* BQL byte count */
 331 };
 332
 333 /* Rx-related ring data */
 334 struct xgbe_rx_ring_data {
 335         struct xgbe_buffer_data hdr;    /* Header locations */
 336         struct xgbe_buffer_data buf;    /* Payload locations */
 337
 338         unsigned short hdr_len;         /* Length of received header */
 339         unsigned short len;             /* Length of received packet */
 340 };
 341
 342 /* Structure used to hold information related to the descriptor
 343  * and the packet associated with the descriptor (always use
 344  * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
 345  */
 346 struct xgbe_ring_data {
 347         struct xgbe_ring_desc *rdesc;   /* Virtual address of descriptor */
 348         dma_addr_t rdesc_dma;           /* DMA address of descriptor */
 349
 350         struct sk_buff *skb;            /* Virtual address of SKB */
 351         dma_addr_t skb_dma;             /* DMA address of SKB data */
 352         unsigned int skb_dma_len;       /* Length of SKB DMA area */
 353
 354         struct xgbe_tx_ring_data tx;    /* Tx-related data */
 355         struct xgbe_rx_ring_data rx;    /* Rx-related data */
 356
 357         unsigned int mapped_as_page;
 358
 359         /* Incomplete receive save location.  If the budget is exhausted
 360          * or the last descriptor (last normal descriptor or a following
 361          * context descriptor) has not been DMA'd yet the current state
 362          * of the receive processing needs to be saved.
 363          */
 364         unsigned int state_saved;
 365         struct {
 366                 struct sk_buff *skb;
 367                 unsigned int len;
 368                 unsigned int error;
 369         } state;
 370 };
 371
 372 struct xgbe_ring {
 373         /* Ring lock - used just for TX rings at the moment */
 374         spinlock_t lock;
 375
 376         /* Per packet related information */
 377         struct xgbe_packet_data packet_data;
 378
 379         /* Virtual/DMA addresses and count of allocated descriptor memory */
 380         struct xgbe_ring_desc *rdesc;
 381         dma_addr_t rdesc_dma;
 382         unsigned int rdesc_count;
 383
 384         /* Array of descriptor data corresponding the descriptor memory
 385          * (always use the XGBE_GET_DESC_DATA macro to access this data)
 386          */
 387         struct xgbe_ring_data *rdata;
 388
 389         /* Page allocation for RX buffers */
 390         struct xgbe_page_alloc rx_hdr_pa;
 391         struct xgbe_page_alloc rx_buf_pa;
 392
 393         /* Ring index values
 394          *  cur   - Tx: index of descriptor to be used for current transfer
 395          *          Rx: index of descriptor to check for packet availability
 396          *  dirty - Tx: index of descriptor to check for transfer complete
 397          *          Rx: index of descriptor to check for buffer reallocation
 398          */
 399         unsigned int cur;
 400         unsigned int dirty;
 401
 402         /* Coalesce frame count used for interrupt bit setting */
 403         unsigned int coalesce_count;
 404
 405         union {
 406                 struct {
 407                         unsigned int queue_stopped;
 408                         unsigned int xmit_more;
 409                         unsigned short cur_mss;
 410                         unsigned short cur_vlan_ctag;
 411                 } tx;
 412         };
 413 } ____cacheline_aligned;
 414
 415 /* Structure used to describe the descriptor rings associated with
 416  * a DMA channel.
 417  */
 418 struct xgbe_channel {
 419         char name[16];
 420
 421         /* Address of private data area for device */
 422         struct xgbe_prv_data *pdata;
 423
 424         /* Queue index and base address of queue's DMA registers */
 425         unsigned int queue_index;
 426         void __iomem *dma_regs;
 427
 428         /* Per channel interrupt irq number */
 429         int dma_irq;
 430         char dma_irq_name[IFNAMSIZ + 32];
 431
 432         /* Netdev related settings */
 433         struct napi_struct napi;
 434
 435         unsigned int saved_ier;
 436
 437         unsigned int tx_timer_active;
 438         struct timer_list tx_timer;
 439
 440         struct xgbe_ring *tx_ring;
 441         struct xgbe_ring *rx_ring;
 442 } ____cacheline_aligned;
 443
 444 enum xgbe_state {
 445         XGBE_DOWN,
 446         XGBE_LINK_INIT,
 447         XGBE_LINK_ERR,
 448 };
 449
 450 enum xgbe_int {
 451         XGMAC_INT_DMA_CH_SR_TI,
 452         XGMAC_INT_DMA_CH_SR_TPS,
 453         XGMAC_INT_DMA_CH_SR_TBU,
 454         XGMAC_INT_DMA_CH_SR_RI,
 455         XGMAC_INT_DMA_CH_SR_RBU,
 456         XGMAC_INT_DMA_CH_SR_RPS,
 457         XGMAC_INT_DMA_CH_SR_TI_RI,
 458         XGMAC_INT_DMA_CH_SR_FBE,
 459         XGMAC_INT_DMA_ALL,
 460 };
 461
 462 enum xgbe_int_state {
 463         XGMAC_INT_STATE_SAVE,
 464         XGMAC_INT_STATE_RESTORE,
 465 };
 466
 467 enum xgbe_speed {
 468         XGBE_SPEED_1000 = 0,
 469         XGBE_SPEED_2500,
 470         XGBE_SPEED_10000,
 471         XGBE_SPEEDS,
 472 };
 473
 474 enum xgbe_xpcs_access {
 475         XGBE_XPCS_ACCESS_V1 = 0,
 476         XGBE_XPCS_ACCESS_V2,
 477 };
 478
 479 enum xgbe_an_mode {
 480         XGBE_AN_MODE_CL73 = 0,
 481         XGBE_AN_MODE_CL37,
 482         XGBE_AN_MODE_CL37_SGMII,
 483         XGBE_AN_MODE_NONE,
 484 };
 485
 486 enum xgbe_an {
 487         XGBE_AN_READY = 0,
 488         XGBE_AN_PAGE_RECEIVED,
 489         XGBE_AN_INCOMPAT_LINK,
 490         XGBE_AN_COMPLETE,
 491         XGBE_AN_NO_LINK,
 492         XGBE_AN_ERROR,
 493 };
 494
 495 enum xgbe_rx {
 496         XGBE_RX_BPA = 0,
 497         XGBE_RX_XNP,
 498         XGBE_RX_COMPLETE,
 499         XGBE_RX_ERROR,
 500 };
 501
 502 enum xgbe_mode {
 503         XGBE_MODE_KX_1000 = 0,
 504         XGBE_MODE_KX_2500,
 505         XGBE_MODE_KR,
 506         XGBE_MODE_UNKNOWN,
 507 };
 508
 509 enum xgbe_speedset {
 510         XGBE_SPEEDSET_1000_10000 = 0,
 511         XGBE_SPEEDSET_2500_10000,
 512 };
 513
 514 struct xgbe_phy {
 515         u32 supported;
 516         u32 advertising;
 517         u32 lp_advertising;
 518
 519         int address;
 520
 521         int autoneg;
 522         int speed;
 523         int duplex;
 524
 525         int link;
 526
 527         int pause_autoneg;
 528         int tx_pause;
 529         int rx_pause;
 530 };
 531
 532 struct xgbe_mmc_stats {
 533         /* Tx Stats */
 534         u64 txoctetcount_gb;
 535         u64 txframecount_gb;
 536         u64 txbroadcastframes_g;
 537         u64 txmulticastframes_g;
 538         u64 tx64octets_gb;
 539         u64 tx65to127octets_gb;
 540         u64 tx128to255octets_gb;
 541         u64 tx256to511octets_gb;
 542         u64 tx512to1023octets_gb;
 543         u64 tx1024tomaxoctets_gb;
 544         u64 txunicastframes_gb;
 545         u64 txmulticastframes_gb;
 546         u64 txbroadcastframes_gb;
 547         u64 txunderflowerror;
 548         u64 txoctetcount_g;
 549         u64 txframecount_g;
 550         u64 txpauseframes;
 551         u64 txvlanframes_g;
 552
 553         /* Rx Stats */
 554         u64 rxframecount_gb;
 555         u64 rxoctetcount_gb;
 556         u64 rxoctetcount_g;
 557         u64 rxbroadcastframes_g;
 558         u64 rxmulticastframes_g;
 559         u64 rxcrcerror;
 560         u64 rxrunterror;
 561         u64 rxjabbererror;
 562         u64 rxundersize_g;
 563         u64 rxoversize_g;
 564         u64 rx64octets_gb;
 565         u64 rx65to127octets_gb;
 566         u64 rx128to255octets_gb;
 567         u64 rx256to511octets_gb;
 568         u64 rx512to1023octets_gb;
 569         u64 rx1024tomaxoctets_gb;
 570         u64 rxunicastframes_g;
 571         u64 rxlengtherror;
 572         u64 rxoutofrangetype;
 573         u64 rxpauseframes;
 574         u64 rxfifooverflow;
 575         u64 rxvlanframes_gb;
 576         u64 rxwatchdogerror;
 577 };
 578
 579 struct xgbe_ext_stats {
 580         u64 tx_tso_packets;
 581         u64 rx_split_header_packets;
 582         u64 rx_buffer_unavailable;
 583 };
 584
 585 struct xgbe_hw_if {
 586         int (*tx_complete)(struct xgbe_ring_desc *);
 587
 588         int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
 589         int (*config_rx_mode)(struct xgbe_prv_data *);
 590
 591         int (*enable_rx_csum)(struct xgbe_prv_data *);
 592         int (*disable_rx_csum)(struct xgbe_prv_data *);
 593
 594         int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
 595         int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
 596         int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
 597         int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
 598         int (*update_vlan_hash_table)(struct xgbe_prv_data *);
 599
 600         int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
 601         void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
 602         int (*set_speed)(struct xgbe_prv_data *, int);
 603
 604         void (*enable_tx)(struct xgbe_prv_data *);
 605         void (*disable_tx)(struct xgbe_prv_data *);
 606         void (*enable_rx)(struct xgbe_prv_data *);
 607         void (*disable_rx)(struct xgbe_prv_data *);
 608
 609         void (*powerup_tx)(struct xgbe_prv_data *);
 610         void (*powerdown_tx)(struct xgbe_prv_data *);
 611         void (*powerup_rx)(struct xgbe_prv_data *);
 612         void (*powerdown_rx)(struct xgbe_prv_data *);
 613
 614         int (*init)(struct xgbe_prv_data *);
 615         int (*exit)(struct xgbe_prv_data *);
 616
 617         int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
 618         int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
 619         void (*dev_xmit)(struct xgbe_channel *);
 620         int (*dev_read)(struct xgbe_channel *);
 621         void (*tx_desc_init)(struct xgbe_channel *);
 622         void (*rx_desc_init)(struct xgbe_channel *);
 623         void (*tx_desc_reset)(struct xgbe_ring_data *);
 624         void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *,
 625                               unsigned int);
 626         int (*is_last_desc)(struct xgbe_ring_desc *);
 627         int (*is_context_desc)(struct xgbe_ring_desc *);
 628         void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
 629
 630         /* For FLOW ctrl */
 631         int (*config_tx_flow_control)(struct xgbe_prv_data *);
 632         int (*config_rx_flow_control)(struct xgbe_prv_data *);
 633
 634         /* For RX coalescing */
 635         int (*config_rx_coalesce)(struct xgbe_prv_data *);
 636         int (*config_tx_coalesce)(struct xgbe_prv_data *);
 637         unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
 638         unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
 639
 640         /* For RX and TX threshold config */
 641         int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
 642         int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
 643
 644         /* For RX and TX Store and Forward Mode config */
 645         int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
 646         int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
 647
 648         /* For TX DMA Operate on Second Frame config */
 649         int (*config_osp_mode)(struct xgbe_prv_data *);
 650
 651         /* For RX and TX PBL config */
 652         int (*config_rx_pbl_val)(struct xgbe_prv_data *);
 653         int (*get_rx_pbl_val)(struct xgbe_prv_data *);
 654         int (*config_tx_pbl_val)(struct xgbe_prv_data *);
 655         int (*get_tx_pbl_val)(struct xgbe_prv_data *);
 656         int (*config_pblx8)(struct xgbe_prv_data *);
 657
 658         /* For MMC statistics */
 659         void (*rx_mmc_int)(struct xgbe_prv_data *);
 660         void (*tx_mmc_int)(struct xgbe_prv_data *);
 661         void (*read_mmc_stats)(struct xgbe_prv_data *);
 662
 663         /* For Timestamp config */
 664         int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
 665         void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
 666         void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
 667                                 unsigned int nsec);
 668         u64 (*get_tstamp_time)(struct xgbe_prv_data *);
 669         u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
 670
 671         /* For Data Center Bridging config */
 672         void (*config_tc)(struct xgbe_prv_data *);
 673         void (*config_dcb_tc)(struct xgbe_prv_data *);
 674         void (*config_dcb_pfc)(struct xgbe_prv_data *);
 675
 676         /* For Receive Side Scaling */
 677         int (*enable_rss)(struct xgbe_prv_data *);
 678         int (*disable_rss)(struct xgbe_prv_data *);
 679         int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
 680         int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
 681 };
 682
 683 /* This structure represents implementation specific routines for an
 684  * implementation of a PHY. All routines are required unless noted below.
 685  *   Optional routines:
 686  *     kr_training_pre, kr_training_post
 687  */
 688 struct xgbe_phy_impl_if {
 689         /* Perform Setup/teardown actions */
 690         int (*init)(struct xgbe_prv_data *);
 691         void (*exit)(struct xgbe_prv_data *);
 692
 693         /* Perform start/stop specific actions */
 694         int (*reset)(struct xgbe_prv_data *);
 695         int (*start)(struct xgbe_prv_data *);
 696         void (*stop)(struct xgbe_prv_data *);
 697
 698         /* Return the link status */
 699         int (*link_status)(struct xgbe_prv_data *);
 700
 701         /* Indicate if a particular speed is valid */
 702         bool (*valid_speed)(struct xgbe_prv_data *, int);
 703
 704         /* Check if the specified mode can/should be used */
 705         bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode);
 706         /* Switch the PHY into various modes */
 707         void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode);
 708         /* Retrieve mode needed for a specific speed */
 709         enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int);
 710         /* Retrieve new/next mode when trying to auto-negotiate */
 711         enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *);
 712         /* Retrieve current mode */
 713         enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *);
 714
 715         /* Retrieve current auto-negotiation mode */
 716         enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *);
 717
 718         /* Process results of auto-negotiation */
 719         enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *);
 720
 721         /* Pre/Post KR training enablement support */
 722         void (*kr_training_pre)(struct xgbe_prv_data *);
 723         void (*kr_training_post)(struct xgbe_prv_data *);
 724 };
 725
 726 struct xgbe_phy_if {
 727         /* For PHY setup/teardown */
 728         int (*phy_init)(struct xgbe_prv_data *);
 729         void (*phy_exit)(struct xgbe_prv_data *);
 730
 731         /* For PHY support when setting device up/down */
 732         int (*phy_reset)(struct xgbe_prv_data *);
 733         int (*phy_start)(struct xgbe_prv_data *);
 734         void (*phy_stop)(struct xgbe_prv_data *);
 735
 736         /* For PHY support while device is up */
 737         void (*phy_status)(struct xgbe_prv_data *);
 738         int (*phy_config_aneg)(struct xgbe_prv_data *);
 739
 740         /* For PHY settings validation */
 741         bool (*phy_valid_speed)(struct xgbe_prv_data *, int);
 742
 743         /* PHY implementation specific services */
 744         struct xgbe_phy_impl_if phy_impl;
 745 };
 746
 747 struct xgbe_desc_if {
 748         int (*alloc_ring_resources)(struct xgbe_prv_data *);
 749         void (*free_ring_resources)(struct xgbe_prv_data *);
 750         int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
 751         int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
 752                              struct xgbe_ring_data *);
 753         void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
 754         void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
 755         void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
 756 };
 757
 758 /* This structure contains flags that indicate what hardware features
 759  * or configurations are present in the device.
 760  */
 761 struct xgbe_hw_features {
 762         /* HW Version */
 763         unsigned int version;
 764
 765         /* HW Feature Register0 */
 766         unsigned int gmii;              /* 1000 Mbps support */
 767         unsigned int vlhash;            /* VLAN Hash Filter */
 768         unsigned int sma;               /* SMA(MDIO) Interface */
 769         unsigned int rwk;               /* PMT remote wake-up packet */
 770         unsigned int mgk;               /* PMT magic packet */
 771         unsigned int mmc;               /* RMON module */
 772         unsigned int aoe;               /* ARP Offload */
 773         unsigned int ts;                /* IEEE 1588-2008 Advanced Timestamp */
 774         unsigned int eee;               /* Energy Efficient Ethernet */
 775         unsigned int tx_coe;            /* Tx Checksum Offload */
 776         unsigned int rx_coe;            /* Rx Checksum Offload */
 777         unsigned int addn_mac;          /* Additional MAC Addresses */
 778         unsigned int ts_src;            /* Timestamp Source */
 779         unsigned int sa_vlan_ins;       /* Source Address or VLAN Insertion */
 780
 781         /* HW Feature Register1 */
 782         unsigned int rx_fifo_size;      /* MTL Receive FIFO Size */
 783         unsigned int tx_fifo_size;      /* MTL Transmit FIFO Size */
 784         unsigned int adv_ts_hi;         /* Advance Timestamping High Word */
 785         unsigned int dma_width;         /* DMA width */
 786         unsigned int dcb;               /* DCB Feature */
 787         unsigned int sph;               /* Split Header Feature */
 788         unsigned int tso;               /* TCP Segmentation Offload */
 789         unsigned int dma_debug;         /* DMA Debug Registers */
 790         unsigned int rss;               /* Receive Side Scaling */
 791         unsigned int tc_cnt;            /* Number of Traffic Classes */
 792         unsigned int hash_table_size;   /* Hash Table Size */
 793         unsigned int l3l4_filter_num;   /* Number of L3-L4 Filters */
 794
 795         /* HW Feature Register2 */
 796         unsigned int rx_q_cnt;          /* Number of MTL Receive Queues */
 797         unsigned int tx_q_cnt;          /* Number of MTL Transmit Queues */
 798         unsigned int rx_ch_cnt;         /* Number of DMA Receive Channels */
 799         unsigned int tx_ch_cnt;         /* Number of DMA Transmit Channels */
 800         unsigned int pps_out_num;       /* Number of PPS outputs */
 801         unsigned int aux_snap_num;      /* Number of Aux snapshot inputs */
 802 };
 803
 804 struct xgbe_version_data {
 805         void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *);
 806         enum xgbe_xpcs_access xpcs_access;
 807         unsigned int mmc_64bit;
 808 };
 809
 810 struct xgbe_prv_data {
 811         struct net_device *netdev;
 812         struct platform_device *pdev;
 813         struct acpi_device *adev;
 814         struct device *dev;
 815         struct platform_device *phy_pdev;
 816         struct device *phy_dev;
 817
 818         /* Version related data */
 819         struct xgbe_version_data *vdata;
 820
 821         /* ACPI or DT flag */
 822         unsigned int use_acpi;
 823
 824         /* XGMAC/XPCS related mmio registers */
 825         void __iomem *xgmac_regs;       /* XGMAC CSRs */
 826         void __iomem *xpcs_regs;        /* XPCS MMD registers */
 827         void __iomem *rxtx_regs;        /* SerDes Rx/Tx CSRs */
 828         void __iomem *sir0_regs;        /* SerDes integration registers (1/2) */
 829         void __iomem *sir1_regs;        /* SerDes integration registers (2/2) */
 830
 831         /* Overall device lock */
 832         spinlock_t lock;
 833
 834         /* XPCS indirect addressing lock */
 835         spinlock_t xpcs_lock;
 836         unsigned int xpcs_window;
 837         unsigned int xpcs_window_size;
 838         unsigned int xpcs_window_mask;
 839
 840         /* RSS addressing mutex */
 841         struct mutex rss_mutex;
 842
 843         /* Flags representing xgbe_state */
 844         unsigned long dev_state;
 845
 846         int dev_irq;
 847         unsigned int per_channel_irq;
 848
 849         struct xgbe_hw_if hw_if;
 850         struct xgbe_phy_if phy_if;
 851         struct xgbe_desc_if desc_if;
 852
 853         /* AXI DMA settings */
 854         unsigned int coherent;
 855         unsigned int axdomain;
 856         unsigned int arcache;
 857         unsigned int awcache;
 858
 859         /* Service routine support */
 860         struct workqueue_struct *dev_workqueue;
 861         struct work_struct service_work;
 862         struct timer_list service_timer;
 863
 864         /* Rings for Tx/Rx on a DMA channel */
 865         struct xgbe_channel *channel;
 866         unsigned int channel_count;
 867         unsigned int tx_ring_count;
 868         unsigned int tx_desc_count;
 869         unsigned int rx_ring_count;
 870         unsigned int rx_desc_count;
 871
 872         unsigned int tx_q_count;
 873         unsigned int rx_q_count;
 874
 875         /* Tx/Rx common settings */
 876         unsigned int pblx8;
 877
 878         /* Tx settings */
 879         unsigned int tx_sf_mode;
 880         unsigned int tx_threshold;
 881         unsigned int tx_pbl;
 882         unsigned int tx_osp_mode;
 883
 884         /* Rx settings */
 885         unsigned int rx_sf_mode;
 886         unsigned int rx_threshold;
 887         unsigned int rx_pbl;
 888
 889         /* Tx coalescing settings */
 890         unsigned int tx_usecs;
 891         unsigned int tx_frames;
 892
 893         /* Rx coalescing settings */
 894         unsigned int rx_riwt;
 895         unsigned int rx_usecs;
 896         unsigned int rx_frames;
 897
 898         /* Current Rx buffer size */
 899         unsigned int rx_buf_size;
 900
 901         /* Flow control settings */
 902         unsigned int pause_autoneg;
 903         unsigned int tx_pause;
 904         unsigned int rx_pause;
 905         unsigned int rx_rfa[XGBE_MAX_QUEUES];
 906         unsigned int rx_rfd[XGBE_MAX_QUEUES];
 907
 908         /* Receive Side Scaling settings */
 909         u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
 910         u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
 911         u32 rss_options;
 912
 913         /* Netdev related settings */
 914         unsigned char mac_addr[ETH_ALEN];
 915         netdev_features_t netdev_features;
 916         struct napi_struct napi;
 917         struct xgbe_mmc_stats mmc_stats;
 918         struct xgbe_ext_stats ext_stats;
 919
 920         /* Filtering support */
 921         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 922
 923         /* Device clocks */
 924         struct clk *sysclk;
 925         unsigned long sysclk_rate;
 926         struct clk *ptpclk;
 927         unsigned long ptpclk_rate;
 928
 929         /* Timestamp support */
 930         spinlock_t tstamp_lock;
 931         struct ptp_clock_info ptp_clock_info;
 932         struct ptp_clock *ptp_clock;
 933         struct hwtstamp_config tstamp_config;
 934         struct cyclecounter tstamp_cc;
 935         struct timecounter tstamp_tc;
 936         unsigned int tstamp_addend;
 937         struct work_struct tx_tstamp_work;
 938         struct sk_buff *tx_tstamp_skb;
 939         u64 tx_tstamp;
 940
 941         /* DCB support */
 942         struct ieee_ets *ets;
 943         struct ieee_pfc *pfc;
 944         unsigned int q2tc_map[XGBE_MAX_QUEUES];
 945         unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
 946         unsigned int pfcq[XGBE_MAX_QUEUES];
 947         unsigned int pfc_rfa;
 948         u8 num_tcs;
 949
 950         /* Hardware features of the device */
 951         struct xgbe_hw_features hw_feat;
 952
 953         /* Device restart work structure */
 954         struct work_struct restart_work;
 955
 956         /* Keeps track of power mode */
 957         unsigned int power_down;
 958
 959         /* Network interface message level setting */
 960         u32 msg_enable;
 961
 962         /* Current PHY settings */
 963         phy_interface_t phy_mode;
 964         int phy_link;
 965         int phy_speed;
 966
 967         /* MDIO/PHY related settings */
 968         unsigned int phy_started;
 969         void *phy_data;
 970         struct xgbe_phy phy;
 971         int mdio_mmd;
 972         unsigned long link_check;
 973
 974         char an_name[IFNAMSIZ + 32];
 975         struct workqueue_struct *an_workqueue;
 976
 977         int an_irq;
 978         struct work_struct an_irq_work;
 979
 980         /* Auto-negotiation state machine support */
 981         unsigned int an_int;
 982         unsigned int an_status;
 983         struct mutex an_mutex;
 984         enum xgbe_an an_result;
 985         enum xgbe_an an_state;
 986         enum xgbe_rx kr_state;
 987         enum xgbe_rx kx_state;
 988         struct work_struct an_work;
 989         unsigned int an_supported;
 990         unsigned int parallel_detect;
 991         unsigned int fec_ability;
 992         unsigned long an_start;
 993         enum xgbe_an_mode an_mode;
 994
 995         unsigned int lpm_ctrl;          /* CTRL1 for resume */
 996
 997 #ifdef CONFIG_DEBUG_FS
 998         struct dentry *xgbe_debugfs;
 999
1000         unsigned int debugfs_xgmac_reg;
1001
1002         unsigned int debugfs_xpcs_mmd;
1003         unsigned int debugfs_xpcs_reg;
1004 #endif
1005 };
1006
1007 /* Function prototypes*/
1008
1009 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
1010 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
1011 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *);
1012 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
1013 const struct net_device_ops *xgbe_get_netdev_ops(void);
1014 const struct ethtool_ops *xgbe_get_ethtool_ops(void);
1015
1016 #ifdef CONFIG_AMD_XGBE_DCB
1017 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
1018 #endif
1019
1020 void xgbe_ptp_register(struct xgbe_prv_data *);
1021 void xgbe_ptp_unregister(struct xgbe_prv_data *);
1022 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1023                        unsigned int, unsigned int, unsigned int);
1024 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1025                        unsigned int);
1026 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
1027 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
1028 int xgbe_powerup(struct net_device *, unsigned int);
1029 int xgbe_powerdown(struct net_device *, unsigned int);
1030 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
1031 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
1032
1033 #ifdef CONFIG_DEBUG_FS
1034 void xgbe_debugfs_init(struct xgbe_prv_data *);
1035 void xgbe_debugfs_exit(struct xgbe_prv_data *);
1036 #else
1037 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
1038 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
1039 #endif /* CONFIG_DEBUG_FS */
1040
1041 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
1042 #if 0
1043 #define YDEBUG
1044 #define YDEBUG_MDIO
1045 #endif
1046
1047 /* For debug prints */
1048 #ifdef YDEBUG
1049 #define DBGPR(x...) pr_alert(x)
1050 #else
1051 #define DBGPR(x...) do { } while (0)
1052 #endif
1053
1054 #ifdef YDEBUG_MDIO
1055 #define DBGPR_MDIO(x...) pr_alert(x)
1056 #else
1057 #define DBGPR_MDIO(x...) do { } while (0)
1058 #endif
1059
1060 #endif