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[thirdparty/kernel/linux.git] / drivers / net / ethernet / aquantia / atlantic / hw_atl / hw_atl_a0.c
1 /*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10 /* File hw_atl_a0.c: Definition of Atlantic hardware specific functions. */
11
12 #include "../aq_hw.h"
13 #include "../aq_hw_utils.h"
14 #include "../aq_ring.h"
15 #include "../aq_nic.h"
16 #include "hw_atl_a0.h"
17 #include "hw_atl_utils.h"
18 #include "hw_atl_llh.h"
19 #include "hw_atl_a0_internal.h"
20
21 #define DEFAULT_A0_BOARD_BASIC_CAPABILITIES \
22 .is_64_dma = true, \
23 .msix_irqs = 4U, \
24 .irq_mask = ~0U, \
25 .vecs = HW_ATL_A0_RSS_MAX, \
26 .tcs = HW_ATL_A0_TC_MAX, \
27 .rxd_alignment = 1U, \
28 .rxd_size = HW_ATL_A0_RXD_SIZE, \
29 .rxds_max = HW_ATL_A0_MAX_RXD, \
30 .rxds_min = HW_ATL_A0_MIN_RXD, \
31 .txd_alignment = 1U, \
32 .txd_size = HW_ATL_A0_TXD_SIZE, \
33 .txds_max = HW_ATL_A0_MAX_TXD, \
34 .txds_min = HW_ATL_A0_MIN_RXD, \
35 .txhwb_alignment = 4096U, \
36 .tx_rings = HW_ATL_A0_TX_RINGS, \
37 .rx_rings = HW_ATL_A0_RX_RINGS, \
38 .hw_features = NETIF_F_HW_CSUM | \
39 NETIF_F_RXHASH | \
40 NETIF_F_RXCSUM | \
41 NETIF_F_SG | \
42 NETIF_F_TSO, \
43 .hw_priv_flags = IFF_UNICAST_FLT, \
44 .flow_control = true, \
45 .mtu = HW_ATL_A0_MTU_JUMBO, \
46 .mac_regs_count = 88, \
47 .hw_alive_check_addr = 0x10U
48
49 const struct aq_hw_caps_s hw_atl_a0_caps_aqc100 = {
50 DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
51 .media_type = AQ_HW_MEDIA_TYPE_FIBRE,
52 .link_speed_msk = AQ_NIC_RATE_5G |
53 AQ_NIC_RATE_2GS |
54 AQ_NIC_RATE_1G |
55 AQ_NIC_RATE_100M,
56 };
57
58 const struct aq_hw_caps_s hw_atl_a0_caps_aqc107 = {
59 DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
60 .media_type = AQ_HW_MEDIA_TYPE_TP,
61 .link_speed_msk = AQ_NIC_RATE_10G |
62 AQ_NIC_RATE_5G |
63 AQ_NIC_RATE_2GS |
64 AQ_NIC_RATE_1G |
65 AQ_NIC_RATE_100M,
66 };
67
68 const struct aq_hw_caps_s hw_atl_a0_caps_aqc108 = {
69 DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
70 .media_type = AQ_HW_MEDIA_TYPE_TP,
71 .link_speed_msk = AQ_NIC_RATE_5G |
72 AQ_NIC_RATE_2GS |
73 AQ_NIC_RATE_1G |
74 AQ_NIC_RATE_100M,
75 };
76
77 const struct aq_hw_caps_s hw_atl_a0_caps_aqc109 = {
78 DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
79 .media_type = AQ_HW_MEDIA_TYPE_TP,
80 .link_speed_msk = AQ_NIC_RATE_2GS |
81 AQ_NIC_RATE_1G |
82 AQ_NIC_RATE_100M,
83 };
84
85 static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
86 {
87 int err = 0;
88 u32 val;
89
90 hw_atl_glb_glb_reg_res_dis_set(self, 1U);
91 hw_atl_pci_pci_reg_res_dis_set(self, 0U);
92 hw_atl_rx_rx_reg_res_dis_set(self, 0U);
93 hw_atl_tx_tx_reg_res_dis_set(self, 0U);
94
95 HW_ATL_FLUSH();
96 hw_atl_glb_soft_res_set(self, 1);
97
98 /* check 10 times by 1ms */
99 err = readx_poll_timeout_atomic(hw_atl_glb_soft_res_get,
100 self, val, val == 0,
101 1000U, 10000U);
102 if (err < 0)
103 goto err_exit;
104
105 hw_atl_itr_irq_reg_res_dis_set(self, 0U);
106 hw_atl_itr_res_irq_set(self, 1U);
107
108 /* check 10 times by 1ms */
109 err = readx_poll_timeout_atomic(hw_atl_itr_res_irq_get,
110 self, val, val == 0,
111 1000U, 10000U);
112 if (err < 0)
113 goto err_exit;
114
115 self->aq_fw_ops->set_state(self, MPI_RESET);
116
117 err = aq_hw_err_from_flags(self);
118
119 err_exit:
120 return err;
121 }
122
123 static int hw_atl_a0_hw_qos_set(struct aq_hw_s *self)
124 {
125 u32 tc = 0U;
126 u32 buff_size = 0U;
127 unsigned int i_priority = 0U;
128 bool is_rx_flow_control = false;
129
130 /* TPS Descriptor rate init */
131 hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
132 hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
133
134 /* TPS VM init */
135 hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
136
137 /* TPS TC credits init */
138 hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
139 hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
140
141 hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
142 hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
143 hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
144 hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
145
146 /* Tx buf size */
147 buff_size = HW_ATL_A0_TXBUF_MAX;
148
149 hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
150 hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,
151 (buff_size *
152 (1024 / 32U) * 66U) /
153 100U, tc);
154 hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,
155 (buff_size *
156 (1024 / 32U) * 50U) /
157 100U, tc);
158
159 /* QoS Rx buf size per TC */
160 tc = 0;
161 is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
162 buff_size = HW_ATL_A0_RXBUF_MAX;
163
164 hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
165 hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,
166 (buff_size *
167 (1024U / 32U) * 66U) /
168 100U, tc);
169 hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,
170 (buff_size *
171 (1024U / 32U) * 50U) /
172 100U, tc);
173 hw_atl_rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
174
175 /* QoS 802.1p priority -> TC mapping */
176 for (i_priority = 8U; i_priority--;)
177 hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
178
179 return aq_hw_err_from_flags(self);
180 }
181
182 static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self,
183 struct aq_rss_parameters *rss_params)
184 {
185 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
186 int err = 0;
187 unsigned int i = 0U;
188 unsigned int addr = 0U;
189 u32 val;
190
191 for (i = 10, addr = 0U; i--; ++addr) {
192 u32 key_data = cfg->is_rss ?
193 __swab32(rss_params->hash_secret_key[i]) : 0U;
194 hw_atl_rpf_rss_key_wr_data_set(self, key_data);
195 hw_atl_rpf_rss_key_addr_set(self, addr);
196 hw_atl_rpf_rss_key_wr_en_set(self, 1U);
197 err = readx_poll_timeout_atomic(hw_atl_rpf_rss_key_wr_en_get,
198 self, val, val == 0,
199 1000U, 10000U);
200 if (err < 0)
201 goto err_exit;
202 }
203
204 err = aq_hw_err_from_flags(self);
205
206 err_exit:
207 return err;
208 }
209
210 static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self,
211 struct aq_rss_parameters *rss_params)
212 {
213 u8 *indirection_table = rss_params->indirection_table;
214 u32 i = 0U;
215 u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
216 int err = 0;
217 u16 bitary[1 + (HW_ATL_A0_RSS_REDIRECTION_MAX *
218 HW_ATL_A0_RSS_REDIRECTION_BITS / 16U)];
219 u32 val;
220
221 memset(bitary, 0, sizeof(bitary));
222
223 for (i = HW_ATL_A0_RSS_REDIRECTION_MAX; i--; ) {
224 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
225 ((indirection_table[i] % num_rss_queues) <<
226 ((i * 3U) & 0xFU));
227 }
228
229 for (i = ARRAY_SIZE(bitary); i--;) {
230 hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
231 hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
232 hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
233 err = readx_poll_timeout_atomic(hw_atl_rpf_rss_redir_wr_en_get,
234 self, val, val == 0,
235 1000U, 10000U);
236 if (err < 0)
237 goto err_exit;
238 }
239
240 err = aq_hw_err_from_flags(self);
241
242 err_exit:
243 return err;
244 }
245
246 static int hw_atl_a0_hw_offload_set(struct aq_hw_s *self,
247 struct aq_nic_cfg_s *aq_nic_cfg)
248 {
249 /* TX checksums offloads*/
250 hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);
251 hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);
252
253 /* RX checksums offloads*/
254 hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1);
255 hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1);
256
257 /* LSO offloads*/
258 hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
259
260 return aq_hw_err_from_flags(self);
261 }
262
263 static int hw_atl_a0_hw_init_tx_path(struct aq_hw_s *self)
264 {
265 hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
266 hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
267 hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
268
269 /* Tx interrupts */
270 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
271
272 /* misc */
273 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
274 0x00010000U : 0x00000000U);
275 hw_atl_tdm_tx_dca_en_set(self, 0U);
276 hw_atl_tdm_tx_dca_mode_set(self, 0U);
277
278 hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);
279
280 return aq_hw_err_from_flags(self);
281 }
282
283 static int hw_atl_a0_hw_init_rx_path(struct aq_hw_s *self)
284 {
285 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
286 int i;
287
288 /* Rx TC/RSS number config */
289 hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U);
290
291 /* Rx flow control */
292 hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);
293
294 /* RSS Ring selection */
295 hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?
296 0xB3333333U : 0x00000000U);
297
298 /* Multicast filters */
299 for (i = HW_ATL_A0_MAC_MAX; i--;) {
300 hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
301 hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);
302 }
303
304 hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
305 hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
306
307 /* Vlan filters */
308 hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);
309 hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);
310 hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
311
312 /* Rx Interrupts */
313 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
314
315 /* misc */
316 hw_atl_rpfl2broadcast_flr_act_set(self, 1U);
317 hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
318
319 hw_atl_rdm_rx_dca_en_set(self, 0U);
320 hw_atl_rdm_rx_dca_mode_set(self, 0U);
321
322 return aq_hw_err_from_flags(self);
323 }
324
325 static int hw_atl_a0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
326 {
327 int err = 0;
328 unsigned int h = 0U;
329 unsigned int l = 0U;
330
331 if (!mac_addr) {
332 err = -EINVAL;
333 goto err_exit;
334 }
335 h = (mac_addr[0] << 8) | (mac_addr[1]);
336 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
337 (mac_addr[4] << 8) | mac_addr[5];
338
339 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC);
340 hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_A0_MAC);
341 hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_A0_MAC);
342 hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_A0_MAC);
343
344 err = aq_hw_err_from_flags(self);
345
346 err_exit:
347 return err;
348 }
349
350 static int hw_atl_a0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
351 {
352 static u32 aq_hw_atl_igcr_table_[4][2] = {
353 [AQ_HW_IRQ_INVALID] = { 0x20000000U, 0x20000000U },
354 [AQ_HW_IRQ_LEGACY] = { 0x20000080U, 0x20000080U },
355 [AQ_HW_IRQ_MSI] = { 0x20000021U, 0x20000025U },
356 [AQ_HW_IRQ_MSIX] = { 0x20000022U, 0x20000026U },
357 };
358
359 int err = 0;
360
361 struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg;
362
363 hw_atl_a0_hw_init_tx_path(self);
364 hw_atl_a0_hw_init_rx_path(self);
365
366 hw_atl_a0_hw_mac_addr_set(self, mac_addr);
367
368 self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk);
369 self->aq_fw_ops->set_state(self, MPI_INIT);
370
371 hw_atl_reg_tx_dma_debug_ctl_set(self, 0x800000b8U);
372 hw_atl_reg_tx_dma_debug_ctl_set(self, 0x000000b8U);
373
374 hw_atl_a0_hw_qos_set(self);
375 hw_atl_a0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
376 hw_atl_a0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
377
378 /* Reset link status and read out initial hardware counters */
379 self->aq_link_status.mbps = 0;
380 self->aq_fw_ops->update_stats(self);
381
382 err = aq_hw_err_from_flags(self);
383 if (err < 0)
384 goto err_exit;
385
386 /* Interrupts */
387 hw_atl_reg_irq_glb_ctl_set(self,
388 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
389 [(aq_nic_cfg->vecs > 1U) ? 1 : 0]);
390
391 hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
392
393 /* Interrupts */
394 hw_atl_reg_gen_irq_map_set(self,
395 ((HW_ATL_A0_ERR_INT << 0x18) | (1U << 0x1F)) |
396 ((HW_ATL_A0_ERR_INT << 0x10) | (1U << 0x17)) |
397 ((HW_ATL_A0_ERR_INT << 8) | (1U << 0xF)) |
398 ((HW_ATL_A0_ERR_INT) | (1U << 0x7)), 0U);
399
400 hw_atl_a0_hw_offload_set(self, aq_nic_cfg);
401
402 err_exit:
403 return err;
404 }
405
406 static int hw_atl_a0_hw_ring_tx_start(struct aq_hw_s *self,
407 struct aq_ring_s *ring)
408 {
409 hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx);
410 return aq_hw_err_from_flags(self);
411 }
412
413 static int hw_atl_a0_hw_ring_rx_start(struct aq_hw_s *self,
414 struct aq_ring_s *ring)
415 {
416 hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx);
417 return aq_hw_err_from_flags(self);
418 }
419
420 static int hw_atl_a0_hw_start(struct aq_hw_s *self)
421 {
422 hw_atl_tpb_tx_buff_en_set(self, 1);
423 hw_atl_rpb_rx_buff_en_set(self, 1);
424 return aq_hw_err_from_flags(self);
425 }
426
427 static int hw_atl_a0_hw_tx_ring_tail_update(struct aq_hw_s *self,
428 struct aq_ring_s *ring)
429 {
430 hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
431 return 0;
432 }
433
434 static int hw_atl_a0_hw_ring_tx_xmit(struct aq_hw_s *self,
435 struct aq_ring_s *ring,
436 unsigned int frags)
437 {
438 struct aq_ring_buff_s *buff = NULL;
439 struct hw_atl_txd_s *txd = NULL;
440 unsigned int buff_pa_len = 0U;
441 unsigned int pkt_len = 0U;
442 unsigned int frag_count = 0U;
443 bool is_gso = false;
444
445 buff = &ring->buff_ring[ring->sw_tail];
446 pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
447
448 for (frag_count = 0; frag_count < frags; frag_count++) {
449 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
450 HW_ATL_A0_TXD_SIZE];
451 txd->ctl = 0;
452 txd->ctl2 = 0;
453 txd->buf_addr = 0;
454
455 buff = &ring->buff_ring[ring->sw_tail];
456
457 if (buff->is_txc) {
458 txd->ctl |= (buff->len_l3 << 31) |
459 (buff->len_l2 << 24) |
460 HW_ATL_A0_TXD_CTL_CMD_TCP |
461 HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC;
462 txd->ctl2 |= (buff->mss << 16) |
463 (buff->len_l4 << 8) |
464 (buff->len_l3 >> 1);
465
466 pkt_len -= (buff->len_l4 +
467 buff->len_l3 +
468 buff->len_l2);
469 is_gso = true;
470
471 if (buff->is_ipv6)
472 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_IPV6;
473 } else {
474 buff_pa_len = buff->len;
475
476 txd->buf_addr = buff->pa;
477 txd->ctl |= (HW_ATL_A0_TXD_CTL_BLEN &
478 ((u32)buff_pa_len << 4));
479 txd->ctl |= HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD;
480 /* PAY_LEN */
481 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_LEN & (pkt_len << 14);
482
483 if (is_gso) {
484 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_LSO;
485 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_CTX_EN;
486 }
487
488 /* Tx checksum offloads */
489 if (buff->is_ip_cso)
490 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_IPCSO;
491
492 if (buff->is_udp_cso || buff->is_tcp_cso)
493 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_TUCSO;
494
495 if (unlikely(buff->is_eop)) {
496 txd->ctl |= HW_ATL_A0_TXD_CTL_EOP;
497 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_WB;
498 is_gso = false;
499 }
500 }
501
502 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
503 }
504
505 hw_atl_a0_hw_tx_ring_tail_update(self, ring);
506 return aq_hw_err_from_flags(self);
507 }
508
509 static int hw_atl_a0_hw_ring_rx_init(struct aq_hw_s *self,
510 struct aq_ring_s *aq_ring,
511 struct aq_ring_param_s *aq_ring_param)
512 {
513 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
514 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
515
516 hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx);
517
518 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
519
520 hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
521 aq_ring->idx);
522
523 hw_atl_reg_rx_dma_desc_base_addressmswset(self,
524 dma_desc_addr_msw,
525 aq_ring->idx);
526
527 hw_atl_rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
528
529 hw_atl_rdm_rx_desc_data_buff_size_set(self,
530 AQ_CFG_RX_FRAME_MAX / 1024U,
531 aq_ring->idx);
532
533 hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
534 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
535 hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
536
537 /* Rx ring set mode */
538
539 /* Mapping interrupt vector */
540 hw_atl_itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
541 hw_atl_itr_irq_map_en_rx_set(self, true, aq_ring->idx);
542
543 hw_atl_rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
544 hw_atl_rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
545 hw_atl_rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
546 hw_atl_rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
547
548 return aq_hw_err_from_flags(self);
549 }
550
551 static int hw_atl_a0_hw_ring_tx_init(struct aq_hw_s *self,
552 struct aq_ring_s *aq_ring,
553 struct aq_ring_param_s *aq_ring_param)
554 {
555 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
556 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
557
558 hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
559 aq_ring->idx);
560
561 hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
562 aq_ring->idx);
563
564 hw_atl_tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
565
566 hw_atl_a0_hw_tx_ring_tail_update(self, aq_ring);
567
568 /* Set Tx threshold */
569 hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
570
571 /* Mapping interrupt vector */
572 hw_atl_itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
573 hw_atl_itr_irq_map_en_tx_set(self, true, aq_ring->idx);
574
575 hw_atl_tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
576 hw_atl_tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
577
578 return aq_hw_err_from_flags(self);
579 }
580
581 static int hw_atl_a0_hw_ring_rx_fill(struct aq_hw_s *self,
582 struct aq_ring_s *ring,
583 unsigned int sw_tail_old)
584 {
585 for (; sw_tail_old != ring->sw_tail;
586 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
587 struct hw_atl_rxd_s *rxd =
588 (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
589 HW_ATL_A0_RXD_SIZE];
590
591 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
592
593 rxd->buf_addr = buff->pa;
594 rxd->hdr_addr = 0U;
595 }
596
597 hw_atl_reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
598
599 return aq_hw_err_from_flags(self);
600 }
601
602 static int hw_atl_a0_hw_ring_tx_head_update(struct aq_hw_s *self,
603 struct aq_ring_s *ring)
604 {
605 int err = 0;
606 unsigned int hw_head = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);
607
608 if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
609 err = -ENXIO;
610 goto err_exit;
611 }
612 ring->hw_head = hw_head;
613 err = aq_hw_err_from_flags(self);
614
615 err_exit:
616 return err;
617 }
618
619 static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s *self,
620 struct aq_ring_s *ring)
621 {
622 for (; ring->hw_head != ring->sw_tail;
623 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
624 struct aq_ring_buff_s *buff = NULL;
625 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
626 &ring->dx_ring[ring->hw_head * HW_ATL_A0_RXD_SIZE];
627
628 unsigned int is_err = 1U;
629 unsigned int is_rx_check_sum_enabled = 0U;
630 unsigned int pkt_type = 0U;
631
632 if (!(rxd_wb->status & 0x5U)) { /* RxD is not done */
633 if ((1U << 4) &
634 hw_atl_reg_rx_dma_desc_status_get(self, ring->idx)) {
635 hw_atl_rdm_rx_desc_en_set(self, false, ring->idx);
636 hw_atl_rdm_rx_desc_res_set(self, true, ring->idx);
637 hw_atl_rdm_rx_desc_res_set(self, false, ring->idx);
638 hw_atl_rdm_rx_desc_en_set(self, true, ring->idx);
639 }
640
641 if (ring->hw_head ||
642 (hw_atl_rdm_rx_desc_head_ptr_get(self,
643 ring->idx) < 2U)) {
644 break;
645 } else if (!(rxd_wb->status & 0x1U)) {
646 struct hw_atl_rxd_wb_s *rxd_wb1 =
647 (struct hw_atl_rxd_wb_s *)
648 (&ring->dx_ring[(1U) *
649 HW_ATL_A0_RXD_SIZE]);
650
651 if ((rxd_wb1->status & 0x1U)) {
652 rxd_wb->pkt_len = 1514U;
653 rxd_wb->status = 3U;
654 } else {
655 break;
656 }
657 }
658 }
659
660 buff = &ring->buff_ring[ring->hw_head];
661
662 if (0x3U != (rxd_wb->status & 0x3U))
663 rxd_wb->status |= 4;
664
665 is_err = (0x0000001CU & rxd_wb->status);
666 is_rx_check_sum_enabled = (rxd_wb->type) & (0x3U << 19);
667 pkt_type = 0xFFU & (rxd_wb->type >> 4);
668
669 if (is_rx_check_sum_enabled) {
670 if (0x0U == (pkt_type & 0x3U))
671 buff->is_ip_cso = (is_err & 0x08U) ? 0 : 1;
672
673 if (0x4U == (pkt_type & 0x1CU))
674 buff->is_udp_cso = (is_err & 0x10U) ? 0 : 1;
675 else if (0x0U == (pkt_type & 0x1CU))
676 buff->is_tcp_cso = (is_err & 0x10U) ? 0 : 1;
677
678 /* Checksum offload workaround for small packets */
679 if (rxd_wb->pkt_len <= 60) {
680 buff->is_ip_cso = 0U;
681 buff->is_cso_err = 0U;
682 }
683 }
684
685 is_err &= ~0x18U;
686 is_err &= ~0x04U;
687
688 if (is_err || rxd_wb->type & 0x1000U) {
689 /* status error or DMA error */
690 buff->is_error = 1U;
691 } else {
692 if (self->aq_nic_cfg->is_rss) {
693 /* last 4 byte */
694 u16 rss_type = rxd_wb->type & 0xFU;
695
696 if (rss_type && rss_type < 0x8U) {
697 buff->is_hash_l4 = (rss_type == 0x4 ||
698 rss_type == 0x5);
699 buff->rss_hash = rxd_wb->rss_hash;
700 }
701 }
702
703 if (HW_ATL_A0_RXD_WB_STAT2_EOP & rxd_wb->status) {
704 buff->len = rxd_wb->pkt_len %
705 AQ_CFG_RX_FRAME_MAX;
706 buff->len = buff->len ?
707 buff->len : AQ_CFG_RX_FRAME_MAX;
708 buff->next = 0U;
709 buff->is_eop = 1U;
710 } else {
711 /* jumbo */
712 buff->next = aq_ring_next_dx(ring,
713 ring->hw_head);
714 ++ring->stats.rx.jumbo_packets;
715 }
716 }
717 }
718
719 return aq_hw_err_from_flags(self);
720 }
721
722 static int hw_atl_a0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
723 {
724 hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask) |
725 (1U << HW_ATL_A0_ERR_INT));
726 return aq_hw_err_from_flags(self);
727 }
728
729 static int hw_atl_a0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
730 {
731 hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));
732 hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));
733
734 if ((1U << 16) & hw_atl_reg_gen_irq_status_get(self))
735 atomic_inc(&self->dpc);
736
737 return aq_hw_err_from_flags(self);
738 }
739
740 static int hw_atl_a0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
741 {
742 *mask = hw_atl_itr_irq_statuslsw_get(self);
743 return aq_hw_err_from_flags(self);
744 }
745
746 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
747
748 static int hw_atl_a0_hw_packet_filter_set(struct aq_hw_s *self,
749 unsigned int packet_filter)
750 {
751 unsigned int i = 0U;
752
753 hw_atl_rpfl2promiscuous_mode_en_set(self,
754 IS_FILTER_ENABLED(IFF_PROMISC));
755 hw_atl_rpfl2multicast_flr_en_set(self,
756 IS_FILTER_ENABLED(IFF_MULTICAST), 0);
757 hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
758
759 self->aq_nic_cfg->is_mc_list_enabled =
760 IS_FILTER_ENABLED(IFF_MULTICAST);
761
762 for (i = HW_ATL_A0_MAC_MIN; i < HW_ATL_A0_MAC_MAX; ++i)
763 hw_atl_rpfl2_uc_flr_en_set(self,
764 (self->aq_nic_cfg->is_mc_list_enabled &&
765 (i <= self->aq_nic_cfg->mc_list_count)) ?
766 1U : 0U, i);
767
768 return aq_hw_err_from_flags(self);
769 }
770
771 #undef IS_FILTER_ENABLED
772
773 static int hw_atl_a0_hw_multicast_list_set(struct aq_hw_s *self,
774 u8 ar_mac
775 [AQ_HW_MULTICAST_ADDRESS_MAX]
776 [ETH_ALEN],
777 u32 count)
778 {
779 int err = 0;
780
781 if (count > (HW_ATL_A0_MAC_MAX - HW_ATL_A0_MAC_MIN)) {
782 err = EBADRQC;
783 goto err_exit;
784 }
785 for (self->aq_nic_cfg->mc_list_count = 0U;
786 self->aq_nic_cfg->mc_list_count < count;
787 ++self->aq_nic_cfg->mc_list_count) {
788 u32 i = self->aq_nic_cfg->mc_list_count;
789 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
790 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
791 (ar_mac[i][4] << 8) | ar_mac[i][5];
792
793 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i);
794
795 hw_atl_rpfl2unicast_dest_addresslsw_set(self,
796 l,
797 HW_ATL_A0_MAC_MIN + i);
798
799 hw_atl_rpfl2unicast_dest_addressmsw_set(self,
800 h,
801 HW_ATL_A0_MAC_MIN + i);
802
803 hw_atl_rpfl2_uc_flr_en_set(self,
804 (self->aq_nic_cfg->is_mc_list_enabled),
805 HW_ATL_A0_MAC_MIN + i);
806 }
807
808 err = aq_hw_err_from_flags(self);
809
810 err_exit:
811 return err;
812 }
813
814 static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s *self)
815 {
816 unsigned int i = 0U;
817 u32 itr_rx;
818
819 if (self->aq_nic_cfg->itr) {
820 if (self->aq_nic_cfg->itr != AQ_CFG_INTERRUPT_MODERATION_AUTO) {
821 u32 itr_ = (self->aq_nic_cfg->itr >> 1);
822
823 itr_ = min(AQ_CFG_IRQ_MASK, itr_);
824
825 itr_rx = 0x80000000U | (itr_ << 0x10);
826 } else {
827 u32 n = 0xFFFFU & aq_hw_read_reg(self, 0x00002A00U);
828
829 if (n < self->aq_link_status.mbps) {
830 itr_rx = 0U;
831 } else {
832 static unsigned int hw_timers_tbl_[] = {
833 0x01CU, /* 10Gbit */
834 0x039U, /* 5Gbit */
835 0x039U, /* 5Gbit 5GS */
836 0x073U, /* 2.5Gbit */
837 0x120U, /* 1Gbit */
838 0x1FFU, /* 100Mbit */
839 };
840
841 unsigned int speed_index =
842 hw_atl_utils_mbps_2_speed_index(
843 self->aq_link_status.mbps);
844
845 itr_rx = 0x80000000U |
846 (hw_timers_tbl_[speed_index] << 0x10U);
847 }
848
849 aq_hw_write_reg(self, 0x00002A00U, 0x40000000U);
850 aq_hw_write_reg(self, 0x00002A00U, 0x8D000000U);
851 }
852 } else {
853 itr_rx = 0U;
854 }
855
856 for (i = HW_ATL_A0_RINGS_MAX; i--;)
857 hw_atl_reg_irq_thr_set(self, itr_rx, i);
858
859 return aq_hw_err_from_flags(self);
860 }
861
862 static int hw_atl_a0_hw_stop(struct aq_hw_s *self)
863 {
864 hw_atl_a0_hw_irq_disable(self, HW_ATL_A0_INT_MASK);
865 return aq_hw_err_from_flags(self);
866 }
867
868 static int hw_atl_a0_hw_ring_tx_stop(struct aq_hw_s *self,
869 struct aq_ring_s *ring)
870 {
871 hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx);
872 return aq_hw_err_from_flags(self);
873 }
874
875 static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s *self,
876 struct aq_ring_s *ring)
877 {
878 hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx);
879 return aq_hw_err_from_flags(self);
880 }
881
882 const struct aq_hw_ops hw_atl_ops_a0 = {
883 .hw_set_mac_address = hw_atl_a0_hw_mac_addr_set,
884 .hw_init = hw_atl_a0_hw_init,
885 .hw_reset = hw_atl_a0_hw_reset,
886 .hw_start = hw_atl_a0_hw_start,
887 .hw_ring_tx_start = hw_atl_a0_hw_ring_tx_start,
888 .hw_ring_tx_stop = hw_atl_a0_hw_ring_tx_stop,
889 .hw_ring_rx_start = hw_atl_a0_hw_ring_rx_start,
890 .hw_ring_rx_stop = hw_atl_a0_hw_ring_rx_stop,
891 .hw_stop = hw_atl_a0_hw_stop,
892
893 .hw_ring_tx_xmit = hw_atl_a0_hw_ring_tx_xmit,
894 .hw_ring_tx_head_update = hw_atl_a0_hw_ring_tx_head_update,
895
896 .hw_ring_rx_receive = hw_atl_a0_hw_ring_rx_receive,
897 .hw_ring_rx_fill = hw_atl_a0_hw_ring_rx_fill,
898
899 .hw_irq_enable = hw_atl_a0_hw_irq_enable,
900 .hw_irq_disable = hw_atl_a0_hw_irq_disable,
901 .hw_irq_read = hw_atl_a0_hw_irq_read,
902
903 .hw_ring_rx_init = hw_atl_a0_hw_ring_rx_init,
904 .hw_ring_tx_init = hw_atl_a0_hw_ring_tx_init,
905 .hw_packet_filter_set = hw_atl_a0_hw_packet_filter_set,
906 .hw_multicast_list_set = hw_atl_a0_hw_multicast_list_set,
907 .hw_interrupt_moderation_set = hw_atl_a0_hw_interrupt_moderation_set,
908 .hw_rss_set = hw_atl_a0_hw_rss_set,
909 .hw_rss_hash_set = hw_atl_a0_hw_rss_hash_set,
910 .hw_get_regs = hw_atl_utils_hw_get_regs,
911 .hw_get_hw_stats = hw_atl_utils_get_hw_stats,
912 .hw_get_fw_version = hw_atl_utils_get_fw_version,
913 };
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