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[thirdparty/kernel/stable.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x.h
1 /* bnx2x.h: QLogic Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 */
15
16 #ifndef BNX2X_H
17 #define BNX2X_H
18
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/types.h>
23 #include <linux/pci_regs.h>
24
25 #include <linux/ptp_clock_kernel.h>
26 #include <linux/net_tstamp.h>
27 #include <linux/timecounter.h>
28
29 /* compilation time flags */
30
31 /* define this to make the driver freeze on error to allow getting debug info
32 * (you will need to reboot afterwards) */
33 /* #define BNX2X_STOP_ON_ERROR */
34
35 #define DRV_MODULE_VERSION "1.712.30-0"
36 #define DRV_MODULE_RELDATE "2014/02/10"
37 #define BNX2X_BC_VER 0x040200
38
39 #if defined(CONFIG_DCB)
40 #define BCM_DCBNL
41 #endif
42
43 #include "bnx2x_hsi.h"
44
45 #include "../cnic_if.h"
46
47 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
48
49 #include <linux/mdio.h>
50
51 #include "bnx2x_reg.h"
52 #include "bnx2x_fw_defs.h"
53 #include "bnx2x_mfw_req.h"
54 #include "bnx2x_link.h"
55 #include "bnx2x_sp.h"
56 #include "bnx2x_dcb.h"
57 #include "bnx2x_stats.h"
58 #include "bnx2x_vfpf.h"
59
60 enum bnx2x_int_mode {
61 BNX2X_INT_MODE_MSIX,
62 BNX2X_INT_MODE_INTX,
63 BNX2X_INT_MODE_MSI
64 };
65
66 /* error/debug prints */
67
68 #define DRV_MODULE_NAME "bnx2x"
69
70 /* for messages that are currently off */
71 #define BNX2X_MSG_OFF 0x0
72 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
73 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
74 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
75 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
76 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
77 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
78 #define BNX2X_MSG_IOV 0x0800000
79 #define BNX2X_MSG_PTP 0x1000000
80 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
81 #define BNX2X_MSG_ETHTOOL 0x4000000
82 #define BNX2X_MSG_DCB 0x8000000
83
84 /* regular debug print */
85 #define DP_INNER(fmt, ...) \
86 pr_notice("[%s:%d(%s)]" fmt, \
87 __func__, __LINE__, \
88 bp->dev ? (bp->dev->name) : "?", \
89 ##__VA_ARGS__);
90
91 #define DP(__mask, fmt, ...) \
92 do { \
93 if (unlikely(bp->msg_enable & (__mask))) \
94 DP_INNER(fmt, ##__VA_ARGS__); \
95 } while (0)
96
97 #define DP_AND(__mask, fmt, ...) \
98 do { \
99 if (unlikely((bp->msg_enable & (__mask)) == __mask)) \
100 DP_INNER(fmt, ##__VA_ARGS__); \
101 } while (0)
102
103 #define DP_CONT(__mask, fmt, ...) \
104 do { \
105 if (unlikely(bp->msg_enable & (__mask))) \
106 pr_cont(fmt, ##__VA_ARGS__); \
107 } while (0)
108
109 /* errors debug print */
110 #define BNX2X_DBG_ERR(fmt, ...) \
111 do { \
112 if (unlikely(netif_msg_probe(bp))) \
113 pr_err("[%s:%d(%s)]" fmt, \
114 __func__, __LINE__, \
115 bp->dev ? (bp->dev->name) : "?", \
116 ##__VA_ARGS__); \
117 } while (0)
118
119 /* for errors (never masked) */
120 #define BNX2X_ERR(fmt, ...) \
121 do { \
122 pr_err("[%s:%d(%s)]" fmt, \
123 __func__, __LINE__, \
124 bp->dev ? (bp->dev->name) : "?", \
125 ##__VA_ARGS__); \
126 } while (0)
127
128 #define BNX2X_ERROR(fmt, ...) \
129 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
130
131 /* before we have a dev->name use dev_info() */
132 #define BNX2X_DEV_INFO(fmt, ...) \
133 do { \
134 if (unlikely(netif_msg_probe(bp))) \
135 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
136 } while (0)
137
138 /* Error handling */
139 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
140 #ifdef BNX2X_STOP_ON_ERROR
141 #define bnx2x_panic() \
142 do { \
143 bp->panic = 1; \
144 BNX2X_ERR("driver assert\n"); \
145 bnx2x_panic_dump(bp, true); \
146 } while (0)
147 #else
148 #define bnx2x_panic() \
149 do { \
150 bp->panic = 1; \
151 BNX2X_ERR("driver assert\n"); \
152 bnx2x_panic_dump(bp, false); \
153 } while (0)
154 #endif
155
156 #define bnx2x_mc_addr(ha) ((ha)->addr)
157 #define bnx2x_uc_addr(ha) ((ha)->addr)
158
159 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff))
160 #define U64_HI(x) ((u32)(((u64)(x)) >> 32))
161 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
162
163 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
164
165 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
166 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
167 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
168
169 #define REG_WR_RELAXED(bp, offset, val) \
170 writel_relaxed((u32)val, REG_ADDR(bp, offset))
171
172 #define REG_WR16_RELAXED(bp, offset, val) \
173 writew_relaxed((u16)val, REG_ADDR(bp, offset))
174
175 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
176 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
177 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
178
179 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
180 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
181
182 #define REG_RD_DMAE(bp, offset, valp, len32) \
183 do { \
184 bnx2x_read_dmae(bp, offset, len32);\
185 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
186 } while (0)
187
188 #define REG_WR_DMAE(bp, offset, valp, len32) \
189 do { \
190 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
191 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
192 offset, len32); \
193 } while (0)
194
195 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
196 REG_WR_DMAE(bp, offset, valp, len32)
197
198 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
199 do { \
200 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
201 bnx2x_write_big_buf_wb(bp, addr, len32); \
202 } while (0)
203
204 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
205 offsetof(struct shmem_region, field))
206 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
207 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
208
209 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
210 offsetof(struct shmem2_region, field))
211 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
212 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
213 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
214 offsetof(struct mf_cfg, field))
215 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
216 offsetof(struct mf2_cfg, field))
217
218 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
219 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
220 MF_CFG_ADDR(bp, field), (val))
221 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
222
223 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
224 (SHMEM2_RD((bp), size) > \
225 offsetof(struct shmem2_region, field)))
226
227 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
228 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
229
230 /* SP SB indices */
231
232 /* General SP events - stats query, cfc delete, etc */
233 #define HC_SP_INDEX_ETH_DEF_CONS 3
234
235 /* EQ completions */
236 #define HC_SP_INDEX_EQ_CONS 7
237
238 /* FCoE L2 connection completions */
239 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
240 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
241 /* iSCSI L2 */
242 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
243 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
244
245 /* Special clients parameters */
246
247 /* SB indices */
248 /* FCoE L2 */
249 #define BNX2X_FCOE_L2_RX_INDEX \
250 (&bp->def_status_blk->sp_sb.\
251 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
252
253 #define BNX2X_FCOE_L2_TX_INDEX \
254 (&bp->def_status_blk->sp_sb.\
255 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
256
257 /**
258 * CIDs and CLIDs:
259 * CLIDs below is a CLID for func 0, then the CLID for other
260 * functions will be calculated by the formula:
261 *
262 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
263 *
264 */
265 enum {
266 BNX2X_ISCSI_ETH_CL_ID_IDX,
267 BNX2X_FCOE_ETH_CL_ID_IDX,
268 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
269 };
270
271 /* use a value high enough to be above all the PFs, which has least significant
272 * nibble as 8, so when cnic needs to come up with a CID for UIO to use to
273 * calculate doorbell address according to old doorbell configuration scheme
274 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number
275 * We must avoid coming up with cid 8 for iscsi since according to this method
276 * the designated UIO cid will come out 0 and it has a special handling for that
277 * case which doesn't suit us. Therefore will will cieling to closes cid which
278 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18.
279 */
280
281 #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \
282 (bp)->max_cos)
283 /* amount of cids traversed by UIO's DPM addition to doorbell */
284 #define UIO_DPM 8
285 /* roundup to DPM offset */
286 #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \
287 UIO_DPM))
288 /* offset to nearest value which has lsb nibble matching DPM */
289 #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \
290 (UIO_DPM * 2))
291 /* add offset to rounded-up cid to get a value which could be used with UIO */
292 #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp))
293 /* but wait - avoid UIO special case for cid 0 */
294 #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \
295 (UIO_DPM_ALIGN(bp) == UIO_DPM))
296 /* Properly DPM aligned CID dajusted to cid 0 secal case */
297 #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \
298 (UIO_DPM_CID0_OFFSET(bp)))
299 /* how many cids were wasted - need this value for cid allocation */
300 #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \
301 BNX2X_1st_NON_L2_ETH_CID(bp))
302 /* iSCSI L2 */
303 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
304 /* FCoE L2 */
305 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
306
307 #define CNIC_SUPPORT(bp) ((bp)->cnic_support)
308 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
309 #define CNIC_LOADED(bp) ((bp)->cnic_loaded)
310 #define FCOE_INIT(bp) ((bp)->fcoe_init)
311
312 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
313 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
314
315 #define SM_RX_ID 0
316 #define SM_TX_ID 1
317
318 /* defines for multiple tx priority indices */
319 #define FIRST_TX_ONLY_COS_INDEX 1
320 #define FIRST_TX_COS_INDEX 0
321
322 /* rules for calculating the cids of tx-only connections */
323 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
324 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
325 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
326
327 /* fp index inside class of service range */
328 #define FP_COS_TO_TXQ(fp, cos, bp) \
329 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
330
331 /* Indexes for transmission queues array:
332 * txdata for RSS i CoS j is at location i + (j * num of RSS)
333 * txdata for FCoE (if exist) is at location max cos * num of RSS
334 * txdata for FWD (if exist) is one location after FCoE
335 * txdata for OOO (if exist) is one location after FWD
336 */
337 enum {
338 FCOE_TXQ_IDX_OFFSET,
339 FWD_TXQ_IDX_OFFSET,
340 OOO_TXQ_IDX_OFFSET,
341 };
342 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
343 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
344
345 /* fast path */
346 /*
347 * This driver uses new build_skb() API :
348 * RX ring buffer contains pointer to kmalloc() data only,
349 * skb are built only after Hardware filled the frame.
350 */
351 struct sw_rx_bd {
352 u8 *data;
353 DEFINE_DMA_UNMAP_ADDR(mapping);
354 };
355
356 struct sw_tx_bd {
357 struct sk_buff *skb;
358 u16 first_bd;
359 u8 flags;
360 /* Set on the first BD descriptor when there is a split BD */
361 #define BNX2X_TSO_SPLIT_BD (1<<0)
362 #define BNX2X_HAS_SECOND_PBD (1<<1)
363 };
364
365 struct sw_rx_page {
366 struct page *page;
367 DEFINE_DMA_UNMAP_ADDR(mapping);
368 unsigned int offset;
369 };
370
371 union db_prod {
372 struct doorbell_set_prod data;
373 u32 raw;
374 };
375
376 /* dropless fc FW/HW related params */
377 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
378 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
379 ETH_MAX_AGGREGATION_QUEUES_E1 :\
380 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
381 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
382 #define FW_PREFETCH_CNT 16
383 #define DROPLESS_FC_HEADROOM 100
384
385 /* MC hsi */
386 #define BCM_PAGE_SHIFT 12
387 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
388 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
389 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
390
391 #define PAGES_PER_SGE_SHIFT 0
392 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
393 #define SGE_PAGE_SHIFT 12
394 #define SGE_PAGE_SIZE (1 << SGE_PAGE_SHIFT)
395 #define SGE_PAGE_MASK (~(SGE_PAGE_SIZE - 1))
396 #define SGE_PAGE_ALIGN(addr) (((addr) + SGE_PAGE_SIZE - 1) & SGE_PAGE_MASK)
397 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
398 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
399 SGE_PAGES), 0xffff)
400
401 /* SGE ring related macros */
402 #define NUM_RX_SGE_PAGES 2
403 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
404 #define NEXT_PAGE_SGE_DESC_CNT 2
405 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
406 /* RX_SGE_CNT is promised to be a power of 2 */
407 #define RX_SGE_MASK (RX_SGE_CNT - 1)
408 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
409 #define MAX_RX_SGE (NUM_RX_SGE - 1)
410 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
411 (MAX_RX_SGE_CNT - 1)) ? \
412 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
413 (x) + 1)
414 #define RX_SGE(x) ((x) & MAX_RX_SGE)
415
416 /*
417 * Number of required SGEs is the sum of two:
418 * 1. Number of possible opened aggregations (next packet for
419 * these aggregations will probably consume SGE immediately)
420 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
421 * after placement on BD for new TPA aggregation)
422 *
423 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
424 */
425 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
426 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
427 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
428 MAX_RX_SGE_CNT)
429 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
430 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
431 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
432
433 /* Manipulate a bit vector defined as an array of u64 */
434
435 /* Number of bits in one sge_mask array element */
436 #define BIT_VEC64_ELEM_SZ 64
437 #define BIT_VEC64_ELEM_SHIFT 6
438 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
439
440 #define __BIT_VEC64_SET_BIT(el, bit) \
441 do { \
442 el = ((el) | ((u64)0x1 << (bit))); \
443 } while (0)
444
445 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
446 do { \
447 el = ((el) & (~((u64)0x1 << (bit)))); \
448 } while (0)
449
450 #define BIT_VEC64_SET_BIT(vec64, idx) \
451 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
452 (idx) & BIT_VEC64_ELEM_MASK)
453
454 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
455 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
456 (idx) & BIT_VEC64_ELEM_MASK)
457
458 #define BIT_VEC64_TEST_BIT(vec64, idx) \
459 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
460 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
461
462 /* Creates a bitmask of all ones in less significant bits.
463 idx - index of the most significant bit in the created mask */
464 #define BIT_VEC64_ONES_MASK(idx) \
465 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
466 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
467
468 /*******************************************************/
469
470 /* Number of u64 elements in SGE mask array */
471 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
472 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
473 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
474
475 union host_hc_status_block {
476 /* pointer to fp status block e1x */
477 struct host_hc_status_block_e1x *e1x_sb;
478 /* pointer to fp status block e2 */
479 struct host_hc_status_block_e2 *e2_sb;
480 };
481
482 struct bnx2x_agg_info {
483 /*
484 * First aggregation buffer is a data buffer, the following - are pages.
485 * We will preallocate the data buffer for each aggregation when
486 * we open the interface and will replace the BD at the consumer
487 * with this one when we receive the TPA_START CQE in order to
488 * keep the Rx BD ring consistent.
489 */
490 struct sw_rx_bd first_buf;
491 u8 tpa_state;
492 #define BNX2X_TPA_START 1
493 #define BNX2X_TPA_STOP 2
494 #define BNX2X_TPA_ERROR 3
495 u8 placement_offset;
496 u16 parsing_flags;
497 u16 vlan_tag;
498 u16 len_on_bd;
499 u32 rxhash;
500 enum pkt_hash_types rxhash_type;
501 u16 gro_size;
502 u16 full_page;
503 };
504
505 #define Q_STATS_OFFSET32(stat_name) \
506 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
507
508 struct bnx2x_fp_txdata {
509
510 struct sw_tx_bd *tx_buf_ring;
511
512 union eth_tx_bd_types *tx_desc_ring;
513 dma_addr_t tx_desc_mapping;
514
515 u32 cid;
516
517 union db_prod tx_db;
518
519 u16 tx_pkt_prod;
520 u16 tx_pkt_cons;
521 u16 tx_bd_prod;
522 u16 tx_bd_cons;
523
524 unsigned long tx_pkt;
525
526 __le16 *tx_cons_sb;
527
528 int txq_index;
529 struct bnx2x_fastpath *parent_fp;
530 int tx_ring_size;
531 };
532
533 enum bnx2x_tpa_mode_t {
534 TPA_MODE_DISABLED,
535 TPA_MODE_LRO,
536 TPA_MODE_GRO
537 };
538
539 struct bnx2x_alloc_pool {
540 struct page *page;
541 unsigned int offset;
542 };
543
544 struct bnx2x_fastpath {
545 struct bnx2x *bp; /* parent */
546
547 struct napi_struct napi;
548
549 union host_hc_status_block status_blk;
550 /* chip independent shortcuts into sb structure */
551 __le16 *sb_index_values;
552 __le16 *sb_running_index;
553 /* chip independent shortcut into rx_prods_offset memory */
554 u32 ustorm_rx_prods_offset;
555
556 u32 rx_buf_size;
557 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
558 dma_addr_t status_blk_mapping;
559
560 enum bnx2x_tpa_mode_t mode;
561
562 u8 max_cos; /* actual number of active tx coses */
563 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
564
565 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
566 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
567
568 struct eth_rx_bd *rx_desc_ring;
569 dma_addr_t rx_desc_mapping;
570
571 union eth_rx_cqe *rx_comp_ring;
572 dma_addr_t rx_comp_mapping;
573
574 /* SGE ring */
575 struct eth_rx_sge *rx_sge_ring;
576 dma_addr_t rx_sge_mapping;
577
578 u64 sge_mask[RX_SGE_MASK_LEN];
579
580 u32 cid;
581
582 __le16 fp_hc_idx;
583
584 u8 index; /* number in fp array */
585 u8 rx_queue; /* index for skb_record */
586 u8 cl_id; /* eth client id */
587 u8 cl_qzone_id;
588 u8 fw_sb_id; /* status block number in FW */
589 u8 igu_sb_id; /* status block number in HW */
590
591 u16 rx_bd_prod;
592 u16 rx_bd_cons;
593 u16 rx_comp_prod;
594 u16 rx_comp_cons;
595 u16 rx_sge_prod;
596 /* The last maximal completed SGE */
597 u16 last_max_sge;
598 __le16 *rx_cons_sb;
599
600 /* TPA related */
601 struct bnx2x_agg_info *tpa_info;
602 #ifdef BNX2X_STOP_ON_ERROR
603 u64 tpa_queue_used;
604 #endif
605 /* The size is calculated using the following:
606 sizeof name field from netdev structure +
607 4 ('-Xx-' string) +
608 4 (for the digits and to make it DWORD aligned) */
609 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
610 char name[FP_NAME_SIZE];
611
612 struct bnx2x_alloc_pool page_pool;
613 };
614
615 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
616 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
617 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
618 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
619
620 /* Use 2500 as a mini-jumbo MTU for FCoE */
621 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
622
623 #define FCOE_IDX_OFFSET 0
624
625 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
626 FCOE_IDX_OFFSET)
627 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
628 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
629 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
630 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
631 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
632 txdata_ptr[FIRST_TX_COS_INDEX] \
633 ->var)
634
635 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
636 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
637 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
638
639 /* MC hsi */
640 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
641 #define RX_COPY_THRESH 92
642
643 #define NUM_TX_RINGS 16
644 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
645 #define NEXT_PAGE_TX_DESC_CNT 1
646 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
647 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
648 #define MAX_TX_BD (NUM_TX_BD - 1)
649 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
650 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
651 (MAX_TX_DESC_CNT - 1)) ? \
652 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
653 (x) + 1)
654 #define TX_BD(x) ((x) & MAX_TX_BD)
655 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
656
657 /* number of NEXT_PAGE descriptors may be required during placement */
658 #define NEXT_CNT_PER_TX_PKT(bds) \
659 (((bds) + MAX_TX_DESC_CNT - 1) / \
660 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
661 /* max BDs per tx packet w/o next_pages:
662 * START_BD - describes packed
663 * START_BD(splitted) - includes unpaged data segment for GSO
664 * PARSING_BD - for TSO and CSUM data
665 * PARSING_BD2 - for encapsulation data
666 * Frag BDs - describes pages for frags
667 */
668 #define BDS_PER_TX_PKT 4
669 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
670 /* max BDs per tx packet including next pages */
671 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
672 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
673
674 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
675 #define NUM_RX_RINGS 8
676 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
677 #define NEXT_PAGE_RX_DESC_CNT 2
678 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
679 #define RX_DESC_MASK (RX_DESC_CNT - 1)
680 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
681 #define MAX_RX_BD (NUM_RX_BD - 1)
682 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
683
684 /* dropless fc calculations for BDs
685 *
686 * Number of BDs should as number of buffers in BRB:
687 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
688 * "next" elements on each page
689 */
690 #define NUM_BD_REQ BRB_SIZE(bp)
691 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
692 MAX_RX_DESC_CNT)
693 #define BD_TH_LO(bp) (NUM_BD_REQ + \
694 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
695 FW_DROP_LEVEL(bp))
696 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
697
698 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
699
700 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
701 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
702 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
703 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
704 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
705 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
706 MIN_RX_AVAIL))
707
708 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
709 (MAX_RX_DESC_CNT - 1)) ? \
710 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
711 (x) + 1)
712 #define RX_BD(x) ((x) & MAX_RX_BD)
713
714 /*
715 * As long as CQE is X times bigger than BD entry we have to allocate X times
716 * more pages for CQ ring in order to keep it balanced with BD ring
717 */
718 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
719 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
720 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
721 #define NEXT_PAGE_RCQ_DESC_CNT 1
722 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
723 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
724 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
725 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
726 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
727 (MAX_RCQ_DESC_CNT - 1)) ? \
728 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
729 (x) + 1)
730 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
731
732 /* dropless fc calculations for RCQs
733 *
734 * Number of RCQs should be as number of buffers in BRB:
735 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
736 * "next" elements on each page
737 */
738 #define NUM_RCQ_REQ BRB_SIZE(bp)
739 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
740 MAX_RCQ_DESC_CNT)
741 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
742 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
743 FW_DROP_LEVEL(bp))
744 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
745
746 /* This is needed for determining of last_max */
747 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
748 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
749
750 #define BNX2X_SWCID_SHIFT 17
751 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
752
753 /* used on a CID received from the HW */
754 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
755 #define CQE_CMD(x) (le32_to_cpu(x) >> \
756 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
757
758 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
759 le32_to_cpu((bd)->addr_lo))
760 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
761
762 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
763 #define BNX2X_DB_SHIFT 3 /* 8 bytes*/
764 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
765 #error "Min DB doorbell stride is 8"
766 #endif
767 #define DOORBELL_RELAXED(bp, cid, val) \
768 writel_relaxed((u32)(val), (bp)->doorbells + ((bp)->db_size * (cid)))
769
770 /* TX CSUM helpers */
771 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
772 skb->csum_offset)
773 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
774 skb->csum_offset))
775
776 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
777
778 #define XMIT_PLAIN 0
779 #define XMIT_CSUM_V4 (1 << 0)
780 #define XMIT_CSUM_V6 (1 << 1)
781 #define XMIT_CSUM_TCP (1 << 2)
782 #define XMIT_GSO_V4 (1 << 3)
783 #define XMIT_GSO_V6 (1 << 4)
784 #define XMIT_CSUM_ENC_V4 (1 << 5)
785 #define XMIT_CSUM_ENC_V6 (1 << 6)
786 #define XMIT_GSO_ENC_V4 (1 << 7)
787 #define XMIT_GSO_ENC_V6 (1 << 8)
788
789 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6)
790 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6)
791
792 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC)
793 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC)
794
795 /* stuff added to make the code fit 80Col */
796 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
797 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
798 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
799 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
800 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
801
802 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
803
804 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
805 (((le16_to_cpu(flags) & \
806 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
807 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
808 == PRS_FLAG_OVERETH_IPV4)
809 #define BNX2X_RX_SUM_FIX(cqe) \
810 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
811
812 #define FP_USB_FUNC_OFF \
813 offsetof(struct cstorm_status_block_u, func)
814 #define FP_CSB_FUNC_OFF \
815 offsetof(struct cstorm_status_block_c, func)
816
817 #define HC_INDEX_ETH_RX_CQ_CONS 1
818
819 #define HC_INDEX_OOO_TX_CQ_CONS 4
820
821 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
822
823 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
824
825 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
826
827 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
828
829 #define BNX2X_RX_SB_INDEX \
830 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
831
832 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
833
834 #define BNX2X_TX_SB_INDEX_COS0 \
835 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
836
837 /* end of fast path */
838
839 /* common */
840
841 struct bnx2x_common {
842
843 u32 chip_id;
844 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
845 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
846
847 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
848 #define CHIP_NUM_57710 0x164e
849 #define CHIP_NUM_57711 0x164f
850 #define CHIP_NUM_57711E 0x1650
851 #define CHIP_NUM_57712 0x1662
852 #define CHIP_NUM_57712_MF 0x1663
853 #define CHIP_NUM_57712_VF 0x166f
854 #define CHIP_NUM_57713 0x1651
855 #define CHIP_NUM_57713E 0x1652
856 #define CHIP_NUM_57800 0x168a
857 #define CHIP_NUM_57800_MF 0x16a5
858 #define CHIP_NUM_57800_VF 0x16a9
859 #define CHIP_NUM_57810 0x168e
860 #define CHIP_NUM_57810_MF 0x16ae
861 #define CHIP_NUM_57810_VF 0x16af
862 #define CHIP_NUM_57811 0x163d
863 #define CHIP_NUM_57811_MF 0x163e
864 #define CHIP_NUM_57811_VF 0x163f
865 #define CHIP_NUM_57840_OBSOLETE 0x168d
866 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
867 #define CHIP_NUM_57840_4_10 0x16a1
868 #define CHIP_NUM_57840_2_20 0x16a2
869 #define CHIP_NUM_57840_MF 0x16a4
870 #define CHIP_NUM_57840_VF 0x16ad
871 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
872 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
873 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
874 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
875 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF)
876 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
877 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
878 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
879 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF)
880 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
881 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
882 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF)
883 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
884 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
885 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF)
886 #define CHIP_IS_57840(bp) \
887 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
888 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
889 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
890 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
891 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
892 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
893 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
894 CHIP_IS_57711E(bp))
895 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \
896 CHIP_IS_57811_MF(bp) || \
897 CHIP_IS_57811_VF(bp))
898 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
899 CHIP_IS_57712_MF(bp) || \
900 CHIP_IS_57712_VF(bp))
901 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
902 CHIP_IS_57800_MF(bp) || \
903 CHIP_IS_57800_VF(bp) || \
904 CHIP_IS_57810(bp) || \
905 CHIP_IS_57810_MF(bp) || \
906 CHIP_IS_57810_VF(bp) || \
907 CHIP_IS_57811xx(bp) || \
908 CHIP_IS_57840(bp) || \
909 CHIP_IS_57840_MF(bp) || \
910 CHIP_IS_57840_VF(bp))
911 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
912 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
913 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
914
915 #define CHIP_REV_SHIFT 12
916 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
917 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
918 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
919 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
920 /* assume maximum 5 revisions */
921 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
922 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
923 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
924 !(CHIP_REV_VAL(bp) & 0x00001000))
925 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
926 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
927 (CHIP_REV_VAL(bp) & 0x00001000))
928
929 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
930 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
931
932 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
933 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
934 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
935 (CHIP_REV_SHIFT + 1)) \
936 << CHIP_REV_SHIFT)
937 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
938 CHIP_REV_SIM(bp) :\
939 CHIP_REV_VAL(bp))
940 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
941 (CHIP_REV(bp) == CHIP_REV_Bx))
942 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
943 (CHIP_REV(bp) == CHIP_REV_Ax))
944 /* This define is used in two main places:
945 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher
946 * to nic-only mode or to offload mode. Offload mode is configured if either the
947 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
948 * registered for this port (which means that the user wants storage services).
949 * 2. During cnic-related load, to know if offload mode is already configured in
950 * the HW or needs to be configured.
951 * Since the transition from nic-mode to offload-mode in HW causes traffic
952 * corruption, nic-mode is configured only in ports on which storage services
953 * where never requested.
954 */
955 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
956
957 int flash_size;
958 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
959 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
960 #define BNX2X_NVRAM_PAGE_SIZE 256
961
962 u32 shmem_base;
963 u32 shmem2_base;
964 u32 mf_cfg_base;
965 u32 mf2_cfg_base;
966
967 u32 hw_config;
968
969 u32 bc_ver;
970
971 u8 int_block;
972 #define INT_BLOCK_HC 0
973 #define INT_BLOCK_IGU 1
974 #define INT_BLOCK_MODE_NORMAL 0
975 #define INT_BLOCK_MODE_BW_COMP 2
976 #define CHIP_INT_MODE_IS_NBC(bp) \
977 (!CHIP_IS_E1x(bp) && \
978 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
979 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
980
981 u8 chip_port_mode;
982 #define CHIP_4_PORT_MODE 0x0
983 #define CHIP_2_PORT_MODE 0x1
984 #define CHIP_PORT_MODE_NONE 0x2
985 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
986 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
987
988 u32 boot_mode;
989 };
990
991 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
992 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
993 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
994
995 #define MAX_IGU_ATTN_ACK_TO 100
996 /* end of common */
997
998 /* port */
999
1000 struct bnx2x_port {
1001 u32 pmf;
1002
1003 u32 link_config[LINK_CONFIG_SIZE];
1004
1005 u32 supported[LINK_CONFIG_SIZE];
1006
1007 u32 advertising[LINK_CONFIG_SIZE];
1008
1009 u32 phy_addr;
1010
1011 /* used to synchronize phy accesses */
1012 struct mutex phy_mutex;
1013
1014 u32 port_stx;
1015
1016 struct nig_stats old_nig_stats;
1017 };
1018
1019 /* end of port */
1020
1021 #define STATS_OFFSET32(stat_name) \
1022 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
1023
1024 /* slow path */
1025 #define BNX2X_MAX_NUM_OF_VFS 64
1026 #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */
1027 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
1028
1029 /* We need to reserve doorbell addresses for all VF and queue combinations */
1030 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
1031
1032 /* The doorbell is configured to have the same number of CIDs for PFs and for
1033 * VFs. For this reason the PF CID zone is as large as the VF zone.
1034 */
1035 #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS
1036 #define BNX2X_MAX_NUM_VF_QUEUES 64
1037 #define BNX2X_VF_ID_INVALID 0xFF
1038
1039 /* the number of VF CIDS multiplied by the amount of bytes reserved for each
1040 * cid must not exceed the size of the VF doorbell
1041 */
1042 #define BNX2X_VF_BAR_SIZE 512
1043 #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT))
1044 #error "VF doorbell bar size is 512"
1045 #endif
1046
1047 /*
1048 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
1049 * control by the number of fast-path status blocks supported by the
1050 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
1051 * status block represents an independent interrupts context that can
1052 * serve a regular L2 networking queue. However special L2 queues such
1053 * as the FCoE queue do not require a FP-SB and other components like
1054 * the CNIC may consume FP-SB reducing the number of possible L2 queues
1055 *
1056 * If the maximum number of FP-SB available is X then:
1057 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
1058 * regular L2 queues is Y=X-1
1059 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
1060 * c. If the FCoE L2 queue is supported the actual number of L2 queues
1061 * is Y+1
1062 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
1063 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
1064 * FP interrupt context for the CNIC).
1065 * e. The number of HW context (CID count) is always X or X+1 if FCoE
1066 * L2 queue is supported. The cid for the FCoE L2 queue is always X.
1067 */
1068
1069 /* fast-path interrupt contexts E1x */
1070 #define FP_SB_MAX_E1x 16
1071 /* fast-path interrupt contexts E2 */
1072 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
1073
1074 union cdu_context {
1075 struct eth_context eth;
1076 char pad[1024];
1077 };
1078
1079 /* CDU host DB constants */
1080 #define CDU_ILT_PAGE_SZ_HW 2
1081 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1082 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1083
1084 #define CNIC_ISCSI_CID_MAX 256
1085 #define CNIC_FCOE_CID_MAX 2048
1086 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1087 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1088
1089 #define QM_ILT_PAGE_SZ_HW 0
1090 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1091 #define QM_CID_ROUND 1024
1092
1093 /* TM (timers) host DB constants */
1094 #define TM_ILT_PAGE_SZ_HW 0
1095 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1096 #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \
1097 BNX2X_VF_CIDS + \
1098 CNIC_ISCSI_CID_MAX)
1099 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1100 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1101
1102 /* SRC (Searcher) host DB constants */
1103 #define SRC_ILT_PAGE_SZ_HW 0
1104 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1105 #define SRC_HASH_BITS 10
1106 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1107 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1108 #define SRC_T2_SZ SRC_ILT_SZ
1109 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1110
1111 #define MAX_DMAE_C 8
1112
1113 /* DMA memory not used in fastpath */
1114 struct bnx2x_slowpath {
1115 union {
1116 struct mac_configuration_cmd e1x;
1117 struct eth_classify_rules_ramrod_data e2;
1118 } mac_rdata;
1119
1120 union {
1121 struct eth_classify_rules_ramrod_data e2;
1122 } vlan_rdata;
1123
1124 union {
1125 struct tstorm_eth_mac_filter_config e1x;
1126 struct eth_filter_rules_ramrod_data e2;
1127 } rx_mode_rdata;
1128
1129 union {
1130 struct mac_configuration_cmd e1;
1131 struct eth_multicast_rules_ramrod_data e2;
1132 } mcast_rdata;
1133
1134 struct eth_rss_update_ramrod_data rss_rdata;
1135
1136 /* Queue State related ramrods are always sent under rtnl_lock */
1137 union {
1138 struct client_init_ramrod_data init_data;
1139 struct client_update_ramrod_data update_data;
1140 struct tpa_update_ramrod_data tpa_data;
1141 } q_rdata;
1142
1143 union {
1144 struct function_start_data func_start;
1145 /* pfc configuration for DCBX ramrod */
1146 struct flow_control_configuration pfc_config;
1147 } func_rdata;
1148
1149 /* afex ramrod can not be a part of func_rdata union because these
1150 * events might arrive in parallel to other events from func_rdata.
1151 * Therefore, if they would have been defined in the same union,
1152 * data can get corrupted.
1153 */
1154 union {
1155 struct afex_vif_list_ramrod_data viflist_data;
1156 struct function_update_data func_update;
1157 } func_afex_rdata;
1158
1159 /* used by dmae command executer */
1160 struct dmae_command dmae[MAX_DMAE_C];
1161
1162 u32 stats_comp;
1163 union mac_stats mac_stats;
1164 struct nig_stats nig_stats;
1165 struct host_port_stats port_stats;
1166 struct host_func_stats func_stats;
1167
1168 u32 wb_comp;
1169 u32 wb_data[4];
1170
1171 union drv_info_to_mcp drv_info_to_mcp;
1172 };
1173
1174 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1175 #define bnx2x_sp_mapping(bp, var) \
1176 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1177
1178 /* attn group wiring */
1179 #define MAX_DYNAMIC_ATTN_GRPS 8
1180
1181 struct attn_route {
1182 u32 sig[5];
1183 };
1184
1185 struct iro {
1186 u32 base;
1187 u16 m1;
1188 u16 m2;
1189 u16 m3;
1190 u16 size;
1191 };
1192
1193 struct hw_context {
1194 union cdu_context *vcxt;
1195 dma_addr_t cxt_mapping;
1196 size_t size;
1197 };
1198
1199 /* forward */
1200 struct bnx2x_ilt;
1201
1202 struct bnx2x_vfdb;
1203
1204 enum bnx2x_recovery_state {
1205 BNX2X_RECOVERY_DONE,
1206 BNX2X_RECOVERY_INIT,
1207 BNX2X_RECOVERY_WAIT,
1208 BNX2X_RECOVERY_FAILED,
1209 BNX2X_RECOVERY_NIC_LOADING
1210 };
1211
1212 /*
1213 * Event queue (EQ or event ring) MC hsi
1214 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1215 */
1216 #define NUM_EQ_PAGES 1
1217 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1218 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1219 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1220 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1221 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1222
1223 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1224 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1225 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1226
1227 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1228 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1229
1230 #define BNX2X_EQ_INDEX \
1231 (&bp->def_status_blk->sp_sb.\
1232 index_values[HC_SP_INDEX_EQ_CONS])
1233
1234 /* This is a data that will be used to create a link report message.
1235 * We will keep the data used for the last link report in order
1236 * to prevent reporting the same link parameters twice.
1237 */
1238 struct bnx2x_link_report_data {
1239 u16 line_speed; /* Effective line speed */
1240 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1241 };
1242
1243 enum {
1244 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1245 BNX2X_LINK_REPORT_LINK_DOWN,
1246 BNX2X_LINK_REPORT_RX_FC_ON,
1247 BNX2X_LINK_REPORT_TX_FC_ON,
1248 };
1249
1250 enum {
1251 BNX2X_PORT_QUERY_IDX,
1252 BNX2X_PF_QUERY_IDX,
1253 BNX2X_FCOE_QUERY_IDX,
1254 BNX2X_FIRST_QUEUE_QUERY_IDX,
1255 };
1256
1257 struct bnx2x_fw_stats_req {
1258 struct stats_query_header hdr;
1259 struct stats_query_entry query[FP_SB_MAX_E1x+
1260 BNX2X_FIRST_QUEUE_QUERY_IDX];
1261 };
1262
1263 struct bnx2x_fw_stats_data {
1264 struct stats_counter storm_counters;
1265 struct per_port_stats port;
1266 struct per_pf_stats pf;
1267 struct fcoe_statistics_params fcoe;
1268 struct per_queue_stats queue_stats[1];
1269 };
1270
1271 /* Public slow path states */
1272 enum sp_rtnl_flag {
1273 BNX2X_SP_RTNL_SETUP_TC,
1274 BNX2X_SP_RTNL_TX_TIMEOUT,
1275 BNX2X_SP_RTNL_FAN_FAILURE,
1276 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1277 BNX2X_SP_RTNL_ENABLE_SRIOV,
1278 BNX2X_SP_RTNL_VFPF_MCAST,
1279 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
1280 BNX2X_SP_RTNL_RX_MODE,
1281 BNX2X_SP_RTNL_HYPERVISOR_VLAN,
1282 BNX2X_SP_RTNL_TX_STOP,
1283 BNX2X_SP_RTNL_GET_DRV_VERSION,
1284 BNX2X_SP_RTNL_CHANGE_UDP_PORT,
1285 };
1286
1287 enum bnx2x_iov_flag {
1288 BNX2X_IOV_HANDLE_VF_MSG,
1289 BNX2X_IOV_HANDLE_FLR,
1290 };
1291
1292 struct bnx2x_prev_path_list {
1293 struct list_head list;
1294 u8 bus;
1295 u8 slot;
1296 u8 path;
1297 u8 aer;
1298 u8 undi;
1299 };
1300
1301 struct bnx2x_sp_objs {
1302 /* MACs object */
1303 struct bnx2x_vlan_mac_obj mac_obj;
1304
1305 /* Queue State object */
1306 struct bnx2x_queue_sp_obj q_obj;
1307
1308 /* VLANs object */
1309 struct bnx2x_vlan_mac_obj vlan_obj;
1310 };
1311
1312 struct bnx2x_fp_stats {
1313 struct tstorm_per_queue_stats old_tclient;
1314 struct ustorm_per_queue_stats old_uclient;
1315 struct xstorm_per_queue_stats old_xclient;
1316 struct bnx2x_eth_q_stats eth_q_stats;
1317 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1318 };
1319
1320 enum {
1321 SUB_MF_MODE_UNKNOWN = 0,
1322 SUB_MF_MODE_UFP,
1323 SUB_MF_MODE_NPAR1_DOT_5,
1324 SUB_MF_MODE_BD,
1325 };
1326
1327 struct bnx2x_vlan_entry {
1328 struct list_head link;
1329 u16 vid;
1330 bool hw;
1331 };
1332
1333 enum bnx2x_udp_port_type {
1334 BNX2X_UDP_PORT_VXLAN,
1335 BNX2X_UDP_PORT_GENEVE,
1336 BNX2X_UDP_PORT_MAX,
1337 };
1338
1339 struct bnx2x_udp_tunnel {
1340 u16 dst_port;
1341 u8 count;
1342 };
1343
1344 struct bnx2x {
1345 /* Fields used in the tx and intr/napi performance paths
1346 * are grouped together in the beginning of the structure
1347 */
1348 struct bnx2x_fastpath *fp;
1349 struct bnx2x_sp_objs *sp_objs;
1350 struct bnx2x_fp_stats *fp_stats;
1351 struct bnx2x_fp_txdata *bnx2x_txq;
1352 void __iomem *regview;
1353 void __iomem *doorbells;
1354 u16 db_size;
1355
1356 u8 pf_num; /* absolute PF number */
1357 u8 pfid; /* per-path PF number */
1358 int base_fw_ndsb; /**/
1359 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1360 #define BP_PORT(bp) (bp->pfid & 1)
1361 #define BP_FUNC(bp) (bp->pfid)
1362 #define BP_ABS_FUNC(bp) (bp->pf_num)
1363 #define BP_VN(bp) ((bp)->pfid >> 1)
1364 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1365 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1366 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1367 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1368 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1369
1370 #ifdef CONFIG_BNX2X_SRIOV
1371 /* protects vf2pf mailbox from simultaneous access */
1372 struct mutex vf2pf_mutex;
1373 /* vf pf channel mailbox contains request and response buffers */
1374 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1375 dma_addr_t vf2pf_mbox_mapping;
1376
1377 /* we set aside a copy of the acquire response */
1378 struct pfvf_acquire_resp_tlv acquire_resp;
1379
1380 /* bulletin board for messages from pf to vf */
1381 union pf_vf_bulletin *pf2vf_bulletin;
1382 dma_addr_t pf2vf_bulletin_mapping;
1383
1384 union pf_vf_bulletin shadow_bulletin;
1385 struct pf_vf_bulletin_content old_bulletin;
1386
1387 u16 requested_nr_virtfn;
1388 #endif /* CONFIG_BNX2X_SRIOV */
1389
1390 struct net_device *dev;
1391 struct pci_dev *pdev;
1392
1393 const struct iro *iro_arr;
1394 #define IRO (bp->iro_arr)
1395
1396 enum bnx2x_recovery_state recovery_state;
1397 int is_leader;
1398 struct msix_entry *msix_table;
1399
1400 int tx_ring_size;
1401
1402 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1403 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
1404 #define ETH_MIN_PACKET_SIZE (ETH_ZLEN - ETH_HLEN)
1405 #define ETH_MAX_PACKET_SIZE ETH_DATA_LEN
1406 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1407 /* TCP with Timestamp Option (32) + IPv6 (40) */
1408 #define ETH_MAX_TPA_HEADER_SIZE 72
1409
1410 /* Max supported alignment is 256 (8 shift)
1411 * minimal alignment shift 6 is optimal for 57xxx HW performance
1412 */
1413 #define BNX2X_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))
1414
1415 /* FW uses 2 Cache lines Alignment for start packet and size
1416 *
1417 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1418 * at the end of skb->data, to avoid wasting a full cache line.
1419 * This reduces memory use (skb->truesize).
1420 */
1421 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1422
1423 #define BNX2X_FW_RX_ALIGN_END \
1424 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1425 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1426
1427 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1428
1429 struct host_sp_status_block *def_status_blk;
1430 #define DEF_SB_IGU_ID 16
1431 #define DEF_SB_ID HC_SP_SB_ID
1432 __le16 def_idx;
1433 __le16 def_att_idx;
1434 u32 attn_state;
1435 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1436
1437 /* slow path ring */
1438 struct eth_spe *spq;
1439 dma_addr_t spq_mapping;
1440 u16 spq_prod_idx;
1441 struct eth_spe *spq_prod_bd;
1442 struct eth_spe *spq_last_bd;
1443 __le16 *dsb_sp_prod;
1444 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1445 /* used to synchronize spq accesses */
1446 spinlock_t spq_lock;
1447
1448 /* event queue */
1449 union event_ring_elem *eq_ring;
1450 dma_addr_t eq_mapping;
1451 u16 eq_prod;
1452 u16 eq_cons;
1453 __le16 *eq_cons_sb;
1454 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1455
1456 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1457 u16 stats_pending;
1458 /* Counter for completed statistics ramrods */
1459 u16 stats_comp;
1460
1461 /* End of fields used in the performance code paths */
1462
1463 int panic;
1464 int msg_enable;
1465
1466 u32 flags;
1467 #define PCIX_FLAG (1 << 0)
1468 #define PCI_32BIT_FLAG (1 << 1)
1469 #define ONE_PORT_FLAG (1 << 2)
1470 #define NO_WOL_FLAG (1 << 3)
1471 #define USING_MSIX_FLAG (1 << 5)
1472 #define USING_MSI_FLAG (1 << 6)
1473 #define DISABLE_MSI_FLAG (1 << 7)
1474 #define NO_MCP_FLAG (1 << 9)
1475 #define MF_FUNC_DIS (1 << 11)
1476 #define OWN_CNIC_IRQ (1 << 12)
1477 #define NO_ISCSI_OOO_FLAG (1 << 13)
1478 #define NO_ISCSI_FLAG (1 << 14)
1479 #define NO_FCOE_FLAG (1 << 15)
1480 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1481 #define TX_SWITCHING (1 << 18)
1482 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1483 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1484 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1485 #define IS_VF_FLAG (1 << 22)
1486 #define BC_SUPPORTS_RMMOD_CMD (1 << 23)
1487 #define HAS_PHYS_PORT_ID (1 << 24)
1488 #define AER_ENABLED (1 << 25)
1489 #define PTP_SUPPORTED (1 << 26)
1490 #define TX_TIMESTAMPING_EN (1 << 27)
1491
1492 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
1493
1494 #ifdef CONFIG_BNX2X_SRIOV
1495 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
1496 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
1497 #else
1498 #define IS_VF(bp) false
1499 #define IS_PF(bp) true
1500 #endif
1501
1502 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1503 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1504 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1505
1506 u8 cnic_support;
1507 bool cnic_enabled;
1508 bool cnic_loaded;
1509 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1510
1511 /* Flag that indicates that we can start looking for FCoE L2 queue
1512 * completions in the default status block.
1513 */
1514 bool fcoe_init;
1515
1516 int mrrs;
1517
1518 struct delayed_work sp_task;
1519 struct delayed_work iov_task;
1520
1521 atomic_t interrupt_occurred;
1522 struct delayed_work sp_rtnl_task;
1523
1524 struct delayed_work period_task;
1525 struct timer_list timer;
1526 int current_interval;
1527
1528 u16 fw_seq;
1529 u16 fw_drv_pulse_wr_seq;
1530 u32 func_stx;
1531
1532 struct link_params link_params;
1533 struct link_vars link_vars;
1534 u32 link_cnt;
1535 struct bnx2x_link_report_data last_reported_link;
1536 bool force_link_down;
1537
1538 struct mdio_if_info mdio;
1539
1540 struct bnx2x_common common;
1541 struct bnx2x_port port;
1542
1543 struct cmng_init cmng;
1544
1545 u32 mf_config[E1HVN_MAX];
1546 u32 mf_ext_config;
1547 u32 path_has_ovlan; /* E3 */
1548 u16 mf_ov;
1549 u8 mf_mode;
1550 #define IS_MF(bp) (bp->mf_mode != 0)
1551 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1552 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1553 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1554 u8 mf_sub_mode;
1555 #define IS_MF_UFP(bp) (IS_MF_SD(bp) && \
1556 bp->mf_sub_mode == SUB_MF_MODE_UFP)
1557 #define IS_MF_BD(bp) (IS_MF_SD(bp) && \
1558 bp->mf_sub_mode == SUB_MF_MODE_BD)
1559
1560 u8 wol;
1561
1562 int rx_ring_size;
1563
1564 u16 tx_quick_cons_trip_int;
1565 u16 tx_quick_cons_trip;
1566 u16 tx_ticks_int;
1567 u16 tx_ticks;
1568
1569 u16 rx_quick_cons_trip_int;
1570 u16 rx_quick_cons_trip;
1571 u16 rx_ticks_int;
1572 u16 rx_ticks;
1573 /* Maximal coalescing timeout in us */
1574 #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR)
1575
1576 u32 lin_cnt;
1577
1578 u16 state;
1579 #define BNX2X_STATE_CLOSED 0
1580 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1581 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1582 #define BNX2X_STATE_OPEN 0x3000
1583 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1584 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1585
1586 #define BNX2X_STATE_DIAG 0xe000
1587 #define BNX2X_STATE_ERROR 0xf000
1588
1589 #define BNX2X_MAX_PRIORITY 8
1590 int num_queues;
1591 uint num_ethernet_queues;
1592 uint num_cnic_queues;
1593 int disable_tpa;
1594
1595 u32 rx_mode;
1596 #define BNX2X_RX_MODE_NONE 0
1597 #define BNX2X_RX_MODE_NORMAL 1
1598 #define BNX2X_RX_MODE_ALLMULTI 2
1599 #define BNX2X_RX_MODE_PROMISC 3
1600 #define BNX2X_MAX_MULTICAST 64
1601
1602 u8 igu_dsb_id;
1603 u8 igu_base_sb;
1604 u8 igu_sb_cnt;
1605 u8 min_msix_vec_cnt;
1606
1607 u32 igu_base_addr;
1608 dma_addr_t def_status_blk_mapping;
1609
1610 struct bnx2x_slowpath *slowpath;
1611 dma_addr_t slowpath_mapping;
1612
1613 /* Mechanism protecting the drv_info_to_mcp */
1614 struct mutex drv_info_mutex;
1615 bool drv_info_mng_owner;
1616
1617 /* Total number of FW statistics requests */
1618 u8 fw_stats_num;
1619
1620 /*
1621 * This is a memory buffer that will contain both statistics
1622 * ramrod request and data.
1623 */
1624 void *fw_stats;
1625 dma_addr_t fw_stats_mapping;
1626
1627 /*
1628 * FW statistics request shortcut (points at the
1629 * beginning of fw_stats buffer).
1630 */
1631 struct bnx2x_fw_stats_req *fw_stats_req;
1632 dma_addr_t fw_stats_req_mapping;
1633 int fw_stats_req_sz;
1634
1635 /*
1636 * FW statistics data shortcut (points at the beginning of
1637 * fw_stats buffer + fw_stats_req_sz).
1638 */
1639 struct bnx2x_fw_stats_data *fw_stats_data;
1640 dma_addr_t fw_stats_data_mapping;
1641 int fw_stats_data_sz;
1642
1643 /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB
1644 * context size we need 8 ILT entries.
1645 */
1646 #define ILT_MAX_L2_LINES 32
1647 struct hw_context context[ILT_MAX_L2_LINES];
1648
1649 struct bnx2x_ilt *ilt;
1650 #define BP_ILT(bp) ((bp)->ilt)
1651 #define ILT_MAX_LINES 256
1652 /*
1653 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1654 * to CNIC.
1655 */
1656 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1657
1658 /*
1659 * Maximum CID count that might be required by the bnx2x:
1660 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1661 */
1662
1663 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1664 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1665 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1666 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1667 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1668 ILT_PAGE_CIDS))
1669
1670 int qm_cid_count;
1671
1672 bool dropless_fc;
1673
1674 void *t2;
1675 dma_addr_t t2_mapping;
1676 struct cnic_ops __rcu *cnic_ops;
1677 void *cnic_data;
1678 u32 cnic_tag;
1679 struct cnic_eth_dev cnic_eth_dev;
1680 union host_hc_status_block cnic_sb;
1681 dma_addr_t cnic_sb_mapping;
1682 struct eth_spe *cnic_kwq;
1683 struct eth_spe *cnic_kwq_prod;
1684 struct eth_spe *cnic_kwq_cons;
1685 struct eth_spe *cnic_kwq_last;
1686 u16 cnic_kwq_pending;
1687 u16 cnic_spq_pending;
1688 u8 fip_mac[ETH_ALEN];
1689 struct mutex cnic_mutex;
1690 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1691
1692 /* Start index of the "special" (CNIC related) L2 clients */
1693 u8 cnic_base_cl_id;
1694
1695 int dmae_ready;
1696 /* used to synchronize dmae accesses */
1697 spinlock_t dmae_lock;
1698
1699 /* used to protect the FW mail box */
1700 struct mutex fw_mb_mutex;
1701
1702 /* used to synchronize stats collecting */
1703 int stats_state;
1704
1705 /* used for synchronization of concurrent threads statistics handling */
1706 struct semaphore stats_lock;
1707
1708 /* used by dmae command loader */
1709 struct dmae_command stats_dmae;
1710 int executer_idx;
1711
1712 u16 stats_counter;
1713 struct bnx2x_eth_stats eth_stats;
1714 struct host_func_stats func_stats;
1715 struct bnx2x_eth_stats_old eth_stats_old;
1716 struct bnx2x_net_stats_old net_stats_old;
1717 struct bnx2x_fw_port_stats_old fw_stats_old;
1718 bool stats_init;
1719
1720 struct z_stream_s *strm;
1721 void *gunzip_buf;
1722 dma_addr_t gunzip_mapping;
1723 int gunzip_outlen;
1724 #define FW_BUF_SIZE 0x8000
1725 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1726 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1727 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1728
1729 struct raw_op *init_ops;
1730 /* Init blocks offsets inside init_ops */
1731 u16 *init_ops_offsets;
1732 /* Data blob - has 32 bit granularity */
1733 u32 *init_data;
1734 u32 init_mode_flags;
1735 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1736 /* Zipped PRAM blobs - raw data */
1737 const u8 *tsem_int_table_data;
1738 const u8 *tsem_pram_data;
1739 const u8 *usem_int_table_data;
1740 const u8 *usem_pram_data;
1741 const u8 *xsem_int_table_data;
1742 const u8 *xsem_pram_data;
1743 const u8 *csem_int_table_data;
1744 const u8 *csem_pram_data;
1745 #define INIT_OPS(bp) (bp->init_ops)
1746 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1747 #define INIT_DATA(bp) (bp->init_data)
1748 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1749 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1750 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1751 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1752 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1753 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1754 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1755 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1756
1757 #define PHY_FW_VER_LEN 20
1758 char fw_ver[32];
1759 const struct firmware *firmware;
1760
1761 struct bnx2x_vfdb *vfdb;
1762 #define IS_SRIOV(bp) ((bp)->vfdb)
1763
1764 /* DCB support on/off */
1765 u16 dcb_state;
1766 #define BNX2X_DCB_STATE_OFF 0
1767 #define BNX2X_DCB_STATE_ON 1
1768
1769 /* DCBX engine mode */
1770 int dcbx_enabled;
1771 #define BNX2X_DCBX_ENABLED_OFF 0
1772 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1773 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1774 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1775
1776 bool dcbx_mode_uset;
1777
1778 struct bnx2x_config_dcbx_params dcbx_config_params;
1779 struct bnx2x_dcbx_port_params dcbx_port_params;
1780 int dcb_version;
1781
1782 /* CAM credit pools */
1783 struct bnx2x_credit_pool_obj vlans_pool;
1784
1785 struct bnx2x_credit_pool_obj macs_pool;
1786
1787 /* RX_MODE object */
1788 struct bnx2x_rx_mode_obj rx_mode_obj;
1789
1790 /* MCAST object */
1791 struct bnx2x_mcast_obj mcast_obj;
1792
1793 /* RSS configuration object */
1794 struct bnx2x_rss_config_obj rss_conf_obj;
1795
1796 /* Function State controlling object */
1797 struct bnx2x_func_sp_obj func_obj;
1798
1799 unsigned long sp_state;
1800
1801 /* operation indication for the sp_rtnl task */
1802 unsigned long sp_rtnl_state;
1803
1804 /* Indication of the IOV tasks */
1805 unsigned long iov_task_state;
1806
1807 /* DCBX Negotiation results */
1808 struct dcbx_features dcbx_local_feat;
1809 u32 dcbx_error;
1810
1811 #ifdef BCM_DCBNL
1812 struct dcbx_features dcbx_remote_feat;
1813 u32 dcbx_remote_flags;
1814 #endif
1815 /* AFEX: store default vlan used */
1816 int afex_def_vlan_tag;
1817 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1818 u32 pending_max;
1819
1820 /* multiple tx classes of service */
1821 u8 max_cos;
1822
1823 /* priority to cos mapping */
1824 u8 prio_to_cos[8];
1825
1826 int fp_array_size;
1827 u32 dump_preset_idx;
1828
1829 u8 phys_port_id[ETH_ALEN];
1830
1831 /* PTP related context */
1832 struct ptp_clock *ptp_clock;
1833 struct ptp_clock_info ptp_clock_info;
1834 struct work_struct ptp_task;
1835 struct cyclecounter cyclecounter;
1836 struct timecounter timecounter;
1837 bool timecounter_init_done;
1838 struct sk_buff *ptp_tx_skb;
1839 unsigned long ptp_tx_start;
1840 bool hwtstamp_ioctl_called;
1841 u16 tx_type;
1842 u16 rx_filter;
1843
1844 struct bnx2x_link_report_data vf_link_vars;
1845 struct list_head vlan_reg;
1846 u16 vlan_cnt;
1847 u16 vlan_credit;
1848 bool accept_any_vlan;
1849
1850 /* Vxlan/Geneve related information */
1851 struct bnx2x_udp_tunnel udp_tunnel_ports[BNX2X_UDP_PORT_MAX];
1852 };
1853
1854 /* Tx queues may be less or equal to Rx queues */
1855 extern int num_queues;
1856 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1857 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1858 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1859 (bp)->num_cnic_queues)
1860 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1861
1862 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1863
1864 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1865 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1866
1867 #define RSS_IPV4_CAP_MASK \
1868 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1869
1870 #define RSS_IPV4_TCP_CAP_MASK \
1871 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1872
1873 #define RSS_IPV6_CAP_MASK \
1874 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1875
1876 #define RSS_IPV6_TCP_CAP_MASK \
1877 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1878
1879 struct bnx2x_func_init_params {
1880 /* dma */
1881 bool spq_active;
1882 dma_addr_t spq_map;
1883 u16 spq_prod;
1884
1885 u16 func_id; /* abs fid */
1886 u16 pf_id;
1887 };
1888
1889 #define for_each_cnic_queue(bp, var) \
1890 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1891 (var)++) \
1892 if (skip_queue(bp, var)) \
1893 continue; \
1894 else
1895
1896 #define for_each_eth_queue(bp, var) \
1897 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1898
1899 #define for_each_nondefault_eth_queue(bp, var) \
1900 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1901
1902 #define for_each_queue(bp, var) \
1903 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1904 if (skip_queue(bp, var)) \
1905 continue; \
1906 else
1907
1908 /* Skip forwarding FP */
1909 #define for_each_valid_rx_queue(bp, var) \
1910 for ((var) = 0; \
1911 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1912 BNX2X_NUM_ETH_QUEUES(bp)); \
1913 (var)++) \
1914 if (skip_rx_queue(bp, var)) \
1915 continue; \
1916 else
1917
1918 #define for_each_rx_queue_cnic(bp, var) \
1919 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1920 (var)++) \
1921 if (skip_rx_queue(bp, var)) \
1922 continue; \
1923 else
1924
1925 #define for_each_rx_queue(bp, var) \
1926 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1927 if (skip_rx_queue(bp, var)) \
1928 continue; \
1929 else
1930
1931 /* Skip OOO FP */
1932 #define for_each_valid_tx_queue(bp, var) \
1933 for ((var) = 0; \
1934 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1935 BNX2X_NUM_ETH_QUEUES(bp)); \
1936 (var)++) \
1937 if (skip_tx_queue(bp, var)) \
1938 continue; \
1939 else
1940
1941 #define for_each_tx_queue_cnic(bp, var) \
1942 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1943 (var)++) \
1944 if (skip_tx_queue(bp, var)) \
1945 continue; \
1946 else
1947
1948 #define for_each_tx_queue(bp, var) \
1949 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1950 if (skip_tx_queue(bp, var)) \
1951 continue; \
1952 else
1953
1954 #define for_each_nondefault_queue(bp, var) \
1955 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1956 if (skip_queue(bp, var)) \
1957 continue; \
1958 else
1959
1960 #define for_each_cos_in_tx_queue(fp, var) \
1961 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1962
1963 /* skip rx queue
1964 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1965 */
1966 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1967
1968 /* skip tx queue
1969 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1970 */
1971 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1972
1973 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1974
1975 /**
1976 * bnx2x_set_mac_one - configure a single MAC address
1977 *
1978 * @bp: driver handle
1979 * @mac: MAC to configure
1980 * @obj: MAC object handle
1981 * @set: if 'true' add a new MAC, otherwise - delete
1982 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1983 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1984 *
1985 * Configures one MAC according to provided parameters or continues the
1986 * execution of previously scheduled commands if RAMROD_CONT is set in
1987 * ramrod_flags.
1988 *
1989 * Returns zero if operation has successfully completed, a positive value if the
1990 * operation has been successfully scheduled and a negative - if a requested
1991 * operations has failed.
1992 */
1993 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1994 struct bnx2x_vlan_mac_obj *obj, bool set,
1995 int mac_type, unsigned long *ramrod_flags);
1996
1997 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
1998 struct bnx2x_vlan_mac_obj *obj, bool set,
1999 unsigned long *ramrod_flags);
2000
2001 /**
2002 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
2003 *
2004 * @bp: driver handle
2005 * @mac_obj: MAC object handle
2006 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
2007 * @wait_for_comp: if 'true' block until completion
2008 *
2009 * Deletes all MACs of the specific type (e.g. ETH, UC list).
2010 *
2011 * Returns zero if operation has successfully completed, a positive value if the
2012 * operation has been successfully scheduled and a negative - if a requested
2013 * operations has failed.
2014 */
2015 int bnx2x_del_all_macs(struct bnx2x *bp,
2016 struct bnx2x_vlan_mac_obj *mac_obj,
2017 int mac_type, bool wait_for_comp);
2018
2019 /* Init Function API */
2020 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
2021 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
2022 u8 vf_valid, int fw_sb_id, int igu_sb_id);
2023 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
2024 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2025 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
2026 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2027 void bnx2x_read_mf_cfg(struct bnx2x *bp);
2028
2029 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
2030
2031 /* dmae */
2032 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
2033 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
2034 u32 len32);
2035 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
2036 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
2037 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
2038 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
2039 bool with_comp, u8 comp_type);
2040
2041 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2042 u8 src_type, u8 dst_type);
2043 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2044 u32 *comp);
2045
2046 /* FLR related routines */
2047 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
2048 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
2049 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
2050 u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
2051 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
2052 char *msg, u32 poll_cnt);
2053
2054 void bnx2x_calc_fc_adv(struct bnx2x *bp);
2055 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2056 u32 data_hi, u32 data_lo, int cmd_type);
2057 void bnx2x_update_coalesce(struct bnx2x *bp);
2058 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
2059
2060 bool bnx2x_port_after_undi(struct bnx2x *bp);
2061
2062 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
2063 int wait)
2064 {
2065 u32 val;
2066
2067 do {
2068 val = REG_RD(bp, reg);
2069 if (val == expected)
2070 break;
2071 ms -= wait;
2072 msleep(wait);
2073
2074 } while (ms > 0);
2075
2076 return val;
2077 }
2078
2079 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
2080 bool is_pf);
2081
2082 #define BNX2X_ILT_ZALLOC(x, y, size) \
2083 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL)
2084
2085 #define BNX2X_ILT_FREE(x, y, size) \
2086 do { \
2087 if (x) { \
2088 dma_free_coherent(&bp->pdev->dev, size, x, y); \
2089 x = NULL; \
2090 y = 0; \
2091 } \
2092 } while (0)
2093
2094 #define ILOG2(x) (ilog2((x)))
2095
2096 #define ILT_NUM_PAGE_ENTRIES (3072)
2097 /* In 57710/11 we use whole table since we have 8 func
2098 * In 57712 we have only 4 func, but use same size per func, then only half of
2099 * the table in use
2100 */
2101 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
2102
2103 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
2104 /*
2105 * the phys address is shifted right 12 bits and has an added
2106 * 1=valid bit added to the 53rd bit
2107 * then since this is a wide register(TM)
2108 * we split it into two 32 bit writes
2109 */
2110 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
2111 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
2112
2113 /* load/unload mode */
2114 #define LOAD_NORMAL 0
2115 #define LOAD_OPEN 1
2116 #define LOAD_DIAG 2
2117 #define LOAD_LOOPBACK_EXT 3
2118 #define UNLOAD_NORMAL 0
2119 #define UNLOAD_CLOSE 1
2120 #define UNLOAD_RECOVERY 2
2121
2122 /* DMAE command defines */
2123 #define DMAE_TIMEOUT -1
2124 #define DMAE_PCI_ERROR -2 /* E2 and onward */
2125 #define DMAE_NOT_RDY -3
2126 #define DMAE_PCI_ERR_FLAG 0x80000000
2127
2128 #define DMAE_SRC_PCI 0
2129 #define DMAE_SRC_GRC 1
2130
2131 #define DMAE_DST_NONE 0
2132 #define DMAE_DST_PCI 1
2133 #define DMAE_DST_GRC 2
2134
2135 #define DMAE_COMP_PCI 0
2136 #define DMAE_COMP_GRC 1
2137
2138 /* E2 and onward - PCI error handling in the completion */
2139
2140 #define DMAE_COMP_REGULAR 0
2141 #define DMAE_COM_SET_ERR 1
2142
2143 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
2144 DMAE_COMMAND_SRC_SHIFT)
2145 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
2146 DMAE_COMMAND_SRC_SHIFT)
2147
2148 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
2149 DMAE_COMMAND_DST_SHIFT)
2150 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
2151 DMAE_COMMAND_DST_SHIFT)
2152
2153 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
2154 DMAE_COMMAND_C_DST_SHIFT)
2155 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
2156 DMAE_COMMAND_C_DST_SHIFT)
2157
2158 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
2159
2160 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2161 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2162 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2163 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2164
2165 #define DMAE_CMD_PORT_0 0
2166 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
2167
2168 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
2169 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
2170 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
2171
2172 #define DMAE_SRC_PF 0
2173 #define DMAE_SRC_VF 1
2174
2175 #define DMAE_DST_PF 0
2176 #define DMAE_DST_VF 1
2177
2178 #define DMAE_C_SRC 0
2179 #define DMAE_C_DST 1
2180
2181 #define DMAE_LEN32_RD_MAX 0x80
2182 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2183
2184 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
2185 * indicates error
2186 */
2187
2188 #define MAX_DMAE_C_PER_PORT 8
2189 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2190 BP_VN(bp))
2191 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2192 E1HVN_MAX)
2193
2194 /* Following is the DMAE channel number allocation for the clients.
2195 * MFW: OCBB/OCSD implementations use DMAE channels 14/15 respectively.
2196 * Driver: 0-3 and 8-11 (for PF dmae operations)
2197 * 4 and 12 (for stats requests)
2198 */
2199 #define BNX2X_FW_DMAE_C 13 /* Channel for FW DMAE operations */
2200
2201 /* PCIE link and speed */
2202 #define PCICFG_LINK_WIDTH 0x1f00000
2203 #define PCICFG_LINK_WIDTH_SHIFT 20
2204 #define PCICFG_LINK_SPEED 0xf0000
2205 #define PCICFG_LINK_SPEED_SHIFT 16
2206
2207 #define BNX2X_NUM_TESTS_SF 7
2208 #define BNX2X_NUM_TESTS_MF 3
2209 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2210 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF)
2211
2212 #define BNX2X_PHY_LOOPBACK 0
2213 #define BNX2X_MAC_LOOPBACK 1
2214 #define BNX2X_EXT_LOOPBACK 2
2215 #define BNX2X_PHY_LOOPBACK_FAILED 1
2216 #define BNX2X_MAC_LOOPBACK_FAILED 2
2217 #define BNX2X_EXT_LOOPBACK_FAILED 3
2218 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
2219 BNX2X_PHY_LOOPBACK_FAILED)
2220
2221 #define STROM_ASSERT_ARRAY_SIZE 50
2222
2223 /* must be used on a CID before placing it on a HW ring */
2224 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
2225 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2226 (x))
2227
2228 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2229 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2230
2231 #define BNX2X_BTR 4
2232 #define MAX_SPQ_PENDING 8
2233
2234 /* CMNG constants, as derived from system spec calculations */
2235 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2236 #define DEF_MIN_RATE 100
2237 /* resolution of the rate shaping timer - 400 usec */
2238 #define RS_PERIODIC_TIMEOUT_USEC 400
2239 /* number of bytes in single QM arbitration cycle -
2240 * coefficient for calculating the fairness timer */
2241 #define QM_ARB_BYTES 160000
2242 /* resolution of Min algorithm 1:100 */
2243 #define MIN_RES 100
2244 /* how many bytes above threshold for the minimal credit of Min algorithm*/
2245 #define MIN_ABOVE_THRESH 32768
2246 /* Fairness algorithm integration time coefficient -
2247 * for calculating the actual Tfair */
2248 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2249 /* Memory of fairness algorithm . 2 cycles */
2250 #define FAIR_MEM 2
2251
2252 #define ATTN_NIG_FOR_FUNC (1L << 8)
2253 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2254 #define GPIO_2_FUNC (1L << 10)
2255 #define GPIO_3_FUNC (1L << 11)
2256 #define GPIO_4_FUNC (1L << 12)
2257 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2258 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2259 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2260 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2261 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2262 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2263
2264 #define ATTN_HARD_WIRED_MASK 0xff00
2265 #define ATTENTION_ID 4
2266
2267 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \
2268 IS_MF_FCOE_AFEX(bp))
2269
2270 /* stuff added to make the code fit 80Col */
2271
2272 #define BNX2X_PMF_LINK_ASSERT \
2273 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2274
2275 #define BNX2X_MC_ASSERT_BITS \
2276 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2277 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2278 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2279 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2280
2281 #define BNX2X_MCP_ASSERT \
2282 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2283
2284 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2285 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2286 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2287 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2288 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2289 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2290 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2291
2292 #define HW_INTERRUPT_ASSERT_SET_0 \
2293 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2294 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2295 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2296 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
2297 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2298 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2299 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2300 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2301 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2302 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2303 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2304 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2305 #define HW_INTERRUPT_ASSERT_SET_1 \
2306 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2307 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2308 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2309 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2310 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2311 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2312 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2313 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2314 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2315 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2316 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2317 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2318 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2319 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2320 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2321 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2322 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2323 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2324 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2325 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2326 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2327 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2328 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2329 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2330 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2331 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2332 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2333 #define HW_INTERRUPT_ASSERT_SET_2 \
2334 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2335 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2336 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2337 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2338 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2339 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2340 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2341 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2342 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2343 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2344 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2345 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2346 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2347
2348 #define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \
2349 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2350 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2351 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
2352
2353 #define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \
2354 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2355
2356 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2357 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2358
2359 #define MULTI_MASK 0x7f
2360
2361 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2362 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2363 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2364 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2365
2366 #define DEF_USB_IGU_INDEX_OFF \
2367 offsetof(struct cstorm_def_status_block_u, igu_index)
2368 #define DEF_CSB_IGU_INDEX_OFF \
2369 offsetof(struct cstorm_def_status_block_c, igu_index)
2370 #define DEF_XSB_IGU_INDEX_OFF \
2371 offsetof(struct xstorm_def_status_block, igu_index)
2372 #define DEF_TSB_IGU_INDEX_OFF \
2373 offsetof(struct tstorm_def_status_block, igu_index)
2374
2375 #define DEF_USB_SEGMENT_OFF \
2376 offsetof(struct cstorm_def_status_block_u, segment)
2377 #define DEF_CSB_SEGMENT_OFF \
2378 offsetof(struct cstorm_def_status_block_c, segment)
2379 #define DEF_XSB_SEGMENT_OFF \
2380 offsetof(struct xstorm_def_status_block, segment)
2381 #define DEF_TSB_SEGMENT_OFF \
2382 offsetof(struct tstorm_def_status_block, segment)
2383
2384 #define BNX2X_SP_DSB_INDEX \
2385 (&bp->def_status_blk->sp_sb.\
2386 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2387
2388 #define CAM_IS_INVALID(x) \
2389 (GET_FLAG(x.flags, \
2390 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2391 (T_ETH_MAC_COMMAND_INVALIDATE))
2392
2393 /* Number of u32 elements in MC hash array */
2394 #define MC_HASH_SIZE 8
2395 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2396 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2397
2398 #ifndef PXP2_REG_PXP2_INT_STS
2399 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2400 #endif
2401
2402 #ifndef ETH_MAX_RX_CLIENTS_E2
2403 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2404 #endif
2405
2406 #define BNX2X_VPD_LEN 128
2407 #define VENDOR_ID_LEN 4
2408
2409 #define VF_ACQUIRE_THRESH 3
2410 #define VF_ACQUIRE_MAC_FILTERS 1
2411 #define VF_ACQUIRE_MC_FILTERS 10
2412 #define VF_ACQUIRE_VLAN_FILTERS 2 /* VLAN0 + 'real' VLAN */
2413
2414 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2415 (!((me_reg) & ME_REG_VF_ERR)))
2416 int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err);
2417
2418 /* Congestion management fairness mode */
2419 #define CMNG_FNS_NONE 0
2420 #define CMNG_FNS_MINMAX 1
2421
2422 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2423 #define HC_SEG_ACCESS_ATTN 4
2424 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2425
2426 static const u32 dmae_reg_go_c[] = {
2427 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2428 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2429 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2430 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2431 };
2432
2433 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
2434 void bnx2x_notify_link_changed(struct bnx2x *bp);
2435
2436 #define BNX2X_MF_SD_PROTOCOL(bp) \
2437 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2438
2439 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2440 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2441
2442 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2443 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2444
2445 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2446 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2447 #define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp))
2448
2449 #define IS_MF_ISCSI_ONLY(bp) (IS_MF_ISCSI_SD(bp) || IS_MF_ISCSI_SI(bp))
2450
2451 #define BNX2X_MF_EXT_PROTOCOL_MASK \
2452 (MACP_FUNC_CFG_FLAGS_ETHERNET | \
2453 MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD | \
2454 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2455
2456 #define BNX2X_MF_EXT_PROT(bp) ((bp)->mf_ext_config & \
2457 BNX2X_MF_EXT_PROTOCOL_MASK)
2458
2459 #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp) \
2460 (BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2461
2462 #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp) \
2463 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2464
2465 #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) \
2466 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD)
2467
2468 #define IS_MF_FCOE_AFEX(bp) \
2469 (IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))
2470
2471 #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) \
2472 (IS_MF_SD(bp) && \
2473 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2474 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2475
2476 #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp) \
2477 (IS_MF_SI(bp) && \
2478 (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) || \
2479 BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)))
2480
2481 #define IS_MF_STORAGE_PERSONALITY_ONLY(bp) \
2482 (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) || \
2483 IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp))
2484
2485 /* Determines whether BW configuration arrives in 100Mb units or in
2486 * percentages from actual physical link speed.
2487 */
2488 #define IS_MF_PERCENT_BW(bp) (IS_MF_SI(bp) || IS_MF_UFP(bp) || IS_MF_BD(bp))
2489
2490 #define SET_FLAG(value, mask, flag) \
2491 do {\
2492 (value) &= ~(mask);\
2493 (value) |= ((flag) << (mask##_SHIFT));\
2494 } while (0)
2495
2496 #define GET_FLAG(value, mask) \
2497 (((value) & (mask)) >> (mask##_SHIFT))
2498
2499 #define GET_FIELD(value, fname) \
2500 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2501
2502 enum {
2503 SWITCH_UPDATE,
2504 AFEX_UPDATE,
2505 };
2506
2507 #define NUM_MACS 8
2508
2509 void bnx2x_set_local_cmng(struct bnx2x *bp);
2510
2511 void bnx2x_update_mng_version(struct bnx2x *bp);
2512
2513 void bnx2x_update_mfw_dump(struct bnx2x *bp);
2514
2515 #define MCPR_SCRATCH_BASE(bp) \
2516 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
2517
2518 #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX))
2519
2520 void bnx2x_init_ptp(struct bnx2x *bp);
2521 int bnx2x_configure_ptp_filters(struct bnx2x *bp);
2522 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb);
2523 void bnx2x_register_phc(struct bnx2x *bp);
2524
2525 #define BNX2X_MAX_PHC_DRIFT 31000000
2526 #define BNX2X_PTP_TX_TIMEOUT
2527
2528 /* Re-configure all previously configured vlan filters.
2529 * Meant for implicit re-load flows.
2530 */
2531 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp);
2532
2533 #endif /* bnx2x.h */
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git