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bnxt_en: Check context memory requirements from firmware.
[thirdparty/kernel/stable.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
31 #include <asm/page.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
34 #include <linux/if.h>
35 #include <linux/if_vlan.h>
36 #include <linux/if_bridge.h>
37 #include <linux/rtc.h>
38 #include <linux/bpf.h>
39 #include <net/ip.h>
40 #include <net/tcp.h>
41 #include <net/udp.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <net/udp_tunnel.h>
45 #include <linux/workqueue.h>
46 #include <linux/prefetch.h>
47 #include <linux/cache.h>
48 #include <linux/log2.h>
49 #include <linux/aer.h>
50 #include <linux/bitmap.h>
51 #include <linux/cpu_rmap.h>
52 #include <linux/cpumask.h>
53 #include <net/pkt_cls.h>
54 #include <linux/hwmon.h>
55 #include <linux/hwmon-sysfs.h>
56
57 #include "bnxt_hsi.h"
58 #include "bnxt.h"
59 #include "bnxt_ulp.h"
60 #include "bnxt_sriov.h"
61 #include "bnxt_ethtool.h"
62 #include "bnxt_dcb.h"
63 #include "bnxt_xdp.h"
64 #include "bnxt_vfr.h"
65 #include "bnxt_tc.h"
66 #include "bnxt_devlink.h"
67 #include "bnxt_debugfs.h"
68
69 #define BNXT_TX_TIMEOUT (5 * HZ)
70
71 static const char version[] =
72 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
73
74 MODULE_LICENSE("GPL");
75 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
76 MODULE_VERSION(DRV_MODULE_VERSION);
77
78 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
79 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
80 #define BNXT_RX_COPY_THRESH 256
81
82 #define BNXT_TX_PUSH_THRESH 164
83
84 enum board_idx {
85 BCM57301,
86 BCM57302,
87 BCM57304,
88 BCM57417_NPAR,
89 BCM58700,
90 BCM57311,
91 BCM57312,
92 BCM57402,
93 BCM57404,
94 BCM57406,
95 BCM57402_NPAR,
96 BCM57407,
97 BCM57412,
98 BCM57414,
99 BCM57416,
100 BCM57417,
101 BCM57412_NPAR,
102 BCM57314,
103 BCM57417_SFP,
104 BCM57416_SFP,
105 BCM57404_NPAR,
106 BCM57406_NPAR,
107 BCM57407_SFP,
108 BCM57407_NPAR,
109 BCM57414_NPAR,
110 BCM57416_NPAR,
111 BCM57452,
112 BCM57454,
113 BCM5745x_NPAR,
114 BCM58802,
115 BCM58804,
116 BCM58808,
117 NETXTREME_E_VF,
118 NETXTREME_C_VF,
119 NETXTREME_S_VF,
120 };
121
122 /* indexed by enum above */
123 static const struct {
124 char *name;
125 } board_info[] = {
126 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
127 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
128 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
129 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
130 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
131 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
132 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
133 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
134 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
135 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
136 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
137 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
138 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
139 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
140 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
141 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
142 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
143 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
144 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
145 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
146 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
147 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
148 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
149 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
150 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
151 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
152 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
153 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
154 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
155 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
156 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
157 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
158 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
159 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
160 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
161 };
162
163 static const struct pci_device_id bnxt_pci_tbl[] = {
164 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
165 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
166 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
167 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
168 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
169 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
170 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
171 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
172 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
173 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
174 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
175 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
176 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
177 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
178 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
179 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
180 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
181 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
182 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
183 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
184 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
185 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
186 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
187 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
188 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
189 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
190 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
191 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
192 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
193 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
194 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
195 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
196 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
197 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
198 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
199 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
200 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
201 #ifdef CONFIG_BNXT_SRIOV
202 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
203 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
204 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
205 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
206 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
207 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
208 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
209 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
210 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
211 #endif
212 { 0 }
213 };
214
215 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
216
217 static const u16 bnxt_vf_req_snif[] = {
218 HWRM_FUNC_CFG,
219 HWRM_FUNC_VF_CFG,
220 HWRM_PORT_PHY_QCFG,
221 HWRM_CFA_L2_FILTER_ALLOC,
222 };
223
224 static const u16 bnxt_async_events_arr[] = {
225 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
226 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
227 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
228 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
229 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
230 };
231
232 static struct workqueue_struct *bnxt_pf_wq;
233
234 static bool bnxt_vf_pciid(enum board_idx idx)
235 {
236 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
237 idx == NETXTREME_S_VF);
238 }
239
240 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
241 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
242 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
243
244 #define BNXT_CP_DB_REARM(db, raw_cons) \
245 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
246
247 #define BNXT_CP_DB(db, raw_cons) \
248 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
249
250 #define BNXT_CP_DB_IRQ_DIS(db) \
251 writel(DB_CP_IRQ_DIS_FLAGS, db)
252
253 const u16 bnxt_lhint_arr[] = {
254 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
255 TX_BD_FLAGS_LHINT_512_TO_1023,
256 TX_BD_FLAGS_LHINT_1024_TO_2047,
257 TX_BD_FLAGS_LHINT_1024_TO_2047,
258 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
259 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
260 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
261 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
262 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
263 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
264 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
265 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
266 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
267 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
268 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
269 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
270 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
271 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
272 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
273 };
274
275 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
276 {
277 struct metadata_dst *md_dst = skb_metadata_dst(skb);
278
279 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
280 return 0;
281
282 return md_dst->u.port_info.port_id;
283 }
284
285 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
286 {
287 struct bnxt *bp = netdev_priv(dev);
288 struct tx_bd *txbd;
289 struct tx_bd_ext *txbd1;
290 struct netdev_queue *txq;
291 int i;
292 dma_addr_t mapping;
293 unsigned int length, pad = 0;
294 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
295 u16 prod, last_frag;
296 struct pci_dev *pdev = bp->pdev;
297 struct bnxt_tx_ring_info *txr;
298 struct bnxt_sw_tx_bd *tx_buf;
299
300 i = skb_get_queue_mapping(skb);
301 if (unlikely(i >= bp->tx_nr_rings)) {
302 dev_kfree_skb_any(skb);
303 return NETDEV_TX_OK;
304 }
305
306 txq = netdev_get_tx_queue(dev, i);
307 txr = &bp->tx_ring[bp->tx_ring_map[i]];
308 prod = txr->tx_prod;
309
310 free_size = bnxt_tx_avail(bp, txr);
311 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
312 netif_tx_stop_queue(txq);
313 return NETDEV_TX_BUSY;
314 }
315
316 length = skb->len;
317 len = skb_headlen(skb);
318 last_frag = skb_shinfo(skb)->nr_frags;
319
320 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
321
322 txbd->tx_bd_opaque = prod;
323
324 tx_buf = &txr->tx_buf_ring[prod];
325 tx_buf->skb = skb;
326 tx_buf->nr_frags = last_frag;
327
328 vlan_tag_flags = 0;
329 cfa_action = bnxt_xmit_get_cfa_action(skb);
330 if (skb_vlan_tag_present(skb)) {
331 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
332 skb_vlan_tag_get(skb);
333 /* Currently supports 8021Q, 8021AD vlan offloads
334 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
335 */
336 if (skb->vlan_proto == htons(ETH_P_8021Q))
337 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
338 }
339
340 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
341 struct tx_push_buffer *tx_push_buf = txr->tx_push;
342 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
343 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
344 void *pdata = tx_push_buf->data;
345 u64 *end;
346 int j, push_len;
347
348 /* Set COAL_NOW to be ready quickly for the next push */
349 tx_push->tx_bd_len_flags_type =
350 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
351 TX_BD_TYPE_LONG_TX_BD |
352 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
353 TX_BD_FLAGS_COAL_NOW |
354 TX_BD_FLAGS_PACKET_END |
355 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
356
357 if (skb->ip_summed == CHECKSUM_PARTIAL)
358 tx_push1->tx_bd_hsize_lflags =
359 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
360 else
361 tx_push1->tx_bd_hsize_lflags = 0;
362
363 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
364 tx_push1->tx_bd_cfa_action =
365 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
366
367 end = pdata + length;
368 end = PTR_ALIGN(end, 8) - 1;
369 *end = 0;
370
371 skb_copy_from_linear_data(skb, pdata, len);
372 pdata += len;
373 for (j = 0; j < last_frag; j++) {
374 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
375 void *fptr;
376
377 fptr = skb_frag_address_safe(frag);
378 if (!fptr)
379 goto normal_tx;
380
381 memcpy(pdata, fptr, skb_frag_size(frag));
382 pdata += skb_frag_size(frag);
383 }
384
385 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
386 txbd->tx_bd_haddr = txr->data_mapping;
387 prod = NEXT_TX(prod);
388 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
389 memcpy(txbd, tx_push1, sizeof(*txbd));
390 prod = NEXT_TX(prod);
391 tx_push->doorbell =
392 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
393 txr->tx_prod = prod;
394
395 tx_buf->is_push = 1;
396 netdev_tx_sent_queue(txq, skb->len);
397 wmb(); /* Sync is_push and byte queue before pushing data */
398
399 push_len = (length + sizeof(*tx_push) + 7) / 8;
400 if (push_len > 16) {
401 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
402 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
403 (push_len - 16) << 1);
404 } else {
405 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
406 push_len);
407 }
408
409 goto tx_done;
410 }
411
412 normal_tx:
413 if (length < BNXT_MIN_PKT_SIZE) {
414 pad = BNXT_MIN_PKT_SIZE - length;
415 if (skb_pad(skb, pad)) {
416 /* SKB already freed. */
417 tx_buf->skb = NULL;
418 return NETDEV_TX_OK;
419 }
420 length = BNXT_MIN_PKT_SIZE;
421 }
422
423 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
424
425 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
426 dev_kfree_skb_any(skb);
427 tx_buf->skb = NULL;
428 return NETDEV_TX_OK;
429 }
430
431 dma_unmap_addr_set(tx_buf, mapping, mapping);
432 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
433 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
434
435 txbd->tx_bd_haddr = cpu_to_le64(mapping);
436
437 prod = NEXT_TX(prod);
438 txbd1 = (struct tx_bd_ext *)
439 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
440
441 txbd1->tx_bd_hsize_lflags = 0;
442 if (skb_is_gso(skb)) {
443 u32 hdr_len;
444
445 if (skb->encapsulation)
446 hdr_len = skb_inner_network_offset(skb) +
447 skb_inner_network_header_len(skb) +
448 inner_tcp_hdrlen(skb);
449 else
450 hdr_len = skb_transport_offset(skb) +
451 tcp_hdrlen(skb);
452
453 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
454 TX_BD_FLAGS_T_IPID |
455 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
456 length = skb_shinfo(skb)->gso_size;
457 txbd1->tx_bd_mss = cpu_to_le32(length);
458 length += hdr_len;
459 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
460 txbd1->tx_bd_hsize_lflags =
461 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
462 txbd1->tx_bd_mss = 0;
463 }
464
465 length >>= 9;
466 flags |= bnxt_lhint_arr[length];
467 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
468
469 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
470 txbd1->tx_bd_cfa_action =
471 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
472 for (i = 0; i < last_frag; i++) {
473 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
474
475 prod = NEXT_TX(prod);
476 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
477
478 len = skb_frag_size(frag);
479 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
480 DMA_TO_DEVICE);
481
482 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
483 goto tx_dma_error;
484
485 tx_buf = &txr->tx_buf_ring[prod];
486 dma_unmap_addr_set(tx_buf, mapping, mapping);
487
488 txbd->tx_bd_haddr = cpu_to_le64(mapping);
489
490 flags = len << TX_BD_LEN_SHIFT;
491 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
492 }
493
494 flags &= ~TX_BD_LEN;
495 txbd->tx_bd_len_flags_type =
496 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
497 TX_BD_FLAGS_PACKET_END);
498
499 netdev_tx_sent_queue(txq, skb->len);
500
501 /* Sync BD data before updating doorbell */
502 wmb();
503
504 prod = NEXT_TX(prod);
505 txr->tx_prod = prod;
506
507 if (!skb->xmit_more || netif_xmit_stopped(txq))
508 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
509
510 tx_done:
511
512 mmiowb();
513
514 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
515 if (skb->xmit_more && !tx_buf->is_push)
516 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
517
518 netif_tx_stop_queue(txq);
519
520 /* netif_tx_stop_queue() must be done before checking
521 * tx index in bnxt_tx_avail() below, because in
522 * bnxt_tx_int(), we update tx index before checking for
523 * netif_tx_queue_stopped().
524 */
525 smp_mb();
526 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
527 netif_tx_wake_queue(txq);
528 }
529 return NETDEV_TX_OK;
530
531 tx_dma_error:
532 last_frag = i;
533
534 /* start back at beginning and unmap skb */
535 prod = txr->tx_prod;
536 tx_buf = &txr->tx_buf_ring[prod];
537 tx_buf->skb = NULL;
538 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
539 skb_headlen(skb), PCI_DMA_TODEVICE);
540 prod = NEXT_TX(prod);
541
542 /* unmap remaining mapped pages */
543 for (i = 0; i < last_frag; i++) {
544 prod = NEXT_TX(prod);
545 tx_buf = &txr->tx_buf_ring[prod];
546 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
547 skb_frag_size(&skb_shinfo(skb)->frags[i]),
548 PCI_DMA_TODEVICE);
549 }
550
551 dev_kfree_skb_any(skb);
552 return NETDEV_TX_OK;
553 }
554
555 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
556 {
557 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
558 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
559 u16 cons = txr->tx_cons;
560 struct pci_dev *pdev = bp->pdev;
561 int i;
562 unsigned int tx_bytes = 0;
563
564 for (i = 0; i < nr_pkts; i++) {
565 struct bnxt_sw_tx_bd *tx_buf;
566 struct sk_buff *skb;
567 int j, last;
568
569 tx_buf = &txr->tx_buf_ring[cons];
570 cons = NEXT_TX(cons);
571 skb = tx_buf->skb;
572 tx_buf->skb = NULL;
573
574 if (tx_buf->is_push) {
575 tx_buf->is_push = 0;
576 goto next_tx_int;
577 }
578
579 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
580 skb_headlen(skb), PCI_DMA_TODEVICE);
581 last = tx_buf->nr_frags;
582
583 for (j = 0; j < last; j++) {
584 cons = NEXT_TX(cons);
585 tx_buf = &txr->tx_buf_ring[cons];
586 dma_unmap_page(
587 &pdev->dev,
588 dma_unmap_addr(tx_buf, mapping),
589 skb_frag_size(&skb_shinfo(skb)->frags[j]),
590 PCI_DMA_TODEVICE);
591 }
592
593 next_tx_int:
594 cons = NEXT_TX(cons);
595
596 tx_bytes += skb->len;
597 dev_kfree_skb_any(skb);
598 }
599
600 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
601 txr->tx_cons = cons;
602
603 /* Need to make the tx_cons update visible to bnxt_start_xmit()
604 * before checking for netif_tx_queue_stopped(). Without the
605 * memory barrier, there is a small possibility that bnxt_start_xmit()
606 * will miss it and cause the queue to be stopped forever.
607 */
608 smp_mb();
609
610 if (unlikely(netif_tx_queue_stopped(txq)) &&
611 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
612 __netif_tx_lock(txq, smp_processor_id());
613 if (netif_tx_queue_stopped(txq) &&
614 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
615 txr->dev_state != BNXT_DEV_STATE_CLOSING)
616 netif_tx_wake_queue(txq);
617 __netif_tx_unlock(txq);
618 }
619 }
620
621 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
622 gfp_t gfp)
623 {
624 struct device *dev = &bp->pdev->dev;
625 struct page *page;
626
627 page = alloc_page(gfp);
628 if (!page)
629 return NULL;
630
631 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
632 DMA_ATTR_WEAK_ORDERING);
633 if (dma_mapping_error(dev, *mapping)) {
634 __free_page(page);
635 return NULL;
636 }
637 *mapping += bp->rx_dma_offset;
638 return page;
639 }
640
641 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
642 gfp_t gfp)
643 {
644 u8 *data;
645 struct pci_dev *pdev = bp->pdev;
646
647 data = kmalloc(bp->rx_buf_size, gfp);
648 if (!data)
649 return NULL;
650
651 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
652 bp->rx_buf_use_size, bp->rx_dir,
653 DMA_ATTR_WEAK_ORDERING);
654
655 if (dma_mapping_error(&pdev->dev, *mapping)) {
656 kfree(data);
657 data = NULL;
658 }
659 return data;
660 }
661
662 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
663 u16 prod, gfp_t gfp)
664 {
665 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
666 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
667 dma_addr_t mapping;
668
669 if (BNXT_RX_PAGE_MODE(bp)) {
670 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
671
672 if (!page)
673 return -ENOMEM;
674
675 rx_buf->data = page;
676 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
677 } else {
678 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
679
680 if (!data)
681 return -ENOMEM;
682
683 rx_buf->data = data;
684 rx_buf->data_ptr = data + bp->rx_offset;
685 }
686 rx_buf->mapping = mapping;
687
688 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
689 return 0;
690 }
691
692 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
693 {
694 u16 prod = rxr->rx_prod;
695 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
696 struct rx_bd *cons_bd, *prod_bd;
697
698 prod_rx_buf = &rxr->rx_buf_ring[prod];
699 cons_rx_buf = &rxr->rx_buf_ring[cons];
700
701 prod_rx_buf->data = data;
702 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
703
704 prod_rx_buf->mapping = cons_rx_buf->mapping;
705
706 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
707 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
708
709 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
710 }
711
712 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
713 {
714 u16 next, max = rxr->rx_agg_bmap_size;
715
716 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
717 if (next >= max)
718 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
719 return next;
720 }
721
722 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
723 struct bnxt_rx_ring_info *rxr,
724 u16 prod, gfp_t gfp)
725 {
726 struct rx_bd *rxbd =
727 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
728 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
729 struct pci_dev *pdev = bp->pdev;
730 struct page *page;
731 dma_addr_t mapping;
732 u16 sw_prod = rxr->rx_sw_agg_prod;
733 unsigned int offset = 0;
734
735 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
736 page = rxr->rx_page;
737 if (!page) {
738 page = alloc_page(gfp);
739 if (!page)
740 return -ENOMEM;
741 rxr->rx_page = page;
742 rxr->rx_page_offset = 0;
743 }
744 offset = rxr->rx_page_offset;
745 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
746 if (rxr->rx_page_offset == PAGE_SIZE)
747 rxr->rx_page = NULL;
748 else
749 get_page(page);
750 } else {
751 page = alloc_page(gfp);
752 if (!page)
753 return -ENOMEM;
754 }
755
756 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
757 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
758 DMA_ATTR_WEAK_ORDERING);
759 if (dma_mapping_error(&pdev->dev, mapping)) {
760 __free_page(page);
761 return -EIO;
762 }
763
764 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
765 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
766
767 __set_bit(sw_prod, rxr->rx_agg_bmap);
768 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
769 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
770
771 rx_agg_buf->page = page;
772 rx_agg_buf->offset = offset;
773 rx_agg_buf->mapping = mapping;
774 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
775 rxbd->rx_bd_opaque = sw_prod;
776 return 0;
777 }
778
779 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
780 u32 agg_bufs)
781 {
782 struct bnxt *bp = bnapi->bp;
783 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
784 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
785 u16 prod = rxr->rx_agg_prod;
786 u16 sw_prod = rxr->rx_sw_agg_prod;
787 u32 i;
788
789 for (i = 0; i < agg_bufs; i++) {
790 u16 cons;
791 struct rx_agg_cmp *agg;
792 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
793 struct rx_bd *prod_bd;
794 struct page *page;
795
796 agg = (struct rx_agg_cmp *)
797 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
798 cons = agg->rx_agg_cmp_opaque;
799 __clear_bit(cons, rxr->rx_agg_bmap);
800
801 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
802 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
803
804 __set_bit(sw_prod, rxr->rx_agg_bmap);
805 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
806 cons_rx_buf = &rxr->rx_agg_ring[cons];
807
808 /* It is possible for sw_prod to be equal to cons, so
809 * set cons_rx_buf->page to NULL first.
810 */
811 page = cons_rx_buf->page;
812 cons_rx_buf->page = NULL;
813 prod_rx_buf->page = page;
814 prod_rx_buf->offset = cons_rx_buf->offset;
815
816 prod_rx_buf->mapping = cons_rx_buf->mapping;
817
818 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
819
820 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
821 prod_bd->rx_bd_opaque = sw_prod;
822
823 prod = NEXT_RX_AGG(prod);
824 sw_prod = NEXT_RX_AGG(sw_prod);
825 cp_cons = NEXT_CMP(cp_cons);
826 }
827 rxr->rx_agg_prod = prod;
828 rxr->rx_sw_agg_prod = sw_prod;
829 }
830
831 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
832 struct bnxt_rx_ring_info *rxr,
833 u16 cons, void *data, u8 *data_ptr,
834 dma_addr_t dma_addr,
835 unsigned int offset_and_len)
836 {
837 unsigned int payload = offset_and_len >> 16;
838 unsigned int len = offset_and_len & 0xffff;
839 struct skb_frag_struct *frag;
840 struct page *page = data;
841 u16 prod = rxr->rx_prod;
842 struct sk_buff *skb;
843 int off, err;
844
845 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
846 if (unlikely(err)) {
847 bnxt_reuse_rx_data(rxr, cons, data);
848 return NULL;
849 }
850 dma_addr -= bp->rx_dma_offset;
851 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
852 DMA_ATTR_WEAK_ORDERING);
853
854 if (unlikely(!payload))
855 payload = eth_get_headlen(data_ptr, len);
856
857 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
858 if (!skb) {
859 __free_page(page);
860 return NULL;
861 }
862
863 off = (void *)data_ptr - page_address(page);
864 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
865 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
866 payload + NET_IP_ALIGN);
867
868 frag = &skb_shinfo(skb)->frags[0];
869 skb_frag_size_sub(frag, payload);
870 frag->page_offset += payload;
871 skb->data_len -= payload;
872 skb->tail += payload;
873
874 return skb;
875 }
876
877 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
878 struct bnxt_rx_ring_info *rxr, u16 cons,
879 void *data, u8 *data_ptr,
880 dma_addr_t dma_addr,
881 unsigned int offset_and_len)
882 {
883 u16 prod = rxr->rx_prod;
884 struct sk_buff *skb;
885 int err;
886
887 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
888 if (unlikely(err)) {
889 bnxt_reuse_rx_data(rxr, cons, data);
890 return NULL;
891 }
892
893 skb = build_skb(data, 0);
894 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
895 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
896 if (!skb) {
897 kfree(data);
898 return NULL;
899 }
900
901 skb_reserve(skb, bp->rx_offset);
902 skb_put(skb, offset_and_len & 0xffff);
903 return skb;
904 }
905
906 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
907 struct sk_buff *skb, u16 cp_cons,
908 u32 agg_bufs)
909 {
910 struct pci_dev *pdev = bp->pdev;
911 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
912 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
913 u16 prod = rxr->rx_agg_prod;
914 u32 i;
915
916 for (i = 0; i < agg_bufs; i++) {
917 u16 cons, frag_len;
918 struct rx_agg_cmp *agg;
919 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
920 struct page *page;
921 dma_addr_t mapping;
922
923 agg = (struct rx_agg_cmp *)
924 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
925 cons = agg->rx_agg_cmp_opaque;
926 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
927 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
928
929 cons_rx_buf = &rxr->rx_agg_ring[cons];
930 skb_fill_page_desc(skb, i, cons_rx_buf->page,
931 cons_rx_buf->offset, frag_len);
932 __clear_bit(cons, rxr->rx_agg_bmap);
933
934 /* It is possible for bnxt_alloc_rx_page() to allocate
935 * a sw_prod index that equals the cons index, so we
936 * need to clear the cons entry now.
937 */
938 mapping = cons_rx_buf->mapping;
939 page = cons_rx_buf->page;
940 cons_rx_buf->page = NULL;
941
942 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
943 struct skb_shared_info *shinfo;
944 unsigned int nr_frags;
945
946 shinfo = skb_shinfo(skb);
947 nr_frags = --shinfo->nr_frags;
948 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
949
950 dev_kfree_skb(skb);
951
952 cons_rx_buf->page = page;
953
954 /* Update prod since possibly some pages have been
955 * allocated already.
956 */
957 rxr->rx_agg_prod = prod;
958 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
959 return NULL;
960 }
961
962 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
963 PCI_DMA_FROMDEVICE,
964 DMA_ATTR_WEAK_ORDERING);
965
966 skb->data_len += frag_len;
967 skb->len += frag_len;
968 skb->truesize += PAGE_SIZE;
969
970 prod = NEXT_RX_AGG(prod);
971 cp_cons = NEXT_CMP(cp_cons);
972 }
973 rxr->rx_agg_prod = prod;
974 return skb;
975 }
976
977 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
978 u8 agg_bufs, u32 *raw_cons)
979 {
980 u16 last;
981 struct rx_agg_cmp *agg;
982
983 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
984 last = RING_CMP(*raw_cons);
985 agg = (struct rx_agg_cmp *)
986 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
987 return RX_AGG_CMP_VALID(agg, *raw_cons);
988 }
989
990 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
991 unsigned int len,
992 dma_addr_t mapping)
993 {
994 struct bnxt *bp = bnapi->bp;
995 struct pci_dev *pdev = bp->pdev;
996 struct sk_buff *skb;
997
998 skb = napi_alloc_skb(&bnapi->napi, len);
999 if (!skb)
1000 return NULL;
1001
1002 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1003 bp->rx_dir);
1004
1005 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1006 len + NET_IP_ALIGN);
1007
1008 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1009 bp->rx_dir);
1010
1011 skb_put(skb, len);
1012 return skb;
1013 }
1014
1015 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
1016 u32 *raw_cons, void *cmp)
1017 {
1018 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1019 struct rx_cmp *rxcmp = cmp;
1020 u32 tmp_raw_cons = *raw_cons;
1021 u8 cmp_type, agg_bufs = 0;
1022
1023 cmp_type = RX_CMP_TYPE(rxcmp);
1024
1025 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1026 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1027 RX_CMP_AGG_BUFS) >>
1028 RX_CMP_AGG_BUFS_SHIFT;
1029 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1030 struct rx_tpa_end_cmp *tpa_end = cmp;
1031
1032 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1033 RX_TPA_END_CMP_AGG_BUFS) >>
1034 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1035 }
1036
1037 if (agg_bufs) {
1038 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1039 return -EBUSY;
1040 }
1041 *raw_cons = tmp_raw_cons;
1042 return 0;
1043 }
1044
1045 static void bnxt_queue_sp_work(struct bnxt *bp)
1046 {
1047 if (BNXT_PF(bp))
1048 queue_work(bnxt_pf_wq, &bp->sp_task);
1049 else
1050 schedule_work(&bp->sp_task);
1051 }
1052
1053 static void bnxt_cancel_sp_work(struct bnxt *bp)
1054 {
1055 if (BNXT_PF(bp))
1056 flush_workqueue(bnxt_pf_wq);
1057 else
1058 cancel_work_sync(&bp->sp_task);
1059 }
1060
1061 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1062 {
1063 if (!rxr->bnapi->in_reset) {
1064 rxr->bnapi->in_reset = true;
1065 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1066 bnxt_queue_sp_work(bp);
1067 }
1068 rxr->rx_next_cons = 0xffff;
1069 }
1070
1071 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1072 struct rx_tpa_start_cmp *tpa_start,
1073 struct rx_tpa_start_cmp_ext *tpa_start1)
1074 {
1075 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1076 u16 cons, prod;
1077 struct bnxt_tpa_info *tpa_info;
1078 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1079 struct rx_bd *prod_bd;
1080 dma_addr_t mapping;
1081
1082 cons = tpa_start->rx_tpa_start_cmp_opaque;
1083 prod = rxr->rx_prod;
1084 cons_rx_buf = &rxr->rx_buf_ring[cons];
1085 prod_rx_buf = &rxr->rx_buf_ring[prod];
1086 tpa_info = &rxr->rx_tpa[agg_id];
1087
1088 if (unlikely(cons != rxr->rx_next_cons)) {
1089 bnxt_sched_reset(bp, rxr);
1090 return;
1091 }
1092 /* Store cfa_code in tpa_info to use in tpa_end
1093 * completion processing.
1094 */
1095 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1096 prod_rx_buf->data = tpa_info->data;
1097 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1098
1099 mapping = tpa_info->mapping;
1100 prod_rx_buf->mapping = mapping;
1101
1102 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1103
1104 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1105
1106 tpa_info->data = cons_rx_buf->data;
1107 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1108 cons_rx_buf->data = NULL;
1109 tpa_info->mapping = cons_rx_buf->mapping;
1110
1111 tpa_info->len =
1112 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1113 RX_TPA_START_CMP_LEN_SHIFT;
1114 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1115 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1116
1117 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1118 tpa_info->gso_type = SKB_GSO_TCPV4;
1119 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1120 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1121 tpa_info->gso_type = SKB_GSO_TCPV6;
1122 tpa_info->rss_hash =
1123 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1124 } else {
1125 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1126 tpa_info->gso_type = 0;
1127 if (netif_msg_rx_err(bp))
1128 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1129 }
1130 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1131 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1132 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1133
1134 rxr->rx_prod = NEXT_RX(prod);
1135 cons = NEXT_RX(cons);
1136 rxr->rx_next_cons = NEXT_RX(cons);
1137 cons_rx_buf = &rxr->rx_buf_ring[cons];
1138
1139 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1140 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1141 cons_rx_buf->data = NULL;
1142 }
1143
1144 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1145 u16 cp_cons, u32 agg_bufs)
1146 {
1147 if (agg_bufs)
1148 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1149 }
1150
1151 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1152 int payload_off, int tcp_ts,
1153 struct sk_buff *skb)
1154 {
1155 #ifdef CONFIG_INET
1156 struct tcphdr *th;
1157 int len, nw_off;
1158 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1159 u32 hdr_info = tpa_info->hdr_info;
1160 bool loopback = false;
1161
1162 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1163 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1164 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1165
1166 /* If the packet is an internal loopback packet, the offsets will
1167 * have an extra 4 bytes.
1168 */
1169 if (inner_mac_off == 4) {
1170 loopback = true;
1171 } else if (inner_mac_off > 4) {
1172 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1173 ETH_HLEN - 2));
1174
1175 /* We only support inner iPv4/ipv6. If we don't see the
1176 * correct protocol ID, it must be a loopback packet where
1177 * the offsets are off by 4.
1178 */
1179 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1180 loopback = true;
1181 }
1182 if (loopback) {
1183 /* internal loopback packet, subtract all offsets by 4 */
1184 inner_ip_off -= 4;
1185 inner_mac_off -= 4;
1186 outer_ip_off -= 4;
1187 }
1188
1189 nw_off = inner_ip_off - ETH_HLEN;
1190 skb_set_network_header(skb, nw_off);
1191 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1192 struct ipv6hdr *iph = ipv6_hdr(skb);
1193
1194 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1195 len = skb->len - skb_transport_offset(skb);
1196 th = tcp_hdr(skb);
1197 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1198 } else {
1199 struct iphdr *iph = ip_hdr(skb);
1200
1201 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1202 len = skb->len - skb_transport_offset(skb);
1203 th = tcp_hdr(skb);
1204 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1205 }
1206
1207 if (inner_mac_off) { /* tunnel */
1208 struct udphdr *uh = NULL;
1209 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1210 ETH_HLEN - 2));
1211
1212 if (proto == htons(ETH_P_IP)) {
1213 struct iphdr *iph = (struct iphdr *)skb->data;
1214
1215 if (iph->protocol == IPPROTO_UDP)
1216 uh = (struct udphdr *)(iph + 1);
1217 } else {
1218 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1219
1220 if (iph->nexthdr == IPPROTO_UDP)
1221 uh = (struct udphdr *)(iph + 1);
1222 }
1223 if (uh) {
1224 if (uh->check)
1225 skb_shinfo(skb)->gso_type |=
1226 SKB_GSO_UDP_TUNNEL_CSUM;
1227 else
1228 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1229 }
1230 }
1231 #endif
1232 return skb;
1233 }
1234
1235 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1236 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1237
1238 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1239 int payload_off, int tcp_ts,
1240 struct sk_buff *skb)
1241 {
1242 #ifdef CONFIG_INET
1243 struct tcphdr *th;
1244 int len, nw_off, tcp_opt_len = 0;
1245
1246 if (tcp_ts)
1247 tcp_opt_len = 12;
1248
1249 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1250 struct iphdr *iph;
1251
1252 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1253 ETH_HLEN;
1254 skb_set_network_header(skb, nw_off);
1255 iph = ip_hdr(skb);
1256 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1257 len = skb->len - skb_transport_offset(skb);
1258 th = tcp_hdr(skb);
1259 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1260 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1261 struct ipv6hdr *iph;
1262
1263 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1264 ETH_HLEN;
1265 skb_set_network_header(skb, nw_off);
1266 iph = ipv6_hdr(skb);
1267 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1268 len = skb->len - skb_transport_offset(skb);
1269 th = tcp_hdr(skb);
1270 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1271 } else {
1272 dev_kfree_skb_any(skb);
1273 return NULL;
1274 }
1275
1276 if (nw_off) { /* tunnel */
1277 struct udphdr *uh = NULL;
1278
1279 if (skb->protocol == htons(ETH_P_IP)) {
1280 struct iphdr *iph = (struct iphdr *)skb->data;
1281
1282 if (iph->protocol == IPPROTO_UDP)
1283 uh = (struct udphdr *)(iph + 1);
1284 } else {
1285 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1286
1287 if (iph->nexthdr == IPPROTO_UDP)
1288 uh = (struct udphdr *)(iph + 1);
1289 }
1290 if (uh) {
1291 if (uh->check)
1292 skb_shinfo(skb)->gso_type |=
1293 SKB_GSO_UDP_TUNNEL_CSUM;
1294 else
1295 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1296 }
1297 }
1298 #endif
1299 return skb;
1300 }
1301
1302 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1303 struct bnxt_tpa_info *tpa_info,
1304 struct rx_tpa_end_cmp *tpa_end,
1305 struct rx_tpa_end_cmp_ext *tpa_end1,
1306 struct sk_buff *skb)
1307 {
1308 #ifdef CONFIG_INET
1309 int payload_off;
1310 u16 segs;
1311
1312 segs = TPA_END_TPA_SEGS(tpa_end);
1313 if (segs == 1)
1314 return skb;
1315
1316 NAPI_GRO_CB(skb)->count = segs;
1317 skb_shinfo(skb)->gso_size =
1318 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1319 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1320 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1321 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1322 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1323 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1324 if (likely(skb))
1325 tcp_gro_complete(skb);
1326 #endif
1327 return skb;
1328 }
1329
1330 /* Given the cfa_code of a received packet determine which
1331 * netdev (vf-rep or PF) the packet is destined to.
1332 */
1333 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1334 {
1335 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1336
1337 /* if vf-rep dev is NULL, the must belongs to the PF */
1338 return dev ? dev : bp->dev;
1339 }
1340
1341 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1342 struct bnxt_napi *bnapi,
1343 u32 *raw_cons,
1344 struct rx_tpa_end_cmp *tpa_end,
1345 struct rx_tpa_end_cmp_ext *tpa_end1,
1346 u8 *event)
1347 {
1348 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1349 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1350 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1351 u8 *data_ptr, agg_bufs;
1352 u16 cp_cons = RING_CMP(*raw_cons);
1353 unsigned int len;
1354 struct bnxt_tpa_info *tpa_info;
1355 dma_addr_t mapping;
1356 struct sk_buff *skb;
1357 void *data;
1358
1359 if (unlikely(bnapi->in_reset)) {
1360 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1361
1362 if (rc < 0)
1363 return ERR_PTR(-EBUSY);
1364 return NULL;
1365 }
1366
1367 tpa_info = &rxr->rx_tpa[agg_id];
1368 data = tpa_info->data;
1369 data_ptr = tpa_info->data_ptr;
1370 prefetch(data_ptr);
1371 len = tpa_info->len;
1372 mapping = tpa_info->mapping;
1373
1374 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1375 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1376
1377 if (agg_bufs) {
1378 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1379 return ERR_PTR(-EBUSY);
1380
1381 *event |= BNXT_AGG_EVENT;
1382 cp_cons = NEXT_CMP(cp_cons);
1383 }
1384
1385 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1386 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1387 if (agg_bufs > MAX_SKB_FRAGS)
1388 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1389 agg_bufs, (int)MAX_SKB_FRAGS);
1390 return NULL;
1391 }
1392
1393 if (len <= bp->rx_copy_thresh) {
1394 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1395 if (!skb) {
1396 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1397 return NULL;
1398 }
1399 } else {
1400 u8 *new_data;
1401 dma_addr_t new_mapping;
1402
1403 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1404 if (!new_data) {
1405 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1406 return NULL;
1407 }
1408
1409 tpa_info->data = new_data;
1410 tpa_info->data_ptr = new_data + bp->rx_offset;
1411 tpa_info->mapping = new_mapping;
1412
1413 skb = build_skb(data, 0);
1414 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1415 bp->rx_buf_use_size, bp->rx_dir,
1416 DMA_ATTR_WEAK_ORDERING);
1417
1418 if (!skb) {
1419 kfree(data);
1420 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1421 return NULL;
1422 }
1423 skb_reserve(skb, bp->rx_offset);
1424 skb_put(skb, len);
1425 }
1426
1427 if (agg_bufs) {
1428 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1429 if (!skb) {
1430 /* Page reuse already handled by bnxt_rx_pages(). */
1431 return NULL;
1432 }
1433 }
1434
1435 skb->protocol =
1436 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1437
1438 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1439 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1440
1441 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1442 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1443 u16 vlan_proto = tpa_info->metadata >>
1444 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1445 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1446
1447 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1448 }
1449
1450 skb_checksum_none_assert(skb);
1451 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1452 skb->ip_summed = CHECKSUM_UNNECESSARY;
1453 skb->csum_level =
1454 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1455 }
1456
1457 if (TPA_END_GRO(tpa_end))
1458 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1459
1460 return skb;
1461 }
1462
1463 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1464 struct sk_buff *skb)
1465 {
1466 if (skb->dev != bp->dev) {
1467 /* this packet belongs to a vf-rep */
1468 bnxt_vf_rep_rx(bp, skb);
1469 return;
1470 }
1471 skb_record_rx_queue(skb, bnapi->index);
1472 napi_gro_receive(&bnapi->napi, skb);
1473 }
1474
1475 /* returns the following:
1476 * 1 - 1 packet successfully received
1477 * 0 - successful TPA_START, packet not completed yet
1478 * -EBUSY - completion ring does not have all the agg buffers yet
1479 * -ENOMEM - packet aborted due to out of memory
1480 * -EIO - packet aborted due to hw error indicated in BD
1481 */
1482 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1483 u8 *event)
1484 {
1485 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1486 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1487 struct net_device *dev = bp->dev;
1488 struct rx_cmp *rxcmp;
1489 struct rx_cmp_ext *rxcmp1;
1490 u32 tmp_raw_cons = *raw_cons;
1491 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1492 struct bnxt_sw_rx_bd *rx_buf;
1493 unsigned int len;
1494 u8 *data_ptr, agg_bufs, cmp_type;
1495 dma_addr_t dma_addr;
1496 struct sk_buff *skb;
1497 void *data;
1498 int rc = 0;
1499 u32 misc;
1500
1501 rxcmp = (struct rx_cmp *)
1502 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1503
1504 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1505 cp_cons = RING_CMP(tmp_raw_cons);
1506 rxcmp1 = (struct rx_cmp_ext *)
1507 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1508
1509 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1510 return -EBUSY;
1511
1512 cmp_type = RX_CMP_TYPE(rxcmp);
1513
1514 prod = rxr->rx_prod;
1515
1516 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1517 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1518 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1519
1520 *event |= BNXT_RX_EVENT;
1521 goto next_rx_no_prod_no_len;
1522
1523 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1524 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1525 (struct rx_tpa_end_cmp *)rxcmp,
1526 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1527
1528 if (IS_ERR(skb))
1529 return -EBUSY;
1530
1531 rc = -ENOMEM;
1532 if (likely(skb)) {
1533 bnxt_deliver_skb(bp, bnapi, skb);
1534 rc = 1;
1535 }
1536 *event |= BNXT_RX_EVENT;
1537 goto next_rx_no_prod_no_len;
1538 }
1539
1540 cons = rxcmp->rx_cmp_opaque;
1541 rx_buf = &rxr->rx_buf_ring[cons];
1542 data = rx_buf->data;
1543 data_ptr = rx_buf->data_ptr;
1544 if (unlikely(cons != rxr->rx_next_cons)) {
1545 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1546
1547 bnxt_sched_reset(bp, rxr);
1548 return rc1;
1549 }
1550 prefetch(data_ptr);
1551
1552 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1553 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1554
1555 if (agg_bufs) {
1556 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1557 return -EBUSY;
1558
1559 cp_cons = NEXT_CMP(cp_cons);
1560 *event |= BNXT_AGG_EVENT;
1561 }
1562 *event |= BNXT_RX_EVENT;
1563
1564 rx_buf->data = NULL;
1565 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1566 bnxt_reuse_rx_data(rxr, cons, data);
1567 if (agg_bufs)
1568 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1569
1570 rc = -EIO;
1571 goto next_rx;
1572 }
1573
1574 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1575 dma_addr = rx_buf->mapping;
1576
1577 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1578 rc = 1;
1579 goto next_rx;
1580 }
1581
1582 if (len <= bp->rx_copy_thresh) {
1583 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1584 bnxt_reuse_rx_data(rxr, cons, data);
1585 if (!skb) {
1586 rc = -ENOMEM;
1587 goto next_rx;
1588 }
1589 } else {
1590 u32 payload;
1591
1592 if (rx_buf->data_ptr == data_ptr)
1593 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1594 else
1595 payload = 0;
1596 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1597 payload | len);
1598 if (!skb) {
1599 rc = -ENOMEM;
1600 goto next_rx;
1601 }
1602 }
1603
1604 if (agg_bufs) {
1605 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1606 if (!skb) {
1607 rc = -ENOMEM;
1608 goto next_rx;
1609 }
1610 }
1611
1612 if (RX_CMP_HASH_VALID(rxcmp)) {
1613 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1614 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1615
1616 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1617 if (hash_type != 1 && hash_type != 3)
1618 type = PKT_HASH_TYPE_L3;
1619 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1620 }
1621
1622 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1623 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1624
1625 if ((rxcmp1->rx_cmp_flags2 &
1626 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1627 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1628 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1629 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1630 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1631
1632 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1633 }
1634
1635 skb_checksum_none_assert(skb);
1636 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1637 if (dev->features & NETIF_F_RXCSUM) {
1638 skb->ip_summed = CHECKSUM_UNNECESSARY;
1639 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1640 }
1641 } else {
1642 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1643 if (dev->features & NETIF_F_RXCSUM)
1644 cpr->rx_l4_csum_errors++;
1645 }
1646 }
1647
1648 bnxt_deliver_skb(bp, bnapi, skb);
1649 rc = 1;
1650
1651 next_rx:
1652 rxr->rx_prod = NEXT_RX(prod);
1653 rxr->rx_next_cons = NEXT_RX(cons);
1654
1655 cpr->rx_packets += 1;
1656 cpr->rx_bytes += len;
1657
1658 next_rx_no_prod_no_len:
1659 *raw_cons = tmp_raw_cons;
1660
1661 return rc;
1662 }
1663
1664 /* In netpoll mode, if we are using a combined completion ring, we need to
1665 * discard the rx packets and recycle the buffers.
1666 */
1667 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi,
1668 u32 *raw_cons, u8 *event)
1669 {
1670 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1671 u32 tmp_raw_cons = *raw_cons;
1672 struct rx_cmp_ext *rxcmp1;
1673 struct rx_cmp *rxcmp;
1674 u16 cp_cons;
1675 u8 cmp_type;
1676
1677 cp_cons = RING_CMP(tmp_raw_cons);
1678 rxcmp = (struct rx_cmp *)
1679 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1680
1681 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1682 cp_cons = RING_CMP(tmp_raw_cons);
1683 rxcmp1 = (struct rx_cmp_ext *)
1684 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1685
1686 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1687 return -EBUSY;
1688
1689 cmp_type = RX_CMP_TYPE(rxcmp);
1690 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1691 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1692 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1693 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1694 struct rx_tpa_end_cmp_ext *tpa_end1;
1695
1696 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1697 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1698 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1699 }
1700 return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
1701 }
1702
1703 #define BNXT_GET_EVENT_PORT(data) \
1704 ((data) & \
1705 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1706
1707 static int bnxt_async_event_process(struct bnxt *bp,
1708 struct hwrm_async_event_cmpl *cmpl)
1709 {
1710 u16 event_id = le16_to_cpu(cmpl->event_id);
1711
1712 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1713 switch (event_id) {
1714 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1715 u32 data1 = le32_to_cpu(cmpl->event_data1);
1716 struct bnxt_link_info *link_info = &bp->link_info;
1717
1718 if (BNXT_VF(bp))
1719 goto async_event_process_exit;
1720
1721 /* print unsupported speed warning in forced speed mode only */
1722 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1723 (data1 & 0x20000)) {
1724 u16 fw_speed = link_info->force_link_speed;
1725 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1726
1727 if (speed != SPEED_UNKNOWN)
1728 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1729 speed);
1730 }
1731 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1732 }
1733 /* fall through */
1734 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1735 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1736 break;
1737 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1738 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1739 break;
1740 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1741 u32 data1 = le32_to_cpu(cmpl->event_data1);
1742 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1743
1744 if (BNXT_VF(bp))
1745 break;
1746
1747 if (bp->pf.port_id != port_id)
1748 break;
1749
1750 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1751 break;
1752 }
1753 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1754 if (BNXT_PF(bp))
1755 goto async_event_process_exit;
1756 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1757 break;
1758 default:
1759 goto async_event_process_exit;
1760 }
1761 bnxt_queue_sp_work(bp);
1762 async_event_process_exit:
1763 bnxt_ulp_async_events(bp, cmpl);
1764 return 0;
1765 }
1766
1767 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1768 {
1769 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1770 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1771 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1772 (struct hwrm_fwd_req_cmpl *)txcmp;
1773
1774 switch (cmpl_type) {
1775 case CMPL_BASE_TYPE_HWRM_DONE:
1776 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1777 if (seq_id == bp->hwrm_intr_seq_id)
1778 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1779 else
1780 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1781 break;
1782
1783 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1784 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1785
1786 if ((vf_id < bp->pf.first_vf_id) ||
1787 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1788 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1789 vf_id);
1790 return -EINVAL;
1791 }
1792
1793 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1794 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1795 bnxt_queue_sp_work(bp);
1796 break;
1797
1798 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1799 bnxt_async_event_process(bp,
1800 (struct hwrm_async_event_cmpl *)txcmp);
1801
1802 default:
1803 break;
1804 }
1805
1806 return 0;
1807 }
1808
1809 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1810 {
1811 struct bnxt_napi *bnapi = dev_instance;
1812 struct bnxt *bp = bnapi->bp;
1813 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1814 u32 cons = RING_CMP(cpr->cp_raw_cons);
1815
1816 cpr->event_ctr++;
1817 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1818 napi_schedule(&bnapi->napi);
1819 return IRQ_HANDLED;
1820 }
1821
1822 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1823 {
1824 u32 raw_cons = cpr->cp_raw_cons;
1825 u16 cons = RING_CMP(raw_cons);
1826 struct tx_cmp *txcmp;
1827
1828 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1829
1830 return TX_CMP_VALID(txcmp, raw_cons);
1831 }
1832
1833 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1834 {
1835 struct bnxt_napi *bnapi = dev_instance;
1836 struct bnxt *bp = bnapi->bp;
1837 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1838 u32 cons = RING_CMP(cpr->cp_raw_cons);
1839 u32 int_status;
1840
1841 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1842
1843 if (!bnxt_has_work(bp, cpr)) {
1844 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1845 /* return if erroneous interrupt */
1846 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1847 return IRQ_NONE;
1848 }
1849
1850 /* disable ring IRQ */
1851 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1852
1853 /* Return here if interrupt is shared and is disabled. */
1854 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1855 return IRQ_HANDLED;
1856
1857 napi_schedule(&bnapi->napi);
1858 return IRQ_HANDLED;
1859 }
1860
1861 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1862 {
1863 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1864 u32 raw_cons = cpr->cp_raw_cons;
1865 u32 cons;
1866 int tx_pkts = 0;
1867 int rx_pkts = 0;
1868 u8 event = 0;
1869 struct tx_cmp *txcmp;
1870
1871 while (1) {
1872 int rc;
1873
1874 cons = RING_CMP(raw_cons);
1875 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1876
1877 if (!TX_CMP_VALID(txcmp, raw_cons))
1878 break;
1879
1880 /* The valid test of the entry must be done first before
1881 * reading any further.
1882 */
1883 dma_rmb();
1884 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1885 tx_pkts++;
1886 /* return full budget so NAPI will complete. */
1887 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1888 rx_pkts = budget;
1889 raw_cons = NEXT_RAW_CMP(raw_cons);
1890 break;
1891 }
1892 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1893 if (likely(budget))
1894 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1895 else
1896 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
1897 &event);
1898 if (likely(rc >= 0))
1899 rx_pkts += rc;
1900 /* Increment rx_pkts when rc is -ENOMEM to count towards
1901 * the NAPI budget. Otherwise, we may potentially loop
1902 * here forever if we consistently cannot allocate
1903 * buffers.
1904 */
1905 else if (rc == -ENOMEM && budget)
1906 rx_pkts++;
1907 else if (rc == -EBUSY) /* partial completion */
1908 break;
1909 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1910 CMPL_BASE_TYPE_HWRM_DONE) ||
1911 (TX_CMP_TYPE(txcmp) ==
1912 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1913 (TX_CMP_TYPE(txcmp) ==
1914 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1915 bnxt_hwrm_handler(bp, txcmp);
1916 }
1917 raw_cons = NEXT_RAW_CMP(raw_cons);
1918
1919 if (rx_pkts && rx_pkts == budget)
1920 break;
1921 }
1922
1923 if (event & BNXT_TX_EVENT) {
1924 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1925 void __iomem *db = txr->tx_doorbell;
1926 u16 prod = txr->tx_prod;
1927
1928 /* Sync BD data before updating doorbell */
1929 wmb();
1930
1931 bnxt_db_write_relaxed(bp, db, DB_KEY_TX | prod);
1932 }
1933
1934 cpr->cp_raw_cons = raw_cons;
1935 /* ACK completion ring before freeing tx ring and producing new
1936 * buffers in rx/agg rings to prevent overflowing the completion
1937 * ring.
1938 */
1939 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1940
1941 if (tx_pkts)
1942 bnapi->tx_int(bp, bnapi, tx_pkts);
1943
1944 if (event & BNXT_RX_EVENT) {
1945 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1946
1947 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1948 if (event & BNXT_AGG_EVENT)
1949 bnxt_db_write(bp, rxr->rx_agg_doorbell,
1950 DB_KEY_RX | rxr->rx_agg_prod);
1951 }
1952 return rx_pkts;
1953 }
1954
1955 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1956 {
1957 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1958 struct bnxt *bp = bnapi->bp;
1959 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1960 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1961 struct tx_cmp *txcmp;
1962 struct rx_cmp_ext *rxcmp1;
1963 u32 cp_cons, tmp_raw_cons;
1964 u32 raw_cons = cpr->cp_raw_cons;
1965 u32 rx_pkts = 0;
1966 u8 event = 0;
1967
1968 while (1) {
1969 int rc;
1970
1971 cp_cons = RING_CMP(raw_cons);
1972 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1973
1974 if (!TX_CMP_VALID(txcmp, raw_cons))
1975 break;
1976
1977 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1978 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1979 cp_cons = RING_CMP(tmp_raw_cons);
1980 rxcmp1 = (struct rx_cmp_ext *)
1981 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1982
1983 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1984 break;
1985
1986 /* force an error to recycle the buffer */
1987 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1988 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1989
1990 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1991 if (likely(rc == -EIO) && budget)
1992 rx_pkts++;
1993 else if (rc == -EBUSY) /* partial completion */
1994 break;
1995 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1996 CMPL_BASE_TYPE_HWRM_DONE)) {
1997 bnxt_hwrm_handler(bp, txcmp);
1998 } else {
1999 netdev_err(bp->dev,
2000 "Invalid completion received on special ring\n");
2001 }
2002 raw_cons = NEXT_RAW_CMP(raw_cons);
2003
2004 if (rx_pkts == budget)
2005 break;
2006 }
2007
2008 cpr->cp_raw_cons = raw_cons;
2009 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
2010 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
2011
2012 if (event & BNXT_AGG_EVENT)
2013 bnxt_db_write(bp, rxr->rx_agg_doorbell,
2014 DB_KEY_RX | rxr->rx_agg_prod);
2015
2016 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2017 napi_complete_done(napi, rx_pkts);
2018 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
2019 }
2020 return rx_pkts;
2021 }
2022
2023 static int bnxt_poll(struct napi_struct *napi, int budget)
2024 {
2025 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2026 struct bnxt *bp = bnapi->bp;
2027 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2028 int work_done = 0;
2029
2030 while (1) {
2031 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
2032
2033 if (work_done >= budget) {
2034 if (!budget)
2035 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2036 cpr->cp_raw_cons);
2037 break;
2038 }
2039
2040 if (!bnxt_has_work(bp, cpr)) {
2041 if (napi_complete_done(napi, work_done))
2042 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2043 cpr->cp_raw_cons);
2044 break;
2045 }
2046 }
2047 if (bp->flags & BNXT_FLAG_DIM) {
2048 struct net_dim_sample dim_sample;
2049
2050 net_dim_sample(cpr->event_ctr,
2051 cpr->rx_packets,
2052 cpr->rx_bytes,
2053 &dim_sample);
2054 net_dim(&cpr->dim, dim_sample);
2055 }
2056 mmiowb();
2057 return work_done;
2058 }
2059
2060 static void bnxt_free_tx_skbs(struct bnxt *bp)
2061 {
2062 int i, max_idx;
2063 struct pci_dev *pdev = bp->pdev;
2064
2065 if (!bp->tx_ring)
2066 return;
2067
2068 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2069 for (i = 0; i < bp->tx_nr_rings; i++) {
2070 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2071 int j;
2072
2073 for (j = 0; j < max_idx;) {
2074 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2075 struct sk_buff *skb = tx_buf->skb;
2076 int k, last;
2077
2078 if (!skb) {
2079 j++;
2080 continue;
2081 }
2082
2083 tx_buf->skb = NULL;
2084
2085 if (tx_buf->is_push) {
2086 dev_kfree_skb(skb);
2087 j += 2;
2088 continue;
2089 }
2090
2091 dma_unmap_single(&pdev->dev,
2092 dma_unmap_addr(tx_buf, mapping),
2093 skb_headlen(skb),
2094 PCI_DMA_TODEVICE);
2095
2096 last = tx_buf->nr_frags;
2097 j += 2;
2098 for (k = 0; k < last; k++, j++) {
2099 int ring_idx = j & bp->tx_ring_mask;
2100 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2101
2102 tx_buf = &txr->tx_buf_ring[ring_idx];
2103 dma_unmap_page(
2104 &pdev->dev,
2105 dma_unmap_addr(tx_buf, mapping),
2106 skb_frag_size(frag), PCI_DMA_TODEVICE);
2107 }
2108 dev_kfree_skb(skb);
2109 }
2110 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2111 }
2112 }
2113
2114 static void bnxt_free_rx_skbs(struct bnxt *bp)
2115 {
2116 int i, max_idx, max_agg_idx;
2117 struct pci_dev *pdev = bp->pdev;
2118
2119 if (!bp->rx_ring)
2120 return;
2121
2122 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2123 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2124 for (i = 0; i < bp->rx_nr_rings; i++) {
2125 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2126 int j;
2127
2128 if (rxr->rx_tpa) {
2129 for (j = 0; j < MAX_TPA; j++) {
2130 struct bnxt_tpa_info *tpa_info =
2131 &rxr->rx_tpa[j];
2132 u8 *data = tpa_info->data;
2133
2134 if (!data)
2135 continue;
2136
2137 dma_unmap_single_attrs(&pdev->dev,
2138 tpa_info->mapping,
2139 bp->rx_buf_use_size,
2140 bp->rx_dir,
2141 DMA_ATTR_WEAK_ORDERING);
2142
2143 tpa_info->data = NULL;
2144
2145 kfree(data);
2146 }
2147 }
2148
2149 for (j = 0; j < max_idx; j++) {
2150 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2151 dma_addr_t mapping = rx_buf->mapping;
2152 void *data = rx_buf->data;
2153
2154 if (!data)
2155 continue;
2156
2157 rx_buf->data = NULL;
2158
2159 if (BNXT_RX_PAGE_MODE(bp)) {
2160 mapping -= bp->rx_dma_offset;
2161 dma_unmap_page_attrs(&pdev->dev, mapping,
2162 PAGE_SIZE, bp->rx_dir,
2163 DMA_ATTR_WEAK_ORDERING);
2164 __free_page(data);
2165 } else {
2166 dma_unmap_single_attrs(&pdev->dev, mapping,
2167 bp->rx_buf_use_size,
2168 bp->rx_dir,
2169 DMA_ATTR_WEAK_ORDERING);
2170 kfree(data);
2171 }
2172 }
2173
2174 for (j = 0; j < max_agg_idx; j++) {
2175 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2176 &rxr->rx_agg_ring[j];
2177 struct page *page = rx_agg_buf->page;
2178
2179 if (!page)
2180 continue;
2181
2182 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2183 BNXT_RX_PAGE_SIZE,
2184 PCI_DMA_FROMDEVICE,
2185 DMA_ATTR_WEAK_ORDERING);
2186
2187 rx_agg_buf->page = NULL;
2188 __clear_bit(j, rxr->rx_agg_bmap);
2189
2190 __free_page(page);
2191 }
2192 if (rxr->rx_page) {
2193 __free_page(rxr->rx_page);
2194 rxr->rx_page = NULL;
2195 }
2196 }
2197 }
2198
2199 static void bnxt_free_skbs(struct bnxt *bp)
2200 {
2201 bnxt_free_tx_skbs(bp);
2202 bnxt_free_rx_skbs(bp);
2203 }
2204
2205 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2206 {
2207 struct pci_dev *pdev = bp->pdev;
2208 int i;
2209
2210 for (i = 0; i < rmem->nr_pages; i++) {
2211 if (!rmem->pg_arr[i])
2212 continue;
2213
2214 dma_free_coherent(&pdev->dev, rmem->page_size,
2215 rmem->pg_arr[i], rmem->dma_arr[i]);
2216
2217 rmem->pg_arr[i] = NULL;
2218 }
2219 if (rmem->pg_tbl) {
2220 dma_free_coherent(&pdev->dev, rmem->nr_pages * 8,
2221 rmem->pg_tbl, rmem->pg_tbl_map);
2222 rmem->pg_tbl = NULL;
2223 }
2224 if (rmem->vmem_size && *rmem->vmem) {
2225 vfree(*rmem->vmem);
2226 *rmem->vmem = NULL;
2227 }
2228 }
2229
2230 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2231 {
2232 struct pci_dev *pdev = bp->pdev;
2233 u64 valid_bit = 0;
2234 int i;
2235
2236 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2237 valid_bit = PTU_PTE_VALID;
2238 if (rmem->nr_pages > 1) {
2239 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev,
2240 rmem->nr_pages * 8,
2241 &rmem->pg_tbl_map,
2242 GFP_KERNEL);
2243 if (!rmem->pg_tbl)
2244 return -ENOMEM;
2245 }
2246
2247 for (i = 0; i < rmem->nr_pages; i++) {
2248 u64 extra_bits = valid_bit;
2249
2250 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2251 rmem->page_size,
2252 &rmem->dma_arr[i],
2253 GFP_KERNEL);
2254 if (!rmem->pg_arr[i])
2255 return -ENOMEM;
2256
2257 if (rmem->nr_pages > 1) {
2258 if (i == rmem->nr_pages - 2 &&
2259 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2260 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2261 else if (i == rmem->nr_pages - 1 &&
2262 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2263 extra_bits |= PTU_PTE_LAST;
2264 rmem->pg_tbl[i] =
2265 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2266 }
2267 }
2268
2269 if (rmem->vmem_size) {
2270 *rmem->vmem = vzalloc(rmem->vmem_size);
2271 if (!(*rmem->vmem))
2272 return -ENOMEM;
2273 }
2274 return 0;
2275 }
2276
2277 static void bnxt_free_rx_rings(struct bnxt *bp)
2278 {
2279 int i;
2280
2281 if (!bp->rx_ring)
2282 return;
2283
2284 for (i = 0; i < bp->rx_nr_rings; i++) {
2285 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2286 struct bnxt_ring_struct *ring;
2287
2288 if (rxr->xdp_prog)
2289 bpf_prog_put(rxr->xdp_prog);
2290
2291 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2292 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2293
2294 kfree(rxr->rx_tpa);
2295 rxr->rx_tpa = NULL;
2296
2297 kfree(rxr->rx_agg_bmap);
2298 rxr->rx_agg_bmap = NULL;
2299
2300 ring = &rxr->rx_ring_struct;
2301 bnxt_free_ring(bp, &ring->ring_mem);
2302
2303 ring = &rxr->rx_agg_ring_struct;
2304 bnxt_free_ring(bp, &ring->ring_mem);
2305 }
2306 }
2307
2308 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2309 {
2310 int i, rc, agg_rings = 0, tpa_rings = 0;
2311
2312 if (!bp->rx_ring)
2313 return -ENOMEM;
2314
2315 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2316 agg_rings = 1;
2317
2318 if (bp->flags & BNXT_FLAG_TPA)
2319 tpa_rings = 1;
2320
2321 for (i = 0; i < bp->rx_nr_rings; i++) {
2322 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2323 struct bnxt_ring_struct *ring;
2324
2325 ring = &rxr->rx_ring_struct;
2326
2327 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2328 if (rc < 0)
2329 return rc;
2330
2331 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2332 if (rc)
2333 return rc;
2334
2335 if (agg_rings) {
2336 u16 mem_size;
2337
2338 ring = &rxr->rx_agg_ring_struct;
2339 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2340 if (rc)
2341 return rc;
2342
2343 ring->grp_idx = i;
2344 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2345 mem_size = rxr->rx_agg_bmap_size / 8;
2346 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2347 if (!rxr->rx_agg_bmap)
2348 return -ENOMEM;
2349
2350 if (tpa_rings) {
2351 rxr->rx_tpa = kcalloc(MAX_TPA,
2352 sizeof(struct bnxt_tpa_info),
2353 GFP_KERNEL);
2354 if (!rxr->rx_tpa)
2355 return -ENOMEM;
2356 }
2357 }
2358 }
2359 return 0;
2360 }
2361
2362 static void bnxt_free_tx_rings(struct bnxt *bp)
2363 {
2364 int i;
2365 struct pci_dev *pdev = bp->pdev;
2366
2367 if (!bp->tx_ring)
2368 return;
2369
2370 for (i = 0; i < bp->tx_nr_rings; i++) {
2371 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2372 struct bnxt_ring_struct *ring;
2373
2374 if (txr->tx_push) {
2375 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2376 txr->tx_push, txr->tx_push_mapping);
2377 txr->tx_push = NULL;
2378 }
2379
2380 ring = &txr->tx_ring_struct;
2381
2382 bnxt_free_ring(bp, &ring->ring_mem);
2383 }
2384 }
2385
2386 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2387 {
2388 int i, j, rc;
2389 struct pci_dev *pdev = bp->pdev;
2390
2391 bp->tx_push_size = 0;
2392 if (bp->tx_push_thresh) {
2393 int push_size;
2394
2395 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2396 bp->tx_push_thresh);
2397
2398 if (push_size > 256) {
2399 push_size = 0;
2400 bp->tx_push_thresh = 0;
2401 }
2402
2403 bp->tx_push_size = push_size;
2404 }
2405
2406 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2407 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2408 struct bnxt_ring_struct *ring;
2409 u8 qidx;
2410
2411 ring = &txr->tx_ring_struct;
2412
2413 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2414 if (rc)
2415 return rc;
2416
2417 ring->grp_idx = txr->bnapi->index;
2418 if (bp->tx_push_size) {
2419 dma_addr_t mapping;
2420
2421 /* One pre-allocated DMA buffer to backup
2422 * TX push operation
2423 */
2424 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2425 bp->tx_push_size,
2426 &txr->tx_push_mapping,
2427 GFP_KERNEL);
2428
2429 if (!txr->tx_push)
2430 return -ENOMEM;
2431
2432 mapping = txr->tx_push_mapping +
2433 sizeof(struct tx_push_bd);
2434 txr->data_mapping = cpu_to_le64(mapping);
2435
2436 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2437 }
2438 qidx = bp->tc_to_qidx[j];
2439 ring->queue_id = bp->q_info[qidx].queue_id;
2440 if (i < bp->tx_nr_rings_xdp)
2441 continue;
2442 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2443 j++;
2444 }
2445 return 0;
2446 }
2447
2448 static void bnxt_free_cp_rings(struct bnxt *bp)
2449 {
2450 int i;
2451
2452 if (!bp->bnapi)
2453 return;
2454
2455 for (i = 0; i < bp->cp_nr_rings; i++) {
2456 struct bnxt_napi *bnapi = bp->bnapi[i];
2457 struct bnxt_cp_ring_info *cpr;
2458 struct bnxt_ring_struct *ring;
2459
2460 if (!bnapi)
2461 continue;
2462
2463 cpr = &bnapi->cp_ring;
2464 ring = &cpr->cp_ring_struct;
2465
2466 bnxt_free_ring(bp, &ring->ring_mem);
2467 }
2468 }
2469
2470 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2471 {
2472 int i, rc, ulp_base_vec, ulp_msix;
2473
2474 ulp_msix = bnxt_get_ulp_msix_num(bp);
2475 ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2476 for (i = 0; i < bp->cp_nr_rings; i++) {
2477 struct bnxt_napi *bnapi = bp->bnapi[i];
2478 struct bnxt_cp_ring_info *cpr;
2479 struct bnxt_ring_struct *ring;
2480
2481 if (!bnapi)
2482 continue;
2483
2484 cpr = &bnapi->cp_ring;
2485 ring = &cpr->cp_ring_struct;
2486
2487 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2488 if (rc)
2489 return rc;
2490
2491 if (ulp_msix && i >= ulp_base_vec)
2492 ring->map_idx = i + ulp_msix;
2493 else
2494 ring->map_idx = i;
2495 }
2496 return 0;
2497 }
2498
2499 static void bnxt_init_ring_struct(struct bnxt *bp)
2500 {
2501 int i;
2502
2503 for (i = 0; i < bp->cp_nr_rings; i++) {
2504 struct bnxt_napi *bnapi = bp->bnapi[i];
2505 struct bnxt_ring_mem_info *rmem;
2506 struct bnxt_cp_ring_info *cpr;
2507 struct bnxt_rx_ring_info *rxr;
2508 struct bnxt_tx_ring_info *txr;
2509 struct bnxt_ring_struct *ring;
2510
2511 if (!bnapi)
2512 continue;
2513
2514 cpr = &bnapi->cp_ring;
2515 ring = &cpr->cp_ring_struct;
2516 rmem = &ring->ring_mem;
2517 rmem->nr_pages = bp->cp_nr_pages;
2518 rmem->page_size = HW_CMPD_RING_SIZE;
2519 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2520 rmem->dma_arr = cpr->cp_desc_mapping;
2521 rmem->vmem_size = 0;
2522
2523 rxr = bnapi->rx_ring;
2524 if (!rxr)
2525 goto skip_rx;
2526
2527 ring = &rxr->rx_ring_struct;
2528 rmem = &ring->ring_mem;
2529 rmem->nr_pages = bp->rx_nr_pages;
2530 rmem->page_size = HW_RXBD_RING_SIZE;
2531 rmem->pg_arr = (void **)rxr->rx_desc_ring;
2532 rmem->dma_arr = rxr->rx_desc_mapping;
2533 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2534 rmem->vmem = (void **)&rxr->rx_buf_ring;
2535
2536 ring = &rxr->rx_agg_ring_struct;
2537 rmem = &ring->ring_mem;
2538 rmem->nr_pages = bp->rx_agg_nr_pages;
2539 rmem->page_size = HW_RXBD_RING_SIZE;
2540 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
2541 rmem->dma_arr = rxr->rx_agg_desc_mapping;
2542 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2543 rmem->vmem = (void **)&rxr->rx_agg_ring;
2544
2545 skip_rx:
2546 txr = bnapi->tx_ring;
2547 if (!txr)
2548 continue;
2549
2550 ring = &txr->tx_ring_struct;
2551 rmem = &ring->ring_mem;
2552 rmem->nr_pages = bp->tx_nr_pages;
2553 rmem->page_size = HW_RXBD_RING_SIZE;
2554 rmem->pg_arr = (void **)txr->tx_desc_ring;
2555 rmem->dma_arr = txr->tx_desc_mapping;
2556 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2557 rmem->vmem = (void **)&txr->tx_buf_ring;
2558 }
2559 }
2560
2561 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2562 {
2563 int i;
2564 u32 prod;
2565 struct rx_bd **rx_buf_ring;
2566
2567 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
2568 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
2569 int j;
2570 struct rx_bd *rxbd;
2571
2572 rxbd = rx_buf_ring[i];
2573 if (!rxbd)
2574 continue;
2575
2576 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2577 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2578 rxbd->rx_bd_opaque = prod;
2579 }
2580 }
2581 }
2582
2583 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2584 {
2585 struct net_device *dev = bp->dev;
2586 struct bnxt_rx_ring_info *rxr;
2587 struct bnxt_ring_struct *ring;
2588 u32 prod, type;
2589 int i;
2590
2591 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2592 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2593
2594 if (NET_IP_ALIGN == 2)
2595 type |= RX_BD_FLAGS_SOP;
2596
2597 rxr = &bp->rx_ring[ring_nr];
2598 ring = &rxr->rx_ring_struct;
2599 bnxt_init_rxbd_pages(ring, type);
2600
2601 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2602 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2603 if (IS_ERR(rxr->xdp_prog)) {
2604 int rc = PTR_ERR(rxr->xdp_prog);
2605
2606 rxr->xdp_prog = NULL;
2607 return rc;
2608 }
2609 }
2610 prod = rxr->rx_prod;
2611 for (i = 0; i < bp->rx_ring_size; i++) {
2612 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2613 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2614 ring_nr, i, bp->rx_ring_size);
2615 break;
2616 }
2617 prod = NEXT_RX(prod);
2618 }
2619 rxr->rx_prod = prod;
2620 ring->fw_ring_id = INVALID_HW_RING_ID;
2621
2622 ring = &rxr->rx_agg_ring_struct;
2623 ring->fw_ring_id = INVALID_HW_RING_ID;
2624
2625 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2626 return 0;
2627
2628 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2629 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2630
2631 bnxt_init_rxbd_pages(ring, type);
2632
2633 prod = rxr->rx_agg_prod;
2634 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2635 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2636 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2637 ring_nr, i, bp->rx_ring_size);
2638 break;
2639 }
2640 prod = NEXT_RX_AGG(prod);
2641 }
2642 rxr->rx_agg_prod = prod;
2643
2644 if (bp->flags & BNXT_FLAG_TPA) {
2645 if (rxr->rx_tpa) {
2646 u8 *data;
2647 dma_addr_t mapping;
2648
2649 for (i = 0; i < MAX_TPA; i++) {
2650 data = __bnxt_alloc_rx_data(bp, &mapping,
2651 GFP_KERNEL);
2652 if (!data)
2653 return -ENOMEM;
2654
2655 rxr->rx_tpa[i].data = data;
2656 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2657 rxr->rx_tpa[i].mapping = mapping;
2658 }
2659 } else {
2660 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2661 return -ENOMEM;
2662 }
2663 }
2664
2665 return 0;
2666 }
2667
2668 static void bnxt_init_cp_rings(struct bnxt *bp)
2669 {
2670 int i;
2671
2672 for (i = 0; i < bp->cp_nr_rings; i++) {
2673 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2674 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2675
2676 ring->fw_ring_id = INVALID_HW_RING_ID;
2677 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2678 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2679 }
2680 }
2681
2682 static int bnxt_init_rx_rings(struct bnxt *bp)
2683 {
2684 int i, rc = 0;
2685
2686 if (BNXT_RX_PAGE_MODE(bp)) {
2687 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2688 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2689 } else {
2690 bp->rx_offset = BNXT_RX_OFFSET;
2691 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2692 }
2693
2694 for (i = 0; i < bp->rx_nr_rings; i++) {
2695 rc = bnxt_init_one_rx_ring(bp, i);
2696 if (rc)
2697 break;
2698 }
2699
2700 return rc;
2701 }
2702
2703 static int bnxt_init_tx_rings(struct bnxt *bp)
2704 {
2705 u16 i;
2706
2707 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2708 MAX_SKB_FRAGS + 1);
2709
2710 for (i = 0; i < bp->tx_nr_rings; i++) {
2711 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2712 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2713
2714 ring->fw_ring_id = INVALID_HW_RING_ID;
2715 }
2716
2717 return 0;
2718 }
2719
2720 static void bnxt_free_ring_grps(struct bnxt *bp)
2721 {
2722 kfree(bp->grp_info);
2723 bp->grp_info = NULL;
2724 }
2725
2726 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2727 {
2728 int i;
2729
2730 if (irq_re_init) {
2731 bp->grp_info = kcalloc(bp->cp_nr_rings,
2732 sizeof(struct bnxt_ring_grp_info),
2733 GFP_KERNEL);
2734 if (!bp->grp_info)
2735 return -ENOMEM;
2736 }
2737 for (i = 0; i < bp->cp_nr_rings; i++) {
2738 if (irq_re_init)
2739 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2740 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2741 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2742 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2743 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2744 }
2745 return 0;
2746 }
2747
2748 static void bnxt_free_vnics(struct bnxt *bp)
2749 {
2750 kfree(bp->vnic_info);
2751 bp->vnic_info = NULL;
2752 bp->nr_vnics = 0;
2753 }
2754
2755 static int bnxt_alloc_vnics(struct bnxt *bp)
2756 {
2757 int num_vnics = 1;
2758
2759 #ifdef CONFIG_RFS_ACCEL
2760 if (bp->flags & BNXT_FLAG_RFS)
2761 num_vnics += bp->rx_nr_rings;
2762 #endif
2763
2764 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2765 num_vnics++;
2766
2767 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2768 GFP_KERNEL);
2769 if (!bp->vnic_info)
2770 return -ENOMEM;
2771
2772 bp->nr_vnics = num_vnics;
2773 return 0;
2774 }
2775
2776 static void bnxt_init_vnics(struct bnxt *bp)
2777 {
2778 int i;
2779
2780 for (i = 0; i < bp->nr_vnics; i++) {
2781 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2782
2783 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2784 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2785 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2786 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2787
2788 if (bp->vnic_info[i].rss_hash_key) {
2789 if (i == 0)
2790 prandom_bytes(vnic->rss_hash_key,
2791 HW_HASH_KEY_SIZE);
2792 else
2793 memcpy(vnic->rss_hash_key,
2794 bp->vnic_info[0].rss_hash_key,
2795 HW_HASH_KEY_SIZE);
2796 }
2797 }
2798 }
2799
2800 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2801 {
2802 int pages;
2803
2804 pages = ring_size / desc_per_pg;
2805
2806 if (!pages)
2807 return 1;
2808
2809 pages++;
2810
2811 while (pages & (pages - 1))
2812 pages++;
2813
2814 return pages;
2815 }
2816
2817 void bnxt_set_tpa_flags(struct bnxt *bp)
2818 {
2819 bp->flags &= ~BNXT_FLAG_TPA;
2820 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2821 return;
2822 if (bp->dev->features & NETIF_F_LRO)
2823 bp->flags |= BNXT_FLAG_LRO;
2824 else if (bp->dev->features & NETIF_F_GRO_HW)
2825 bp->flags |= BNXT_FLAG_GRO;
2826 }
2827
2828 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2829 * be set on entry.
2830 */
2831 void bnxt_set_ring_params(struct bnxt *bp)
2832 {
2833 u32 ring_size, rx_size, rx_space;
2834 u32 agg_factor = 0, agg_ring_size = 0;
2835
2836 /* 8 for CRC and VLAN */
2837 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2838
2839 rx_space = rx_size + NET_SKB_PAD +
2840 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2841
2842 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2843 ring_size = bp->rx_ring_size;
2844 bp->rx_agg_ring_size = 0;
2845 bp->rx_agg_nr_pages = 0;
2846
2847 if (bp->flags & BNXT_FLAG_TPA)
2848 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2849
2850 bp->flags &= ~BNXT_FLAG_JUMBO;
2851 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2852 u32 jumbo_factor;
2853
2854 bp->flags |= BNXT_FLAG_JUMBO;
2855 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2856 if (jumbo_factor > agg_factor)
2857 agg_factor = jumbo_factor;
2858 }
2859 agg_ring_size = ring_size * agg_factor;
2860
2861 if (agg_ring_size) {
2862 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2863 RX_DESC_CNT);
2864 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2865 u32 tmp = agg_ring_size;
2866
2867 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2868 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2869 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2870 tmp, agg_ring_size);
2871 }
2872 bp->rx_agg_ring_size = agg_ring_size;
2873 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2874 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2875 rx_space = rx_size + NET_SKB_PAD +
2876 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2877 }
2878
2879 bp->rx_buf_use_size = rx_size;
2880 bp->rx_buf_size = rx_space;
2881
2882 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2883 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2884
2885 ring_size = bp->tx_ring_size;
2886 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2887 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2888
2889 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2890 bp->cp_ring_size = ring_size;
2891
2892 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2893 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2894 bp->cp_nr_pages = MAX_CP_PAGES;
2895 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2896 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2897 ring_size, bp->cp_ring_size);
2898 }
2899 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2900 bp->cp_ring_mask = bp->cp_bit - 1;
2901 }
2902
2903 /* Changing allocation mode of RX rings.
2904 * TODO: Update when extending xdp_rxq_info to support allocation modes.
2905 */
2906 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2907 {
2908 if (page_mode) {
2909 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2910 return -EOPNOTSUPP;
2911 bp->dev->max_mtu =
2912 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
2913 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2914 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2915 bp->rx_dir = DMA_BIDIRECTIONAL;
2916 bp->rx_skb_func = bnxt_rx_page_skb;
2917 /* Disable LRO or GRO_HW */
2918 netdev_update_features(bp->dev);
2919 } else {
2920 bp->dev->max_mtu = bp->max_mtu;
2921 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2922 bp->rx_dir = DMA_FROM_DEVICE;
2923 bp->rx_skb_func = bnxt_rx_skb;
2924 }
2925 return 0;
2926 }
2927
2928 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2929 {
2930 int i;
2931 struct bnxt_vnic_info *vnic;
2932 struct pci_dev *pdev = bp->pdev;
2933
2934 if (!bp->vnic_info)
2935 return;
2936
2937 for (i = 0; i < bp->nr_vnics; i++) {
2938 vnic = &bp->vnic_info[i];
2939
2940 kfree(vnic->fw_grp_ids);
2941 vnic->fw_grp_ids = NULL;
2942
2943 kfree(vnic->uc_list);
2944 vnic->uc_list = NULL;
2945
2946 if (vnic->mc_list) {
2947 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2948 vnic->mc_list, vnic->mc_list_mapping);
2949 vnic->mc_list = NULL;
2950 }
2951
2952 if (vnic->rss_table) {
2953 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2954 vnic->rss_table,
2955 vnic->rss_table_dma_addr);
2956 vnic->rss_table = NULL;
2957 }
2958
2959 vnic->rss_hash_key = NULL;
2960 vnic->flags = 0;
2961 }
2962 }
2963
2964 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2965 {
2966 int i, rc = 0, size;
2967 struct bnxt_vnic_info *vnic;
2968 struct pci_dev *pdev = bp->pdev;
2969 int max_rings;
2970
2971 for (i = 0; i < bp->nr_vnics; i++) {
2972 vnic = &bp->vnic_info[i];
2973
2974 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2975 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2976
2977 if (mem_size > 0) {
2978 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2979 if (!vnic->uc_list) {
2980 rc = -ENOMEM;
2981 goto out;
2982 }
2983 }
2984 }
2985
2986 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2987 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2988 vnic->mc_list =
2989 dma_alloc_coherent(&pdev->dev,
2990 vnic->mc_list_size,
2991 &vnic->mc_list_mapping,
2992 GFP_KERNEL);
2993 if (!vnic->mc_list) {
2994 rc = -ENOMEM;
2995 goto out;
2996 }
2997 }
2998
2999 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3000 max_rings = bp->rx_nr_rings;
3001 else
3002 max_rings = 1;
3003
3004 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3005 if (!vnic->fw_grp_ids) {
3006 rc = -ENOMEM;
3007 goto out;
3008 }
3009
3010 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3011 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3012 continue;
3013
3014 /* Allocate rss table and hash key */
3015 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3016 &vnic->rss_table_dma_addr,
3017 GFP_KERNEL);
3018 if (!vnic->rss_table) {
3019 rc = -ENOMEM;
3020 goto out;
3021 }
3022
3023 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3024
3025 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3026 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3027 }
3028 return 0;
3029
3030 out:
3031 return rc;
3032 }
3033
3034 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3035 {
3036 struct pci_dev *pdev = bp->pdev;
3037
3038 if (bp->hwrm_cmd_resp_addr) {
3039 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3040 bp->hwrm_cmd_resp_dma_addr);
3041 bp->hwrm_cmd_resp_addr = NULL;
3042 }
3043 }
3044
3045 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3046 {
3047 struct pci_dev *pdev = bp->pdev;
3048
3049 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3050 &bp->hwrm_cmd_resp_dma_addr,
3051 GFP_KERNEL);
3052 if (!bp->hwrm_cmd_resp_addr)
3053 return -ENOMEM;
3054
3055 return 0;
3056 }
3057
3058 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3059 {
3060 if (bp->hwrm_short_cmd_req_addr) {
3061 struct pci_dev *pdev = bp->pdev;
3062
3063 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3064 bp->hwrm_short_cmd_req_addr,
3065 bp->hwrm_short_cmd_req_dma_addr);
3066 bp->hwrm_short_cmd_req_addr = NULL;
3067 }
3068 }
3069
3070 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3071 {
3072 struct pci_dev *pdev = bp->pdev;
3073
3074 bp->hwrm_short_cmd_req_addr =
3075 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3076 &bp->hwrm_short_cmd_req_dma_addr,
3077 GFP_KERNEL);
3078 if (!bp->hwrm_short_cmd_req_addr)
3079 return -ENOMEM;
3080
3081 return 0;
3082 }
3083
3084 static void bnxt_free_stats(struct bnxt *bp)
3085 {
3086 u32 size, i;
3087 struct pci_dev *pdev = bp->pdev;
3088
3089 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3090 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3091
3092 if (bp->hw_rx_port_stats) {
3093 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3094 bp->hw_rx_port_stats,
3095 bp->hw_rx_port_stats_map);
3096 bp->hw_rx_port_stats = NULL;
3097 }
3098
3099 if (bp->hw_tx_port_stats_ext) {
3100 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext),
3101 bp->hw_tx_port_stats_ext,
3102 bp->hw_tx_port_stats_ext_map);
3103 bp->hw_tx_port_stats_ext = NULL;
3104 }
3105
3106 if (bp->hw_rx_port_stats_ext) {
3107 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3108 bp->hw_rx_port_stats_ext,
3109 bp->hw_rx_port_stats_ext_map);
3110 bp->hw_rx_port_stats_ext = NULL;
3111 }
3112
3113 if (!bp->bnapi)
3114 return;
3115
3116 size = sizeof(struct ctx_hw_stats);
3117
3118 for (i = 0; i < bp->cp_nr_rings; i++) {
3119 struct bnxt_napi *bnapi = bp->bnapi[i];
3120 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3121
3122 if (cpr->hw_stats) {
3123 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3124 cpr->hw_stats_map);
3125 cpr->hw_stats = NULL;
3126 }
3127 }
3128 }
3129
3130 static int bnxt_alloc_stats(struct bnxt *bp)
3131 {
3132 u32 size, i;
3133 struct pci_dev *pdev = bp->pdev;
3134
3135 size = sizeof(struct ctx_hw_stats);
3136
3137 for (i = 0; i < bp->cp_nr_rings; i++) {
3138 struct bnxt_napi *bnapi = bp->bnapi[i];
3139 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3140
3141 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3142 &cpr->hw_stats_map,
3143 GFP_KERNEL);
3144 if (!cpr->hw_stats)
3145 return -ENOMEM;
3146
3147 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3148 }
3149
3150 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3151 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3152 sizeof(struct tx_port_stats) + 1024;
3153
3154 bp->hw_rx_port_stats =
3155 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3156 &bp->hw_rx_port_stats_map,
3157 GFP_KERNEL);
3158 if (!bp->hw_rx_port_stats)
3159 return -ENOMEM;
3160
3161 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3162 512;
3163 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3164 sizeof(struct rx_port_stats) + 512;
3165 bp->flags |= BNXT_FLAG_PORT_STATS;
3166
3167 /* Display extended statistics only if FW supports it */
3168 if (bp->hwrm_spec_code < 0x10804 ||
3169 bp->hwrm_spec_code == 0x10900)
3170 return 0;
3171
3172 bp->hw_rx_port_stats_ext =
3173 dma_zalloc_coherent(&pdev->dev,
3174 sizeof(struct rx_port_stats_ext),
3175 &bp->hw_rx_port_stats_ext_map,
3176 GFP_KERNEL);
3177 if (!bp->hw_rx_port_stats_ext)
3178 return 0;
3179
3180 if (bp->hwrm_spec_code >= 0x10902) {
3181 bp->hw_tx_port_stats_ext =
3182 dma_zalloc_coherent(&pdev->dev,
3183 sizeof(struct tx_port_stats_ext),
3184 &bp->hw_tx_port_stats_ext_map,
3185 GFP_KERNEL);
3186 }
3187 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3188 }
3189 return 0;
3190 }
3191
3192 static void bnxt_clear_ring_indices(struct bnxt *bp)
3193 {
3194 int i;
3195
3196 if (!bp->bnapi)
3197 return;
3198
3199 for (i = 0; i < bp->cp_nr_rings; i++) {
3200 struct bnxt_napi *bnapi = bp->bnapi[i];
3201 struct bnxt_cp_ring_info *cpr;
3202 struct bnxt_rx_ring_info *rxr;
3203 struct bnxt_tx_ring_info *txr;
3204
3205 if (!bnapi)
3206 continue;
3207
3208 cpr = &bnapi->cp_ring;
3209 cpr->cp_raw_cons = 0;
3210
3211 txr = bnapi->tx_ring;
3212 if (txr) {
3213 txr->tx_prod = 0;
3214 txr->tx_cons = 0;
3215 }
3216
3217 rxr = bnapi->rx_ring;
3218 if (rxr) {
3219 rxr->rx_prod = 0;
3220 rxr->rx_agg_prod = 0;
3221 rxr->rx_sw_agg_prod = 0;
3222 rxr->rx_next_cons = 0;
3223 }
3224 }
3225 }
3226
3227 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3228 {
3229 #ifdef CONFIG_RFS_ACCEL
3230 int i;
3231
3232 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3233 * safe to delete the hash table.
3234 */
3235 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3236 struct hlist_head *head;
3237 struct hlist_node *tmp;
3238 struct bnxt_ntuple_filter *fltr;
3239
3240 head = &bp->ntp_fltr_hash_tbl[i];
3241 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3242 hlist_del(&fltr->hash);
3243 kfree(fltr);
3244 }
3245 }
3246 if (irq_reinit) {
3247 kfree(bp->ntp_fltr_bmap);
3248 bp->ntp_fltr_bmap = NULL;
3249 }
3250 bp->ntp_fltr_count = 0;
3251 #endif
3252 }
3253
3254 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3255 {
3256 #ifdef CONFIG_RFS_ACCEL
3257 int i, rc = 0;
3258
3259 if (!(bp->flags & BNXT_FLAG_RFS))
3260 return 0;
3261
3262 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3263 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3264
3265 bp->ntp_fltr_count = 0;
3266 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3267 sizeof(long),
3268 GFP_KERNEL);
3269
3270 if (!bp->ntp_fltr_bmap)
3271 rc = -ENOMEM;
3272
3273 return rc;
3274 #else
3275 return 0;
3276 #endif
3277 }
3278
3279 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3280 {
3281 bnxt_free_vnic_attributes(bp);
3282 bnxt_free_tx_rings(bp);
3283 bnxt_free_rx_rings(bp);
3284 bnxt_free_cp_rings(bp);
3285 bnxt_free_ntp_fltrs(bp, irq_re_init);
3286 if (irq_re_init) {
3287 bnxt_free_stats(bp);
3288 bnxt_free_ring_grps(bp);
3289 bnxt_free_vnics(bp);
3290 kfree(bp->tx_ring_map);
3291 bp->tx_ring_map = NULL;
3292 kfree(bp->tx_ring);
3293 bp->tx_ring = NULL;
3294 kfree(bp->rx_ring);
3295 bp->rx_ring = NULL;
3296 kfree(bp->bnapi);
3297 bp->bnapi = NULL;
3298 } else {
3299 bnxt_clear_ring_indices(bp);
3300 }
3301 }
3302
3303 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3304 {
3305 int i, j, rc, size, arr_size;
3306 void *bnapi;
3307
3308 if (irq_re_init) {
3309 /* Allocate bnapi mem pointer array and mem block for
3310 * all queues
3311 */
3312 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3313 bp->cp_nr_rings);
3314 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3315 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3316 if (!bnapi)
3317 return -ENOMEM;
3318
3319 bp->bnapi = bnapi;
3320 bnapi += arr_size;
3321 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3322 bp->bnapi[i] = bnapi;
3323 bp->bnapi[i]->index = i;
3324 bp->bnapi[i]->bp = bp;
3325 }
3326
3327 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3328 sizeof(struct bnxt_rx_ring_info),
3329 GFP_KERNEL);
3330 if (!bp->rx_ring)
3331 return -ENOMEM;
3332
3333 for (i = 0; i < bp->rx_nr_rings; i++) {
3334 bp->rx_ring[i].bnapi = bp->bnapi[i];
3335 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3336 }
3337
3338 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3339 sizeof(struct bnxt_tx_ring_info),
3340 GFP_KERNEL);
3341 if (!bp->tx_ring)
3342 return -ENOMEM;
3343
3344 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3345 GFP_KERNEL);
3346
3347 if (!bp->tx_ring_map)
3348 return -ENOMEM;
3349
3350 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3351 j = 0;
3352 else
3353 j = bp->rx_nr_rings;
3354
3355 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3356 bp->tx_ring[i].bnapi = bp->bnapi[j];
3357 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3358 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3359 if (i >= bp->tx_nr_rings_xdp) {
3360 bp->tx_ring[i].txq_index = i -
3361 bp->tx_nr_rings_xdp;
3362 bp->bnapi[j]->tx_int = bnxt_tx_int;
3363 } else {
3364 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3365 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3366 }
3367 }
3368
3369 rc = bnxt_alloc_stats(bp);
3370 if (rc)
3371 goto alloc_mem_err;
3372
3373 rc = bnxt_alloc_ntp_fltrs(bp);
3374 if (rc)
3375 goto alloc_mem_err;
3376
3377 rc = bnxt_alloc_vnics(bp);
3378 if (rc)
3379 goto alloc_mem_err;
3380 }
3381
3382 bnxt_init_ring_struct(bp);
3383
3384 rc = bnxt_alloc_rx_rings(bp);
3385 if (rc)
3386 goto alloc_mem_err;
3387
3388 rc = bnxt_alloc_tx_rings(bp);
3389 if (rc)
3390 goto alloc_mem_err;
3391
3392 rc = bnxt_alloc_cp_rings(bp);
3393 if (rc)
3394 goto alloc_mem_err;
3395
3396 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3397 BNXT_VNIC_UCAST_FLAG;
3398 rc = bnxt_alloc_vnic_attributes(bp);
3399 if (rc)
3400 goto alloc_mem_err;
3401 return 0;
3402
3403 alloc_mem_err:
3404 bnxt_free_mem(bp, true);
3405 return rc;
3406 }
3407
3408 static void bnxt_disable_int(struct bnxt *bp)
3409 {
3410 int i;
3411
3412 if (!bp->bnapi)
3413 return;
3414
3415 for (i = 0; i < bp->cp_nr_rings; i++) {
3416 struct bnxt_napi *bnapi = bp->bnapi[i];
3417 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3418 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3419
3420 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3421 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3422 }
3423 }
3424
3425 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3426 {
3427 struct bnxt_napi *bnapi = bp->bnapi[n];
3428 struct bnxt_cp_ring_info *cpr;
3429
3430 cpr = &bnapi->cp_ring;
3431 return cpr->cp_ring_struct.map_idx;
3432 }
3433
3434 static void bnxt_disable_int_sync(struct bnxt *bp)
3435 {
3436 int i;
3437
3438 atomic_inc(&bp->intr_sem);
3439
3440 bnxt_disable_int(bp);
3441 for (i = 0; i < bp->cp_nr_rings; i++) {
3442 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3443
3444 synchronize_irq(bp->irq_tbl[map_idx].vector);
3445 }
3446 }
3447
3448 static void bnxt_enable_int(struct bnxt *bp)
3449 {
3450 int i;
3451
3452 atomic_set(&bp->intr_sem, 0);
3453 for (i = 0; i < bp->cp_nr_rings; i++) {
3454 struct bnxt_napi *bnapi = bp->bnapi[i];
3455 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3456
3457 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3458 }
3459 }
3460
3461 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3462 u16 cmpl_ring, u16 target_id)
3463 {
3464 struct input *req = request;
3465
3466 req->req_type = cpu_to_le16(req_type);
3467 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3468 req->target_id = cpu_to_le16(target_id);
3469 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3470 }
3471
3472 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3473 int timeout, bool silent)
3474 {
3475 int i, intr_process, rc, tmo_count;
3476 struct input *req = msg;
3477 u32 *data = msg;
3478 __le32 *resp_len;
3479 u8 *valid;
3480 u16 cp_ring_id, len = 0;
3481 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3482 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3483 struct hwrm_short_input short_input = {0};
3484
3485 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3486 memset(resp, 0, PAGE_SIZE);
3487 cp_ring_id = le16_to_cpu(req->cmpl_ring);
3488 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3489
3490 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3491 if (msg_len > bp->hwrm_max_ext_req_len ||
3492 !bp->hwrm_short_cmd_req_addr)
3493 return -EINVAL;
3494 }
3495
3496 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
3497 msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3498 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3499 u16 max_msg_len;
3500
3501 /* Set boundary for maximum extended request length for short
3502 * cmd format. If passed up from device use the max supported
3503 * internal req length.
3504 */
3505 max_msg_len = bp->hwrm_max_ext_req_len;
3506
3507 memcpy(short_cmd_req, req, msg_len);
3508 if (msg_len < max_msg_len)
3509 memset(short_cmd_req + msg_len, 0,
3510 max_msg_len - msg_len);
3511
3512 short_input.req_type = req->req_type;
3513 short_input.signature =
3514 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3515 short_input.size = cpu_to_le16(msg_len);
3516 short_input.req_addr =
3517 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3518
3519 data = (u32 *)&short_input;
3520 msg_len = sizeof(short_input);
3521
3522 /* Sync memory write before updating doorbell */
3523 wmb();
3524
3525 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3526 }
3527
3528 /* Write request msg to hwrm channel */
3529 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3530
3531 for (i = msg_len; i < max_req_len; i += 4)
3532 writel(0, bp->bar0 + i);
3533
3534 /* currently supports only one outstanding message */
3535 if (intr_process)
3536 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3537
3538 /* Ring channel doorbell */
3539 writel(1, bp->bar0 + 0x100);
3540
3541 if (!timeout)
3542 timeout = DFLT_HWRM_CMD_TIMEOUT;
3543 /* convert timeout to usec */
3544 timeout *= 1000;
3545
3546 i = 0;
3547 /* Short timeout for the first few iterations:
3548 * number of loops = number of loops for short timeout +
3549 * number of loops for standard timeout.
3550 */
3551 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3552 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3553 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3554 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3555 if (intr_process) {
3556 /* Wait until hwrm response cmpl interrupt is processed */
3557 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3558 i++ < tmo_count) {
3559 /* on first few passes, just barely sleep */
3560 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3561 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3562 HWRM_SHORT_MAX_TIMEOUT);
3563 else
3564 usleep_range(HWRM_MIN_TIMEOUT,
3565 HWRM_MAX_TIMEOUT);
3566 }
3567
3568 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3569 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3570 le16_to_cpu(req->req_type));
3571 return -1;
3572 }
3573 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3574 HWRM_RESP_LEN_SFT;
3575 valid = bp->hwrm_cmd_resp_addr + len - 1;
3576 } else {
3577 int j;
3578
3579 /* Check if response len is updated */
3580 for (i = 0; i < tmo_count; i++) {
3581 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3582 HWRM_RESP_LEN_SFT;
3583 if (len)
3584 break;
3585 /* on first few passes, just barely sleep */
3586 if (i < DFLT_HWRM_CMD_TIMEOUT)
3587 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3588 HWRM_SHORT_MAX_TIMEOUT);
3589 else
3590 usleep_range(HWRM_MIN_TIMEOUT,
3591 HWRM_MAX_TIMEOUT);
3592 }
3593
3594 if (i >= tmo_count) {
3595 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3596 HWRM_TOTAL_TIMEOUT(i),
3597 le16_to_cpu(req->req_type),
3598 le16_to_cpu(req->seq_id), len);
3599 return -1;
3600 }
3601
3602 /* Last byte of resp contains valid bit */
3603 valid = bp->hwrm_cmd_resp_addr + len - 1;
3604 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
3605 /* make sure we read from updated DMA memory */
3606 dma_rmb();
3607 if (*valid)
3608 break;
3609 udelay(1);
3610 }
3611
3612 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
3613 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3614 HWRM_TOTAL_TIMEOUT(i),
3615 le16_to_cpu(req->req_type),
3616 le16_to_cpu(req->seq_id), len, *valid);
3617 return -1;
3618 }
3619 }
3620
3621 /* Zero valid bit for compatibility. Valid bit in an older spec
3622 * may become a new field in a newer spec. We must make sure that
3623 * a new field not implemented by old spec will read zero.
3624 */
3625 *valid = 0;
3626 rc = le16_to_cpu(resp->error_code);
3627 if (rc && !silent)
3628 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3629 le16_to_cpu(resp->req_type),
3630 le16_to_cpu(resp->seq_id), rc);
3631 return rc;
3632 }
3633
3634 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3635 {
3636 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3637 }
3638
3639 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3640 int timeout)
3641 {
3642 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3643 }
3644
3645 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3646 {
3647 int rc;
3648
3649 mutex_lock(&bp->hwrm_cmd_lock);
3650 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3651 mutex_unlock(&bp->hwrm_cmd_lock);
3652 return rc;
3653 }
3654
3655 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3656 int timeout)
3657 {
3658 int rc;
3659
3660 mutex_lock(&bp->hwrm_cmd_lock);
3661 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3662 mutex_unlock(&bp->hwrm_cmd_lock);
3663 return rc;
3664 }
3665
3666 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3667 int bmap_size)
3668 {
3669 struct hwrm_func_drv_rgtr_input req = {0};
3670 DECLARE_BITMAP(async_events_bmap, 256);
3671 u32 *events = (u32 *)async_events_bmap;
3672 int i;
3673
3674 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3675
3676 req.enables =
3677 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3678
3679 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3680 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3681 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3682
3683 if (bmap && bmap_size) {
3684 for (i = 0; i < bmap_size; i++) {
3685 if (test_bit(i, bmap))
3686 __set_bit(i, async_events_bmap);
3687 }
3688 }
3689
3690 for (i = 0; i < 8; i++)
3691 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3692
3693 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3694 }
3695
3696 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3697 {
3698 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3699 struct hwrm_func_drv_rgtr_input req = {0};
3700 int rc;
3701
3702 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3703
3704 req.enables =
3705 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3706 FUNC_DRV_RGTR_REQ_ENABLES_VER);
3707
3708 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3709 req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
3710 req.ver_maj_8b = DRV_VER_MAJ;
3711 req.ver_min_8b = DRV_VER_MIN;
3712 req.ver_upd_8b = DRV_VER_UPD;
3713 req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
3714 req.ver_min = cpu_to_le16(DRV_VER_MIN);
3715 req.ver_upd = cpu_to_le16(DRV_VER_UPD);
3716
3717 if (BNXT_PF(bp)) {
3718 u32 data[8];
3719 int i;
3720
3721 memset(data, 0, sizeof(data));
3722 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3723 u16 cmd = bnxt_vf_req_snif[i];
3724 unsigned int bit, idx;
3725
3726 idx = cmd / 32;
3727 bit = cmd % 32;
3728 data[idx] |= 1 << bit;
3729 }
3730
3731 for (i = 0; i < 8; i++)
3732 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3733
3734 req.enables |=
3735 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3736 }
3737
3738 mutex_lock(&bp->hwrm_cmd_lock);
3739 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3740 if (rc)
3741 rc = -EIO;
3742 else if (resp->flags &
3743 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
3744 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
3745 mutex_unlock(&bp->hwrm_cmd_lock);
3746 return rc;
3747 }
3748
3749 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3750 {
3751 struct hwrm_func_drv_unrgtr_input req = {0};
3752
3753 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3754 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3755 }
3756
3757 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3758 {
3759 u32 rc = 0;
3760 struct hwrm_tunnel_dst_port_free_input req = {0};
3761
3762 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3763 req.tunnel_type = tunnel_type;
3764
3765 switch (tunnel_type) {
3766 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3767 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3768 break;
3769 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3770 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3771 break;
3772 default:
3773 break;
3774 }
3775
3776 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3777 if (rc)
3778 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3779 rc);
3780 return rc;
3781 }
3782
3783 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3784 u8 tunnel_type)
3785 {
3786 u32 rc = 0;
3787 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3788 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3789
3790 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3791
3792 req.tunnel_type = tunnel_type;
3793 req.tunnel_dst_port_val = port;
3794
3795 mutex_lock(&bp->hwrm_cmd_lock);
3796 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3797 if (rc) {
3798 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3799 rc);
3800 goto err_out;
3801 }
3802
3803 switch (tunnel_type) {
3804 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3805 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3806 break;
3807 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3808 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3809 break;
3810 default:
3811 break;
3812 }
3813
3814 err_out:
3815 mutex_unlock(&bp->hwrm_cmd_lock);
3816 return rc;
3817 }
3818
3819 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3820 {
3821 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3822 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3823
3824 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3825 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3826
3827 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3828 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3829 req.mask = cpu_to_le32(vnic->rx_mask);
3830 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3831 }
3832
3833 #ifdef CONFIG_RFS_ACCEL
3834 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3835 struct bnxt_ntuple_filter *fltr)
3836 {
3837 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3838
3839 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3840 req.ntuple_filter_id = fltr->filter_id;
3841 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3842 }
3843
3844 #define BNXT_NTP_FLTR_FLAGS \
3845 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3846 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3847 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3848 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3849 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3850 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3851 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3852 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3853 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3854 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3855 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3856 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3857 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3858 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3859
3860 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
3861 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3862
3863 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3864 struct bnxt_ntuple_filter *fltr)
3865 {
3866 int rc = 0;
3867 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3868 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3869 bp->hwrm_cmd_resp_addr;
3870 struct flow_keys *keys = &fltr->fkeys;
3871 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3872
3873 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3874 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3875
3876 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3877
3878 req.ethertype = htons(ETH_P_IP);
3879 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3880 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3881 req.ip_protocol = keys->basic.ip_proto;
3882
3883 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3884 int i;
3885
3886 req.ethertype = htons(ETH_P_IPV6);
3887 req.ip_addr_type =
3888 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3889 *(struct in6_addr *)&req.src_ipaddr[0] =
3890 keys->addrs.v6addrs.src;
3891 *(struct in6_addr *)&req.dst_ipaddr[0] =
3892 keys->addrs.v6addrs.dst;
3893 for (i = 0; i < 4; i++) {
3894 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3895 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3896 }
3897 } else {
3898 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3899 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3900 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3901 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3902 }
3903 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3904 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3905 req.tunnel_type =
3906 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3907 }
3908
3909 req.src_port = keys->ports.src;
3910 req.src_port_mask = cpu_to_be16(0xffff);
3911 req.dst_port = keys->ports.dst;
3912 req.dst_port_mask = cpu_to_be16(0xffff);
3913
3914 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3915 mutex_lock(&bp->hwrm_cmd_lock);
3916 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3917 if (!rc)
3918 fltr->filter_id = resp->ntuple_filter_id;
3919 mutex_unlock(&bp->hwrm_cmd_lock);
3920 return rc;
3921 }
3922 #endif
3923
3924 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3925 u8 *mac_addr)
3926 {
3927 u32 rc = 0;
3928 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3929 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3930
3931 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3932 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3933 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3934 req.flags |=
3935 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3936 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3937 req.enables =
3938 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3939 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3940 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3941 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3942 req.l2_addr_mask[0] = 0xff;
3943 req.l2_addr_mask[1] = 0xff;
3944 req.l2_addr_mask[2] = 0xff;
3945 req.l2_addr_mask[3] = 0xff;
3946 req.l2_addr_mask[4] = 0xff;
3947 req.l2_addr_mask[5] = 0xff;
3948
3949 mutex_lock(&bp->hwrm_cmd_lock);
3950 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3951 if (!rc)
3952 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3953 resp->l2_filter_id;
3954 mutex_unlock(&bp->hwrm_cmd_lock);
3955 return rc;
3956 }
3957
3958 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3959 {
3960 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3961 int rc = 0;
3962
3963 /* Any associated ntuple filters will also be cleared by firmware. */
3964 mutex_lock(&bp->hwrm_cmd_lock);
3965 for (i = 0; i < num_of_vnics; i++) {
3966 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3967
3968 for (j = 0; j < vnic->uc_filter_count; j++) {
3969 struct hwrm_cfa_l2_filter_free_input req = {0};
3970
3971 bnxt_hwrm_cmd_hdr_init(bp, &req,
3972 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3973
3974 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3975
3976 rc = _hwrm_send_message(bp, &req, sizeof(req),
3977 HWRM_CMD_TIMEOUT);
3978 }
3979 vnic->uc_filter_count = 0;
3980 }
3981 mutex_unlock(&bp->hwrm_cmd_lock);
3982
3983 return rc;
3984 }
3985
3986 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3987 {
3988 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3989 struct hwrm_vnic_tpa_cfg_input req = {0};
3990
3991 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
3992 return 0;
3993
3994 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3995
3996 if (tpa_flags) {
3997 u16 mss = bp->dev->mtu - 40;
3998 u32 nsegs, n, segs = 0, flags;
3999
4000 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4001 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4002 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4003 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4004 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4005 if (tpa_flags & BNXT_FLAG_GRO)
4006 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4007
4008 req.flags = cpu_to_le32(flags);
4009
4010 req.enables =
4011 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4012 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4013 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4014
4015 /* Number of segs are log2 units, and first packet is not
4016 * included as part of this units.
4017 */
4018 if (mss <= BNXT_RX_PAGE_SIZE) {
4019 n = BNXT_RX_PAGE_SIZE / mss;
4020 nsegs = (MAX_SKB_FRAGS - 1) * n;
4021 } else {
4022 n = mss / BNXT_RX_PAGE_SIZE;
4023 if (mss & (BNXT_RX_PAGE_SIZE - 1))
4024 n++;
4025 nsegs = (MAX_SKB_FRAGS - n) / n;
4026 }
4027
4028 segs = ilog2(nsegs);
4029 req.max_agg_segs = cpu_to_le16(segs);
4030 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
4031
4032 req.min_agg_len = cpu_to_le32(512);
4033 }
4034 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4035
4036 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4037 }
4038
4039 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4040 {
4041 u32 i, j, max_rings;
4042 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4043 struct hwrm_vnic_rss_cfg_input req = {0};
4044
4045 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4046 return 0;
4047
4048 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4049 if (set_rss) {
4050 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4051 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4052 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4053 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4054 max_rings = bp->rx_nr_rings - 1;
4055 else
4056 max_rings = bp->rx_nr_rings;
4057 } else {
4058 max_rings = 1;
4059 }
4060
4061 /* Fill the RSS indirection table with ring group ids */
4062 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4063 if (j == max_rings)
4064 j = 0;
4065 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4066 }
4067
4068 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4069 req.hash_key_tbl_addr =
4070 cpu_to_le64(vnic->rss_hash_key_dma_addr);
4071 }
4072 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4073 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4074 }
4075
4076 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4077 {
4078 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4079 struct hwrm_vnic_plcmodes_cfg_input req = {0};
4080
4081 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4082 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4083 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4084 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4085 req.enables =
4086 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4087 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4088 /* thresholds not implemented in firmware yet */
4089 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4090 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4091 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4092 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4093 }
4094
4095 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4096 u16 ctx_idx)
4097 {
4098 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4099
4100 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4101 req.rss_cos_lb_ctx_id =
4102 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4103
4104 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4105 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4106 }
4107
4108 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4109 {
4110 int i, j;
4111
4112 for (i = 0; i < bp->nr_vnics; i++) {
4113 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4114
4115 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4116 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4117 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4118 }
4119 }
4120 bp->rsscos_nr_ctxs = 0;
4121 }
4122
4123 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4124 {
4125 int rc;
4126 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4127 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4128 bp->hwrm_cmd_resp_addr;
4129
4130 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4131 -1);
4132
4133 mutex_lock(&bp->hwrm_cmd_lock);
4134 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4135 if (!rc)
4136 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4137 le16_to_cpu(resp->rss_cos_lb_ctx_id);
4138 mutex_unlock(&bp->hwrm_cmd_lock);
4139
4140 return rc;
4141 }
4142
4143 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4144 {
4145 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4146 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4147 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4148 }
4149
4150 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4151 {
4152 unsigned int ring = 0, grp_idx;
4153 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4154 struct hwrm_vnic_cfg_input req = {0};
4155 u16 def_vlan = 0;
4156
4157 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4158
4159 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4160 /* Only RSS support for now TBD: COS & LB */
4161 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4162 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4163 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4164 VNIC_CFG_REQ_ENABLES_MRU);
4165 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4166 req.rss_rule =
4167 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4168 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4169 VNIC_CFG_REQ_ENABLES_MRU);
4170 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4171 } else {
4172 req.rss_rule = cpu_to_le16(0xffff);
4173 }
4174
4175 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4176 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4177 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4178 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4179 } else {
4180 req.cos_rule = cpu_to_le16(0xffff);
4181 }
4182
4183 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4184 ring = 0;
4185 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4186 ring = vnic_id - 1;
4187 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4188 ring = bp->rx_nr_rings - 1;
4189
4190 grp_idx = bp->rx_ring[ring].bnapi->index;
4191 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4192 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4193
4194 req.lb_rule = cpu_to_le16(0xffff);
4195 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4196 VLAN_HLEN);
4197
4198 #ifdef CONFIG_BNXT_SRIOV
4199 if (BNXT_VF(bp))
4200 def_vlan = bp->vf.vlan;
4201 #endif
4202 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4203 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4204 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4205 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4206
4207 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4208 }
4209
4210 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4211 {
4212 u32 rc = 0;
4213
4214 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4215 struct hwrm_vnic_free_input req = {0};
4216
4217 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4218 req.vnic_id =
4219 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4220
4221 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4222 if (rc)
4223 return rc;
4224 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4225 }
4226 return rc;
4227 }
4228
4229 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4230 {
4231 u16 i;
4232
4233 for (i = 0; i < bp->nr_vnics; i++)
4234 bnxt_hwrm_vnic_free_one(bp, i);
4235 }
4236
4237 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4238 unsigned int start_rx_ring_idx,
4239 unsigned int nr_rings)
4240 {
4241 int rc = 0;
4242 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4243 struct hwrm_vnic_alloc_input req = {0};
4244 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4245
4246 /* map ring groups to this vnic */
4247 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4248 grp_idx = bp->rx_ring[i].bnapi->index;
4249 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4250 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4251 j, nr_rings);
4252 break;
4253 }
4254 bp->vnic_info[vnic_id].fw_grp_ids[j] =
4255 bp->grp_info[grp_idx].fw_grp_id;
4256 }
4257
4258 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4259 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
4260 if (vnic_id == 0)
4261 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4262
4263 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4264
4265 mutex_lock(&bp->hwrm_cmd_lock);
4266 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4267 if (!rc)
4268 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
4269 mutex_unlock(&bp->hwrm_cmd_lock);
4270 return rc;
4271 }
4272
4273 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4274 {
4275 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4276 struct hwrm_vnic_qcaps_input req = {0};
4277 int rc;
4278
4279 if (bp->hwrm_spec_code < 0x10600)
4280 return 0;
4281
4282 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4283 mutex_lock(&bp->hwrm_cmd_lock);
4284 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4285 if (!rc) {
4286 u32 flags = le32_to_cpu(resp->flags);
4287
4288 if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)
4289 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4290 if (flags &
4291 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4292 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4293 }
4294 mutex_unlock(&bp->hwrm_cmd_lock);
4295 return rc;
4296 }
4297
4298 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4299 {
4300 u16 i;
4301 u32 rc = 0;
4302
4303 mutex_lock(&bp->hwrm_cmd_lock);
4304 for (i = 0; i < bp->rx_nr_rings; i++) {
4305 struct hwrm_ring_grp_alloc_input req = {0};
4306 struct hwrm_ring_grp_alloc_output *resp =
4307 bp->hwrm_cmd_resp_addr;
4308 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4309
4310 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4311
4312 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4313 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4314 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4315 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4316
4317 rc = _hwrm_send_message(bp, &req, sizeof(req),
4318 HWRM_CMD_TIMEOUT);
4319 if (rc)
4320 break;
4321
4322 bp->grp_info[grp_idx].fw_grp_id =
4323 le32_to_cpu(resp->ring_group_id);
4324 }
4325 mutex_unlock(&bp->hwrm_cmd_lock);
4326 return rc;
4327 }
4328
4329 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4330 {
4331 u16 i;
4332 u32 rc = 0;
4333 struct hwrm_ring_grp_free_input req = {0};
4334
4335 if (!bp->grp_info)
4336 return 0;
4337
4338 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4339
4340 mutex_lock(&bp->hwrm_cmd_lock);
4341 for (i = 0; i < bp->cp_nr_rings; i++) {
4342 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4343 continue;
4344 req.ring_group_id =
4345 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4346
4347 rc = _hwrm_send_message(bp, &req, sizeof(req),
4348 HWRM_CMD_TIMEOUT);
4349 if (rc)
4350 break;
4351 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4352 }
4353 mutex_unlock(&bp->hwrm_cmd_lock);
4354 return rc;
4355 }
4356
4357 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4358 struct bnxt_ring_struct *ring,
4359 u32 ring_type, u32 map_index)
4360 {
4361 int rc = 0, err = 0;
4362 struct hwrm_ring_alloc_input req = {0};
4363 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4364 struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
4365 struct bnxt_ring_grp_info *grp_info;
4366 u16 ring_id;
4367
4368 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4369
4370 req.enables = 0;
4371 if (rmem->nr_pages > 1) {
4372 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
4373 /* Page size is in log2 units */
4374 req.page_size = BNXT_PAGE_SHIFT;
4375 req.page_tbl_depth = 1;
4376 } else {
4377 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
4378 }
4379 req.fbo = 0;
4380 /* Association of ring index with doorbell index and MSIX number */
4381 req.logical_id = cpu_to_le16(map_index);
4382
4383 switch (ring_type) {
4384 case HWRM_RING_ALLOC_TX:
4385 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4386 /* Association of transmit ring with completion ring */
4387 grp_info = &bp->grp_info[ring->grp_idx];
4388 req.cmpl_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4389 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4390 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4391 req.queue_id = cpu_to_le16(ring->queue_id);
4392 break;
4393 case HWRM_RING_ALLOC_RX:
4394 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4395 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4396 break;
4397 case HWRM_RING_ALLOC_AGG:
4398 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4399 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4400 break;
4401 case HWRM_RING_ALLOC_CMPL:
4402 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4403 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4404 if (bp->flags & BNXT_FLAG_USING_MSIX)
4405 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4406 break;
4407 default:
4408 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4409 ring_type);
4410 return -1;
4411 }
4412
4413 mutex_lock(&bp->hwrm_cmd_lock);
4414 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4415 err = le16_to_cpu(resp->error_code);
4416 ring_id = le16_to_cpu(resp->ring_id);
4417 mutex_unlock(&bp->hwrm_cmd_lock);
4418
4419 if (rc || err) {
4420 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4421 ring_type, rc, err);
4422 return -EIO;
4423 }
4424 ring->fw_ring_id = ring_id;
4425 return rc;
4426 }
4427
4428 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4429 {
4430 int rc;
4431
4432 if (BNXT_PF(bp)) {
4433 struct hwrm_func_cfg_input req = {0};
4434
4435 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4436 req.fid = cpu_to_le16(0xffff);
4437 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4438 req.async_event_cr = cpu_to_le16(idx);
4439 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4440 } else {
4441 struct hwrm_func_vf_cfg_input req = {0};
4442
4443 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4444 req.enables =
4445 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4446 req.async_event_cr = cpu_to_le16(idx);
4447 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4448 }
4449 return rc;
4450 }
4451
4452 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4453 {
4454 int i, rc = 0;
4455
4456 for (i = 0; i < bp->cp_nr_rings; i++) {
4457 struct bnxt_napi *bnapi = bp->bnapi[i];
4458 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4459 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4460 u32 map_idx = ring->map_idx;
4461
4462 cpr->cp_doorbell = bp->bar1 + map_idx * 0x80;
4463 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL,
4464 map_idx);
4465 if (rc)
4466 goto err_out;
4467 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4468 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4469
4470 if (!i) {
4471 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4472 if (rc)
4473 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4474 }
4475 }
4476
4477 for (i = 0; i < bp->tx_nr_rings; i++) {
4478 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4479 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4480 u32 map_idx = i;
4481
4482 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4483 map_idx);
4484 if (rc)
4485 goto err_out;
4486 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4487 }
4488
4489 for (i = 0; i < bp->rx_nr_rings; i++) {
4490 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4491 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4492 u32 map_idx = rxr->bnapi->index;
4493
4494 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4495 map_idx);
4496 if (rc)
4497 goto err_out;
4498 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4499 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4500 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4501 }
4502
4503 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4504 for (i = 0; i < bp->rx_nr_rings; i++) {
4505 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4506 struct bnxt_ring_struct *ring =
4507 &rxr->rx_agg_ring_struct;
4508 u32 grp_idx = ring->grp_idx;
4509 u32 map_idx = grp_idx + bp->rx_nr_rings;
4510
4511 rc = hwrm_ring_alloc_send_msg(bp, ring,
4512 HWRM_RING_ALLOC_AGG,
4513 map_idx);
4514 if (rc)
4515 goto err_out;
4516
4517 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4518 writel(DB_KEY_RX | rxr->rx_agg_prod,
4519 rxr->rx_agg_doorbell);
4520 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4521 }
4522 }
4523 err_out:
4524 return rc;
4525 }
4526
4527 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4528 struct bnxt_ring_struct *ring,
4529 u32 ring_type, int cmpl_ring_id)
4530 {
4531 int rc;
4532 struct hwrm_ring_free_input req = {0};
4533 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4534 u16 error_code;
4535
4536 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4537 req.ring_type = ring_type;
4538 req.ring_id = cpu_to_le16(ring->fw_ring_id);
4539
4540 mutex_lock(&bp->hwrm_cmd_lock);
4541 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4542 error_code = le16_to_cpu(resp->error_code);
4543 mutex_unlock(&bp->hwrm_cmd_lock);
4544
4545 if (rc || error_code) {
4546 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
4547 ring_type, rc, error_code);
4548 return -EIO;
4549 }
4550 return 0;
4551 }
4552
4553 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4554 {
4555 int i;
4556
4557 if (!bp->bnapi)
4558 return;
4559
4560 for (i = 0; i < bp->tx_nr_rings; i++) {
4561 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4562 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4563 u32 grp_idx = txr->bnapi->index;
4564 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4565
4566 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4567 hwrm_ring_free_send_msg(bp, ring,
4568 RING_FREE_REQ_RING_TYPE_TX,
4569 close_path ? cmpl_ring_id :
4570 INVALID_HW_RING_ID);
4571 ring->fw_ring_id = INVALID_HW_RING_ID;
4572 }
4573 }
4574
4575 for (i = 0; i < bp->rx_nr_rings; i++) {
4576 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4577 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4578 u32 grp_idx = rxr->bnapi->index;
4579 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4580
4581 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4582 hwrm_ring_free_send_msg(bp, ring,
4583 RING_FREE_REQ_RING_TYPE_RX,
4584 close_path ? cmpl_ring_id :
4585 INVALID_HW_RING_ID);
4586 ring->fw_ring_id = INVALID_HW_RING_ID;
4587 bp->grp_info[grp_idx].rx_fw_ring_id =
4588 INVALID_HW_RING_ID;
4589 }
4590 }
4591
4592 for (i = 0; i < bp->rx_nr_rings; i++) {
4593 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4594 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4595 u32 grp_idx = rxr->bnapi->index;
4596 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4597
4598 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4599 hwrm_ring_free_send_msg(bp, ring,
4600 RING_FREE_REQ_RING_TYPE_RX,
4601 close_path ? cmpl_ring_id :
4602 INVALID_HW_RING_ID);
4603 ring->fw_ring_id = INVALID_HW_RING_ID;
4604 bp->grp_info[grp_idx].agg_fw_ring_id =
4605 INVALID_HW_RING_ID;
4606 }
4607 }
4608
4609 /* The completion rings are about to be freed. After that the
4610 * IRQ doorbell will not work anymore. So we need to disable
4611 * IRQ here.
4612 */
4613 bnxt_disable_int_sync(bp);
4614
4615 for (i = 0; i < bp->cp_nr_rings; i++) {
4616 struct bnxt_napi *bnapi = bp->bnapi[i];
4617 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4618 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4619
4620 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4621 hwrm_ring_free_send_msg(bp, ring,
4622 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4623 INVALID_HW_RING_ID);
4624 ring->fw_ring_id = INVALID_HW_RING_ID;
4625 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4626 }
4627 }
4628 }
4629
4630 static int bnxt_hwrm_get_rings(struct bnxt *bp)
4631 {
4632 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4633 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4634 struct hwrm_func_qcfg_input req = {0};
4635 int rc;
4636
4637 if (bp->hwrm_spec_code < 0x10601)
4638 return 0;
4639
4640 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4641 req.fid = cpu_to_le16(0xffff);
4642 mutex_lock(&bp->hwrm_cmd_lock);
4643 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4644 if (rc) {
4645 mutex_unlock(&bp->hwrm_cmd_lock);
4646 return -EIO;
4647 }
4648
4649 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4650 if (BNXT_NEW_RM(bp)) {
4651 u16 cp, stats;
4652
4653 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
4654 hw_resc->resv_hw_ring_grps =
4655 le32_to_cpu(resp->alloc_hw_ring_grps);
4656 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
4657 cp = le16_to_cpu(resp->alloc_cmpl_rings);
4658 stats = le16_to_cpu(resp->alloc_stat_ctx);
4659 cp = min_t(u16, cp, stats);
4660 hw_resc->resv_cp_rings = cp;
4661 }
4662 mutex_unlock(&bp->hwrm_cmd_lock);
4663 return 0;
4664 }
4665
4666 /* Caller must hold bp->hwrm_cmd_lock */
4667 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4668 {
4669 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4670 struct hwrm_func_qcfg_input req = {0};
4671 int rc;
4672
4673 if (bp->hwrm_spec_code < 0x10601)
4674 return 0;
4675
4676 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4677 req.fid = cpu_to_le16(fid);
4678 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4679 if (!rc)
4680 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4681
4682 return rc;
4683 }
4684
4685 static void
4686 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
4687 int tx_rings, int rx_rings, int ring_grps,
4688 int cp_rings, int vnics)
4689 {
4690 u32 enables = 0;
4691
4692 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
4693 req->fid = cpu_to_le16(0xffff);
4694 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4695 req->num_tx_rings = cpu_to_le16(tx_rings);
4696 if (BNXT_NEW_RM(bp)) {
4697 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4698 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4699 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4700 enables |= ring_grps ?
4701 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4702 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
4703
4704 req->num_rx_rings = cpu_to_le16(rx_rings);
4705 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4706 req->num_cmpl_rings = cpu_to_le16(cp_rings);
4707 req->num_stat_ctxs = req->num_cmpl_rings;
4708 req->num_vnics = cpu_to_le16(vnics);
4709 }
4710 req->enables = cpu_to_le32(enables);
4711 }
4712
4713 static void
4714 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
4715 struct hwrm_func_vf_cfg_input *req, int tx_rings,
4716 int rx_rings, int ring_grps, int cp_rings,
4717 int vnics)
4718 {
4719 u32 enables = 0;
4720
4721 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
4722 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4723 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4724 enables |= cp_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4725 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4726 enables |= ring_grps ? FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4727 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
4728
4729 req->num_tx_rings = cpu_to_le16(tx_rings);
4730 req->num_rx_rings = cpu_to_le16(rx_rings);
4731 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4732 req->num_cmpl_rings = cpu_to_le16(cp_rings);
4733 req->num_stat_ctxs = req->num_cmpl_rings;
4734 req->num_vnics = cpu_to_le16(vnics);
4735
4736 req->enables = cpu_to_le32(enables);
4737 }
4738
4739 static int
4740 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4741 int ring_grps, int cp_rings, int vnics)
4742 {
4743 struct hwrm_func_cfg_input req = {0};
4744 int rc;
4745
4746 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4747 cp_rings, vnics);
4748 if (!req.enables)
4749 return 0;
4750
4751 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4752 if (rc)
4753 return -ENOMEM;
4754
4755 if (bp->hwrm_spec_code < 0x10601)
4756 bp->hw_resc.resv_tx_rings = tx_rings;
4757
4758 rc = bnxt_hwrm_get_rings(bp);
4759 return rc;
4760 }
4761
4762 static int
4763 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4764 int ring_grps, int cp_rings, int vnics)
4765 {
4766 struct hwrm_func_vf_cfg_input req = {0};
4767 int rc;
4768
4769 if (!BNXT_NEW_RM(bp)) {
4770 bp->hw_resc.resv_tx_rings = tx_rings;
4771 return 0;
4772 }
4773
4774 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4775 cp_rings, vnics);
4776 req.enables |= cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS |
4777 FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS);
4778 req.num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
4779 req.num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
4780 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4781 if (rc)
4782 return -ENOMEM;
4783
4784 rc = bnxt_hwrm_get_rings(bp);
4785 return rc;
4786 }
4787
4788 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
4789 int cp, int vnic)
4790 {
4791 if (BNXT_PF(bp))
4792 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, vnic);
4793 else
4794 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, vnic);
4795 }
4796
4797 static int bnxt_cp_rings_in_use(struct bnxt *bp)
4798 {
4799 int cp = bp->cp_nr_rings;
4800 int ulp_msix, ulp_base;
4801
4802 ulp_msix = bnxt_get_ulp_msix_num(bp);
4803 if (ulp_msix) {
4804 ulp_base = bnxt_get_ulp_msix_base(bp);
4805 cp += ulp_msix;
4806 if ((ulp_base + ulp_msix) > cp)
4807 cp = ulp_base + ulp_msix;
4808 }
4809 return cp;
4810 }
4811
4812 static bool bnxt_need_reserve_rings(struct bnxt *bp)
4813 {
4814 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4815 int cp = bnxt_cp_rings_in_use(bp);
4816 int rx = bp->rx_nr_rings;
4817 int vnic = 1, grp = rx;
4818
4819 if (bp->hwrm_spec_code < 0x10601)
4820 return false;
4821
4822 if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
4823 return true;
4824
4825 if (bp->flags & BNXT_FLAG_RFS)
4826 vnic = rx + 1;
4827 if (bp->flags & BNXT_FLAG_AGG_RINGS)
4828 rx <<= 1;
4829 if (BNXT_NEW_RM(bp) &&
4830 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
4831 hw_resc->resv_hw_ring_grps != grp || hw_resc->resv_vnics != vnic))
4832 return true;
4833 return false;
4834 }
4835
4836 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4837 bool shared);
4838
4839 static int __bnxt_reserve_rings(struct bnxt *bp)
4840 {
4841 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4842 int cp = bnxt_cp_rings_in_use(bp);
4843 int tx = bp->tx_nr_rings;
4844 int rx = bp->rx_nr_rings;
4845 int grp, rx_rings, rc;
4846 bool sh = false;
4847 int vnic = 1;
4848
4849 if (!bnxt_need_reserve_rings(bp))
4850 return 0;
4851
4852 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4853 sh = true;
4854 if (bp->flags & BNXT_FLAG_RFS)
4855 vnic = rx + 1;
4856 if (bp->flags & BNXT_FLAG_AGG_RINGS)
4857 rx <<= 1;
4858 grp = bp->rx_nr_rings;
4859
4860 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, vnic);
4861 if (rc)
4862 return rc;
4863
4864 tx = hw_resc->resv_tx_rings;
4865 if (BNXT_NEW_RM(bp)) {
4866 rx = hw_resc->resv_rx_rings;
4867 cp = hw_resc->resv_cp_rings;
4868 grp = hw_resc->resv_hw_ring_grps;
4869 vnic = hw_resc->resv_vnics;
4870 }
4871
4872 rx_rings = rx;
4873 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4874 if (rx >= 2) {
4875 rx_rings = rx >> 1;
4876 } else {
4877 if (netif_running(bp->dev))
4878 return -ENOMEM;
4879
4880 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
4881 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
4882 bp->dev->hw_features &= ~NETIF_F_LRO;
4883 bp->dev->features &= ~NETIF_F_LRO;
4884 bnxt_set_ring_params(bp);
4885 }
4886 }
4887 rx_rings = min_t(int, rx_rings, grp);
4888 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
4889 if (bp->flags & BNXT_FLAG_AGG_RINGS)
4890 rx = rx_rings << 1;
4891 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
4892 bp->tx_nr_rings = tx;
4893 bp->rx_nr_rings = rx_rings;
4894 bp->cp_nr_rings = cp;
4895
4896 if (!tx || !rx || !cp || !grp || !vnic)
4897 return -ENOMEM;
4898
4899 return rc;
4900 }
4901
4902 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4903 int ring_grps, int cp_rings, int vnics)
4904 {
4905 struct hwrm_func_vf_cfg_input req = {0};
4906 u32 flags;
4907 int rc;
4908
4909 if (!BNXT_NEW_RM(bp))
4910 return 0;
4911
4912 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4913 cp_rings, vnics);
4914 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
4915 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4916 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4917 FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4918 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4919 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4920
4921 req.flags = cpu_to_le32(flags);
4922 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4923 if (rc)
4924 return -ENOMEM;
4925 return 0;
4926 }
4927
4928 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4929 int ring_grps, int cp_rings, int vnics)
4930 {
4931 struct hwrm_func_cfg_input req = {0};
4932 u32 flags;
4933 int rc;
4934
4935 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4936 cp_rings, vnics);
4937 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
4938 if (BNXT_NEW_RM(bp))
4939 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4940 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4941 FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4942 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4943 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4944
4945 req.flags = cpu_to_le32(flags);
4946 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4947 if (rc)
4948 return -ENOMEM;
4949 return 0;
4950 }
4951
4952 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4953 int ring_grps, int cp_rings, int vnics)
4954 {
4955 if (bp->hwrm_spec_code < 0x10801)
4956 return 0;
4957
4958 if (BNXT_PF(bp))
4959 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
4960 ring_grps, cp_rings, vnics);
4961
4962 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
4963 cp_rings, vnics);
4964 }
4965
4966 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
4967 {
4968 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4969 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
4970 struct hwrm_ring_aggint_qcaps_input req = {0};
4971 int rc;
4972
4973 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
4974 coal_cap->num_cmpl_dma_aggr_max = 63;
4975 coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
4976 coal_cap->cmpl_aggr_dma_tmr_max = 65535;
4977 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
4978 coal_cap->int_lat_tmr_min_max = 65535;
4979 coal_cap->int_lat_tmr_max_max = 65535;
4980 coal_cap->num_cmpl_aggr_int_max = 65535;
4981 coal_cap->timer_units = 80;
4982
4983 if (bp->hwrm_spec_code < 0x10902)
4984 return;
4985
4986 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
4987 mutex_lock(&bp->hwrm_cmd_lock);
4988 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4989 if (!rc) {
4990 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
4991 coal_cap->num_cmpl_dma_aggr_max =
4992 le16_to_cpu(resp->num_cmpl_dma_aggr_max);
4993 coal_cap->num_cmpl_dma_aggr_during_int_max =
4994 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
4995 coal_cap->cmpl_aggr_dma_tmr_max =
4996 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
4997 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
4998 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
4999 coal_cap->int_lat_tmr_min_max =
5000 le16_to_cpu(resp->int_lat_tmr_min_max);
5001 coal_cap->int_lat_tmr_max_max =
5002 le16_to_cpu(resp->int_lat_tmr_max_max);
5003 coal_cap->num_cmpl_aggr_int_max =
5004 le16_to_cpu(resp->num_cmpl_aggr_int_max);
5005 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
5006 }
5007 mutex_unlock(&bp->hwrm_cmd_lock);
5008 }
5009
5010 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
5011 {
5012 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5013
5014 return usec * 1000 / coal_cap->timer_units;
5015 }
5016
5017 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
5018 struct bnxt_coal *hw_coal,
5019 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5020 {
5021 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5022 u32 cmpl_params = coal_cap->cmpl_params;
5023 u16 val, tmr, max, flags = 0;
5024
5025 max = hw_coal->bufs_per_record * 128;
5026 if (hw_coal->budget)
5027 max = hw_coal->bufs_per_record * hw_coal->budget;
5028 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
5029
5030 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
5031 req->num_cmpl_aggr_int = cpu_to_le16(val);
5032
5033 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
5034 req->num_cmpl_dma_aggr = cpu_to_le16(val);
5035
5036 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
5037 coal_cap->num_cmpl_dma_aggr_during_int_max);
5038 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
5039
5040 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
5041 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
5042 req->int_lat_tmr_max = cpu_to_le16(tmr);
5043
5044 /* min timer set to 1/2 of interrupt timer */
5045 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
5046 val = tmr / 2;
5047 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
5048 req->int_lat_tmr_min = cpu_to_le16(val);
5049 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5050 }
5051
5052 /* buf timer set to 1/4 of interrupt timer */
5053 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
5054 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
5055
5056 if (cmpl_params &
5057 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
5058 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
5059 val = clamp_t(u16, tmr, 1,
5060 coal_cap->cmpl_aggr_dma_tmr_during_int_max);
5061 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
5062 req->enables |=
5063 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
5064 }
5065
5066 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
5067 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
5068 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
5069 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
5070 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
5071 req->flags = cpu_to_le16(flags);
5072 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
5073 }
5074
5075 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
5076 {
5077 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
5078 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5079 struct bnxt_coal coal;
5080 unsigned int grp_idx;
5081
5082 /* Tick values in micro seconds.
5083 * 1 coal_buf x bufs_per_record = 1 completion record.
5084 */
5085 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
5086
5087 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
5088 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
5089
5090 if (!bnapi->rx_ring)
5091 return -ENODEV;
5092
5093 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5094 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5095
5096 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
5097
5098 grp_idx = bnapi->index;
5099 req_rx.ring_id = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
5100
5101 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5102 HWRM_CMD_TIMEOUT);
5103 }
5104
5105 int bnxt_hwrm_set_coal(struct bnxt *bp)
5106 {
5107 int i, rc = 0;
5108 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5109 req_tx = {0}, *req;
5110
5111 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5112 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5113 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5114 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5115
5116 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
5117 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
5118
5119 mutex_lock(&bp->hwrm_cmd_lock);
5120 for (i = 0; i < bp->cp_nr_rings; i++) {
5121 struct bnxt_napi *bnapi = bp->bnapi[i];
5122
5123 req = &req_rx;
5124 if (!bnapi->rx_ring)
5125 req = &req_tx;
5126 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
5127
5128 rc = _hwrm_send_message(bp, req, sizeof(*req),
5129 HWRM_CMD_TIMEOUT);
5130 if (rc)
5131 break;
5132 }
5133 mutex_unlock(&bp->hwrm_cmd_lock);
5134 return rc;
5135 }
5136
5137 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5138 {
5139 int rc = 0, i;
5140 struct hwrm_stat_ctx_free_input req = {0};
5141
5142 if (!bp->bnapi)
5143 return 0;
5144
5145 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5146 return 0;
5147
5148 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5149
5150 mutex_lock(&bp->hwrm_cmd_lock);
5151 for (i = 0; i < bp->cp_nr_rings; i++) {
5152 struct bnxt_napi *bnapi = bp->bnapi[i];
5153 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5154
5155 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5156 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5157
5158 rc = _hwrm_send_message(bp, &req, sizeof(req),
5159 HWRM_CMD_TIMEOUT);
5160 if (rc)
5161 break;
5162
5163 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5164 }
5165 }
5166 mutex_unlock(&bp->hwrm_cmd_lock);
5167 return rc;
5168 }
5169
5170 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5171 {
5172 int rc = 0, i;
5173 struct hwrm_stat_ctx_alloc_input req = {0};
5174 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5175
5176 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5177 return 0;
5178
5179 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5180
5181 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5182
5183 mutex_lock(&bp->hwrm_cmd_lock);
5184 for (i = 0; i < bp->cp_nr_rings; i++) {
5185 struct bnxt_napi *bnapi = bp->bnapi[i];
5186 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5187
5188 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5189
5190 rc = _hwrm_send_message(bp, &req, sizeof(req),
5191 HWRM_CMD_TIMEOUT);
5192 if (rc)
5193 break;
5194
5195 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5196
5197 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5198 }
5199 mutex_unlock(&bp->hwrm_cmd_lock);
5200 return rc;
5201 }
5202
5203 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5204 {
5205 struct hwrm_func_qcfg_input req = {0};
5206 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5207 u16 flags;
5208 int rc;
5209
5210 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5211 req.fid = cpu_to_le16(0xffff);
5212 mutex_lock(&bp->hwrm_cmd_lock);
5213 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5214 if (rc)
5215 goto func_qcfg_exit;
5216
5217 #ifdef CONFIG_BNXT_SRIOV
5218 if (BNXT_VF(bp)) {
5219 struct bnxt_vf_info *vf = &bp->vf;
5220
5221 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5222 }
5223 #endif
5224 flags = le16_to_cpu(resp->flags);
5225 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5226 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5227 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
5228 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5229 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
5230 }
5231 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5232 bp->flags |= BNXT_FLAG_MULTI_HOST;
5233
5234 switch (resp->port_partition_type) {
5235 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
5236 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
5237 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
5238 bp->port_partition_type = resp->port_partition_type;
5239 break;
5240 }
5241 if (bp->hwrm_spec_code < 0x10707 ||
5242 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
5243 bp->br_mode = BRIDGE_MODE_VEB;
5244 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
5245 bp->br_mode = BRIDGE_MODE_VEPA;
5246 else
5247 bp->br_mode = BRIDGE_MODE_UNDEF;
5248
5249 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
5250 if (!bp->max_mtu)
5251 bp->max_mtu = BNXT_MAX_MTU;
5252
5253 func_qcfg_exit:
5254 mutex_unlock(&bp->hwrm_cmd_lock);
5255 return rc;
5256 }
5257
5258 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5259 {
5260 struct hwrm_func_backing_store_qcaps_input req = {0};
5261 struct hwrm_func_backing_store_qcaps_output *resp =
5262 bp->hwrm_cmd_resp_addr;
5263 int rc;
5264
5265 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
5266 return 0;
5267
5268 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
5269 mutex_lock(&bp->hwrm_cmd_lock);
5270 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5271 if (!rc) {
5272 struct bnxt_ctx_pg_info *ctx_pg;
5273 struct bnxt_ctx_mem_info *ctx;
5274 int i;
5275
5276 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
5277 if (!ctx) {
5278 rc = -ENOMEM;
5279 goto ctx_err;
5280 }
5281 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
5282 if (!ctx_pg) {
5283 kfree(ctx);
5284 rc = -ENOMEM;
5285 goto ctx_err;
5286 }
5287 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
5288 ctx->tqm_mem[i] = ctx_pg;
5289
5290 bp->ctx = ctx;
5291 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
5292 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
5293 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
5294 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
5295 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
5296 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
5297 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
5298 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
5299 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
5300 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
5301 ctx->vnic_max_vnic_entries =
5302 le16_to_cpu(resp->vnic_max_vnic_entries);
5303 ctx->vnic_max_ring_table_entries =
5304 le16_to_cpu(resp->vnic_max_ring_table_entries);
5305 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
5306 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
5307 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
5308 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
5309 ctx->tqm_min_entries_per_ring =
5310 le32_to_cpu(resp->tqm_min_entries_per_ring);
5311 ctx->tqm_max_entries_per_ring =
5312 le32_to_cpu(resp->tqm_max_entries_per_ring);
5313 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5314 if (!ctx->tqm_entries_multiple)
5315 ctx->tqm_entries_multiple = 1;
5316 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
5317 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
5318 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
5319 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
5320 } else {
5321 rc = 0;
5322 }
5323 ctx_err:
5324 mutex_unlock(&bp->hwrm_cmd_lock);
5325 return rc;
5326 }
5327
5328 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
5329 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size)
5330 {
5331 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
5332
5333 if (!mem_size)
5334 return 0;
5335
5336 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
5337 if (rmem->nr_pages > MAX_CTX_PAGES) {
5338 rmem->nr_pages = 0;
5339 return -EINVAL;
5340 }
5341 rmem->page_size = BNXT_PAGE_SIZE;
5342 rmem->pg_arr = ctx_pg->ctx_pg_arr;
5343 rmem->dma_arr = ctx_pg->ctx_dma_arr;
5344 return bnxt_alloc_ring(bp, rmem);
5345 }
5346
5347 static void bnxt_free_ctx_mem(struct bnxt *bp)
5348 {
5349 struct bnxt_ctx_mem_info *ctx = bp->ctx;
5350 int i;
5351
5352 if (!ctx)
5353 return;
5354
5355 if (ctx->tqm_mem[0]) {
5356 for (i = 0; i < bp->max_q + 1; i++)
5357 bnxt_free_ring(bp, &ctx->tqm_mem[i]->ring_mem);
5358 kfree(ctx->tqm_mem[0]);
5359 ctx->tqm_mem[0] = NULL;
5360 }
5361
5362 bnxt_free_ring(bp, &ctx->stat_mem.ring_mem);
5363 bnxt_free_ring(bp, &ctx->vnic_mem.ring_mem);
5364 bnxt_free_ring(bp, &ctx->cq_mem.ring_mem);
5365 bnxt_free_ring(bp, &ctx->srq_mem.ring_mem);
5366 bnxt_free_ring(bp, &ctx->qp_mem.ring_mem);
5367 ctx->flags &= ~BNXT_CTX_FLAG_INITED;
5368 }
5369
5370 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
5371 {
5372 struct bnxt_ctx_pg_info *ctx_pg;
5373 struct bnxt_ctx_mem_info *ctx;
5374 u32 mem_size, entries;
5375 int i, rc;
5376
5377 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
5378 if (rc) {
5379 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
5380 rc);
5381 return rc;
5382 }
5383 ctx = bp->ctx;
5384 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
5385 return 0;
5386
5387 ctx_pg = &ctx->qp_mem;
5388 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
5389 mem_size = ctx->qp_entry_size * ctx_pg->entries;
5390 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
5391 if (rc)
5392 return rc;
5393
5394 ctx_pg = &ctx->srq_mem;
5395 ctx_pg->entries = ctx->srq_max_l2_entries;
5396 mem_size = ctx->srq_entry_size * ctx_pg->entries;
5397 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
5398 if (rc)
5399 return rc;
5400
5401 ctx_pg = &ctx->cq_mem;
5402 ctx_pg->entries = ctx->cq_max_l2_entries;
5403 mem_size = ctx->cq_entry_size * ctx_pg->entries;
5404 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
5405 if (rc)
5406 return rc;
5407
5408 ctx_pg = &ctx->vnic_mem;
5409 ctx_pg->entries = ctx->vnic_max_vnic_entries +
5410 ctx->vnic_max_ring_table_entries;
5411 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
5412 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
5413 if (rc)
5414 return rc;
5415
5416 ctx_pg = &ctx->stat_mem;
5417 ctx_pg->entries = ctx->stat_max_entries;
5418 mem_size = ctx->stat_entry_size * ctx_pg->entries;
5419 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
5420 if (rc)
5421 return rc;
5422
5423 entries = ctx->qp_max_l2_entries;
5424 entries = roundup(entries, ctx->tqm_entries_multiple);
5425 entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
5426 ctx->tqm_max_entries_per_ring);
5427 for (i = 0; i < bp->max_q + 1; i++) {
5428 ctx_pg = ctx->tqm_mem[i];
5429 ctx_pg->entries = entries;
5430 mem_size = ctx->tqm_entry_size * entries;
5431 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
5432 if (rc)
5433 return rc;
5434 }
5435 ctx->flags |= BNXT_CTX_FLAG_INITED;
5436 return 0;
5437 }
5438
5439 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
5440 {
5441 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5442 struct hwrm_func_resource_qcaps_input req = {0};
5443 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5444 int rc;
5445
5446 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
5447 req.fid = cpu_to_le16(0xffff);
5448
5449 mutex_lock(&bp->hwrm_cmd_lock);
5450 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5451 if (rc) {
5452 rc = -EIO;
5453 goto hwrm_func_resc_qcaps_exit;
5454 }
5455
5456 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
5457 if (!all)
5458 goto hwrm_func_resc_qcaps_exit;
5459
5460 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
5461 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5462 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
5463 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5464 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
5465 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5466 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
5467 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5468 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
5469 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
5470 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
5471 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5472 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
5473 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5474 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
5475 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5476
5477 if (BNXT_PF(bp)) {
5478 struct bnxt_pf_info *pf = &bp->pf;
5479
5480 pf->vf_resv_strategy =
5481 le16_to_cpu(resp->vf_reservation_strategy);
5482 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
5483 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
5484 }
5485 hwrm_func_resc_qcaps_exit:
5486 mutex_unlock(&bp->hwrm_cmd_lock);
5487 return rc;
5488 }
5489
5490 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
5491 {
5492 int rc = 0;
5493 struct hwrm_func_qcaps_input req = {0};
5494 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5495 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5496 u32 flags;
5497
5498 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
5499 req.fid = cpu_to_le16(0xffff);
5500
5501 mutex_lock(&bp->hwrm_cmd_lock);
5502 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5503 if (rc)
5504 goto hwrm_func_qcaps_exit;
5505
5506 flags = le32_to_cpu(resp->flags);
5507 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
5508 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
5509 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
5510 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
5511
5512 bp->tx_push_thresh = 0;
5513 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
5514 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
5515
5516 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5517 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5518 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5519 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5520 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
5521 if (!hw_resc->max_hw_ring_grps)
5522 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
5523 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5524 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5525 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5526
5527 if (BNXT_PF(bp)) {
5528 struct bnxt_pf_info *pf = &bp->pf;
5529
5530 pf->fw_fid = le16_to_cpu(resp->fid);
5531 pf->port_id = le16_to_cpu(resp->port_id);
5532 bp->dev->dev_port = pf->port_id;
5533 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
5534 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
5535 pf->max_vfs = le16_to_cpu(resp->max_vfs);
5536 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
5537 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
5538 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
5539 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
5540 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
5541 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
5542 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
5543 bp->flags |= BNXT_FLAG_WOL_CAP;
5544 } else {
5545 #ifdef CONFIG_BNXT_SRIOV
5546 struct bnxt_vf_info *vf = &bp->vf;
5547
5548 vf->fw_fid = le16_to_cpu(resp->fid);
5549 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
5550 #endif
5551 }
5552
5553 hwrm_func_qcaps_exit:
5554 mutex_unlock(&bp->hwrm_cmd_lock);
5555 return rc;
5556 }
5557
5558 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
5559 {
5560 int rc;
5561
5562 rc = __bnxt_hwrm_func_qcaps(bp);
5563 if (rc)
5564 return rc;
5565 if (bp->hwrm_spec_code >= 0x10803) {
5566 rc = bnxt_alloc_ctx_mem(bp);
5567 if (rc)
5568 return rc;
5569 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
5570 if (!rc)
5571 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
5572 }
5573 return 0;
5574 }
5575
5576 static int bnxt_hwrm_func_reset(struct bnxt *bp)
5577 {
5578 struct hwrm_func_reset_input req = {0};
5579
5580 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
5581 req.enables = 0;
5582
5583 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
5584 }
5585
5586 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
5587 {
5588 int rc = 0;
5589 struct hwrm_queue_qportcfg_input req = {0};
5590 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
5591 u8 i, j, *qptr;
5592 bool no_rdma;
5593
5594 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
5595
5596 mutex_lock(&bp->hwrm_cmd_lock);
5597 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5598 if (rc)
5599 goto qportcfg_exit;
5600
5601 if (!resp->max_configurable_queues) {
5602 rc = -EINVAL;
5603 goto qportcfg_exit;
5604 }
5605 bp->max_tc = resp->max_configurable_queues;
5606 bp->max_lltc = resp->max_configurable_lossless_queues;
5607 if (bp->max_tc > BNXT_MAX_QUEUE)
5608 bp->max_tc = BNXT_MAX_QUEUE;
5609
5610 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
5611 qptr = &resp->queue_id0;
5612 for (i = 0, j = 0; i < bp->max_tc; i++) {
5613 bp->q_info[j].queue_id = *qptr;
5614 bp->q_ids[i] = *qptr++;
5615 bp->q_info[j].queue_profile = *qptr++;
5616 bp->tc_to_qidx[j] = j;
5617 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
5618 (no_rdma && BNXT_PF(bp)))
5619 j++;
5620 }
5621 bp->max_q = bp->max_tc;
5622 bp->max_tc = max_t(u8, j, 1);
5623
5624 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
5625 bp->max_tc = 1;
5626
5627 if (bp->max_lltc > bp->max_tc)
5628 bp->max_lltc = bp->max_tc;
5629
5630 qportcfg_exit:
5631 mutex_unlock(&bp->hwrm_cmd_lock);
5632 return rc;
5633 }
5634
5635 static int bnxt_hwrm_ver_get(struct bnxt *bp)
5636 {
5637 int rc;
5638 struct hwrm_ver_get_input req = {0};
5639 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
5640 u32 dev_caps_cfg;
5641
5642 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
5643 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
5644 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
5645 req.hwrm_intf_min = HWRM_VERSION_MINOR;
5646 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
5647 mutex_lock(&bp->hwrm_cmd_lock);
5648 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5649 if (rc)
5650 goto hwrm_ver_get_exit;
5651
5652 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
5653
5654 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
5655 resp->hwrm_intf_min_8b << 8 |
5656 resp->hwrm_intf_upd_8b;
5657 if (resp->hwrm_intf_maj_8b < 1) {
5658 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
5659 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
5660 resp->hwrm_intf_upd_8b);
5661 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
5662 }
5663 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
5664 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
5665 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
5666
5667 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
5668 if (!bp->hwrm_cmd_timeout)
5669 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
5670
5671 if (resp->hwrm_intf_maj_8b >= 1) {
5672 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
5673 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
5674 }
5675 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
5676 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
5677
5678 bp->chip_num = le16_to_cpu(resp->chip_num);
5679 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
5680 !resp->chip_metal)
5681 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
5682
5683 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
5684 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
5685 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
5686 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
5687
5688 hwrm_ver_get_exit:
5689 mutex_unlock(&bp->hwrm_cmd_lock);
5690 return rc;
5691 }
5692
5693 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
5694 {
5695 struct hwrm_fw_set_time_input req = {0};
5696 struct tm tm;
5697 time64_t now = ktime_get_real_seconds();
5698
5699 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
5700 bp->hwrm_spec_code < 0x10400)
5701 return -EOPNOTSUPP;
5702
5703 time64_to_tm(now, 0, &tm);
5704 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
5705 req.year = cpu_to_le16(1900 + tm.tm_year);
5706 req.month = 1 + tm.tm_mon;
5707 req.day = tm.tm_mday;
5708 req.hour = tm.tm_hour;
5709 req.minute = tm.tm_min;
5710 req.second = tm.tm_sec;
5711 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5712 }
5713
5714 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
5715 {
5716 int rc;
5717 struct bnxt_pf_info *pf = &bp->pf;
5718 struct hwrm_port_qstats_input req = {0};
5719
5720 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
5721 return 0;
5722
5723 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
5724 req.port_id = cpu_to_le16(pf->port_id);
5725 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
5726 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
5727 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5728 return rc;
5729 }
5730
5731 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
5732 {
5733 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5734 struct hwrm_port_qstats_ext_input req = {0};
5735 struct bnxt_pf_info *pf = &bp->pf;
5736 int rc;
5737
5738 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5739 return 0;
5740
5741 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
5742 req.port_id = cpu_to_le16(pf->port_id);
5743 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
5744 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
5745 req.tx_stat_size = cpu_to_le16(sizeof(struct tx_port_stats_ext));
5746 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map);
5747 mutex_lock(&bp->hwrm_cmd_lock);
5748 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5749 if (!rc) {
5750 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
5751 bp->fw_tx_stats_ext_size = le16_to_cpu(resp->tx_stat_size) / 8;
5752 } else {
5753 bp->fw_rx_stats_ext_size = 0;
5754 bp->fw_tx_stats_ext_size = 0;
5755 }
5756 mutex_unlock(&bp->hwrm_cmd_lock);
5757 return rc;
5758 }
5759
5760 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
5761 {
5762 if (bp->vxlan_port_cnt) {
5763 bnxt_hwrm_tunnel_dst_port_free(
5764 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5765 }
5766 bp->vxlan_port_cnt = 0;
5767 if (bp->nge_port_cnt) {
5768 bnxt_hwrm_tunnel_dst_port_free(
5769 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5770 }
5771 bp->nge_port_cnt = 0;
5772 }
5773
5774 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
5775 {
5776 int rc, i;
5777 u32 tpa_flags = 0;
5778
5779 if (set_tpa)
5780 tpa_flags = bp->flags & BNXT_FLAG_TPA;
5781 for (i = 0; i < bp->nr_vnics; i++) {
5782 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
5783 if (rc) {
5784 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
5785 i, rc);
5786 return rc;
5787 }
5788 }
5789 return 0;
5790 }
5791
5792 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
5793 {
5794 int i;
5795
5796 for (i = 0; i < bp->nr_vnics; i++)
5797 bnxt_hwrm_vnic_set_rss(bp, i, false);
5798 }
5799
5800 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
5801 bool irq_re_init)
5802 {
5803 if (bp->vnic_info) {
5804 bnxt_hwrm_clear_vnic_filter(bp);
5805 /* clear all RSS setting before free vnic ctx */
5806 bnxt_hwrm_clear_vnic_rss(bp);
5807 bnxt_hwrm_vnic_ctx_free(bp);
5808 /* before free the vnic, undo the vnic tpa settings */
5809 if (bp->flags & BNXT_FLAG_TPA)
5810 bnxt_set_tpa(bp, false);
5811 bnxt_hwrm_vnic_free(bp);
5812 }
5813 bnxt_hwrm_ring_free(bp, close_path);
5814 bnxt_hwrm_ring_grp_free(bp);
5815 if (irq_re_init) {
5816 bnxt_hwrm_stat_ctx_free(bp);
5817 bnxt_hwrm_free_tunnel_ports(bp);
5818 }
5819 }
5820
5821 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
5822 {
5823 struct hwrm_func_cfg_input req = {0};
5824 int rc;
5825
5826 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5827 req.fid = cpu_to_le16(0xffff);
5828 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
5829 if (br_mode == BRIDGE_MODE_VEB)
5830 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
5831 else if (br_mode == BRIDGE_MODE_VEPA)
5832 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5833 else
5834 return -EINVAL;
5835 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5836 if (rc)
5837 rc = -EIO;
5838 return rc;
5839 }
5840
5841 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
5842 {
5843 struct hwrm_func_cfg_input req = {0};
5844 int rc;
5845
5846 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
5847 return 0;
5848
5849 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5850 req.fid = cpu_to_le16(0xffff);
5851 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
5852 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
5853 if (size == 128)
5854 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
5855
5856 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5857 if (rc)
5858 rc = -EIO;
5859 return rc;
5860 }
5861
5862 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5863 {
5864 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5865 int rc;
5866
5867 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
5868 goto skip_rss_ctx;
5869
5870 /* allocate context for vnic */
5871 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
5872 if (rc) {
5873 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5874 vnic_id, rc);
5875 goto vnic_setup_err;
5876 }
5877 bp->rsscos_nr_ctxs++;
5878
5879 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5880 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
5881 if (rc) {
5882 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5883 vnic_id, rc);
5884 goto vnic_setup_err;
5885 }
5886 bp->rsscos_nr_ctxs++;
5887 }
5888
5889 skip_rss_ctx:
5890 /* configure default vnic, ring grp */
5891 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
5892 if (rc) {
5893 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
5894 vnic_id, rc);
5895 goto vnic_setup_err;
5896 }
5897
5898 /* Enable RSS hashing on vnic */
5899 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
5900 if (rc) {
5901 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
5902 vnic_id, rc);
5903 goto vnic_setup_err;
5904 }
5905
5906 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5907 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
5908 if (rc) {
5909 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
5910 vnic_id, rc);
5911 }
5912 }
5913
5914 vnic_setup_err:
5915 return rc;
5916 }
5917
5918 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5919 {
5920 #ifdef CONFIG_RFS_ACCEL
5921 int i, rc = 0;
5922
5923 for (i = 0; i < bp->rx_nr_rings; i++) {
5924 struct bnxt_vnic_info *vnic;
5925 u16 vnic_id = i + 1;
5926 u16 ring_id = i;
5927
5928 if (vnic_id >= bp->nr_vnics)
5929 break;
5930
5931 vnic = &bp->vnic_info[vnic_id];
5932 vnic->flags |= BNXT_VNIC_RFS_FLAG;
5933 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
5934 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
5935 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
5936 if (rc) {
5937 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5938 vnic_id, rc);
5939 break;
5940 }
5941 rc = bnxt_setup_vnic(bp, vnic_id);
5942 if (rc)
5943 break;
5944 }
5945 return rc;
5946 #else
5947 return 0;
5948 #endif
5949 }
5950
5951 /* Allow PF and VF with default VLAN to be in promiscuous mode */
5952 static bool bnxt_promisc_ok(struct bnxt *bp)
5953 {
5954 #ifdef CONFIG_BNXT_SRIOV
5955 if (BNXT_VF(bp) && !bp->vf.vlan)
5956 return false;
5957 #endif
5958 return true;
5959 }
5960
5961 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
5962 {
5963 unsigned int rc = 0;
5964
5965 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
5966 if (rc) {
5967 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5968 rc);
5969 return rc;
5970 }
5971
5972 rc = bnxt_hwrm_vnic_cfg(bp, 1);
5973 if (rc) {
5974 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5975 rc);
5976 return rc;
5977 }
5978 return rc;
5979 }
5980
5981 static int bnxt_cfg_rx_mode(struct bnxt *);
5982 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
5983
5984 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
5985 {
5986 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5987 int rc = 0;
5988 unsigned int rx_nr_rings = bp->rx_nr_rings;
5989
5990 if (irq_re_init) {
5991 rc = bnxt_hwrm_stat_ctx_alloc(bp);
5992 if (rc) {
5993 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
5994 rc);
5995 goto err_out;
5996 }
5997 }
5998
5999 rc = bnxt_hwrm_ring_alloc(bp);
6000 if (rc) {
6001 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
6002 goto err_out;
6003 }
6004
6005 rc = bnxt_hwrm_ring_grp_alloc(bp);
6006 if (rc) {
6007 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
6008 goto err_out;
6009 }
6010
6011 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6012 rx_nr_rings--;
6013
6014 /* default vnic 0 */
6015 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
6016 if (rc) {
6017 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
6018 goto err_out;
6019 }
6020
6021 rc = bnxt_setup_vnic(bp, 0);
6022 if (rc)
6023 goto err_out;
6024
6025 if (bp->flags & BNXT_FLAG_RFS) {
6026 rc = bnxt_alloc_rfs_vnics(bp);
6027 if (rc)
6028 goto err_out;
6029 }
6030
6031 if (bp->flags & BNXT_FLAG_TPA) {
6032 rc = bnxt_set_tpa(bp, true);
6033 if (rc)
6034 goto err_out;
6035 }
6036
6037 if (BNXT_VF(bp))
6038 bnxt_update_vf_mac(bp);
6039
6040 /* Filter for default vnic 0 */
6041 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
6042 if (rc) {
6043 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
6044 goto err_out;
6045 }
6046 vnic->uc_filter_count = 1;
6047
6048 vnic->rx_mask = 0;
6049 if (bp->dev->flags & IFF_BROADCAST)
6050 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
6051
6052 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
6053 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6054
6055 if (bp->dev->flags & IFF_ALLMULTI) {
6056 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6057 vnic->mc_list_count = 0;
6058 } else {
6059 u32 mask = 0;
6060
6061 bnxt_mc_list_updated(bp, &mask);
6062 vnic->rx_mask |= mask;
6063 }
6064
6065 rc = bnxt_cfg_rx_mode(bp);
6066 if (rc)
6067 goto err_out;
6068
6069 rc = bnxt_hwrm_set_coal(bp);
6070 if (rc)
6071 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
6072 rc);
6073
6074 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6075 rc = bnxt_setup_nitroa0_vnic(bp);
6076 if (rc)
6077 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
6078 rc);
6079 }
6080
6081 if (BNXT_VF(bp)) {
6082 bnxt_hwrm_func_qcfg(bp);
6083 netdev_update_features(bp->dev);
6084 }
6085
6086 return 0;
6087
6088 err_out:
6089 bnxt_hwrm_resource_free(bp, 0, true);
6090
6091 return rc;
6092 }
6093
6094 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
6095 {
6096 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
6097 return 0;
6098 }
6099
6100 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
6101 {
6102 bnxt_init_cp_rings(bp);
6103 bnxt_init_rx_rings(bp);
6104 bnxt_init_tx_rings(bp);
6105 bnxt_init_ring_grps(bp, irq_re_init);
6106 bnxt_init_vnics(bp);
6107
6108 return bnxt_init_chip(bp, irq_re_init);
6109 }
6110
6111 static int bnxt_set_real_num_queues(struct bnxt *bp)
6112 {
6113 int rc;
6114 struct net_device *dev = bp->dev;
6115
6116 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
6117 bp->tx_nr_rings_xdp);
6118 if (rc)
6119 return rc;
6120
6121 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
6122 if (rc)
6123 return rc;
6124
6125 #ifdef CONFIG_RFS_ACCEL
6126 if (bp->flags & BNXT_FLAG_RFS)
6127 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
6128 #endif
6129
6130 return rc;
6131 }
6132
6133 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
6134 bool shared)
6135 {
6136 int _rx = *rx, _tx = *tx;
6137
6138 if (shared) {
6139 *rx = min_t(int, _rx, max);
6140 *tx = min_t(int, _tx, max);
6141 } else {
6142 if (max < 2)
6143 return -ENOMEM;
6144
6145 while (_rx + _tx > max) {
6146 if (_rx > _tx && _rx > 1)
6147 _rx--;
6148 else if (_tx > 1)
6149 _tx--;
6150 }
6151 *rx = _rx;
6152 *tx = _tx;
6153 }
6154 return 0;
6155 }
6156
6157 static void bnxt_setup_msix(struct bnxt *bp)
6158 {
6159 const int len = sizeof(bp->irq_tbl[0].name);
6160 struct net_device *dev = bp->dev;
6161 int tcs, i;
6162
6163 tcs = netdev_get_num_tc(dev);
6164 if (tcs > 1) {
6165 int i, off, count;
6166
6167 for (i = 0; i < tcs; i++) {
6168 count = bp->tx_nr_rings_per_tc;
6169 off = i * count;
6170 netdev_set_tc_queue(dev, i, count, off);
6171 }
6172 }
6173
6174 for (i = 0; i < bp->cp_nr_rings; i++) {
6175 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
6176 char *attr;
6177
6178 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6179 attr = "TxRx";
6180 else if (i < bp->rx_nr_rings)
6181 attr = "rx";
6182 else
6183 attr = "tx";
6184
6185 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
6186 attr, i);
6187 bp->irq_tbl[map_idx].handler = bnxt_msix;
6188 }
6189 }
6190
6191 static void bnxt_setup_inta(struct bnxt *bp)
6192 {
6193 const int len = sizeof(bp->irq_tbl[0].name);
6194
6195 if (netdev_get_num_tc(bp->dev))
6196 netdev_reset_tc(bp->dev);
6197
6198 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
6199 0);
6200 bp->irq_tbl[0].handler = bnxt_inta;
6201 }
6202
6203 static int bnxt_setup_int_mode(struct bnxt *bp)
6204 {
6205 int rc;
6206
6207 if (bp->flags & BNXT_FLAG_USING_MSIX)
6208 bnxt_setup_msix(bp);
6209 else
6210 bnxt_setup_inta(bp);
6211
6212 rc = bnxt_set_real_num_queues(bp);
6213 return rc;
6214 }
6215
6216 #ifdef CONFIG_RFS_ACCEL
6217 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
6218 {
6219 return bp->hw_resc.max_rsscos_ctxs;
6220 }
6221
6222 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
6223 {
6224 return bp->hw_resc.max_vnics;
6225 }
6226 #endif
6227
6228 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
6229 {
6230 return bp->hw_resc.max_stat_ctxs;
6231 }
6232
6233 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
6234 {
6235 bp->hw_resc.max_stat_ctxs = max;
6236 }
6237
6238 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
6239 {
6240 return bp->hw_resc.max_cp_rings;
6241 }
6242
6243 unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
6244 {
6245 return bp->hw_resc.max_cp_rings - bnxt_get_ulp_msix_num(bp);
6246 }
6247
6248 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
6249 {
6250 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6251
6252 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
6253 }
6254
6255 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
6256 {
6257 bp->hw_resc.max_irqs = max_irqs;
6258 }
6259
6260 int bnxt_get_avail_msix(struct bnxt *bp, int num)
6261 {
6262 int max_cp = bnxt_get_max_func_cp_rings(bp);
6263 int max_irq = bnxt_get_max_func_irqs(bp);
6264 int total_req = bp->cp_nr_rings + num;
6265 int max_idx, avail_msix;
6266
6267 max_idx = min_t(int, bp->total_irqs, max_cp);
6268 avail_msix = max_idx - bp->cp_nr_rings;
6269 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
6270 return avail_msix;
6271
6272 if (max_irq < total_req) {
6273 num = max_irq - bp->cp_nr_rings;
6274 if (num <= 0)
6275 return 0;
6276 }
6277 return num;
6278 }
6279
6280 static int bnxt_get_num_msix(struct bnxt *bp)
6281 {
6282 if (!BNXT_NEW_RM(bp))
6283 return bnxt_get_max_func_irqs(bp);
6284
6285 return bnxt_cp_rings_in_use(bp);
6286 }
6287
6288 static int bnxt_init_msix(struct bnxt *bp)
6289 {
6290 int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
6291 struct msix_entry *msix_ent;
6292
6293 total_vecs = bnxt_get_num_msix(bp);
6294 max = bnxt_get_max_func_irqs(bp);
6295 if (total_vecs > max)
6296 total_vecs = max;
6297
6298 if (!total_vecs)
6299 return 0;
6300
6301 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
6302 if (!msix_ent)
6303 return -ENOMEM;
6304
6305 for (i = 0; i < total_vecs; i++) {
6306 msix_ent[i].entry = i;
6307 msix_ent[i].vector = 0;
6308 }
6309
6310 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
6311 min = 2;
6312
6313 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
6314 ulp_msix = bnxt_get_ulp_msix_num(bp);
6315 if (total_vecs < 0 || total_vecs < ulp_msix) {
6316 rc = -ENODEV;
6317 goto msix_setup_exit;
6318 }
6319
6320 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
6321 if (bp->irq_tbl) {
6322 for (i = 0; i < total_vecs; i++)
6323 bp->irq_tbl[i].vector = msix_ent[i].vector;
6324
6325 bp->total_irqs = total_vecs;
6326 /* Trim rings based upon num of vectors allocated */
6327 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
6328 total_vecs - ulp_msix, min == 1);
6329 if (rc)
6330 goto msix_setup_exit;
6331
6332 bp->cp_nr_rings = (min == 1) ?
6333 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6334 bp->tx_nr_rings + bp->rx_nr_rings;
6335
6336 } else {
6337 rc = -ENOMEM;
6338 goto msix_setup_exit;
6339 }
6340 bp->flags |= BNXT_FLAG_USING_MSIX;
6341 kfree(msix_ent);
6342 return 0;
6343
6344 msix_setup_exit:
6345 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
6346 kfree(bp->irq_tbl);
6347 bp->irq_tbl = NULL;
6348 pci_disable_msix(bp->pdev);
6349 kfree(msix_ent);
6350 return rc;
6351 }
6352
6353 static int bnxt_init_inta(struct bnxt *bp)
6354 {
6355 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
6356 if (!bp->irq_tbl)
6357 return -ENOMEM;
6358
6359 bp->total_irqs = 1;
6360 bp->rx_nr_rings = 1;
6361 bp->tx_nr_rings = 1;
6362 bp->cp_nr_rings = 1;
6363 bp->flags |= BNXT_FLAG_SHARED_RINGS;
6364 bp->irq_tbl[0].vector = bp->pdev->irq;
6365 return 0;
6366 }
6367
6368 static int bnxt_init_int_mode(struct bnxt *bp)
6369 {
6370 int rc = 0;
6371
6372 if (bp->flags & BNXT_FLAG_MSIX_CAP)
6373 rc = bnxt_init_msix(bp);
6374
6375 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
6376 /* fallback to INTA */
6377 rc = bnxt_init_inta(bp);
6378 }
6379 return rc;
6380 }
6381
6382 static void bnxt_clear_int_mode(struct bnxt *bp)
6383 {
6384 if (bp->flags & BNXT_FLAG_USING_MSIX)
6385 pci_disable_msix(bp->pdev);
6386
6387 kfree(bp->irq_tbl);
6388 bp->irq_tbl = NULL;
6389 bp->flags &= ~BNXT_FLAG_USING_MSIX;
6390 }
6391
6392 int bnxt_reserve_rings(struct bnxt *bp)
6393 {
6394 int tcs = netdev_get_num_tc(bp->dev);
6395 int rc;
6396
6397 if (!bnxt_need_reserve_rings(bp))
6398 return 0;
6399
6400 rc = __bnxt_reserve_rings(bp);
6401 if (rc) {
6402 netdev_err(bp->dev, "ring reservation failure rc: %d\n", rc);
6403 return rc;
6404 }
6405 if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) {
6406 bnxt_ulp_irq_stop(bp);
6407 bnxt_clear_int_mode(bp);
6408 rc = bnxt_init_int_mode(bp);
6409 bnxt_ulp_irq_restart(bp, rc);
6410 if (rc)
6411 return rc;
6412 }
6413 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
6414 netdev_err(bp->dev, "tx ring reservation failure\n");
6415 netdev_reset_tc(bp->dev);
6416 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
6417 return -ENOMEM;
6418 }
6419 bp->num_stat_ctxs = bp->cp_nr_rings;
6420 return 0;
6421 }
6422
6423 static void bnxt_free_irq(struct bnxt *bp)
6424 {
6425 struct bnxt_irq *irq;
6426 int i;
6427
6428 #ifdef CONFIG_RFS_ACCEL
6429 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
6430 bp->dev->rx_cpu_rmap = NULL;
6431 #endif
6432 if (!bp->irq_tbl || !bp->bnapi)
6433 return;
6434
6435 for (i = 0; i < bp->cp_nr_rings; i++) {
6436 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
6437
6438 irq = &bp->irq_tbl[map_idx];
6439 if (irq->requested) {
6440 if (irq->have_cpumask) {
6441 irq_set_affinity_hint(irq->vector, NULL);
6442 free_cpumask_var(irq->cpu_mask);
6443 irq->have_cpumask = 0;
6444 }
6445 free_irq(irq->vector, bp->bnapi[i]);
6446 }
6447
6448 irq->requested = 0;
6449 }
6450 }
6451
6452 static int bnxt_request_irq(struct bnxt *bp)
6453 {
6454 int i, j, rc = 0;
6455 unsigned long flags = 0;
6456 #ifdef CONFIG_RFS_ACCEL
6457 struct cpu_rmap *rmap;
6458 #endif
6459
6460 rc = bnxt_setup_int_mode(bp);
6461 if (rc) {
6462 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6463 rc);
6464 return rc;
6465 }
6466 #ifdef CONFIG_RFS_ACCEL
6467 rmap = bp->dev->rx_cpu_rmap;
6468 #endif
6469 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
6470 flags = IRQF_SHARED;
6471
6472 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
6473 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
6474 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
6475
6476 #ifdef CONFIG_RFS_ACCEL
6477 if (rmap && bp->bnapi[i]->rx_ring) {
6478 rc = irq_cpu_rmap_add(rmap, irq->vector);
6479 if (rc)
6480 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
6481 j);
6482 j++;
6483 }
6484 #endif
6485 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6486 bp->bnapi[i]);
6487 if (rc)
6488 break;
6489
6490 irq->requested = 1;
6491
6492 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
6493 int numa_node = dev_to_node(&bp->pdev->dev);
6494
6495 irq->have_cpumask = 1;
6496 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
6497 irq->cpu_mask);
6498 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
6499 if (rc) {
6500 netdev_warn(bp->dev,
6501 "Set affinity failed, IRQ = %d\n",
6502 irq->vector);
6503 break;
6504 }
6505 }
6506 }
6507 return rc;
6508 }
6509
6510 static void bnxt_del_napi(struct bnxt *bp)
6511 {
6512 int i;
6513
6514 if (!bp->bnapi)
6515 return;
6516
6517 for (i = 0; i < bp->cp_nr_rings; i++) {
6518 struct bnxt_napi *bnapi = bp->bnapi[i];
6519
6520 napi_hash_del(&bnapi->napi);
6521 netif_napi_del(&bnapi->napi);
6522 }
6523 /* We called napi_hash_del() before netif_napi_del(), we need
6524 * to respect an RCU grace period before freeing napi structures.
6525 */
6526 synchronize_net();
6527 }
6528
6529 static void bnxt_init_napi(struct bnxt *bp)
6530 {
6531 int i;
6532 unsigned int cp_nr_rings = bp->cp_nr_rings;
6533 struct bnxt_napi *bnapi;
6534
6535 if (bp->flags & BNXT_FLAG_USING_MSIX) {
6536 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6537 cp_nr_rings--;
6538 for (i = 0; i < cp_nr_rings; i++) {
6539 bnapi = bp->bnapi[i];
6540 netif_napi_add(bp->dev, &bnapi->napi,
6541 bnxt_poll, 64);
6542 }
6543 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6544 bnapi = bp->bnapi[cp_nr_rings];
6545 netif_napi_add(bp->dev, &bnapi->napi,
6546 bnxt_poll_nitroa0, 64);
6547 }
6548 } else {
6549 bnapi = bp->bnapi[0];
6550 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
6551 }
6552 }
6553
6554 static void bnxt_disable_napi(struct bnxt *bp)
6555 {
6556 int i;
6557
6558 if (!bp->bnapi)
6559 return;
6560
6561 for (i = 0; i < bp->cp_nr_rings; i++) {
6562 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6563
6564 if (bp->bnapi[i]->rx_ring)
6565 cancel_work_sync(&cpr->dim.work);
6566
6567 napi_disable(&bp->bnapi[i]->napi);
6568 }
6569 }
6570
6571 static void bnxt_enable_napi(struct bnxt *bp)
6572 {
6573 int i;
6574
6575 for (i = 0; i < bp->cp_nr_rings; i++) {
6576 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6577 bp->bnapi[i]->in_reset = false;
6578
6579 if (bp->bnapi[i]->rx_ring) {
6580 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
6581 cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
6582 }
6583 napi_enable(&bp->bnapi[i]->napi);
6584 }
6585 }
6586
6587 void bnxt_tx_disable(struct bnxt *bp)
6588 {
6589 int i;
6590 struct bnxt_tx_ring_info *txr;
6591
6592 if (bp->tx_ring) {
6593 for (i = 0; i < bp->tx_nr_rings; i++) {
6594 txr = &bp->tx_ring[i];
6595 txr->dev_state = BNXT_DEV_STATE_CLOSING;
6596 }
6597 }
6598 /* Stop all TX queues */
6599 netif_tx_disable(bp->dev);
6600 netif_carrier_off(bp->dev);
6601 }
6602
6603 void bnxt_tx_enable(struct bnxt *bp)
6604 {
6605 int i;
6606 struct bnxt_tx_ring_info *txr;
6607
6608 for (i = 0; i < bp->tx_nr_rings; i++) {
6609 txr = &bp->tx_ring[i];
6610 txr->dev_state = 0;
6611 }
6612 netif_tx_wake_all_queues(bp->dev);
6613 if (bp->link_info.link_up)
6614 netif_carrier_on(bp->dev);
6615 }
6616
6617 static void bnxt_report_link(struct bnxt *bp)
6618 {
6619 if (bp->link_info.link_up) {
6620 const char *duplex;
6621 const char *flow_ctrl;
6622 u32 speed;
6623 u16 fec;
6624
6625 netif_carrier_on(bp->dev);
6626 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
6627 duplex = "full";
6628 else
6629 duplex = "half";
6630 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
6631 flow_ctrl = "ON - receive & transmit";
6632 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
6633 flow_ctrl = "ON - transmit";
6634 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
6635 flow_ctrl = "ON - receive";
6636 else
6637 flow_ctrl = "none";
6638 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
6639 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
6640 speed, duplex, flow_ctrl);
6641 if (bp->flags & BNXT_FLAG_EEE_CAP)
6642 netdev_info(bp->dev, "EEE is %s\n",
6643 bp->eee.eee_active ? "active" :
6644 "not active");
6645 fec = bp->link_info.fec_cfg;
6646 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
6647 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
6648 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
6649 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
6650 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
6651 } else {
6652 netif_carrier_off(bp->dev);
6653 netdev_err(bp->dev, "NIC Link is Down\n");
6654 }
6655 }
6656
6657 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
6658 {
6659 int rc = 0;
6660 struct hwrm_port_phy_qcaps_input req = {0};
6661 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6662 struct bnxt_link_info *link_info = &bp->link_info;
6663
6664 if (bp->hwrm_spec_code < 0x10201)
6665 return 0;
6666
6667 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
6668
6669 mutex_lock(&bp->hwrm_cmd_lock);
6670 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6671 if (rc)
6672 goto hwrm_phy_qcaps_exit;
6673
6674 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
6675 struct ethtool_eee *eee = &bp->eee;
6676 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
6677
6678 bp->flags |= BNXT_FLAG_EEE_CAP;
6679 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6680 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
6681 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
6682 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
6683 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
6684 }
6685 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
6686 if (bp->test_info)
6687 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
6688 }
6689 if (resp->supported_speeds_auto_mode)
6690 link_info->support_auto_speeds =
6691 le16_to_cpu(resp->supported_speeds_auto_mode);
6692
6693 bp->port_count = resp->port_cnt;
6694
6695 hwrm_phy_qcaps_exit:
6696 mutex_unlock(&bp->hwrm_cmd_lock);
6697 return rc;
6698 }
6699
6700 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
6701 {
6702 int rc = 0;
6703 struct bnxt_link_info *link_info = &bp->link_info;
6704 struct hwrm_port_phy_qcfg_input req = {0};
6705 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6706 u8 link_up = link_info->link_up;
6707 u16 diff;
6708
6709 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
6710
6711 mutex_lock(&bp->hwrm_cmd_lock);
6712 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6713 if (rc) {
6714 mutex_unlock(&bp->hwrm_cmd_lock);
6715 return rc;
6716 }
6717
6718 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
6719 link_info->phy_link_status = resp->link;
6720 link_info->duplex = resp->duplex_cfg;
6721 if (bp->hwrm_spec_code >= 0x10800)
6722 link_info->duplex = resp->duplex_state;
6723 link_info->pause = resp->pause;
6724 link_info->auto_mode = resp->auto_mode;
6725 link_info->auto_pause_setting = resp->auto_pause;
6726 link_info->lp_pause = resp->link_partner_adv_pause;
6727 link_info->force_pause_setting = resp->force_pause;
6728 link_info->duplex_setting = resp->duplex_cfg;
6729 if (link_info->phy_link_status == BNXT_LINK_LINK)
6730 link_info->link_speed = le16_to_cpu(resp->link_speed);
6731 else
6732 link_info->link_speed = 0;
6733 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
6734 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
6735 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
6736 link_info->lp_auto_link_speeds =
6737 le16_to_cpu(resp->link_partner_adv_speeds);
6738 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
6739 link_info->phy_ver[0] = resp->phy_maj;
6740 link_info->phy_ver[1] = resp->phy_min;
6741 link_info->phy_ver[2] = resp->phy_bld;
6742 link_info->media_type = resp->media_type;
6743 link_info->phy_type = resp->phy_type;
6744 link_info->transceiver = resp->xcvr_pkg_type;
6745 link_info->phy_addr = resp->eee_config_phy_addr &
6746 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
6747 link_info->module_status = resp->module_status;
6748
6749 if (bp->flags & BNXT_FLAG_EEE_CAP) {
6750 struct ethtool_eee *eee = &bp->eee;
6751 u16 fw_speeds;
6752
6753 eee->eee_active = 0;
6754 if (resp->eee_config_phy_addr &
6755 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
6756 eee->eee_active = 1;
6757 fw_speeds = le16_to_cpu(
6758 resp->link_partner_adv_eee_link_speed_mask);
6759 eee->lp_advertised =
6760 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6761 }
6762
6763 /* Pull initial EEE config */
6764 if (!chng_link_state) {
6765 if (resp->eee_config_phy_addr &
6766 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
6767 eee->eee_enabled = 1;
6768
6769 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
6770 eee->advertised =
6771 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6772
6773 if (resp->eee_config_phy_addr &
6774 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
6775 __le32 tmr;
6776
6777 eee->tx_lpi_enabled = 1;
6778 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
6779 eee->tx_lpi_timer = le32_to_cpu(tmr) &
6780 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
6781 }
6782 }
6783 }
6784
6785 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
6786 if (bp->hwrm_spec_code >= 0x10504)
6787 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
6788
6789 /* TODO: need to add more logic to report VF link */
6790 if (chng_link_state) {
6791 if (link_info->phy_link_status == BNXT_LINK_LINK)
6792 link_info->link_up = 1;
6793 else
6794 link_info->link_up = 0;
6795 if (link_up != link_info->link_up)
6796 bnxt_report_link(bp);
6797 } else {
6798 /* alwasy link down if not require to update link state */
6799 link_info->link_up = 0;
6800 }
6801 mutex_unlock(&bp->hwrm_cmd_lock);
6802
6803 if (!BNXT_SINGLE_PF(bp))
6804 return 0;
6805
6806 diff = link_info->support_auto_speeds ^ link_info->advertising;
6807 if ((link_info->support_auto_speeds | diff) !=
6808 link_info->support_auto_speeds) {
6809 /* An advertised speed is no longer supported, so we need to
6810 * update the advertisement settings. Caller holds RTNL
6811 * so we can modify link settings.
6812 */
6813 link_info->advertising = link_info->support_auto_speeds;
6814 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
6815 bnxt_hwrm_set_link_setting(bp, true, false);
6816 }
6817 return 0;
6818 }
6819
6820 static void bnxt_get_port_module_status(struct bnxt *bp)
6821 {
6822 struct bnxt_link_info *link_info = &bp->link_info;
6823 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
6824 u8 module_status;
6825
6826 if (bnxt_update_link(bp, true))
6827 return;
6828
6829 module_status = link_info->module_status;
6830 switch (module_status) {
6831 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
6832 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
6833 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
6834 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
6835 bp->pf.port_id);
6836 if (bp->hwrm_spec_code >= 0x10201) {
6837 netdev_warn(bp->dev, "Module part number %s\n",
6838 resp->phy_vendor_partnumber);
6839 }
6840 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
6841 netdev_warn(bp->dev, "TX is disabled\n");
6842 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
6843 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
6844 }
6845 }
6846
6847 static void
6848 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
6849 {
6850 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
6851 if (bp->hwrm_spec_code >= 0x10201)
6852 req->auto_pause =
6853 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
6854 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6855 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
6856 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6857 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
6858 req->enables |=
6859 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6860 } else {
6861 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6862 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
6863 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6864 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
6865 req->enables |=
6866 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
6867 if (bp->hwrm_spec_code >= 0x10201) {
6868 req->auto_pause = req->force_pause;
6869 req->enables |= cpu_to_le32(
6870 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6871 }
6872 }
6873 }
6874
6875 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
6876 struct hwrm_port_phy_cfg_input *req)
6877 {
6878 u8 autoneg = bp->link_info.autoneg;
6879 u16 fw_link_speed = bp->link_info.req_link_speed;
6880 u16 advertising = bp->link_info.advertising;
6881
6882 if (autoneg & BNXT_AUTONEG_SPEED) {
6883 req->auto_mode |=
6884 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
6885
6886 req->enables |= cpu_to_le32(
6887 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
6888 req->auto_link_speed_mask = cpu_to_le16(advertising);
6889
6890 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
6891 req->flags |=
6892 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
6893 } else {
6894 req->force_link_speed = cpu_to_le16(fw_link_speed);
6895 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
6896 }
6897
6898 /* tell chimp that the setting takes effect immediately */
6899 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
6900 }
6901
6902 int bnxt_hwrm_set_pause(struct bnxt *bp)
6903 {
6904 struct hwrm_port_phy_cfg_input req = {0};
6905 int rc;
6906
6907 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6908 bnxt_hwrm_set_pause_common(bp, &req);
6909
6910 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
6911 bp->link_info.force_link_chng)
6912 bnxt_hwrm_set_link_common(bp, &req);
6913
6914 mutex_lock(&bp->hwrm_cmd_lock);
6915 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6916 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
6917 /* since changing of pause setting doesn't trigger any link
6918 * change event, the driver needs to update the current pause
6919 * result upon successfully return of the phy_cfg command
6920 */
6921 bp->link_info.pause =
6922 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
6923 bp->link_info.auto_pause_setting = 0;
6924 if (!bp->link_info.force_link_chng)
6925 bnxt_report_link(bp);
6926 }
6927 bp->link_info.force_link_chng = false;
6928 mutex_unlock(&bp->hwrm_cmd_lock);
6929 return rc;
6930 }
6931
6932 static void bnxt_hwrm_set_eee(struct bnxt *bp,
6933 struct hwrm_port_phy_cfg_input *req)
6934 {
6935 struct ethtool_eee *eee = &bp->eee;
6936
6937 if (eee->eee_enabled) {
6938 u16 eee_speeds;
6939 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
6940
6941 if (eee->tx_lpi_enabled)
6942 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
6943 else
6944 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
6945
6946 req->flags |= cpu_to_le32(flags);
6947 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
6948 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
6949 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
6950 } else {
6951 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
6952 }
6953 }
6954
6955 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
6956 {
6957 struct hwrm_port_phy_cfg_input req = {0};
6958
6959 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6960 if (set_pause)
6961 bnxt_hwrm_set_pause_common(bp, &req);
6962
6963 bnxt_hwrm_set_link_common(bp, &req);
6964
6965 if (set_eee)
6966 bnxt_hwrm_set_eee(bp, &req);
6967 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6968 }
6969
6970 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6971 {
6972 struct hwrm_port_phy_cfg_input req = {0};
6973
6974 if (!BNXT_SINGLE_PF(bp))
6975 return 0;
6976
6977 if (pci_num_vf(bp->pdev))
6978 return 0;
6979
6980 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6981 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
6982 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6983 }
6984
6985 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
6986 {
6987 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
6988 struct hwrm_func_drv_if_change_input req = {0};
6989 bool resc_reinit = false;
6990 int rc;
6991
6992 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
6993 return 0;
6994
6995 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
6996 if (up)
6997 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
6998 mutex_lock(&bp->hwrm_cmd_lock);
6999 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7000 if (!rc && (resp->flags &
7001 cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
7002 resc_reinit = true;
7003 mutex_unlock(&bp->hwrm_cmd_lock);
7004
7005 if (up && resc_reinit && BNXT_NEW_RM(bp)) {
7006 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7007
7008 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
7009 hw_resc->resv_cp_rings = 0;
7010 hw_resc->resv_tx_rings = 0;
7011 hw_resc->resv_rx_rings = 0;
7012 hw_resc->resv_hw_ring_grps = 0;
7013 hw_resc->resv_vnics = 0;
7014 bp->tx_nr_rings = 0;
7015 bp->rx_nr_rings = 0;
7016 }
7017 return rc;
7018 }
7019
7020 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
7021 {
7022 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7023 struct hwrm_port_led_qcaps_input req = {0};
7024 struct bnxt_pf_info *pf = &bp->pf;
7025 int rc;
7026
7027 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
7028 return 0;
7029
7030 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
7031 req.port_id = cpu_to_le16(pf->port_id);
7032 mutex_lock(&bp->hwrm_cmd_lock);
7033 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7034 if (rc) {
7035 mutex_unlock(&bp->hwrm_cmd_lock);
7036 return rc;
7037 }
7038 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
7039 int i;
7040
7041 bp->num_leds = resp->num_leds;
7042 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
7043 bp->num_leds);
7044 for (i = 0; i < bp->num_leds; i++) {
7045 struct bnxt_led_info *led = &bp->leds[i];
7046 __le16 caps = led->led_state_caps;
7047
7048 if (!led->led_group_id ||
7049 !BNXT_LED_ALT_BLINK_CAP(caps)) {
7050 bp->num_leds = 0;
7051 break;
7052 }
7053 }
7054 }
7055 mutex_unlock(&bp->hwrm_cmd_lock);
7056 return 0;
7057 }
7058
7059 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
7060 {
7061 struct hwrm_wol_filter_alloc_input req = {0};
7062 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
7063 int rc;
7064
7065 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
7066 req.port_id = cpu_to_le16(bp->pf.port_id);
7067 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
7068 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
7069 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
7070 mutex_lock(&bp->hwrm_cmd_lock);
7071 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7072 if (!rc)
7073 bp->wol_filter_id = resp->wol_filter_id;
7074 mutex_unlock(&bp->hwrm_cmd_lock);
7075 return rc;
7076 }
7077
7078 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
7079 {
7080 struct hwrm_wol_filter_free_input req = {0};
7081 int rc;
7082
7083 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
7084 req.port_id = cpu_to_le16(bp->pf.port_id);
7085 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
7086 req.wol_filter_id = bp->wol_filter_id;
7087 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7088 return rc;
7089 }
7090
7091 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
7092 {
7093 struct hwrm_wol_filter_qcfg_input req = {0};
7094 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7095 u16 next_handle = 0;
7096 int rc;
7097
7098 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
7099 req.port_id = cpu_to_le16(bp->pf.port_id);
7100 req.handle = cpu_to_le16(handle);
7101 mutex_lock(&bp->hwrm_cmd_lock);
7102 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7103 if (!rc) {
7104 next_handle = le16_to_cpu(resp->next_handle);
7105 if (next_handle != 0) {
7106 if (resp->wol_type ==
7107 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
7108 bp->wol = 1;
7109 bp->wol_filter_id = resp->wol_filter_id;
7110 }
7111 }
7112 }
7113 mutex_unlock(&bp->hwrm_cmd_lock);
7114 return next_handle;
7115 }
7116
7117 static void bnxt_get_wol_settings(struct bnxt *bp)
7118 {
7119 u16 handle = 0;
7120
7121 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
7122 return;
7123
7124 do {
7125 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
7126 } while (handle && handle != 0xffff);
7127 }
7128
7129 #ifdef CONFIG_BNXT_HWMON
7130 static ssize_t bnxt_show_temp(struct device *dev,
7131 struct device_attribute *devattr, char *buf)
7132 {
7133 struct hwrm_temp_monitor_query_input req = {0};
7134 struct hwrm_temp_monitor_query_output *resp;
7135 struct bnxt *bp = dev_get_drvdata(dev);
7136 u32 temp = 0;
7137
7138 resp = bp->hwrm_cmd_resp_addr;
7139 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
7140 mutex_lock(&bp->hwrm_cmd_lock);
7141 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
7142 temp = resp->temp * 1000; /* display millidegree */
7143 mutex_unlock(&bp->hwrm_cmd_lock);
7144
7145 return sprintf(buf, "%u\n", temp);
7146 }
7147 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
7148
7149 static struct attribute *bnxt_attrs[] = {
7150 &sensor_dev_attr_temp1_input.dev_attr.attr,
7151 NULL
7152 };
7153 ATTRIBUTE_GROUPS(bnxt);
7154
7155 static void bnxt_hwmon_close(struct bnxt *bp)
7156 {
7157 if (bp->hwmon_dev) {
7158 hwmon_device_unregister(bp->hwmon_dev);
7159 bp->hwmon_dev = NULL;
7160 }
7161 }
7162
7163 static void bnxt_hwmon_open(struct bnxt *bp)
7164 {
7165 struct pci_dev *pdev = bp->pdev;
7166
7167 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
7168 DRV_MODULE_NAME, bp,
7169 bnxt_groups);
7170 if (IS_ERR(bp->hwmon_dev)) {
7171 bp->hwmon_dev = NULL;
7172 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
7173 }
7174 }
7175 #else
7176 static void bnxt_hwmon_close(struct bnxt *bp)
7177 {
7178 }
7179
7180 static void bnxt_hwmon_open(struct bnxt *bp)
7181 {
7182 }
7183 #endif
7184
7185 static bool bnxt_eee_config_ok(struct bnxt *bp)
7186 {
7187 struct ethtool_eee *eee = &bp->eee;
7188 struct bnxt_link_info *link_info = &bp->link_info;
7189
7190 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
7191 return true;
7192
7193 if (eee->eee_enabled) {
7194 u32 advertising =
7195 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
7196
7197 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
7198 eee->eee_enabled = 0;
7199 return false;
7200 }
7201 if (eee->advertised & ~advertising) {
7202 eee->advertised = advertising & eee->supported;
7203 return false;
7204 }
7205 }
7206 return true;
7207 }
7208
7209 static int bnxt_update_phy_setting(struct bnxt *bp)
7210 {
7211 int rc;
7212 bool update_link = false;
7213 bool update_pause = false;
7214 bool update_eee = false;
7215 struct bnxt_link_info *link_info = &bp->link_info;
7216
7217 rc = bnxt_update_link(bp, true);
7218 if (rc) {
7219 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
7220 rc);
7221 return rc;
7222 }
7223 if (!BNXT_SINGLE_PF(bp))
7224 return 0;
7225
7226 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
7227 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
7228 link_info->req_flow_ctrl)
7229 update_pause = true;
7230 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
7231 link_info->force_pause_setting != link_info->req_flow_ctrl)
7232 update_pause = true;
7233 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
7234 if (BNXT_AUTO_MODE(link_info->auto_mode))
7235 update_link = true;
7236 if (link_info->req_link_speed != link_info->force_link_speed)
7237 update_link = true;
7238 if (link_info->req_duplex != link_info->duplex_setting)
7239 update_link = true;
7240 } else {
7241 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
7242 update_link = true;
7243 if (link_info->advertising != link_info->auto_link_speeds)
7244 update_link = true;
7245 }
7246
7247 /* The last close may have shutdown the link, so need to call
7248 * PHY_CFG to bring it back up.
7249 */
7250 if (!netif_carrier_ok(bp->dev))
7251 update_link = true;
7252
7253 if (!bnxt_eee_config_ok(bp))
7254 update_eee = true;
7255
7256 if (update_link)
7257 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
7258 else if (update_pause)
7259 rc = bnxt_hwrm_set_pause(bp);
7260 if (rc) {
7261 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
7262 rc);
7263 return rc;
7264 }
7265
7266 return rc;
7267 }
7268
7269 /* Common routine to pre-map certain register block to different GRC window.
7270 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
7271 * in PF and 3 windows in VF that can be customized to map in different
7272 * register blocks.
7273 */
7274 static void bnxt_preset_reg_win(struct bnxt *bp)
7275 {
7276 if (BNXT_PF(bp)) {
7277 /* CAG registers map to GRC window #4 */
7278 writel(BNXT_CAG_REG_BASE,
7279 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
7280 }
7281 }
7282
7283 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
7284
7285 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
7286 {
7287 int rc = 0;
7288
7289 bnxt_preset_reg_win(bp);
7290 netif_carrier_off(bp->dev);
7291 if (irq_re_init) {
7292 /* Reserve rings now if none were reserved at driver probe. */
7293 rc = bnxt_init_dflt_ring_mode(bp);
7294 if (rc) {
7295 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
7296 return rc;
7297 }
7298 rc = bnxt_reserve_rings(bp);
7299 if (rc)
7300 return rc;
7301 }
7302 if ((bp->flags & BNXT_FLAG_RFS) &&
7303 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
7304 /* disable RFS if falling back to INTA */
7305 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
7306 bp->flags &= ~BNXT_FLAG_RFS;
7307 }
7308
7309 rc = bnxt_alloc_mem(bp, irq_re_init);
7310 if (rc) {
7311 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
7312 goto open_err_free_mem;
7313 }
7314
7315 if (irq_re_init) {
7316 bnxt_init_napi(bp);
7317 rc = bnxt_request_irq(bp);
7318 if (rc) {
7319 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
7320 goto open_err_irq;
7321 }
7322 }
7323
7324 bnxt_enable_napi(bp);
7325 bnxt_debug_dev_init(bp);
7326
7327 rc = bnxt_init_nic(bp, irq_re_init);
7328 if (rc) {
7329 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
7330 goto open_err;
7331 }
7332
7333 if (link_re_init) {
7334 mutex_lock(&bp->link_lock);
7335 rc = bnxt_update_phy_setting(bp);
7336 mutex_unlock(&bp->link_lock);
7337 if (rc) {
7338 netdev_warn(bp->dev, "failed to update phy settings\n");
7339 if (BNXT_SINGLE_PF(bp)) {
7340 bp->link_info.phy_retry = true;
7341 bp->link_info.phy_retry_expires =
7342 jiffies + 5 * HZ;
7343 }
7344 }
7345 }
7346
7347 if (irq_re_init)
7348 udp_tunnel_get_rx_info(bp->dev);
7349
7350 set_bit(BNXT_STATE_OPEN, &bp->state);
7351 bnxt_enable_int(bp);
7352 /* Enable TX queues */
7353 bnxt_tx_enable(bp);
7354 mod_timer(&bp->timer, jiffies + bp->current_interval);
7355 /* Poll link status and check for SFP+ module status */
7356 bnxt_get_port_module_status(bp);
7357
7358 /* VF-reps may need to be re-opened after the PF is re-opened */
7359 if (BNXT_PF(bp))
7360 bnxt_vf_reps_open(bp);
7361 return 0;
7362
7363 open_err:
7364 bnxt_debug_dev_exit(bp);
7365 bnxt_disable_napi(bp);
7366
7367 open_err_irq:
7368 bnxt_del_napi(bp);
7369
7370 open_err_free_mem:
7371 bnxt_free_skbs(bp);
7372 bnxt_free_irq(bp);
7373 bnxt_free_mem(bp, true);
7374 return rc;
7375 }
7376
7377 /* rtnl_lock held */
7378 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
7379 {
7380 int rc = 0;
7381
7382 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
7383 if (rc) {
7384 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
7385 dev_close(bp->dev);
7386 }
7387 return rc;
7388 }
7389
7390 /* rtnl_lock held, open the NIC half way by allocating all resources, but
7391 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
7392 * self tests.
7393 */
7394 int bnxt_half_open_nic(struct bnxt *bp)
7395 {
7396 int rc = 0;
7397
7398 rc = bnxt_alloc_mem(bp, false);
7399 if (rc) {
7400 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
7401 goto half_open_err;
7402 }
7403 rc = bnxt_init_nic(bp, false);
7404 if (rc) {
7405 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
7406 goto half_open_err;
7407 }
7408 return 0;
7409
7410 half_open_err:
7411 bnxt_free_skbs(bp);
7412 bnxt_free_mem(bp, false);
7413 dev_close(bp->dev);
7414 return rc;
7415 }
7416
7417 /* rtnl_lock held, this call can only be made after a previous successful
7418 * call to bnxt_half_open_nic().
7419 */
7420 void bnxt_half_close_nic(struct bnxt *bp)
7421 {
7422 bnxt_hwrm_resource_free(bp, false, false);
7423 bnxt_free_skbs(bp);
7424 bnxt_free_mem(bp, false);
7425 }
7426
7427 static int bnxt_open(struct net_device *dev)
7428 {
7429 struct bnxt *bp = netdev_priv(dev);
7430 int rc;
7431
7432 bnxt_hwrm_if_change(bp, true);
7433 rc = __bnxt_open_nic(bp, true, true);
7434 if (rc)
7435 bnxt_hwrm_if_change(bp, false);
7436
7437 bnxt_hwmon_open(bp);
7438
7439 return rc;
7440 }
7441
7442 static bool bnxt_drv_busy(struct bnxt *bp)
7443 {
7444 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
7445 test_bit(BNXT_STATE_READ_STATS, &bp->state));
7446 }
7447
7448 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
7449 bool link_re_init)
7450 {
7451 /* Close the VF-reps before closing PF */
7452 if (BNXT_PF(bp))
7453 bnxt_vf_reps_close(bp);
7454
7455 /* Change device state to avoid TX queue wake up's */
7456 bnxt_tx_disable(bp);
7457
7458 clear_bit(BNXT_STATE_OPEN, &bp->state);
7459 smp_mb__after_atomic();
7460 while (bnxt_drv_busy(bp))
7461 msleep(20);
7462
7463 /* Flush rings and and disable interrupts */
7464 bnxt_shutdown_nic(bp, irq_re_init);
7465
7466 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
7467
7468 bnxt_debug_dev_exit(bp);
7469 bnxt_disable_napi(bp);
7470 del_timer_sync(&bp->timer);
7471 bnxt_free_skbs(bp);
7472
7473 if (irq_re_init) {
7474 bnxt_free_irq(bp);
7475 bnxt_del_napi(bp);
7476 }
7477 bnxt_free_mem(bp, irq_re_init);
7478 }
7479
7480 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
7481 {
7482 int rc = 0;
7483
7484 #ifdef CONFIG_BNXT_SRIOV
7485 if (bp->sriov_cfg) {
7486 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
7487 !bp->sriov_cfg,
7488 BNXT_SRIOV_CFG_WAIT_TMO);
7489 if (rc)
7490 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
7491 }
7492 #endif
7493 __bnxt_close_nic(bp, irq_re_init, link_re_init);
7494 return rc;
7495 }
7496
7497 static int bnxt_close(struct net_device *dev)
7498 {
7499 struct bnxt *bp = netdev_priv(dev);
7500
7501 bnxt_hwmon_close(bp);
7502 bnxt_close_nic(bp, true, true);
7503 bnxt_hwrm_shutdown_link(bp);
7504 bnxt_hwrm_if_change(bp, false);
7505 return 0;
7506 }
7507
7508 /* rtnl_lock held */
7509 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7510 {
7511 switch (cmd) {
7512 case SIOCGMIIPHY:
7513 /* fallthru */
7514 case SIOCGMIIREG: {
7515 if (!netif_running(dev))
7516 return -EAGAIN;
7517
7518 return 0;
7519 }
7520
7521 case SIOCSMIIREG:
7522 if (!netif_running(dev))
7523 return -EAGAIN;
7524
7525 return 0;
7526
7527 default:
7528 /* do nothing */
7529 break;
7530 }
7531 return -EOPNOTSUPP;
7532 }
7533
7534 static void
7535 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7536 {
7537 u32 i;
7538 struct bnxt *bp = netdev_priv(dev);
7539
7540 set_bit(BNXT_STATE_READ_STATS, &bp->state);
7541 /* Make sure bnxt_close_nic() sees that we are reading stats before
7542 * we check the BNXT_STATE_OPEN flag.
7543 */
7544 smp_mb__after_atomic();
7545 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7546 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
7547 return;
7548 }
7549
7550 /* TODO check if we need to synchronize with bnxt_close path */
7551 for (i = 0; i < bp->cp_nr_rings; i++) {
7552 struct bnxt_napi *bnapi = bp->bnapi[i];
7553 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7554 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
7555
7556 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
7557 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
7558 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
7559
7560 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
7561 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
7562 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
7563
7564 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
7565 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
7566 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
7567
7568 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
7569 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
7570 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
7571
7572 stats->rx_missed_errors +=
7573 le64_to_cpu(hw_stats->rx_discard_pkts);
7574
7575 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
7576
7577 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
7578 }
7579
7580 if (bp->flags & BNXT_FLAG_PORT_STATS) {
7581 struct rx_port_stats *rx = bp->hw_rx_port_stats;
7582 struct tx_port_stats *tx = bp->hw_tx_port_stats;
7583
7584 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
7585 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
7586 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
7587 le64_to_cpu(rx->rx_ovrsz_frames) +
7588 le64_to_cpu(rx->rx_runt_frames);
7589 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
7590 le64_to_cpu(rx->rx_jbr_frames);
7591 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
7592 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
7593 stats->tx_errors = le64_to_cpu(tx->tx_err);
7594 }
7595 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
7596 }
7597
7598 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
7599 {
7600 struct net_device *dev = bp->dev;
7601 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7602 struct netdev_hw_addr *ha;
7603 u8 *haddr;
7604 int mc_count = 0;
7605 bool update = false;
7606 int off = 0;
7607
7608 netdev_for_each_mc_addr(ha, dev) {
7609 if (mc_count >= BNXT_MAX_MC_ADDRS) {
7610 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7611 vnic->mc_list_count = 0;
7612 return false;
7613 }
7614 haddr = ha->addr;
7615 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
7616 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
7617 update = true;
7618 }
7619 off += ETH_ALEN;
7620 mc_count++;
7621 }
7622 if (mc_count)
7623 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
7624
7625 if (mc_count != vnic->mc_list_count) {
7626 vnic->mc_list_count = mc_count;
7627 update = true;
7628 }
7629 return update;
7630 }
7631
7632 static bool bnxt_uc_list_updated(struct bnxt *bp)
7633 {
7634 struct net_device *dev = bp->dev;
7635 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7636 struct netdev_hw_addr *ha;
7637 int off = 0;
7638
7639 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
7640 return true;
7641
7642 netdev_for_each_uc_addr(ha, dev) {
7643 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
7644 return true;
7645
7646 off += ETH_ALEN;
7647 }
7648 return false;
7649 }
7650
7651 static void bnxt_set_rx_mode(struct net_device *dev)
7652 {
7653 struct bnxt *bp = netdev_priv(dev);
7654 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7655 u32 mask = vnic->rx_mask;
7656 bool mc_update = false;
7657 bool uc_update;
7658
7659 if (!netif_running(dev))
7660 return;
7661
7662 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
7663 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
7664 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
7665 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
7666
7667 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7668 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7669
7670 uc_update = bnxt_uc_list_updated(bp);
7671
7672 if (dev->flags & IFF_BROADCAST)
7673 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7674 if (dev->flags & IFF_ALLMULTI) {
7675 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7676 vnic->mc_list_count = 0;
7677 } else {
7678 mc_update = bnxt_mc_list_updated(bp, &mask);
7679 }
7680
7681 if (mask != vnic->rx_mask || uc_update || mc_update) {
7682 vnic->rx_mask = mask;
7683
7684 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
7685 bnxt_queue_sp_work(bp);
7686 }
7687 }
7688
7689 static int bnxt_cfg_rx_mode(struct bnxt *bp)
7690 {
7691 struct net_device *dev = bp->dev;
7692 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7693 struct netdev_hw_addr *ha;
7694 int i, off = 0, rc;
7695 bool uc_update;
7696
7697 netif_addr_lock_bh(dev);
7698 uc_update = bnxt_uc_list_updated(bp);
7699 netif_addr_unlock_bh(dev);
7700
7701 if (!uc_update)
7702 goto skip_uc;
7703
7704 mutex_lock(&bp->hwrm_cmd_lock);
7705 for (i = 1; i < vnic->uc_filter_count; i++) {
7706 struct hwrm_cfa_l2_filter_free_input req = {0};
7707
7708 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
7709 -1);
7710
7711 req.l2_filter_id = vnic->fw_l2_filter_id[i];
7712
7713 rc = _hwrm_send_message(bp, &req, sizeof(req),
7714 HWRM_CMD_TIMEOUT);
7715 }
7716 mutex_unlock(&bp->hwrm_cmd_lock);
7717
7718 vnic->uc_filter_count = 1;
7719
7720 netif_addr_lock_bh(dev);
7721 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
7722 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7723 } else {
7724 netdev_for_each_uc_addr(ha, dev) {
7725 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
7726 off += ETH_ALEN;
7727 vnic->uc_filter_count++;
7728 }
7729 }
7730 netif_addr_unlock_bh(dev);
7731
7732 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
7733 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
7734 if (rc) {
7735 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
7736 rc);
7737 vnic->uc_filter_count = i;
7738 return rc;
7739 }
7740 }
7741
7742 skip_uc:
7743 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
7744 if (rc)
7745 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
7746 rc);
7747
7748 return rc;
7749 }
7750
7751 static bool bnxt_can_reserve_rings(struct bnxt *bp)
7752 {
7753 #ifdef CONFIG_BNXT_SRIOV
7754 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
7755 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7756
7757 /* No minimum rings were provisioned by the PF. Don't
7758 * reserve rings by default when device is down.
7759 */
7760 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
7761 return true;
7762
7763 if (!netif_running(bp->dev))
7764 return false;
7765 }
7766 #endif
7767 return true;
7768 }
7769
7770 /* If the chip and firmware supports RFS */
7771 static bool bnxt_rfs_supported(struct bnxt *bp)
7772 {
7773 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
7774 return true;
7775 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7776 return true;
7777 return false;
7778 }
7779
7780 /* If runtime conditions support RFS */
7781 static bool bnxt_rfs_capable(struct bnxt *bp)
7782 {
7783 #ifdef CONFIG_RFS_ACCEL
7784 int vnics, max_vnics, max_rss_ctxs;
7785
7786 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
7787 return false;
7788
7789 vnics = 1 + bp->rx_nr_rings;
7790 max_vnics = bnxt_get_max_func_vnics(bp);
7791 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
7792
7793 /* RSS contexts not a limiting factor */
7794 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7795 max_rss_ctxs = max_vnics;
7796 if (vnics > max_vnics || vnics > max_rss_ctxs) {
7797 if (bp->rx_nr_rings > 1)
7798 netdev_warn(bp->dev,
7799 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
7800 min(max_rss_ctxs - 1, max_vnics - 1));
7801 return false;
7802 }
7803
7804 if (!BNXT_NEW_RM(bp))
7805 return true;
7806
7807 if (vnics == bp->hw_resc.resv_vnics)
7808 return true;
7809
7810 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, vnics);
7811 if (vnics <= bp->hw_resc.resv_vnics)
7812 return true;
7813
7814 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
7815 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 1);
7816 return false;
7817 #else
7818 return false;
7819 #endif
7820 }
7821
7822 static netdev_features_t bnxt_fix_features(struct net_device *dev,
7823 netdev_features_t features)
7824 {
7825 struct bnxt *bp = netdev_priv(dev);
7826
7827 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
7828 features &= ~NETIF_F_NTUPLE;
7829
7830 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7831 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
7832
7833 if (!(features & NETIF_F_GRO))
7834 features &= ~NETIF_F_GRO_HW;
7835
7836 if (features & NETIF_F_GRO_HW)
7837 features &= ~NETIF_F_LRO;
7838
7839 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
7840 * turned on or off together.
7841 */
7842 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
7843 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
7844 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
7845 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7846 NETIF_F_HW_VLAN_STAG_RX);
7847 else
7848 features |= NETIF_F_HW_VLAN_CTAG_RX |
7849 NETIF_F_HW_VLAN_STAG_RX;
7850 }
7851 #ifdef CONFIG_BNXT_SRIOV
7852 if (BNXT_VF(bp)) {
7853 if (bp->vf.vlan) {
7854 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7855 NETIF_F_HW_VLAN_STAG_RX);
7856 }
7857 }
7858 #endif
7859 return features;
7860 }
7861
7862 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
7863 {
7864 struct bnxt *bp = netdev_priv(dev);
7865 u32 flags = bp->flags;
7866 u32 changes;
7867 int rc = 0;
7868 bool re_init = false;
7869 bool update_tpa = false;
7870
7871 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
7872 if (features & NETIF_F_GRO_HW)
7873 flags |= BNXT_FLAG_GRO;
7874 else if (features & NETIF_F_LRO)
7875 flags |= BNXT_FLAG_LRO;
7876
7877 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7878 flags &= ~BNXT_FLAG_TPA;
7879
7880 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7881 flags |= BNXT_FLAG_STRIP_VLAN;
7882
7883 if (features & NETIF_F_NTUPLE)
7884 flags |= BNXT_FLAG_RFS;
7885
7886 changes = flags ^ bp->flags;
7887 if (changes & BNXT_FLAG_TPA) {
7888 update_tpa = true;
7889 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
7890 (flags & BNXT_FLAG_TPA) == 0)
7891 re_init = true;
7892 }
7893
7894 if (changes & ~BNXT_FLAG_TPA)
7895 re_init = true;
7896
7897 if (flags != bp->flags) {
7898 u32 old_flags = bp->flags;
7899
7900 bp->flags = flags;
7901
7902 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7903 if (update_tpa)
7904 bnxt_set_ring_params(bp);
7905 return rc;
7906 }
7907
7908 if (re_init) {
7909 bnxt_close_nic(bp, false, false);
7910 if (update_tpa)
7911 bnxt_set_ring_params(bp);
7912
7913 return bnxt_open_nic(bp, false, false);
7914 }
7915 if (update_tpa) {
7916 rc = bnxt_set_tpa(bp,
7917 (flags & BNXT_FLAG_TPA) ?
7918 true : false);
7919 if (rc)
7920 bp->flags = old_flags;
7921 }
7922 }
7923 return rc;
7924 }
7925
7926 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
7927 {
7928 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
7929 int i = bnapi->index;
7930
7931 if (!txr)
7932 return;
7933
7934 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
7935 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
7936 txr->tx_cons);
7937 }
7938
7939 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
7940 {
7941 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
7942 int i = bnapi->index;
7943
7944 if (!rxr)
7945 return;
7946
7947 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
7948 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
7949 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
7950 rxr->rx_sw_agg_prod);
7951 }
7952
7953 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
7954 {
7955 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7956 int i = bnapi->index;
7957
7958 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
7959 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
7960 }
7961
7962 static void bnxt_dbg_dump_states(struct bnxt *bp)
7963 {
7964 int i;
7965 struct bnxt_napi *bnapi;
7966
7967 for (i = 0; i < bp->cp_nr_rings; i++) {
7968 bnapi = bp->bnapi[i];
7969 if (netif_msg_drv(bp)) {
7970 bnxt_dump_tx_sw_state(bnapi);
7971 bnxt_dump_rx_sw_state(bnapi);
7972 bnxt_dump_cp_sw_state(bnapi);
7973 }
7974 }
7975 }
7976
7977 static void bnxt_reset_task(struct bnxt *bp, bool silent)
7978 {
7979 if (!silent)
7980 bnxt_dbg_dump_states(bp);
7981 if (netif_running(bp->dev)) {
7982 int rc;
7983
7984 if (!silent)
7985 bnxt_ulp_stop(bp);
7986 bnxt_close_nic(bp, false, false);
7987 rc = bnxt_open_nic(bp, false, false);
7988 if (!silent && !rc)
7989 bnxt_ulp_start(bp);
7990 }
7991 }
7992
7993 static void bnxt_tx_timeout(struct net_device *dev)
7994 {
7995 struct bnxt *bp = netdev_priv(dev);
7996
7997 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
7998 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
7999 bnxt_queue_sp_work(bp);
8000 }
8001
8002 static void bnxt_timer(struct timer_list *t)
8003 {
8004 struct bnxt *bp = from_timer(bp, t, timer);
8005 struct net_device *dev = bp->dev;
8006
8007 if (!netif_running(dev))
8008 return;
8009
8010 if (atomic_read(&bp->intr_sem) != 0)
8011 goto bnxt_restart_timer;
8012
8013 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
8014 bp->stats_coal_ticks) {
8015 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
8016 bnxt_queue_sp_work(bp);
8017 }
8018
8019 if (bnxt_tc_flower_enabled(bp)) {
8020 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
8021 bnxt_queue_sp_work(bp);
8022 }
8023
8024 if (bp->link_info.phy_retry) {
8025 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
8026 bp->link_info.phy_retry = 0;
8027 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
8028 } else {
8029 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
8030 bnxt_queue_sp_work(bp);
8031 }
8032 }
8033 bnxt_restart_timer:
8034 mod_timer(&bp->timer, jiffies + bp->current_interval);
8035 }
8036
8037 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
8038 {
8039 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
8040 * set. If the device is being closed, bnxt_close() may be holding
8041 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
8042 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
8043 */
8044 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
8045 rtnl_lock();
8046 }
8047
8048 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
8049 {
8050 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
8051 rtnl_unlock();
8052 }
8053
8054 /* Only called from bnxt_sp_task() */
8055 static void bnxt_reset(struct bnxt *bp, bool silent)
8056 {
8057 bnxt_rtnl_lock_sp(bp);
8058 if (test_bit(BNXT_STATE_OPEN, &bp->state))
8059 bnxt_reset_task(bp, silent);
8060 bnxt_rtnl_unlock_sp(bp);
8061 }
8062
8063 static void bnxt_cfg_ntp_filters(struct bnxt *);
8064
8065 static void bnxt_sp_task(struct work_struct *work)
8066 {
8067 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
8068
8069 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
8070 smp_mb__after_atomic();
8071 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
8072 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
8073 return;
8074 }
8075
8076 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
8077 bnxt_cfg_rx_mode(bp);
8078
8079 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
8080 bnxt_cfg_ntp_filters(bp);
8081 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
8082 bnxt_hwrm_exec_fwd_req(bp);
8083 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
8084 bnxt_hwrm_tunnel_dst_port_alloc(
8085 bp, bp->vxlan_port,
8086 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
8087 }
8088 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
8089 bnxt_hwrm_tunnel_dst_port_free(
8090 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
8091 }
8092 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
8093 bnxt_hwrm_tunnel_dst_port_alloc(
8094 bp, bp->nge_port,
8095 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
8096 }
8097 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
8098 bnxt_hwrm_tunnel_dst_port_free(
8099 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
8100 }
8101 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
8102 bnxt_hwrm_port_qstats(bp);
8103 bnxt_hwrm_port_qstats_ext(bp);
8104 }
8105
8106 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
8107 int rc;
8108
8109 mutex_lock(&bp->link_lock);
8110 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
8111 &bp->sp_event))
8112 bnxt_hwrm_phy_qcaps(bp);
8113
8114 rc = bnxt_update_link(bp, true);
8115 mutex_unlock(&bp->link_lock);
8116 if (rc)
8117 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
8118 rc);
8119 }
8120 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
8121 int rc;
8122
8123 mutex_lock(&bp->link_lock);
8124 rc = bnxt_update_phy_setting(bp);
8125 mutex_unlock(&bp->link_lock);
8126 if (rc) {
8127 netdev_warn(bp->dev, "update phy settings retry failed\n");
8128 } else {
8129 bp->link_info.phy_retry = false;
8130 netdev_info(bp->dev, "update phy settings retry succeeded\n");
8131 }
8132 }
8133 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
8134 mutex_lock(&bp->link_lock);
8135 bnxt_get_port_module_status(bp);
8136 mutex_unlock(&bp->link_lock);
8137 }
8138
8139 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
8140 bnxt_tc_flow_stats_work(bp);
8141
8142 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
8143 * must be the last functions to be called before exiting.
8144 */
8145 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
8146 bnxt_reset(bp, false);
8147
8148 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
8149 bnxt_reset(bp, true);
8150
8151 smp_mb__before_atomic();
8152 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
8153 }
8154
8155 /* Under rtnl_lock */
8156 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
8157 int tx_xdp)
8158 {
8159 int max_rx, max_tx, tx_sets = 1;
8160 int tx_rings_needed;
8161 int rx_rings = rx;
8162 int cp, vnics, rc;
8163
8164 if (tcs)
8165 tx_sets = tcs;
8166
8167 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
8168 if (rc)
8169 return rc;
8170
8171 if (max_rx < rx)
8172 return -ENOMEM;
8173
8174 tx_rings_needed = tx * tx_sets + tx_xdp;
8175 if (max_tx < tx_rings_needed)
8176 return -ENOMEM;
8177
8178 vnics = 1;
8179 if (bp->flags & BNXT_FLAG_RFS)
8180 vnics += rx_rings;
8181
8182 if (bp->flags & BNXT_FLAG_AGG_RINGS)
8183 rx_rings <<= 1;
8184 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
8185 if (BNXT_NEW_RM(bp))
8186 cp += bnxt_get_ulp_msix_num(bp);
8187 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
8188 vnics);
8189 }
8190
8191 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
8192 {
8193 if (bp->bar2) {
8194 pci_iounmap(pdev, bp->bar2);
8195 bp->bar2 = NULL;
8196 }
8197
8198 if (bp->bar1) {
8199 pci_iounmap(pdev, bp->bar1);
8200 bp->bar1 = NULL;
8201 }
8202
8203 if (bp->bar0) {
8204 pci_iounmap(pdev, bp->bar0);
8205 bp->bar0 = NULL;
8206 }
8207 }
8208
8209 static void bnxt_cleanup_pci(struct bnxt *bp)
8210 {
8211 bnxt_unmap_bars(bp, bp->pdev);
8212 pci_release_regions(bp->pdev);
8213 pci_disable_device(bp->pdev);
8214 }
8215
8216 static void bnxt_init_dflt_coal(struct bnxt *bp)
8217 {
8218 struct bnxt_coal *coal;
8219
8220 /* Tick values in micro seconds.
8221 * 1 coal_buf x bufs_per_record = 1 completion record.
8222 */
8223 coal = &bp->rx_coal;
8224 coal->coal_ticks = 14;
8225 coal->coal_bufs = 30;
8226 coal->coal_ticks_irq = 1;
8227 coal->coal_bufs_irq = 2;
8228 coal->idle_thresh = 50;
8229 coal->bufs_per_record = 2;
8230 coal->budget = 64; /* NAPI budget */
8231
8232 coal = &bp->tx_coal;
8233 coal->coal_ticks = 28;
8234 coal->coal_bufs = 30;
8235 coal->coal_ticks_irq = 2;
8236 coal->coal_bufs_irq = 2;
8237 coal->bufs_per_record = 1;
8238
8239 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
8240 }
8241
8242 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
8243 {
8244 int rc;
8245 struct bnxt *bp = netdev_priv(dev);
8246
8247 SET_NETDEV_DEV(dev, &pdev->dev);
8248
8249 /* enable device (incl. PCI PM wakeup), and bus-mastering */
8250 rc = pci_enable_device(pdev);
8251 if (rc) {
8252 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
8253 goto init_err;
8254 }
8255
8256 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
8257 dev_err(&pdev->dev,
8258 "Cannot find PCI device base address, aborting\n");
8259 rc = -ENODEV;
8260 goto init_err_disable;
8261 }
8262
8263 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
8264 if (rc) {
8265 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
8266 goto init_err_disable;
8267 }
8268
8269 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
8270 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
8271 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
8272 goto init_err_disable;
8273 }
8274
8275 pci_set_master(pdev);
8276
8277 bp->dev = dev;
8278 bp->pdev = pdev;
8279
8280 bp->bar0 = pci_ioremap_bar(pdev, 0);
8281 if (!bp->bar0) {
8282 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
8283 rc = -ENOMEM;
8284 goto init_err_release;
8285 }
8286
8287 bp->bar1 = pci_ioremap_bar(pdev, 2);
8288 if (!bp->bar1) {
8289 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
8290 rc = -ENOMEM;
8291 goto init_err_release;
8292 }
8293
8294 bp->bar2 = pci_ioremap_bar(pdev, 4);
8295 if (!bp->bar2) {
8296 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
8297 rc = -ENOMEM;
8298 goto init_err_release;
8299 }
8300
8301 pci_enable_pcie_error_reporting(pdev);
8302
8303 INIT_WORK(&bp->sp_task, bnxt_sp_task);
8304
8305 spin_lock_init(&bp->ntp_fltr_lock);
8306
8307 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
8308 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
8309
8310 bnxt_init_dflt_coal(bp);
8311
8312 timer_setup(&bp->timer, bnxt_timer, 0);
8313 bp->current_interval = BNXT_TIMER_INTERVAL;
8314
8315 clear_bit(BNXT_STATE_OPEN, &bp->state);
8316 return 0;
8317
8318 init_err_release:
8319 bnxt_unmap_bars(bp, pdev);
8320 pci_release_regions(pdev);
8321
8322 init_err_disable:
8323 pci_disable_device(pdev);
8324
8325 init_err:
8326 return rc;
8327 }
8328
8329 /* rtnl_lock held */
8330 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
8331 {
8332 struct sockaddr *addr = p;
8333 struct bnxt *bp = netdev_priv(dev);
8334 int rc = 0;
8335
8336 if (!is_valid_ether_addr(addr->sa_data))
8337 return -EADDRNOTAVAIL;
8338
8339 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
8340 return 0;
8341
8342 rc = bnxt_approve_mac(bp, addr->sa_data, true);
8343 if (rc)
8344 return rc;
8345
8346 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8347 if (netif_running(dev)) {
8348 bnxt_close_nic(bp, false, false);
8349 rc = bnxt_open_nic(bp, false, false);
8350 }
8351
8352 return rc;
8353 }
8354
8355 /* rtnl_lock held */
8356 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
8357 {
8358 struct bnxt *bp = netdev_priv(dev);
8359
8360 if (netif_running(dev))
8361 bnxt_close_nic(bp, false, false);
8362
8363 dev->mtu = new_mtu;
8364 bnxt_set_ring_params(bp);
8365
8366 if (netif_running(dev))
8367 return bnxt_open_nic(bp, false, false);
8368
8369 return 0;
8370 }
8371
8372 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
8373 {
8374 struct bnxt *bp = netdev_priv(dev);
8375 bool sh = false;
8376 int rc;
8377
8378 if (tc > bp->max_tc) {
8379 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
8380 tc, bp->max_tc);
8381 return -EINVAL;
8382 }
8383
8384 if (netdev_get_num_tc(dev) == tc)
8385 return 0;
8386
8387 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
8388 sh = true;
8389
8390 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
8391 sh, tc, bp->tx_nr_rings_xdp);
8392 if (rc)
8393 return rc;
8394
8395 /* Needs to close the device and do hw resource re-allocations */
8396 if (netif_running(bp->dev))
8397 bnxt_close_nic(bp, true, false);
8398
8399 if (tc) {
8400 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
8401 netdev_set_num_tc(dev, tc);
8402 } else {
8403 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8404 netdev_reset_tc(dev);
8405 }
8406 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
8407 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
8408 bp->tx_nr_rings + bp->rx_nr_rings;
8409 bp->num_stat_ctxs = bp->cp_nr_rings;
8410
8411 if (netif_running(bp->dev))
8412 return bnxt_open_nic(bp, true, false);
8413
8414 return 0;
8415 }
8416
8417 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
8418 void *cb_priv)
8419 {
8420 struct bnxt *bp = cb_priv;
8421
8422 if (!bnxt_tc_flower_enabled(bp) ||
8423 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
8424 return -EOPNOTSUPP;
8425
8426 switch (type) {
8427 case TC_SETUP_CLSFLOWER:
8428 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
8429 default:
8430 return -EOPNOTSUPP;
8431 }
8432 }
8433
8434 static int bnxt_setup_tc_block(struct net_device *dev,
8435 struct tc_block_offload *f)
8436 {
8437 struct bnxt *bp = netdev_priv(dev);
8438
8439 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
8440 return -EOPNOTSUPP;
8441
8442 switch (f->command) {
8443 case TC_BLOCK_BIND:
8444 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
8445 bp, bp, f->extack);
8446 case TC_BLOCK_UNBIND:
8447 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
8448 return 0;
8449 default:
8450 return -EOPNOTSUPP;
8451 }
8452 }
8453
8454 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
8455 void *type_data)
8456 {
8457 switch (type) {
8458 case TC_SETUP_BLOCK:
8459 return bnxt_setup_tc_block(dev, type_data);
8460 case TC_SETUP_QDISC_MQPRIO: {
8461 struct tc_mqprio_qopt *mqprio = type_data;
8462
8463 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
8464
8465 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
8466 }
8467 default:
8468 return -EOPNOTSUPP;
8469 }
8470 }
8471
8472 #ifdef CONFIG_RFS_ACCEL
8473 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
8474 struct bnxt_ntuple_filter *f2)
8475 {
8476 struct flow_keys *keys1 = &f1->fkeys;
8477 struct flow_keys *keys2 = &f2->fkeys;
8478
8479 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
8480 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
8481 keys1->ports.ports == keys2->ports.ports &&
8482 keys1->basic.ip_proto == keys2->basic.ip_proto &&
8483 keys1->basic.n_proto == keys2->basic.n_proto &&
8484 keys1->control.flags == keys2->control.flags &&
8485 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
8486 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
8487 return true;
8488
8489 return false;
8490 }
8491
8492 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
8493 u16 rxq_index, u32 flow_id)
8494 {
8495 struct bnxt *bp = netdev_priv(dev);
8496 struct bnxt_ntuple_filter *fltr, *new_fltr;
8497 struct flow_keys *fkeys;
8498 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
8499 int rc = 0, idx, bit_id, l2_idx = 0;
8500 struct hlist_head *head;
8501
8502 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
8503 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8504 int off = 0, j;
8505
8506 netif_addr_lock_bh(dev);
8507 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
8508 if (ether_addr_equal(eth->h_dest,
8509 vnic->uc_list + off)) {
8510 l2_idx = j + 1;
8511 break;
8512 }
8513 }
8514 netif_addr_unlock_bh(dev);
8515 if (!l2_idx)
8516 return -EINVAL;
8517 }
8518 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
8519 if (!new_fltr)
8520 return -ENOMEM;
8521
8522 fkeys = &new_fltr->fkeys;
8523 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
8524 rc = -EPROTONOSUPPORT;
8525 goto err_free;
8526 }
8527
8528 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
8529 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
8530 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
8531 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
8532 rc = -EPROTONOSUPPORT;
8533 goto err_free;
8534 }
8535 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
8536 bp->hwrm_spec_code < 0x10601) {
8537 rc = -EPROTONOSUPPORT;
8538 goto err_free;
8539 }
8540 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
8541 bp->hwrm_spec_code < 0x10601) {
8542 rc = -EPROTONOSUPPORT;
8543 goto err_free;
8544 }
8545
8546 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
8547 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
8548
8549 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
8550 head = &bp->ntp_fltr_hash_tbl[idx];
8551 rcu_read_lock();
8552 hlist_for_each_entry_rcu(fltr, head, hash) {
8553 if (bnxt_fltr_match(fltr, new_fltr)) {
8554 rcu_read_unlock();
8555 rc = 0;
8556 goto err_free;
8557 }
8558 }
8559 rcu_read_unlock();
8560
8561 spin_lock_bh(&bp->ntp_fltr_lock);
8562 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
8563 BNXT_NTP_FLTR_MAX_FLTR, 0);
8564 if (bit_id < 0) {
8565 spin_unlock_bh(&bp->ntp_fltr_lock);
8566 rc = -ENOMEM;
8567 goto err_free;
8568 }
8569
8570 new_fltr->sw_id = (u16)bit_id;
8571 new_fltr->flow_id = flow_id;
8572 new_fltr->l2_fltr_idx = l2_idx;
8573 new_fltr->rxq = rxq_index;
8574 hlist_add_head_rcu(&new_fltr->hash, head);
8575 bp->ntp_fltr_count++;
8576 spin_unlock_bh(&bp->ntp_fltr_lock);
8577
8578 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
8579 bnxt_queue_sp_work(bp);
8580
8581 return new_fltr->sw_id;
8582
8583 err_free:
8584 kfree(new_fltr);
8585 return rc;
8586 }
8587
8588 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
8589 {
8590 int i;
8591
8592 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
8593 struct hlist_head *head;
8594 struct hlist_node *tmp;
8595 struct bnxt_ntuple_filter *fltr;
8596 int rc;
8597
8598 head = &bp->ntp_fltr_hash_tbl[i];
8599 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
8600 bool del = false;
8601
8602 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
8603 if (rps_may_expire_flow(bp->dev, fltr->rxq,
8604 fltr->flow_id,
8605 fltr->sw_id)) {
8606 bnxt_hwrm_cfa_ntuple_filter_free(bp,
8607 fltr);
8608 del = true;
8609 }
8610 } else {
8611 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
8612 fltr);
8613 if (rc)
8614 del = true;
8615 else
8616 set_bit(BNXT_FLTR_VALID, &fltr->state);
8617 }
8618
8619 if (del) {
8620 spin_lock_bh(&bp->ntp_fltr_lock);
8621 hlist_del_rcu(&fltr->hash);
8622 bp->ntp_fltr_count--;
8623 spin_unlock_bh(&bp->ntp_fltr_lock);
8624 synchronize_rcu();
8625 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
8626 kfree(fltr);
8627 }
8628 }
8629 }
8630 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
8631 netdev_info(bp->dev, "Receive PF driver unload event!");
8632 }
8633
8634 #else
8635
8636 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
8637 {
8638 }
8639
8640 #endif /* CONFIG_RFS_ACCEL */
8641
8642 static void bnxt_udp_tunnel_add(struct net_device *dev,
8643 struct udp_tunnel_info *ti)
8644 {
8645 struct bnxt *bp = netdev_priv(dev);
8646
8647 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8648 return;
8649
8650 if (!netif_running(dev))
8651 return;
8652
8653 switch (ti->type) {
8654 case UDP_TUNNEL_TYPE_VXLAN:
8655 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
8656 return;
8657
8658 bp->vxlan_port_cnt++;
8659 if (bp->vxlan_port_cnt == 1) {
8660 bp->vxlan_port = ti->port;
8661 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
8662 bnxt_queue_sp_work(bp);
8663 }
8664 break;
8665 case UDP_TUNNEL_TYPE_GENEVE:
8666 if (bp->nge_port_cnt && bp->nge_port != ti->port)
8667 return;
8668
8669 bp->nge_port_cnt++;
8670 if (bp->nge_port_cnt == 1) {
8671 bp->nge_port = ti->port;
8672 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
8673 }
8674 break;
8675 default:
8676 return;
8677 }
8678
8679 bnxt_queue_sp_work(bp);
8680 }
8681
8682 static void bnxt_udp_tunnel_del(struct net_device *dev,
8683 struct udp_tunnel_info *ti)
8684 {
8685 struct bnxt *bp = netdev_priv(dev);
8686
8687 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8688 return;
8689
8690 if (!netif_running(dev))
8691 return;
8692
8693 switch (ti->type) {
8694 case UDP_TUNNEL_TYPE_VXLAN:
8695 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
8696 return;
8697 bp->vxlan_port_cnt--;
8698
8699 if (bp->vxlan_port_cnt != 0)
8700 return;
8701
8702 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
8703 break;
8704 case UDP_TUNNEL_TYPE_GENEVE:
8705 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
8706 return;
8707 bp->nge_port_cnt--;
8708
8709 if (bp->nge_port_cnt != 0)
8710 return;
8711
8712 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
8713 break;
8714 default:
8715 return;
8716 }
8717
8718 bnxt_queue_sp_work(bp);
8719 }
8720
8721 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8722 struct net_device *dev, u32 filter_mask,
8723 int nlflags)
8724 {
8725 struct bnxt *bp = netdev_priv(dev);
8726
8727 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
8728 nlflags, filter_mask, NULL);
8729 }
8730
8731 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
8732 u16 flags)
8733 {
8734 struct bnxt *bp = netdev_priv(dev);
8735 struct nlattr *attr, *br_spec;
8736 int rem, rc = 0;
8737
8738 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
8739 return -EOPNOTSUPP;
8740
8741 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8742 if (!br_spec)
8743 return -EINVAL;
8744
8745 nla_for_each_nested(attr, br_spec, rem) {
8746 u16 mode;
8747
8748 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8749 continue;
8750
8751 if (nla_len(attr) < sizeof(mode))
8752 return -EINVAL;
8753
8754 mode = nla_get_u16(attr);
8755 if (mode == bp->br_mode)
8756 break;
8757
8758 rc = bnxt_hwrm_set_br_mode(bp, mode);
8759 if (!rc)
8760 bp->br_mode = mode;
8761 break;
8762 }
8763 return rc;
8764 }
8765
8766 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
8767 size_t len)
8768 {
8769 struct bnxt *bp = netdev_priv(dev);
8770 int rc;
8771
8772 /* The PF and it's VF-reps only support the switchdev framework */
8773 if (!BNXT_PF(bp))
8774 return -EOPNOTSUPP;
8775
8776 rc = snprintf(buf, len, "p%d", bp->pf.port_id);
8777
8778 if (rc >= len)
8779 return -EOPNOTSUPP;
8780 return 0;
8781 }
8782
8783 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
8784 {
8785 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
8786 return -EOPNOTSUPP;
8787
8788 /* The PF and it's VF-reps only support the switchdev framework */
8789 if (!BNXT_PF(bp))
8790 return -EOPNOTSUPP;
8791
8792 switch (attr->id) {
8793 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
8794 attr->u.ppid.id_len = sizeof(bp->switch_id);
8795 memcpy(attr->u.ppid.id, bp->switch_id, attr->u.ppid.id_len);
8796 break;
8797 default:
8798 return -EOPNOTSUPP;
8799 }
8800 return 0;
8801 }
8802
8803 static int bnxt_swdev_port_attr_get(struct net_device *dev,
8804 struct switchdev_attr *attr)
8805 {
8806 return bnxt_port_attr_get(netdev_priv(dev), attr);
8807 }
8808
8809 static const struct switchdev_ops bnxt_switchdev_ops = {
8810 .switchdev_port_attr_get = bnxt_swdev_port_attr_get
8811 };
8812
8813 static const struct net_device_ops bnxt_netdev_ops = {
8814 .ndo_open = bnxt_open,
8815 .ndo_start_xmit = bnxt_start_xmit,
8816 .ndo_stop = bnxt_close,
8817 .ndo_get_stats64 = bnxt_get_stats64,
8818 .ndo_set_rx_mode = bnxt_set_rx_mode,
8819 .ndo_do_ioctl = bnxt_ioctl,
8820 .ndo_validate_addr = eth_validate_addr,
8821 .ndo_set_mac_address = bnxt_change_mac_addr,
8822 .ndo_change_mtu = bnxt_change_mtu,
8823 .ndo_fix_features = bnxt_fix_features,
8824 .ndo_set_features = bnxt_set_features,
8825 .ndo_tx_timeout = bnxt_tx_timeout,
8826 #ifdef CONFIG_BNXT_SRIOV
8827 .ndo_get_vf_config = bnxt_get_vf_config,
8828 .ndo_set_vf_mac = bnxt_set_vf_mac,
8829 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
8830 .ndo_set_vf_rate = bnxt_set_vf_bw,
8831 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
8832 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
8833 .ndo_set_vf_trust = bnxt_set_vf_trust,
8834 #endif
8835 .ndo_setup_tc = bnxt_setup_tc,
8836 #ifdef CONFIG_RFS_ACCEL
8837 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
8838 #endif
8839 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
8840 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
8841 .ndo_bpf = bnxt_xdp,
8842 .ndo_bridge_getlink = bnxt_bridge_getlink,
8843 .ndo_bridge_setlink = bnxt_bridge_setlink,
8844 .ndo_get_phys_port_name = bnxt_get_phys_port_name
8845 };
8846
8847 static void bnxt_remove_one(struct pci_dev *pdev)
8848 {
8849 struct net_device *dev = pci_get_drvdata(pdev);
8850 struct bnxt *bp = netdev_priv(dev);
8851
8852 if (BNXT_PF(bp)) {
8853 bnxt_sriov_disable(bp);
8854 bnxt_dl_unregister(bp);
8855 }
8856
8857 pci_disable_pcie_error_reporting(pdev);
8858 unregister_netdev(dev);
8859 bnxt_shutdown_tc(bp);
8860 bnxt_cancel_sp_work(bp);
8861 bp->sp_event = 0;
8862
8863 bnxt_clear_int_mode(bp);
8864 bnxt_hwrm_func_drv_unrgtr(bp);
8865 bnxt_free_hwrm_resources(bp);
8866 bnxt_free_hwrm_short_cmd_req(bp);
8867 bnxt_ethtool_free(bp);
8868 bnxt_dcb_free(bp);
8869 kfree(bp->edev);
8870 bp->edev = NULL;
8871 bnxt_free_ctx_mem(bp);
8872 kfree(bp->ctx);
8873 bp->ctx = NULL;
8874 bnxt_cleanup_pci(bp);
8875 free_netdev(dev);
8876 }
8877
8878 static int bnxt_probe_phy(struct bnxt *bp)
8879 {
8880 int rc = 0;
8881 struct bnxt_link_info *link_info = &bp->link_info;
8882
8883 rc = bnxt_hwrm_phy_qcaps(bp);
8884 if (rc) {
8885 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
8886 rc);
8887 return rc;
8888 }
8889 mutex_init(&bp->link_lock);
8890
8891 rc = bnxt_update_link(bp, false);
8892 if (rc) {
8893 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
8894 rc);
8895 return rc;
8896 }
8897
8898 /* Older firmware does not have supported_auto_speeds, so assume
8899 * that all supported speeds can be autonegotiated.
8900 */
8901 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
8902 link_info->support_auto_speeds = link_info->support_speeds;
8903
8904 /*initialize the ethool setting copy with NVM settings */
8905 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
8906 link_info->autoneg = BNXT_AUTONEG_SPEED;
8907 if (bp->hwrm_spec_code >= 0x10201) {
8908 if (link_info->auto_pause_setting &
8909 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
8910 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8911 } else {
8912 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8913 }
8914 link_info->advertising = link_info->auto_link_speeds;
8915 } else {
8916 link_info->req_link_speed = link_info->force_link_speed;
8917 link_info->req_duplex = link_info->duplex_setting;
8918 }
8919 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
8920 link_info->req_flow_ctrl =
8921 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
8922 else
8923 link_info->req_flow_ctrl = link_info->force_pause_setting;
8924 return rc;
8925 }
8926
8927 static int bnxt_get_max_irq(struct pci_dev *pdev)
8928 {
8929 u16 ctrl;
8930
8931 if (!pdev->msix_cap)
8932 return 1;
8933
8934 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
8935 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
8936 }
8937
8938 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8939 int *max_cp)
8940 {
8941 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8942 int max_ring_grps = 0;
8943
8944 *max_tx = hw_resc->max_tx_rings;
8945 *max_rx = hw_resc->max_rx_rings;
8946 *max_cp = min_t(int, bnxt_get_max_func_cp_rings_for_en(bp),
8947 hw_resc->max_irqs - bnxt_get_ulp_msix_num(bp));
8948 *max_cp = min_t(int, *max_cp, hw_resc->max_stat_ctxs);
8949 max_ring_grps = hw_resc->max_hw_ring_grps;
8950 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
8951 *max_cp -= 1;
8952 *max_rx -= 2;
8953 }
8954 if (bp->flags & BNXT_FLAG_AGG_RINGS)
8955 *max_rx >>= 1;
8956 *max_rx = min_t(int, *max_rx, max_ring_grps);
8957 }
8958
8959 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
8960 {
8961 int rx, tx, cp;
8962
8963 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
8964 *max_rx = rx;
8965 *max_tx = tx;
8966 if (!rx || !tx || !cp)
8967 return -ENOMEM;
8968
8969 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
8970 }
8971
8972 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8973 bool shared)
8974 {
8975 int rc;
8976
8977 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8978 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
8979 /* Not enough rings, try disabling agg rings. */
8980 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
8981 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8982 if (rc) {
8983 /* set BNXT_FLAG_AGG_RINGS back for consistency */
8984 bp->flags |= BNXT_FLAG_AGG_RINGS;
8985 return rc;
8986 }
8987 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
8988 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8989 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8990 bnxt_set_ring_params(bp);
8991 }
8992
8993 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
8994 int max_cp, max_stat, max_irq;
8995
8996 /* Reserve minimum resources for RoCE */
8997 max_cp = bnxt_get_max_func_cp_rings(bp);
8998 max_stat = bnxt_get_max_func_stat_ctxs(bp);
8999 max_irq = bnxt_get_max_func_irqs(bp);
9000 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
9001 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
9002 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
9003 return 0;
9004
9005 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
9006 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
9007 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
9008 max_cp = min_t(int, max_cp, max_irq);
9009 max_cp = min_t(int, max_cp, max_stat);
9010 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
9011 if (rc)
9012 rc = 0;
9013 }
9014 return rc;
9015 }
9016
9017 /* In initial default shared ring setting, each shared ring must have a
9018 * RX/TX ring pair.
9019 */
9020 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
9021 {
9022 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
9023 bp->rx_nr_rings = bp->cp_nr_rings;
9024 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
9025 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9026 }
9027
9028 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
9029 {
9030 int dflt_rings, max_rx_rings, max_tx_rings, rc;
9031
9032 if (!bnxt_can_reserve_rings(bp))
9033 return 0;
9034
9035 if (sh)
9036 bp->flags |= BNXT_FLAG_SHARED_RINGS;
9037 dflt_rings = netif_get_num_default_rss_queues();
9038 /* Reduce default rings on multi-port cards so that total default
9039 * rings do not exceed CPU count.
9040 */
9041 if (bp->port_count > 1) {
9042 int max_rings =
9043 max_t(int, num_online_cpus() / bp->port_count, 1);
9044
9045 dflt_rings = min_t(int, dflt_rings, max_rings);
9046 }
9047 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
9048 if (rc)
9049 return rc;
9050 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
9051 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
9052 if (sh)
9053 bnxt_trim_dflt_sh_rings(bp);
9054 else
9055 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
9056 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9057
9058 rc = __bnxt_reserve_rings(bp);
9059 if (rc)
9060 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
9061 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9062 if (sh)
9063 bnxt_trim_dflt_sh_rings(bp);
9064
9065 /* Rings may have been trimmed, re-reserve the trimmed rings. */
9066 if (bnxt_need_reserve_rings(bp)) {
9067 rc = __bnxt_reserve_rings(bp);
9068 if (rc)
9069 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
9070 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9071 }
9072 bp->num_stat_ctxs = bp->cp_nr_rings;
9073 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
9074 bp->rx_nr_rings++;
9075 bp->cp_nr_rings++;
9076 }
9077 return rc;
9078 }
9079
9080 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
9081 {
9082 int rc;
9083
9084 if (bp->tx_nr_rings)
9085 return 0;
9086
9087 bnxt_ulp_irq_stop(bp);
9088 bnxt_clear_int_mode(bp);
9089 rc = bnxt_set_dflt_rings(bp, true);
9090 if (rc) {
9091 netdev_err(bp->dev, "Not enough rings available.\n");
9092 goto init_dflt_ring_err;
9093 }
9094 rc = bnxt_init_int_mode(bp);
9095 if (rc)
9096 goto init_dflt_ring_err;
9097
9098 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9099 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
9100 bp->flags |= BNXT_FLAG_RFS;
9101 bp->dev->features |= NETIF_F_NTUPLE;
9102 }
9103 init_dflt_ring_err:
9104 bnxt_ulp_irq_restart(bp, rc);
9105 return rc;
9106 }
9107
9108 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
9109 {
9110 int rc;
9111
9112 ASSERT_RTNL();
9113 bnxt_hwrm_func_qcaps(bp);
9114
9115 if (netif_running(bp->dev))
9116 __bnxt_close_nic(bp, true, false);
9117
9118 bnxt_ulp_irq_stop(bp);
9119 bnxt_clear_int_mode(bp);
9120 rc = bnxt_init_int_mode(bp);
9121 bnxt_ulp_irq_restart(bp, rc);
9122
9123 if (netif_running(bp->dev)) {
9124 if (rc)
9125 dev_close(bp->dev);
9126 else
9127 rc = bnxt_open_nic(bp, true, false);
9128 }
9129
9130 return rc;
9131 }
9132
9133 static int bnxt_init_mac_addr(struct bnxt *bp)
9134 {
9135 int rc = 0;
9136
9137 if (BNXT_PF(bp)) {
9138 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
9139 } else {
9140 #ifdef CONFIG_BNXT_SRIOV
9141 struct bnxt_vf_info *vf = &bp->vf;
9142 bool strict_approval = true;
9143
9144 if (is_valid_ether_addr(vf->mac_addr)) {
9145 /* overwrite netdev dev_addr with admin VF MAC */
9146 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
9147 /* Older PF driver or firmware may not approve this
9148 * correctly.
9149 */
9150 strict_approval = false;
9151 } else {
9152 eth_hw_addr_random(bp->dev);
9153 }
9154 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
9155 #endif
9156 }
9157 return rc;
9158 }
9159
9160 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
9161 {
9162 static int version_printed;
9163 struct net_device *dev;
9164 struct bnxt *bp;
9165 int rc, max_irqs;
9166
9167 if (pci_is_bridge(pdev))
9168 return -ENODEV;
9169
9170 if (version_printed++ == 0)
9171 pr_info("%s", version);
9172
9173 max_irqs = bnxt_get_max_irq(pdev);
9174 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
9175 if (!dev)
9176 return -ENOMEM;
9177
9178 bp = netdev_priv(dev);
9179
9180 if (bnxt_vf_pciid(ent->driver_data))
9181 bp->flags |= BNXT_FLAG_VF;
9182
9183 if (pdev->msix_cap)
9184 bp->flags |= BNXT_FLAG_MSIX_CAP;
9185
9186 rc = bnxt_init_board(pdev, dev);
9187 if (rc < 0)
9188 goto init_err_free;
9189
9190 dev->netdev_ops = &bnxt_netdev_ops;
9191 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
9192 dev->ethtool_ops = &bnxt_ethtool_ops;
9193 SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
9194 pci_set_drvdata(pdev, dev);
9195
9196 rc = bnxt_alloc_hwrm_resources(bp);
9197 if (rc)
9198 goto init_err_pci_clean;
9199
9200 mutex_init(&bp->hwrm_cmd_lock);
9201 rc = bnxt_hwrm_ver_get(bp);
9202 if (rc)
9203 goto init_err_pci_clean;
9204
9205 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
9206 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
9207 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
9208 if (rc)
9209 goto init_err_pci_clean;
9210 }
9211
9212 rc = bnxt_hwrm_func_reset(bp);
9213 if (rc)
9214 goto init_err_pci_clean;
9215
9216 bnxt_hwrm_fw_set_time(bp);
9217
9218 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
9219 NETIF_F_TSO | NETIF_F_TSO6 |
9220 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
9221 NETIF_F_GSO_IPXIP4 |
9222 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
9223 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
9224 NETIF_F_RXCSUM | NETIF_F_GRO;
9225
9226 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
9227 dev->hw_features |= NETIF_F_LRO;
9228
9229 dev->hw_enc_features =
9230 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
9231 NETIF_F_TSO | NETIF_F_TSO6 |
9232 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
9233 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
9234 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
9235 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
9236 NETIF_F_GSO_GRE_CSUM;
9237 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
9238 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
9239 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
9240 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
9241 dev->hw_features |= NETIF_F_GRO_HW;
9242 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
9243 if (dev->features & NETIF_F_GRO_HW)
9244 dev->features &= ~NETIF_F_LRO;
9245 dev->priv_flags |= IFF_UNICAST_FLT;
9246
9247 #ifdef CONFIG_BNXT_SRIOV
9248 init_waitqueue_head(&bp->sriov_cfg_wait);
9249 mutex_init(&bp->sriov_lock);
9250 #endif
9251 bp->gro_func = bnxt_gro_func_5730x;
9252 if (BNXT_CHIP_P4_PLUS(bp))
9253 bp->gro_func = bnxt_gro_func_5731x;
9254 else
9255 bp->flags |= BNXT_FLAG_DOUBLE_DB;
9256
9257 rc = bnxt_hwrm_func_drv_rgtr(bp);
9258 if (rc)
9259 goto init_err_pci_clean;
9260
9261 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
9262 if (rc)
9263 goto init_err_pci_clean;
9264
9265 bp->ulp_probe = bnxt_ulp_probe;
9266
9267 rc = bnxt_hwrm_queue_qportcfg(bp);
9268 if (rc) {
9269 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
9270 rc);
9271 rc = -1;
9272 goto init_err_pci_clean;
9273 }
9274 /* Get the MAX capabilities for this function */
9275 rc = bnxt_hwrm_func_qcaps(bp);
9276 if (rc) {
9277 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
9278 rc);
9279 rc = -1;
9280 goto init_err_pci_clean;
9281 }
9282 rc = bnxt_init_mac_addr(bp);
9283 if (rc) {
9284 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
9285 rc = -EADDRNOTAVAIL;
9286 goto init_err_pci_clean;
9287 }
9288
9289 bnxt_hwrm_func_qcfg(bp);
9290 bnxt_hwrm_port_led_qcaps(bp);
9291 bnxt_ethtool_init(bp);
9292 bnxt_dcb_init(bp);
9293
9294 /* MTU range: 60 - FW defined max */
9295 dev->min_mtu = ETH_ZLEN;
9296 dev->max_mtu = bp->max_mtu;
9297
9298 rc = bnxt_probe_phy(bp);
9299 if (rc)
9300 goto init_err_pci_clean;
9301
9302 bnxt_set_rx_skb_mode(bp, false);
9303 bnxt_set_tpa_flags(bp);
9304 bnxt_set_ring_params(bp);
9305 bnxt_set_max_func_irqs(bp, max_irqs);
9306 rc = bnxt_set_dflt_rings(bp, true);
9307 if (rc) {
9308 netdev_err(bp->dev, "Not enough rings available.\n");
9309 rc = -ENOMEM;
9310 goto init_err_pci_clean;
9311 }
9312
9313 /* Default RSS hash cfg. */
9314 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
9315 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
9316 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
9317 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
9318 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
9319 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
9320 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
9321 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
9322 }
9323
9324 bnxt_hwrm_vnic_qcaps(bp);
9325 if (bnxt_rfs_supported(bp)) {
9326 dev->hw_features |= NETIF_F_NTUPLE;
9327 if (bnxt_rfs_capable(bp)) {
9328 bp->flags |= BNXT_FLAG_RFS;
9329 dev->features |= NETIF_F_NTUPLE;
9330 }
9331 }
9332
9333 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
9334 bp->flags |= BNXT_FLAG_STRIP_VLAN;
9335
9336 rc = bnxt_init_int_mode(bp);
9337 if (rc)
9338 goto init_err_pci_clean;
9339
9340 /* No TC has been set yet and rings may have been trimmed due to
9341 * limited MSIX, so we re-initialize the TX rings per TC.
9342 */
9343 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9344
9345 bnxt_get_wol_settings(bp);
9346 if (bp->flags & BNXT_FLAG_WOL_CAP)
9347 device_set_wakeup_enable(&pdev->dev, bp->wol);
9348 else
9349 device_set_wakeup_capable(&pdev->dev, false);
9350
9351 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
9352
9353 bnxt_hwrm_coal_params_qcaps(bp);
9354
9355 if (BNXT_PF(bp)) {
9356 if (!bnxt_pf_wq) {
9357 bnxt_pf_wq =
9358 create_singlethread_workqueue("bnxt_pf_wq");
9359 if (!bnxt_pf_wq) {
9360 dev_err(&pdev->dev, "Unable to create workqueue.\n");
9361 goto init_err_pci_clean;
9362 }
9363 }
9364 bnxt_init_tc(bp);
9365 }
9366
9367 rc = register_netdev(dev);
9368 if (rc)
9369 goto init_err_cleanup_tc;
9370
9371 if (BNXT_PF(bp))
9372 bnxt_dl_register(bp);
9373
9374 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
9375 board_info[ent->driver_data].name,
9376 (long)pci_resource_start(pdev, 0), dev->dev_addr);
9377 pcie_print_link_status(pdev);
9378
9379 return 0;
9380
9381 init_err_cleanup_tc:
9382 bnxt_shutdown_tc(bp);
9383 bnxt_clear_int_mode(bp);
9384
9385 init_err_pci_clean:
9386 bnxt_free_hwrm_resources(bp);
9387 bnxt_free_ctx_mem(bp);
9388 kfree(bp->ctx);
9389 bp->ctx = NULL;
9390 bnxt_cleanup_pci(bp);
9391
9392 init_err_free:
9393 free_netdev(dev);
9394 return rc;
9395 }
9396
9397 static void bnxt_shutdown(struct pci_dev *pdev)
9398 {
9399 struct net_device *dev = pci_get_drvdata(pdev);
9400 struct bnxt *bp;
9401
9402 if (!dev)
9403 return;
9404
9405 rtnl_lock();
9406 bp = netdev_priv(dev);
9407 if (!bp)
9408 goto shutdown_exit;
9409
9410 if (netif_running(dev))
9411 dev_close(dev);
9412
9413 bnxt_ulp_shutdown(bp);
9414
9415 if (system_state == SYSTEM_POWER_OFF) {
9416 bnxt_clear_int_mode(bp);
9417 pci_wake_from_d3(pdev, bp->wol);
9418 pci_set_power_state(pdev, PCI_D3hot);
9419 }
9420
9421 shutdown_exit:
9422 rtnl_unlock();
9423 }
9424
9425 #ifdef CONFIG_PM_SLEEP
9426 static int bnxt_suspend(struct device *device)
9427 {
9428 struct pci_dev *pdev = to_pci_dev(device);
9429 struct net_device *dev = pci_get_drvdata(pdev);
9430 struct bnxt *bp = netdev_priv(dev);
9431 int rc = 0;
9432
9433 rtnl_lock();
9434 if (netif_running(dev)) {
9435 netif_device_detach(dev);
9436 rc = bnxt_close(dev);
9437 }
9438 bnxt_hwrm_func_drv_unrgtr(bp);
9439 rtnl_unlock();
9440 return rc;
9441 }
9442
9443 static int bnxt_resume(struct device *device)
9444 {
9445 struct pci_dev *pdev = to_pci_dev(device);
9446 struct net_device *dev = pci_get_drvdata(pdev);
9447 struct bnxt *bp = netdev_priv(dev);
9448 int rc = 0;
9449
9450 rtnl_lock();
9451 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
9452 rc = -ENODEV;
9453 goto resume_exit;
9454 }
9455 rc = bnxt_hwrm_func_reset(bp);
9456 if (rc) {
9457 rc = -EBUSY;
9458 goto resume_exit;
9459 }
9460 bnxt_get_wol_settings(bp);
9461 if (netif_running(dev)) {
9462 rc = bnxt_open(dev);
9463 if (!rc)
9464 netif_device_attach(dev);
9465 }
9466
9467 resume_exit:
9468 rtnl_unlock();
9469 return rc;
9470 }
9471
9472 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
9473 #define BNXT_PM_OPS (&bnxt_pm_ops)
9474
9475 #else
9476
9477 #define BNXT_PM_OPS NULL
9478
9479 #endif /* CONFIG_PM_SLEEP */
9480
9481 /**
9482 * bnxt_io_error_detected - called when PCI error is detected
9483 * @pdev: Pointer to PCI device
9484 * @state: The current pci connection state
9485 *
9486 * This function is called after a PCI bus error affecting
9487 * this device has been detected.
9488 */
9489 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
9490 pci_channel_state_t state)
9491 {
9492 struct net_device *netdev = pci_get_drvdata(pdev);
9493 struct bnxt *bp = netdev_priv(netdev);
9494
9495 netdev_info(netdev, "PCI I/O error detected\n");
9496
9497 rtnl_lock();
9498 netif_device_detach(netdev);
9499
9500 bnxt_ulp_stop(bp);
9501
9502 if (state == pci_channel_io_perm_failure) {
9503 rtnl_unlock();
9504 return PCI_ERS_RESULT_DISCONNECT;
9505 }
9506
9507 if (netif_running(netdev))
9508 bnxt_close(netdev);
9509
9510 pci_disable_device(pdev);
9511 rtnl_unlock();
9512
9513 /* Request a slot slot reset. */
9514 return PCI_ERS_RESULT_NEED_RESET;
9515 }
9516
9517 /**
9518 * bnxt_io_slot_reset - called after the pci bus has been reset.
9519 * @pdev: Pointer to PCI device
9520 *
9521 * Restart the card from scratch, as if from a cold-boot.
9522 * At this point, the card has exprienced a hard reset,
9523 * followed by fixups by BIOS, and has its config space
9524 * set up identically to what it was at cold boot.
9525 */
9526 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
9527 {
9528 struct net_device *netdev = pci_get_drvdata(pdev);
9529 struct bnxt *bp = netdev_priv(netdev);
9530 int err = 0;
9531 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
9532
9533 netdev_info(bp->dev, "PCI Slot Reset\n");
9534
9535 rtnl_lock();
9536
9537 if (pci_enable_device(pdev)) {
9538 dev_err(&pdev->dev,
9539 "Cannot re-enable PCI device after reset.\n");
9540 } else {
9541 pci_set_master(pdev);
9542
9543 err = bnxt_hwrm_func_reset(bp);
9544 if (!err && netif_running(netdev))
9545 err = bnxt_open(netdev);
9546
9547 if (!err) {
9548 result = PCI_ERS_RESULT_RECOVERED;
9549 bnxt_ulp_start(bp);
9550 }
9551 }
9552
9553 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
9554 dev_close(netdev);
9555
9556 rtnl_unlock();
9557
9558 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9559 if (err) {
9560 dev_err(&pdev->dev,
9561 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9562 err); /* non-fatal, continue */
9563 }
9564
9565 return PCI_ERS_RESULT_RECOVERED;
9566 }
9567
9568 /**
9569 * bnxt_io_resume - called when traffic can start flowing again.
9570 * @pdev: Pointer to PCI device
9571 *
9572 * This callback is called when the error recovery driver tells
9573 * us that its OK to resume normal operation.
9574 */
9575 static void bnxt_io_resume(struct pci_dev *pdev)
9576 {
9577 struct net_device *netdev = pci_get_drvdata(pdev);
9578
9579 rtnl_lock();
9580
9581 netif_device_attach(netdev);
9582
9583 rtnl_unlock();
9584 }
9585
9586 static const struct pci_error_handlers bnxt_err_handler = {
9587 .error_detected = bnxt_io_error_detected,
9588 .slot_reset = bnxt_io_slot_reset,
9589 .resume = bnxt_io_resume
9590 };
9591
9592 static struct pci_driver bnxt_pci_driver = {
9593 .name = DRV_MODULE_NAME,
9594 .id_table = bnxt_pci_tbl,
9595 .probe = bnxt_init_one,
9596 .remove = bnxt_remove_one,
9597 .shutdown = bnxt_shutdown,
9598 .driver.pm = BNXT_PM_OPS,
9599 .err_handler = &bnxt_err_handler,
9600 #if defined(CONFIG_BNXT_SRIOV)
9601 .sriov_configure = bnxt_sriov_configure,
9602 #endif
9603 };
9604
9605 static int __init bnxt_init(void)
9606 {
9607 bnxt_debug_init();
9608 return pci_register_driver(&bnxt_pci_driver);
9609 }
9610
9611 static void __exit bnxt_exit(void)
9612 {
9613 pci_unregister_driver(&bnxt_pci_driver);
9614 if (bnxt_pf_wq)
9615 destroy_workqueue(bnxt_pf_wq);
9616 bnxt_debug_exit();
9617 }
9618
9619 module_init(bnxt_init);
9620 module_exit(bnxt_exit);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git