1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
11 #include <linux/module.h>
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/if_bridge.h>
37 #include <linux/rtc.h>
38 #include <linux/bpf.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <net/udp_tunnel.h>
45 #include <linux/workqueue.h>
46 #include <linux/prefetch.h>
47 #include <linux/cache.h>
48 #include <linux/log2.h>
49 #include <linux/aer.h>
50 #include <linux/bitmap.h>
51 #include <linux/cpu_rmap.h>
52 #include <linux/cpumask.h>
53 #include <net/pkt_cls.h>
54 #include <linux/hwmon.h>
55 #include <linux/hwmon-sysfs.h>
60 #include "bnxt_sriov.h"
61 #include "bnxt_ethtool.h"
66 #include "bnxt_devlink.h"
67 #include "bnxt_debugfs.h"
69 #define BNXT_TX_TIMEOUT (5 * HZ)
71 static const char version
[] =
72 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
74 MODULE_LICENSE("GPL");
75 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
76 MODULE_VERSION(DRV_MODULE_VERSION
);
78 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
79 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
80 #define BNXT_RX_COPY_THRESH 256
82 #define BNXT_TX_PUSH_THRESH 164
123 /* indexed by enum above */
124 static const struct {
127 [BCM57301
] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
128 [BCM57302
] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
129 [BCM57304
] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
130 [BCM57417_NPAR
] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
131 [BCM58700
] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
132 [BCM57311
] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
133 [BCM57312
] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
134 [BCM57402
] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
135 [BCM57404
] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
136 [BCM57406
] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
137 [BCM57402_NPAR
] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
138 [BCM57407
] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
139 [BCM57412
] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
140 [BCM57414
] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
141 [BCM57416
] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
142 [BCM57417
] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
143 [BCM57412_NPAR
] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
144 [BCM57314
] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
145 [BCM57417_SFP
] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
146 [BCM57416_SFP
] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
147 [BCM57404_NPAR
] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
148 [BCM57406_NPAR
] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
149 [BCM57407_SFP
] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
150 [BCM57407_NPAR
] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
151 [BCM57414_NPAR
] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
152 [BCM57416_NPAR
] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
153 [BCM57452
] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
154 [BCM57454
] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
155 [BCM5745x_NPAR
] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
156 [BCM57508
] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
157 [BCM58802
] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
158 [BCM58804
] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
159 [BCM58808
] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
160 [NETXTREME_E_VF
] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
161 [NETXTREME_C_VF
] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
162 [NETXTREME_S_VF
] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
165 static const struct pci_device_id bnxt_pci_tbl
[] = {
166 { PCI_VDEVICE(BROADCOM
, 0x1604), .driver_data
= BCM5745x_NPAR
},
167 { PCI_VDEVICE(BROADCOM
, 0x1605), .driver_data
= BCM5745x_NPAR
},
168 { PCI_VDEVICE(BROADCOM
, 0x1614), .driver_data
= BCM57454
},
169 { PCI_VDEVICE(BROADCOM
, 0x16c0), .driver_data
= BCM57417_NPAR
},
170 { PCI_VDEVICE(BROADCOM
, 0x16c8), .driver_data
= BCM57301
},
171 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
172 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
173 { PCI_VDEVICE(BROADCOM
, 0x16cc), .driver_data
= BCM57417_NPAR
},
174 { PCI_VDEVICE(BROADCOM
, 0x16cd), .driver_data
= BCM58700
},
175 { PCI_VDEVICE(BROADCOM
, 0x16ce), .driver_data
= BCM57311
},
176 { PCI_VDEVICE(BROADCOM
, 0x16cf), .driver_data
= BCM57312
},
177 { PCI_VDEVICE(BROADCOM
, 0x16d0), .driver_data
= BCM57402
},
178 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
179 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
180 { PCI_VDEVICE(BROADCOM
, 0x16d4), .driver_data
= BCM57402_NPAR
},
181 { PCI_VDEVICE(BROADCOM
, 0x16d5), .driver_data
= BCM57407
},
182 { PCI_VDEVICE(BROADCOM
, 0x16d6), .driver_data
= BCM57412
},
183 { PCI_VDEVICE(BROADCOM
, 0x16d7), .driver_data
= BCM57414
},
184 { PCI_VDEVICE(BROADCOM
, 0x16d8), .driver_data
= BCM57416
},
185 { PCI_VDEVICE(BROADCOM
, 0x16d9), .driver_data
= BCM57417
},
186 { PCI_VDEVICE(BROADCOM
, 0x16de), .driver_data
= BCM57412_NPAR
},
187 { PCI_VDEVICE(BROADCOM
, 0x16df), .driver_data
= BCM57314
},
188 { PCI_VDEVICE(BROADCOM
, 0x16e2), .driver_data
= BCM57417_SFP
},
189 { PCI_VDEVICE(BROADCOM
, 0x16e3), .driver_data
= BCM57416_SFP
},
190 { PCI_VDEVICE(BROADCOM
, 0x16e7), .driver_data
= BCM57404_NPAR
},
191 { PCI_VDEVICE(BROADCOM
, 0x16e8), .driver_data
= BCM57406_NPAR
},
192 { PCI_VDEVICE(BROADCOM
, 0x16e9), .driver_data
= BCM57407_SFP
},
193 { PCI_VDEVICE(BROADCOM
, 0x16ea), .driver_data
= BCM57407_NPAR
},
194 { PCI_VDEVICE(BROADCOM
, 0x16eb), .driver_data
= BCM57412_NPAR
},
195 { PCI_VDEVICE(BROADCOM
, 0x16ec), .driver_data
= BCM57414_NPAR
},
196 { PCI_VDEVICE(BROADCOM
, 0x16ed), .driver_data
= BCM57414_NPAR
},
197 { PCI_VDEVICE(BROADCOM
, 0x16ee), .driver_data
= BCM57416_NPAR
},
198 { PCI_VDEVICE(BROADCOM
, 0x16ef), .driver_data
= BCM57416_NPAR
},
199 { PCI_VDEVICE(BROADCOM
, 0x16f0), .driver_data
= BCM58808
},
200 { PCI_VDEVICE(BROADCOM
, 0x16f1), .driver_data
= BCM57452
},
201 { PCI_VDEVICE(BROADCOM
, 0x1750), .driver_data
= BCM57508
},
202 { PCI_VDEVICE(BROADCOM
, 0xd802), .driver_data
= BCM58802
},
203 { PCI_VDEVICE(BROADCOM
, 0xd804), .driver_data
= BCM58804
},
204 #ifdef CONFIG_BNXT_SRIOV
205 { PCI_VDEVICE(BROADCOM
, 0x1606), .driver_data
= NETXTREME_E_VF
},
206 { PCI_VDEVICE(BROADCOM
, 0x1609), .driver_data
= NETXTREME_E_VF
},
207 { PCI_VDEVICE(BROADCOM
, 0x16c1), .driver_data
= NETXTREME_E_VF
},
208 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= NETXTREME_C_VF
},
209 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= NETXTREME_E_VF
},
210 { PCI_VDEVICE(BROADCOM
, 0x16dc), .driver_data
= NETXTREME_E_VF
},
211 { PCI_VDEVICE(BROADCOM
, 0x16e1), .driver_data
= NETXTREME_C_VF
},
212 { PCI_VDEVICE(BROADCOM
, 0x16e5), .driver_data
= NETXTREME_C_VF
},
213 { PCI_VDEVICE(BROADCOM
, 0xd800), .driver_data
= NETXTREME_S_VF
},
218 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
220 static const u16 bnxt_vf_req_snif
[] = {
224 HWRM_CFA_L2_FILTER_ALLOC
,
227 static const u16 bnxt_async_events_arr
[] = {
228 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
,
229 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
,
230 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
,
231 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE
,
232 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
,
235 static struct workqueue_struct
*bnxt_pf_wq
;
237 static bool bnxt_vf_pciid(enum board_idx idx
)
239 return (idx
== NETXTREME_C_VF
|| idx
== NETXTREME_E_VF
||
240 idx
== NETXTREME_S_VF
);
243 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
244 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
245 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
247 #define BNXT_CP_DB_IRQ_DIS(db) \
248 writel(DB_CP_IRQ_DIS_FLAGS, db)
250 #define BNXT_DB_CQ(db, idx) \
251 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
253 #define BNXT_DB_NQ_P5(db, idx) \
254 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
256 #define BNXT_DB_CQ_ARM(db, idx) \
257 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
259 #define BNXT_DB_NQ_ARM_P5(db, idx) \
260 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
262 static void bnxt_db_nq(struct bnxt
*bp
, struct bnxt_db_info
*db
, u32 idx
)
264 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
265 BNXT_DB_NQ_P5(db
, idx
);
270 static void bnxt_db_nq_arm(struct bnxt
*bp
, struct bnxt_db_info
*db
, u32 idx
)
272 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
273 BNXT_DB_NQ_ARM_P5(db
, idx
);
275 BNXT_DB_CQ_ARM(db
, idx
);
278 static void bnxt_db_cq(struct bnxt
*bp
, struct bnxt_db_info
*db
, u32 idx
)
280 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
281 writeq(db
->db_key64
| DBR_TYPE_CQ_ARMALL
| RING_CMP(idx
),
287 const u16 bnxt_lhint_arr
[] = {
288 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
289 TX_BD_FLAGS_LHINT_512_TO_1023
,
290 TX_BD_FLAGS_LHINT_1024_TO_2047
,
291 TX_BD_FLAGS_LHINT_1024_TO_2047
,
292 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
293 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
294 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
295 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
296 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
297 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
298 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
299 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
300 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
301 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
302 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
303 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
304 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
305 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
306 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
309 static u16
bnxt_xmit_get_cfa_action(struct sk_buff
*skb
)
311 struct metadata_dst
*md_dst
= skb_metadata_dst(skb
);
313 if (!md_dst
|| md_dst
->type
!= METADATA_HW_PORT_MUX
)
316 return md_dst
->u
.port_info
.port_id
;
319 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
321 struct bnxt
*bp
= netdev_priv(dev
);
323 struct tx_bd_ext
*txbd1
;
324 struct netdev_queue
*txq
;
327 unsigned int length
, pad
= 0;
328 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
330 struct pci_dev
*pdev
= bp
->pdev
;
331 struct bnxt_tx_ring_info
*txr
;
332 struct bnxt_sw_tx_bd
*tx_buf
;
334 i
= skb_get_queue_mapping(skb
);
335 if (unlikely(i
>= bp
->tx_nr_rings
)) {
336 dev_kfree_skb_any(skb
);
340 txq
= netdev_get_tx_queue(dev
, i
);
341 txr
= &bp
->tx_ring
[bp
->tx_ring_map
[i
]];
344 free_size
= bnxt_tx_avail(bp
, txr
);
345 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
346 netif_tx_stop_queue(txq
);
347 return NETDEV_TX_BUSY
;
351 len
= skb_headlen(skb
);
352 last_frag
= skb_shinfo(skb
)->nr_frags
;
354 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
356 txbd
->tx_bd_opaque
= prod
;
358 tx_buf
= &txr
->tx_buf_ring
[prod
];
360 tx_buf
->nr_frags
= last_frag
;
363 cfa_action
= bnxt_xmit_get_cfa_action(skb
);
364 if (skb_vlan_tag_present(skb
)) {
365 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
366 skb_vlan_tag_get(skb
);
367 /* Currently supports 8021Q, 8021AD vlan offloads
368 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
370 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
371 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
374 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
375 struct tx_push_buffer
*tx_push_buf
= txr
->tx_push
;
376 struct tx_push_bd
*tx_push
= &tx_push_buf
->push_bd
;
377 struct tx_bd_ext
*tx_push1
= &tx_push
->txbd2
;
378 void __iomem
*db
= txr
->tx_db
.doorbell
;
379 void *pdata
= tx_push_buf
->data
;
383 /* Set COAL_NOW to be ready quickly for the next push */
384 tx_push
->tx_bd_len_flags_type
=
385 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
386 TX_BD_TYPE_LONG_TX_BD
|
387 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
388 TX_BD_FLAGS_COAL_NOW
|
389 TX_BD_FLAGS_PACKET_END
|
390 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
392 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
393 tx_push1
->tx_bd_hsize_lflags
=
394 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
396 tx_push1
->tx_bd_hsize_lflags
= 0;
398 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
399 tx_push1
->tx_bd_cfa_action
=
400 cpu_to_le32(cfa_action
<< TX_BD_CFA_ACTION_SHIFT
);
402 end
= pdata
+ length
;
403 end
= PTR_ALIGN(end
, 8) - 1;
406 skb_copy_from_linear_data(skb
, pdata
, len
);
408 for (j
= 0; j
< last_frag
; j
++) {
409 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
412 fptr
= skb_frag_address_safe(frag
);
416 memcpy(pdata
, fptr
, skb_frag_size(frag
));
417 pdata
+= skb_frag_size(frag
);
420 txbd
->tx_bd_len_flags_type
= tx_push
->tx_bd_len_flags_type
;
421 txbd
->tx_bd_haddr
= txr
->data_mapping
;
422 prod
= NEXT_TX(prod
);
423 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
424 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
425 prod
= NEXT_TX(prod
);
427 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
431 netdev_tx_sent_queue(txq
, skb
->len
);
432 wmb(); /* Sync is_push and byte queue before pushing data */
434 push_len
= (length
+ sizeof(*tx_push
) + 7) / 8;
436 __iowrite64_copy(db
, tx_push_buf
, 16);
437 __iowrite32_copy(db
+ 4, tx_push_buf
+ 1,
438 (push_len
- 16) << 1);
440 __iowrite64_copy(db
, tx_push_buf
, push_len
);
447 if (length
< BNXT_MIN_PKT_SIZE
) {
448 pad
= BNXT_MIN_PKT_SIZE
- length
;
449 if (skb_pad(skb
, pad
)) {
450 /* SKB already freed. */
454 length
= BNXT_MIN_PKT_SIZE
;
457 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
459 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
460 dev_kfree_skb_any(skb
);
465 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
466 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
467 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
469 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
471 prod
= NEXT_TX(prod
);
472 txbd1
= (struct tx_bd_ext
*)
473 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
475 txbd1
->tx_bd_hsize_lflags
= 0;
476 if (skb_is_gso(skb
)) {
479 if (skb
->encapsulation
)
480 hdr_len
= skb_inner_network_offset(skb
) +
481 skb_inner_network_header_len(skb
) +
482 inner_tcp_hdrlen(skb
);
484 hdr_len
= skb_transport_offset(skb
) +
487 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
489 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
490 length
= skb_shinfo(skb
)->gso_size
;
491 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
493 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
494 txbd1
->tx_bd_hsize_lflags
=
495 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
496 txbd1
->tx_bd_mss
= 0;
500 flags
|= bnxt_lhint_arr
[length
];
501 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
503 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
504 txbd1
->tx_bd_cfa_action
=
505 cpu_to_le32(cfa_action
<< TX_BD_CFA_ACTION_SHIFT
);
506 for (i
= 0; i
< last_frag
; i
++) {
507 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
509 prod
= NEXT_TX(prod
);
510 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
512 len
= skb_frag_size(frag
);
513 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
516 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
519 tx_buf
= &txr
->tx_buf_ring
[prod
];
520 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
522 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
524 flags
= len
<< TX_BD_LEN_SHIFT
;
525 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
529 txbd
->tx_bd_len_flags_type
=
530 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
531 TX_BD_FLAGS_PACKET_END
);
533 netdev_tx_sent_queue(txq
, skb
->len
);
535 /* Sync BD data before updating doorbell */
538 prod
= NEXT_TX(prod
);
541 if (!skb
->xmit_more
|| netif_xmit_stopped(txq
))
542 bnxt_db_write(bp
, &txr
->tx_db
, prod
);
548 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
549 if (skb
->xmit_more
&& !tx_buf
->is_push
)
550 bnxt_db_write(bp
, &txr
->tx_db
, prod
);
552 netif_tx_stop_queue(txq
);
554 /* netif_tx_stop_queue() must be done before checking
555 * tx index in bnxt_tx_avail() below, because in
556 * bnxt_tx_int(), we update tx index before checking for
557 * netif_tx_queue_stopped().
560 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
561 netif_tx_wake_queue(txq
);
568 /* start back at beginning and unmap skb */
570 tx_buf
= &txr
->tx_buf_ring
[prod
];
572 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
573 skb_headlen(skb
), PCI_DMA_TODEVICE
);
574 prod
= NEXT_TX(prod
);
576 /* unmap remaining mapped pages */
577 for (i
= 0; i
< last_frag
; i
++) {
578 prod
= NEXT_TX(prod
);
579 tx_buf
= &txr
->tx_buf_ring
[prod
];
580 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
581 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
585 dev_kfree_skb_any(skb
);
589 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
591 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
592 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, txr
->txq_index
);
593 u16 cons
= txr
->tx_cons
;
594 struct pci_dev
*pdev
= bp
->pdev
;
596 unsigned int tx_bytes
= 0;
598 for (i
= 0; i
< nr_pkts
; i
++) {
599 struct bnxt_sw_tx_bd
*tx_buf
;
603 tx_buf
= &txr
->tx_buf_ring
[cons
];
604 cons
= NEXT_TX(cons
);
608 if (tx_buf
->is_push
) {
613 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
614 skb_headlen(skb
), PCI_DMA_TODEVICE
);
615 last
= tx_buf
->nr_frags
;
617 for (j
= 0; j
< last
; j
++) {
618 cons
= NEXT_TX(cons
);
619 tx_buf
= &txr
->tx_buf_ring
[cons
];
622 dma_unmap_addr(tx_buf
, mapping
),
623 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
628 cons
= NEXT_TX(cons
);
630 tx_bytes
+= skb
->len
;
631 dev_kfree_skb_any(skb
);
634 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
637 /* Need to make the tx_cons update visible to bnxt_start_xmit()
638 * before checking for netif_tx_queue_stopped(). Without the
639 * memory barrier, there is a small possibility that bnxt_start_xmit()
640 * will miss it and cause the queue to be stopped forever.
644 if (unlikely(netif_tx_queue_stopped(txq
)) &&
645 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
646 __netif_tx_lock(txq
, smp_processor_id());
647 if (netif_tx_queue_stopped(txq
) &&
648 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
649 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
650 netif_tx_wake_queue(txq
);
651 __netif_tx_unlock(txq
);
655 static struct page
*__bnxt_alloc_rx_page(struct bnxt
*bp
, dma_addr_t
*mapping
,
658 struct device
*dev
= &bp
->pdev
->dev
;
661 page
= alloc_page(gfp
);
665 *mapping
= dma_map_page_attrs(dev
, page
, 0, PAGE_SIZE
, bp
->rx_dir
,
666 DMA_ATTR_WEAK_ORDERING
);
667 if (dma_mapping_error(dev
, *mapping
)) {
671 *mapping
+= bp
->rx_dma_offset
;
675 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
679 struct pci_dev
*pdev
= bp
->pdev
;
681 data
= kmalloc(bp
->rx_buf_size
, gfp
);
685 *mapping
= dma_map_single_attrs(&pdev
->dev
, data
+ bp
->rx_dma_offset
,
686 bp
->rx_buf_use_size
, bp
->rx_dir
,
687 DMA_ATTR_WEAK_ORDERING
);
689 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
696 int bnxt_alloc_rx_data(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
699 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
700 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
703 if (BNXT_RX_PAGE_MODE(bp
)) {
704 struct page
*page
= __bnxt_alloc_rx_page(bp
, &mapping
, gfp
);
710 rx_buf
->data_ptr
= page_address(page
) + bp
->rx_offset
;
712 u8
*data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
718 rx_buf
->data_ptr
= data
+ bp
->rx_offset
;
720 rx_buf
->mapping
= mapping
;
722 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
726 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
, void *data
)
728 u16 prod
= rxr
->rx_prod
;
729 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
730 struct rx_bd
*cons_bd
, *prod_bd
;
732 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
733 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
735 prod_rx_buf
->data
= data
;
736 prod_rx_buf
->data_ptr
= cons_rx_buf
->data_ptr
;
738 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
740 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
741 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
743 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
746 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
748 u16 next
, max
= rxr
->rx_agg_bmap_size
;
750 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
752 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
756 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
757 struct bnxt_rx_ring_info
*rxr
,
761 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
762 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
763 struct pci_dev
*pdev
= bp
->pdev
;
766 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
767 unsigned int offset
= 0;
769 if (PAGE_SIZE
> BNXT_RX_PAGE_SIZE
) {
772 page
= alloc_page(gfp
);
776 rxr
->rx_page_offset
= 0;
778 offset
= rxr
->rx_page_offset
;
779 rxr
->rx_page_offset
+= BNXT_RX_PAGE_SIZE
;
780 if (rxr
->rx_page_offset
== PAGE_SIZE
)
785 page
= alloc_page(gfp
);
790 mapping
= dma_map_page_attrs(&pdev
->dev
, page
, offset
,
791 BNXT_RX_PAGE_SIZE
, PCI_DMA_FROMDEVICE
,
792 DMA_ATTR_WEAK_ORDERING
);
793 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
798 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
799 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
801 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
802 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
803 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
805 rx_agg_buf
->page
= page
;
806 rx_agg_buf
->offset
= offset
;
807 rx_agg_buf
->mapping
= mapping
;
808 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
809 rxbd
->rx_bd_opaque
= sw_prod
;
813 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info
*cpr
, u16 cp_cons
,
816 struct bnxt_napi
*bnapi
= cpr
->bnapi
;
817 struct bnxt
*bp
= bnapi
->bp
;
818 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
819 u16 prod
= rxr
->rx_agg_prod
;
820 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
823 for (i
= 0; i
< agg_bufs
; i
++) {
825 struct rx_agg_cmp
*agg
;
826 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
827 struct rx_bd
*prod_bd
;
830 agg
= (struct rx_agg_cmp
*)
831 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
832 cons
= agg
->rx_agg_cmp_opaque
;
833 __clear_bit(cons
, rxr
->rx_agg_bmap
);
835 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
836 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
838 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
839 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
840 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
842 /* It is possible for sw_prod to be equal to cons, so
843 * set cons_rx_buf->page to NULL first.
845 page
= cons_rx_buf
->page
;
846 cons_rx_buf
->page
= NULL
;
847 prod_rx_buf
->page
= page
;
848 prod_rx_buf
->offset
= cons_rx_buf
->offset
;
850 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
852 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
854 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
855 prod_bd
->rx_bd_opaque
= sw_prod
;
857 prod
= NEXT_RX_AGG(prod
);
858 sw_prod
= NEXT_RX_AGG(sw_prod
);
859 cp_cons
= NEXT_CMP(cp_cons
);
861 rxr
->rx_agg_prod
= prod
;
862 rxr
->rx_sw_agg_prod
= sw_prod
;
865 static struct sk_buff
*bnxt_rx_page_skb(struct bnxt
*bp
,
866 struct bnxt_rx_ring_info
*rxr
,
867 u16 cons
, void *data
, u8
*data_ptr
,
869 unsigned int offset_and_len
)
871 unsigned int payload
= offset_and_len
>> 16;
872 unsigned int len
= offset_and_len
& 0xffff;
873 struct skb_frag_struct
*frag
;
874 struct page
*page
= data
;
875 u16 prod
= rxr
->rx_prod
;
879 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
881 bnxt_reuse_rx_data(rxr
, cons
, data
);
884 dma_addr
-= bp
->rx_dma_offset
;
885 dma_unmap_page_attrs(&bp
->pdev
->dev
, dma_addr
, PAGE_SIZE
, bp
->rx_dir
,
886 DMA_ATTR_WEAK_ORDERING
);
888 if (unlikely(!payload
))
889 payload
= eth_get_headlen(data_ptr
, len
);
891 skb
= napi_alloc_skb(&rxr
->bnapi
->napi
, payload
);
897 off
= (void *)data_ptr
- page_address(page
);
898 skb_add_rx_frag(skb
, 0, page
, off
, len
, PAGE_SIZE
);
899 memcpy(skb
->data
- NET_IP_ALIGN
, data_ptr
- NET_IP_ALIGN
,
900 payload
+ NET_IP_ALIGN
);
902 frag
= &skb_shinfo(skb
)->frags
[0];
903 skb_frag_size_sub(frag
, payload
);
904 frag
->page_offset
+= payload
;
905 skb
->data_len
-= payload
;
906 skb
->tail
+= payload
;
911 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
912 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
913 void *data
, u8
*data_ptr
,
915 unsigned int offset_and_len
)
917 u16 prod
= rxr
->rx_prod
;
921 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
923 bnxt_reuse_rx_data(rxr
, cons
, data
);
927 skb
= build_skb(data
, 0);
928 dma_unmap_single_attrs(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
929 bp
->rx_dir
, DMA_ATTR_WEAK_ORDERING
);
935 skb_reserve(skb
, bp
->rx_offset
);
936 skb_put(skb
, offset_and_len
& 0xffff);
940 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
,
941 struct bnxt_cp_ring_info
*cpr
,
942 struct sk_buff
*skb
, u16 cp_cons
,
945 struct bnxt_napi
*bnapi
= cpr
->bnapi
;
946 struct pci_dev
*pdev
= bp
->pdev
;
947 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
948 u16 prod
= rxr
->rx_agg_prod
;
951 for (i
= 0; i
< agg_bufs
; i
++) {
953 struct rx_agg_cmp
*agg
;
954 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
958 agg
= (struct rx_agg_cmp
*)
959 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
960 cons
= agg
->rx_agg_cmp_opaque
;
961 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
962 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
964 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
965 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
,
966 cons_rx_buf
->offset
, frag_len
);
967 __clear_bit(cons
, rxr
->rx_agg_bmap
);
969 /* It is possible for bnxt_alloc_rx_page() to allocate
970 * a sw_prod index that equals the cons index, so we
971 * need to clear the cons entry now.
973 mapping
= cons_rx_buf
->mapping
;
974 page
= cons_rx_buf
->page
;
975 cons_rx_buf
->page
= NULL
;
977 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
978 struct skb_shared_info
*shinfo
;
979 unsigned int nr_frags
;
981 shinfo
= skb_shinfo(skb
);
982 nr_frags
= --shinfo
->nr_frags
;
983 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
987 cons_rx_buf
->page
= page
;
989 /* Update prod since possibly some pages have been
992 rxr
->rx_agg_prod
= prod
;
993 bnxt_reuse_rx_agg_bufs(cpr
, cp_cons
, agg_bufs
- i
);
997 dma_unmap_page_attrs(&pdev
->dev
, mapping
, BNXT_RX_PAGE_SIZE
,
999 DMA_ATTR_WEAK_ORDERING
);
1001 skb
->data_len
+= frag_len
;
1002 skb
->len
+= frag_len
;
1003 skb
->truesize
+= PAGE_SIZE
;
1005 prod
= NEXT_RX_AGG(prod
);
1006 cp_cons
= NEXT_CMP(cp_cons
);
1008 rxr
->rx_agg_prod
= prod
;
1012 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
1013 u8 agg_bufs
, u32
*raw_cons
)
1016 struct rx_agg_cmp
*agg
;
1018 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
1019 last
= RING_CMP(*raw_cons
);
1020 agg
= (struct rx_agg_cmp
*)
1021 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
1022 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
1025 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
1029 struct bnxt
*bp
= bnapi
->bp
;
1030 struct pci_dev
*pdev
= bp
->pdev
;
1031 struct sk_buff
*skb
;
1033 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
1037 dma_sync_single_for_cpu(&pdev
->dev
, mapping
, bp
->rx_copy_thresh
,
1040 memcpy(skb
->data
- NET_IP_ALIGN
, data
- NET_IP_ALIGN
,
1041 len
+ NET_IP_ALIGN
);
1043 dma_sync_single_for_device(&pdev
->dev
, mapping
, bp
->rx_copy_thresh
,
1050 static int bnxt_discard_rx(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
1051 u32
*raw_cons
, void *cmp
)
1053 struct rx_cmp
*rxcmp
= cmp
;
1054 u32 tmp_raw_cons
= *raw_cons
;
1055 u8 cmp_type
, agg_bufs
= 0;
1057 cmp_type
= RX_CMP_TYPE(rxcmp
);
1059 if (cmp_type
== CMP_TYPE_RX_L2_CMP
) {
1060 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) &
1062 RX_CMP_AGG_BUFS_SHIFT
;
1063 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1064 struct rx_tpa_end_cmp
*tpa_end
= cmp
;
1066 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1067 RX_TPA_END_CMP_AGG_BUFS
) >>
1068 RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
1072 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1075 *raw_cons
= tmp_raw_cons
;
1079 static void bnxt_queue_sp_work(struct bnxt
*bp
)
1082 queue_work(bnxt_pf_wq
, &bp
->sp_task
);
1084 schedule_work(&bp
->sp_task
);
1087 static void bnxt_cancel_sp_work(struct bnxt
*bp
)
1090 flush_workqueue(bnxt_pf_wq
);
1092 cancel_work_sync(&bp
->sp_task
);
1095 static void bnxt_sched_reset(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
)
1097 if (!rxr
->bnapi
->in_reset
) {
1098 rxr
->bnapi
->in_reset
= true;
1099 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
1100 bnxt_queue_sp_work(bp
);
1102 rxr
->rx_next_cons
= 0xffff;
1105 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
1106 struct rx_tpa_start_cmp
*tpa_start
,
1107 struct rx_tpa_start_cmp_ext
*tpa_start1
)
1109 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
1111 struct bnxt_tpa_info
*tpa_info
;
1112 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
1113 struct rx_bd
*prod_bd
;
1116 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
1117 prod
= rxr
->rx_prod
;
1118 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
1119 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
1120 tpa_info
= &rxr
->rx_tpa
[agg_id
];
1122 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
1123 bnxt_sched_reset(bp
, rxr
);
1126 /* Store cfa_code in tpa_info to use in tpa_end
1127 * completion processing.
1129 tpa_info
->cfa_code
= TPA_START_CFA_CODE(tpa_start1
);
1130 prod_rx_buf
->data
= tpa_info
->data
;
1131 prod_rx_buf
->data_ptr
= tpa_info
->data_ptr
;
1133 mapping
= tpa_info
->mapping
;
1134 prod_rx_buf
->mapping
= mapping
;
1136 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
1138 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
1140 tpa_info
->data
= cons_rx_buf
->data
;
1141 tpa_info
->data_ptr
= cons_rx_buf
->data_ptr
;
1142 cons_rx_buf
->data
= NULL
;
1143 tpa_info
->mapping
= cons_rx_buf
->mapping
;
1146 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
1147 RX_TPA_START_CMP_LEN_SHIFT
;
1148 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
1149 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
1151 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
1152 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
1153 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1154 if (hash_type
== 3 || TPA_START_IS_IPV6(tpa_start1
))
1155 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
1156 tpa_info
->rss_hash
=
1157 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
1159 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
1160 tpa_info
->gso_type
= 0;
1161 if (netif_msg_rx_err(bp
))
1162 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
1164 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
1165 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
1166 tpa_info
->hdr_info
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_hdr_info
);
1168 rxr
->rx_prod
= NEXT_RX(prod
);
1169 cons
= NEXT_RX(cons
);
1170 rxr
->rx_next_cons
= NEXT_RX(cons
);
1171 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
1173 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
1174 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
1175 cons_rx_buf
->data
= NULL
;
1178 static void bnxt_abort_tpa(struct bnxt_cp_ring_info
*cpr
, u16 cp_cons
,
1182 bnxt_reuse_rx_agg_bufs(cpr
, cp_cons
, agg_bufs
);
1185 static struct sk_buff
*bnxt_gro_func_5731x(struct bnxt_tpa_info
*tpa_info
,
1186 int payload_off
, int tcp_ts
,
1187 struct sk_buff
*skb
)
1192 u16 outer_ip_off
, inner_ip_off
, inner_mac_off
;
1193 u32 hdr_info
= tpa_info
->hdr_info
;
1194 bool loopback
= false;
1196 inner_ip_off
= BNXT_TPA_INNER_L3_OFF(hdr_info
);
1197 inner_mac_off
= BNXT_TPA_INNER_L2_OFF(hdr_info
);
1198 outer_ip_off
= BNXT_TPA_OUTER_L3_OFF(hdr_info
);
1200 /* If the packet is an internal loopback packet, the offsets will
1201 * have an extra 4 bytes.
1203 if (inner_mac_off
== 4) {
1205 } else if (inner_mac_off
> 4) {
1206 __be16 proto
= *((__be16
*)(skb
->data
+ inner_ip_off
-
1209 /* We only support inner iPv4/ipv6. If we don't see the
1210 * correct protocol ID, it must be a loopback packet where
1211 * the offsets are off by 4.
1213 if (proto
!= htons(ETH_P_IP
) && proto
!= htons(ETH_P_IPV6
))
1217 /* internal loopback packet, subtract all offsets by 4 */
1223 nw_off
= inner_ip_off
- ETH_HLEN
;
1224 skb_set_network_header(skb
, nw_off
);
1225 if (tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_IP_TYPE
) {
1226 struct ipv6hdr
*iph
= ipv6_hdr(skb
);
1228 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
1229 len
= skb
->len
- skb_transport_offset(skb
);
1231 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
1233 struct iphdr
*iph
= ip_hdr(skb
);
1235 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
1236 len
= skb
->len
- skb_transport_offset(skb
);
1238 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
1241 if (inner_mac_off
) { /* tunnel */
1242 struct udphdr
*uh
= NULL
;
1243 __be16 proto
= *((__be16
*)(skb
->data
+ outer_ip_off
-
1246 if (proto
== htons(ETH_P_IP
)) {
1247 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
1249 if (iph
->protocol
== IPPROTO_UDP
)
1250 uh
= (struct udphdr
*)(iph
+ 1);
1252 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
1254 if (iph
->nexthdr
== IPPROTO_UDP
)
1255 uh
= (struct udphdr
*)(iph
+ 1);
1259 skb_shinfo(skb
)->gso_type
|=
1260 SKB_GSO_UDP_TUNNEL_CSUM
;
1262 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
1269 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1270 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1272 static struct sk_buff
*bnxt_gro_func_5730x(struct bnxt_tpa_info
*tpa_info
,
1273 int payload_off
, int tcp_ts
,
1274 struct sk_buff
*skb
)
1278 int len
, nw_off
, tcp_opt_len
= 0;
1283 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
1286 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
1288 skb_set_network_header(skb
, nw_off
);
1290 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
1291 len
= skb
->len
- skb_transport_offset(skb
);
1293 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
1294 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
1295 struct ipv6hdr
*iph
;
1297 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
1299 skb_set_network_header(skb
, nw_off
);
1300 iph
= ipv6_hdr(skb
);
1301 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
1302 len
= skb
->len
- skb_transport_offset(skb
);
1304 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
1306 dev_kfree_skb_any(skb
);
1310 if (nw_off
) { /* tunnel */
1311 struct udphdr
*uh
= NULL
;
1313 if (skb
->protocol
== htons(ETH_P_IP
)) {
1314 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
1316 if (iph
->protocol
== IPPROTO_UDP
)
1317 uh
= (struct udphdr
*)(iph
+ 1);
1319 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
1321 if (iph
->nexthdr
== IPPROTO_UDP
)
1322 uh
= (struct udphdr
*)(iph
+ 1);
1326 skb_shinfo(skb
)->gso_type
|=
1327 SKB_GSO_UDP_TUNNEL_CSUM
;
1329 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
1336 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt
*bp
,
1337 struct bnxt_tpa_info
*tpa_info
,
1338 struct rx_tpa_end_cmp
*tpa_end
,
1339 struct rx_tpa_end_cmp_ext
*tpa_end1
,
1340 struct sk_buff
*skb
)
1346 segs
= TPA_END_TPA_SEGS(tpa_end
);
1350 NAPI_GRO_CB(skb
)->count
= segs
;
1351 skb_shinfo(skb
)->gso_size
=
1352 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
1353 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
1354 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1355 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
1356 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
1357 skb
= bp
->gro_func(tpa_info
, payload_off
, TPA_END_GRO_TS(tpa_end
), skb
);
1359 tcp_gro_complete(skb
);
1364 /* Given the cfa_code of a received packet determine which
1365 * netdev (vf-rep or PF) the packet is destined to.
1367 static struct net_device
*bnxt_get_pkt_dev(struct bnxt
*bp
, u16 cfa_code
)
1369 struct net_device
*dev
= bnxt_get_vf_rep(bp
, cfa_code
);
1371 /* if vf-rep dev is NULL, the must belongs to the PF */
1372 return dev
? dev
: bp
->dev
;
1375 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
1376 struct bnxt_cp_ring_info
*cpr
,
1378 struct rx_tpa_end_cmp
*tpa_end
,
1379 struct rx_tpa_end_cmp_ext
*tpa_end1
,
1382 struct bnxt_napi
*bnapi
= cpr
->bnapi
;
1383 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1384 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
1385 u8
*data_ptr
, agg_bufs
;
1386 u16 cp_cons
= RING_CMP(*raw_cons
);
1388 struct bnxt_tpa_info
*tpa_info
;
1390 struct sk_buff
*skb
;
1393 if (unlikely(bnapi
->in_reset
)) {
1394 int rc
= bnxt_discard_rx(bp
, cpr
, raw_cons
, tpa_end
);
1397 return ERR_PTR(-EBUSY
);
1401 tpa_info
= &rxr
->rx_tpa
[agg_id
];
1402 data
= tpa_info
->data
;
1403 data_ptr
= tpa_info
->data_ptr
;
1405 len
= tpa_info
->len
;
1406 mapping
= tpa_info
->mapping
;
1408 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1409 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
1412 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
1413 return ERR_PTR(-EBUSY
);
1415 *event
|= BNXT_AGG_EVENT
;
1416 cp_cons
= NEXT_CMP(cp_cons
);
1419 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
|| TPA_END_ERRORS(tpa_end1
))) {
1420 bnxt_abort_tpa(cpr
, cp_cons
, agg_bufs
);
1421 if (agg_bufs
> MAX_SKB_FRAGS
)
1422 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1423 agg_bufs
, (int)MAX_SKB_FRAGS
);
1427 if (len
<= bp
->rx_copy_thresh
) {
1428 skb
= bnxt_copy_skb(bnapi
, data_ptr
, len
, mapping
);
1430 bnxt_abort_tpa(cpr
, cp_cons
, agg_bufs
);
1435 dma_addr_t new_mapping
;
1437 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
1439 bnxt_abort_tpa(cpr
, cp_cons
, agg_bufs
);
1443 tpa_info
->data
= new_data
;
1444 tpa_info
->data_ptr
= new_data
+ bp
->rx_offset
;
1445 tpa_info
->mapping
= new_mapping
;
1447 skb
= build_skb(data
, 0);
1448 dma_unmap_single_attrs(&bp
->pdev
->dev
, mapping
,
1449 bp
->rx_buf_use_size
, bp
->rx_dir
,
1450 DMA_ATTR_WEAK_ORDERING
);
1454 bnxt_abort_tpa(cpr
, cp_cons
, agg_bufs
);
1457 skb_reserve(skb
, bp
->rx_offset
);
1462 skb
= bnxt_rx_pages(bp
, cpr
, skb
, cp_cons
, agg_bufs
);
1464 /* Page reuse already handled by bnxt_rx_pages(). */
1470 eth_type_trans(skb
, bnxt_get_pkt_dev(bp
, tpa_info
->cfa_code
));
1472 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1473 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1475 if ((tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) &&
1476 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1477 u16 vlan_proto
= tpa_info
->metadata
>>
1478 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1479 u16 vtag
= tpa_info
->metadata
& RX_CMP_FLAGS2_METADATA_TCI_MASK
;
1481 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1484 skb_checksum_none_assert(skb
);
1485 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1486 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1488 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1491 if (TPA_END_GRO(tpa_end
))
1492 skb
= bnxt_gro_skb(bp
, tpa_info
, tpa_end
, tpa_end1
, skb
);
1497 static void bnxt_deliver_skb(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
1498 struct sk_buff
*skb
)
1500 if (skb
->dev
!= bp
->dev
) {
1501 /* this packet belongs to a vf-rep */
1502 bnxt_vf_rep_rx(bp
, skb
);
1505 skb_record_rx_queue(skb
, bnapi
->index
);
1506 napi_gro_receive(&bnapi
->napi
, skb
);
1509 /* returns the following:
1510 * 1 - 1 packet successfully received
1511 * 0 - successful TPA_START, packet not completed yet
1512 * -EBUSY - completion ring does not have all the agg buffers yet
1513 * -ENOMEM - packet aborted due to out of memory
1514 * -EIO - packet aborted due to hw error indicated in BD
1516 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
1517 u32
*raw_cons
, u8
*event
)
1519 struct bnxt_napi
*bnapi
= cpr
->bnapi
;
1520 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1521 struct net_device
*dev
= bp
->dev
;
1522 struct rx_cmp
*rxcmp
;
1523 struct rx_cmp_ext
*rxcmp1
;
1524 u32 tmp_raw_cons
= *raw_cons
;
1525 u16 cfa_code
, cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1526 struct bnxt_sw_rx_bd
*rx_buf
;
1528 u8
*data_ptr
, agg_bufs
, cmp_type
;
1529 dma_addr_t dma_addr
;
1530 struct sk_buff
*skb
;
1535 rxcmp
= (struct rx_cmp
*)
1536 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1538 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1539 cp_cons
= RING_CMP(tmp_raw_cons
);
1540 rxcmp1
= (struct rx_cmp_ext
*)
1541 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1543 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1546 cmp_type
= RX_CMP_TYPE(rxcmp
);
1548 prod
= rxr
->rx_prod
;
1550 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1551 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1552 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1554 *event
|= BNXT_RX_EVENT
;
1555 goto next_rx_no_prod_no_len
;
1557 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1558 skb
= bnxt_tpa_end(bp
, cpr
, &tmp_raw_cons
,
1559 (struct rx_tpa_end_cmp
*)rxcmp
,
1560 (struct rx_tpa_end_cmp_ext
*)rxcmp1
, event
);
1567 bnxt_deliver_skb(bp
, bnapi
, skb
);
1570 *event
|= BNXT_RX_EVENT
;
1571 goto next_rx_no_prod_no_len
;
1574 cons
= rxcmp
->rx_cmp_opaque
;
1575 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1576 data
= rx_buf
->data
;
1577 data_ptr
= rx_buf
->data_ptr
;
1578 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
1579 int rc1
= bnxt_discard_rx(bp
, cpr
, raw_cons
, rxcmp
);
1581 bnxt_sched_reset(bp
, rxr
);
1586 misc
= le32_to_cpu(rxcmp
->rx_cmp_misc_v1
);
1587 agg_bufs
= (misc
& RX_CMP_AGG_BUFS
) >> RX_CMP_AGG_BUFS_SHIFT
;
1590 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1593 cp_cons
= NEXT_CMP(cp_cons
);
1594 *event
|= BNXT_AGG_EVENT
;
1596 *event
|= BNXT_RX_EVENT
;
1598 rx_buf
->data
= NULL
;
1599 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1600 bnxt_reuse_rx_data(rxr
, cons
, data
);
1602 bnxt_reuse_rx_agg_bufs(cpr
, cp_cons
, agg_bufs
);
1608 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1609 dma_addr
= rx_buf
->mapping
;
1611 if (bnxt_rx_xdp(bp
, rxr
, cons
, data
, &data_ptr
, &len
, event
)) {
1616 if (len
<= bp
->rx_copy_thresh
) {
1617 skb
= bnxt_copy_skb(bnapi
, data_ptr
, len
, dma_addr
);
1618 bnxt_reuse_rx_data(rxr
, cons
, data
);
1626 if (rx_buf
->data_ptr
== data_ptr
)
1627 payload
= misc
& RX_CMP_PAYLOAD_OFFSET
;
1630 skb
= bp
->rx_skb_func(bp
, rxr
, cons
, data
, data_ptr
, dma_addr
,
1639 skb
= bnxt_rx_pages(bp
, cpr
, skb
, cp_cons
, agg_bufs
);
1646 if (RX_CMP_HASH_VALID(rxcmp
)) {
1647 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1648 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1650 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1651 if (hash_type
!= 1 && hash_type
!= 3)
1652 type
= PKT_HASH_TYPE_L3
;
1653 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1656 cfa_code
= RX_CMP_CFA_CODE(rxcmp1
);
1657 skb
->protocol
= eth_type_trans(skb
, bnxt_get_pkt_dev(bp
, cfa_code
));
1659 if ((rxcmp1
->rx_cmp_flags2
&
1660 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) &&
1661 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1662 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1663 u16 vtag
= meta_data
& RX_CMP_FLAGS2_METADATA_TCI_MASK
;
1664 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1666 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1669 skb_checksum_none_assert(skb
);
1670 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1671 if (dev
->features
& NETIF_F_RXCSUM
) {
1672 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1673 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1676 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
) {
1677 if (dev
->features
& NETIF_F_RXCSUM
)
1678 bnapi
->cp_ring
.rx_l4_csum_errors
++;
1682 bnxt_deliver_skb(bp
, bnapi
, skb
);
1686 rxr
->rx_prod
= NEXT_RX(prod
);
1687 rxr
->rx_next_cons
= NEXT_RX(cons
);
1689 cpr
->rx_packets
+= 1;
1690 cpr
->rx_bytes
+= len
;
1692 next_rx_no_prod_no_len
:
1693 *raw_cons
= tmp_raw_cons
;
1698 /* In netpoll mode, if we are using a combined completion ring, we need to
1699 * discard the rx packets and recycle the buffers.
1701 static int bnxt_force_rx_discard(struct bnxt
*bp
,
1702 struct bnxt_cp_ring_info
*cpr
,
1703 u32
*raw_cons
, u8
*event
)
1705 u32 tmp_raw_cons
= *raw_cons
;
1706 struct rx_cmp_ext
*rxcmp1
;
1707 struct rx_cmp
*rxcmp
;
1711 cp_cons
= RING_CMP(tmp_raw_cons
);
1712 rxcmp
= (struct rx_cmp
*)
1713 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1715 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1716 cp_cons
= RING_CMP(tmp_raw_cons
);
1717 rxcmp1
= (struct rx_cmp_ext
*)
1718 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1720 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1723 cmp_type
= RX_CMP_TYPE(rxcmp
);
1724 if (cmp_type
== CMP_TYPE_RX_L2_CMP
) {
1725 rxcmp1
->rx_cmp_cfa_code_errors_v2
|=
1726 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR
);
1727 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1728 struct rx_tpa_end_cmp_ext
*tpa_end1
;
1730 tpa_end1
= (struct rx_tpa_end_cmp_ext
*)rxcmp1
;
1731 tpa_end1
->rx_tpa_end_cmp_errors_v2
|=
1732 cpu_to_le32(RX_TPA_END_CMP_ERRORS
);
1734 return bnxt_rx_pkt(bp
, cpr
, raw_cons
, event
);
1737 #define BNXT_GET_EVENT_PORT(data) \
1739 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1741 static int bnxt_async_event_process(struct bnxt
*bp
,
1742 struct hwrm_async_event_cmpl
*cmpl
)
1744 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1746 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1748 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
: {
1749 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1750 struct bnxt_link_info
*link_info
= &bp
->link_info
;
1753 goto async_event_process_exit
;
1755 /* print unsupported speed warning in forced speed mode only */
1756 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
) &&
1757 (data1
& 0x20000)) {
1758 u16 fw_speed
= link_info
->force_link_speed
;
1759 u32 speed
= bnxt_fw_to_ethtool_speed(fw_speed
);
1761 if (speed
!= SPEED_UNKNOWN
)
1762 netdev_warn(bp
->dev
, "Link speed %d no longer supported\n",
1765 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT
, &bp
->sp_event
);
1768 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1769 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1771 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
:
1772 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
);
1774 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
: {
1775 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1776 u16 port_id
= BNXT_GET_EVENT_PORT(data1
);
1781 if (bp
->pf
.port_id
!= port_id
)
1784 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
);
1787 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE
:
1789 goto async_event_process_exit
;
1790 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT
, &bp
->sp_event
);
1793 goto async_event_process_exit
;
1795 bnxt_queue_sp_work(bp
);
1796 async_event_process_exit
:
1797 bnxt_ulp_async_events(bp
, cmpl
);
1801 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1803 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1804 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1805 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1806 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1808 switch (cmpl_type
) {
1809 case CMPL_BASE_TYPE_HWRM_DONE
:
1810 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1811 if (seq_id
== bp
->hwrm_intr_seq_id
)
1812 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1814 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1817 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1818 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1820 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1821 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1822 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1827 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1828 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1829 bnxt_queue_sp_work(bp
);
1832 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1833 bnxt_async_event_process(bp
,
1834 (struct hwrm_async_event_cmpl
*)txcmp
);
1843 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1845 struct bnxt_napi
*bnapi
= dev_instance
;
1846 struct bnxt
*bp
= bnapi
->bp
;
1847 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1848 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1851 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1852 napi_schedule(&bnapi
->napi
);
1856 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1858 u32 raw_cons
= cpr
->cp_raw_cons
;
1859 u16 cons
= RING_CMP(raw_cons
);
1860 struct tx_cmp
*txcmp
;
1862 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1864 return TX_CMP_VALID(txcmp
, raw_cons
);
1867 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1869 struct bnxt_napi
*bnapi
= dev_instance
;
1870 struct bnxt
*bp
= bnapi
->bp
;
1871 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1872 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1875 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1877 if (!bnxt_has_work(bp
, cpr
)) {
1878 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1879 /* return if erroneous interrupt */
1880 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1884 /* disable ring IRQ */
1885 BNXT_CP_DB_IRQ_DIS(cpr
->cp_db
.doorbell
);
1887 /* Return here if interrupt is shared and is disabled. */
1888 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1891 napi_schedule(&bnapi
->napi
);
1895 static int __bnxt_poll_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
1898 struct bnxt_napi
*bnapi
= cpr
->bnapi
;
1899 u32 raw_cons
= cpr
->cp_raw_cons
;
1904 struct tx_cmp
*txcmp
;
1906 cpr
->has_more_work
= 0;
1910 cons
= RING_CMP(raw_cons
);
1911 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1913 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1916 /* The valid test of the entry must be done first before
1917 * reading any further.
1920 cpr
->had_work_done
= 1;
1921 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1923 /* return full budget so NAPI will complete. */
1924 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
)) {
1926 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1928 cpr
->has_more_work
= 1;
1931 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1933 rc
= bnxt_rx_pkt(bp
, cpr
, &raw_cons
, &event
);
1935 rc
= bnxt_force_rx_discard(bp
, cpr
, &raw_cons
,
1937 if (likely(rc
>= 0))
1939 /* Increment rx_pkts when rc is -ENOMEM to count towards
1940 * the NAPI budget. Otherwise, we may potentially loop
1941 * here forever if we consistently cannot allocate
1944 else if (rc
== -ENOMEM
&& budget
)
1946 else if (rc
== -EBUSY
) /* partial completion */
1948 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1949 CMPL_BASE_TYPE_HWRM_DONE
) ||
1950 (TX_CMP_TYPE(txcmp
) ==
1951 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1952 (TX_CMP_TYPE(txcmp
) ==
1953 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1954 bnxt_hwrm_handler(bp
, txcmp
);
1956 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1958 if (rx_pkts
&& rx_pkts
== budget
) {
1959 cpr
->has_more_work
= 1;
1964 if (event
& BNXT_TX_EVENT
) {
1965 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
1966 u16 prod
= txr
->tx_prod
;
1968 /* Sync BD data before updating doorbell */
1971 bnxt_db_write_relaxed(bp
, &txr
->tx_db
, prod
);
1974 cpr
->cp_raw_cons
= raw_cons
;
1975 bnapi
->tx_pkts
+= tx_pkts
;
1976 bnapi
->events
|= event
;
1980 static void __bnxt_poll_work_done(struct bnxt
*bp
, struct bnxt_napi
*bnapi
)
1982 if (bnapi
->tx_pkts
) {
1983 bnapi
->tx_int(bp
, bnapi
, bnapi
->tx_pkts
);
1987 if (bnapi
->events
& BNXT_RX_EVENT
) {
1988 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1990 bnxt_db_write(bp
, &rxr
->rx_db
, rxr
->rx_prod
);
1991 if (bnapi
->events
& BNXT_AGG_EVENT
)
1992 bnxt_db_write(bp
, &rxr
->rx_agg_db
, rxr
->rx_agg_prod
);
1997 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
2000 struct bnxt_napi
*bnapi
= cpr
->bnapi
;
2003 rx_pkts
= __bnxt_poll_work(bp
, cpr
, budget
);
2005 /* ACK completion ring before freeing tx ring and producing new
2006 * buffers in rx/agg rings to prevent overflowing the completion
2009 bnxt_db_cq(bp
, &cpr
->cp_db
, cpr
->cp_raw_cons
);
2011 __bnxt_poll_work_done(bp
, bnapi
);
2015 static int bnxt_poll_nitroa0(struct napi_struct
*napi
, int budget
)
2017 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
2018 struct bnxt
*bp
= bnapi
->bp
;
2019 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2020 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
2021 struct tx_cmp
*txcmp
;
2022 struct rx_cmp_ext
*rxcmp1
;
2023 u32 cp_cons
, tmp_raw_cons
;
2024 u32 raw_cons
= cpr
->cp_raw_cons
;
2031 cp_cons
= RING_CMP(raw_cons
);
2032 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
2034 if (!TX_CMP_VALID(txcmp
, raw_cons
))
2037 if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
2038 tmp_raw_cons
= NEXT_RAW_CMP(raw_cons
);
2039 cp_cons
= RING_CMP(tmp_raw_cons
);
2040 rxcmp1
= (struct rx_cmp_ext
*)
2041 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
2043 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
2046 /* force an error to recycle the buffer */
2047 rxcmp1
->rx_cmp_cfa_code_errors_v2
|=
2048 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR
);
2050 rc
= bnxt_rx_pkt(bp
, cpr
, &raw_cons
, &event
);
2051 if (likely(rc
== -EIO
) && budget
)
2053 else if (rc
== -EBUSY
) /* partial completion */
2055 } else if (unlikely(TX_CMP_TYPE(txcmp
) ==
2056 CMPL_BASE_TYPE_HWRM_DONE
)) {
2057 bnxt_hwrm_handler(bp
, txcmp
);
2060 "Invalid completion received on special ring\n");
2062 raw_cons
= NEXT_RAW_CMP(raw_cons
);
2064 if (rx_pkts
== budget
)
2068 cpr
->cp_raw_cons
= raw_cons
;
2069 BNXT_DB_CQ(&cpr
->cp_db
, cpr
->cp_raw_cons
);
2070 bnxt_db_write(bp
, &rxr
->rx_db
, rxr
->rx_prod
);
2072 if (event
& BNXT_AGG_EVENT
)
2073 bnxt_db_write(bp
, &rxr
->rx_agg_db
, rxr
->rx_agg_prod
);
2075 if (!bnxt_has_work(bp
, cpr
) && rx_pkts
< budget
) {
2076 napi_complete_done(napi
, rx_pkts
);
2077 BNXT_DB_CQ_ARM(&cpr
->cp_db
, cpr
->cp_raw_cons
);
2082 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
2084 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
2085 struct bnxt
*bp
= bnapi
->bp
;
2086 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2090 work_done
+= bnxt_poll_work(bp
, cpr
, budget
- work_done
);
2092 if (work_done
>= budget
) {
2094 BNXT_DB_CQ_ARM(&cpr
->cp_db
, cpr
->cp_raw_cons
);
2098 if (!bnxt_has_work(bp
, cpr
)) {
2099 if (napi_complete_done(napi
, work_done
))
2100 BNXT_DB_CQ_ARM(&cpr
->cp_db
, cpr
->cp_raw_cons
);
2104 if (bp
->flags
& BNXT_FLAG_DIM
) {
2105 struct net_dim_sample dim_sample
;
2107 net_dim_sample(cpr
->event_ctr
,
2111 net_dim(&cpr
->dim
, dim_sample
);
2117 static int __bnxt_poll_cqs(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
2119 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2120 int i
, work_done
= 0;
2122 for (i
= 0; i
< 2; i
++) {
2123 struct bnxt_cp_ring_info
*cpr2
= cpr
->cp_ring_arr
[i
];
2126 work_done
+= __bnxt_poll_work(bp
, cpr2
,
2127 budget
- work_done
);
2128 cpr
->has_more_work
|= cpr2
->has_more_work
;
2134 static void __bnxt_poll_cqs_done(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
2135 u64 dbr_type
, bool all
)
2137 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2140 for (i
= 0; i
< 2; i
++) {
2141 struct bnxt_cp_ring_info
*cpr2
= cpr
->cp_ring_arr
[i
];
2142 struct bnxt_db_info
*db
;
2144 if (cpr2
&& (all
|| cpr2
->had_work_done
)) {
2146 writeq(db
->db_key64
| dbr_type
|
2147 RING_CMP(cpr2
->cp_raw_cons
), db
->doorbell
);
2148 cpr2
->had_work_done
= 0;
2151 __bnxt_poll_work_done(bp
, bnapi
);
2154 static int bnxt_poll_p5(struct napi_struct
*napi
, int budget
)
2156 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
2157 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2158 u32 raw_cons
= cpr
->cp_raw_cons
;
2159 struct bnxt
*bp
= bnapi
->bp
;
2160 struct nqe_cn
*nqcmp
;
2164 if (cpr
->has_more_work
) {
2165 cpr
->has_more_work
= 0;
2166 work_done
= __bnxt_poll_cqs(bp
, bnapi
, budget
);
2167 if (cpr
->has_more_work
) {
2168 __bnxt_poll_cqs_done(bp
, bnapi
, DBR_TYPE_CQ
, false);
2171 __bnxt_poll_cqs_done(bp
, bnapi
, DBR_TYPE_CQ_ARMALL
, true);
2172 if (napi_complete_done(napi
, work_done
))
2173 BNXT_DB_NQ_ARM_P5(&cpr
->cp_db
, cpr
->cp_raw_cons
);
2177 cons
= RING_CMP(raw_cons
);
2178 nqcmp
= &cpr
->nq_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
2180 if (!NQ_CMP_VALID(nqcmp
, raw_cons
)) {
2181 __bnxt_poll_cqs_done(bp
, bnapi
, DBR_TYPE_CQ_ARMALL
,
2183 cpr
->cp_raw_cons
= raw_cons
;
2184 if (napi_complete_done(napi
, work_done
))
2185 BNXT_DB_NQ_ARM_P5(&cpr
->cp_db
,
2190 /* The valid test of the entry must be done first before
2191 * reading any further.
2195 if (nqcmp
->type
== cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION
)) {
2196 u32 idx
= le32_to_cpu(nqcmp
->cq_handle_low
);
2197 struct bnxt_cp_ring_info
*cpr2
;
2199 cpr2
= cpr
->cp_ring_arr
[idx
];
2200 work_done
+= __bnxt_poll_work(bp
, cpr2
,
2201 budget
- work_done
);
2202 cpr
->has_more_work
= cpr2
->has_more_work
;
2204 bnxt_hwrm_handler(bp
, (struct tx_cmp
*)nqcmp
);
2206 raw_cons
= NEXT_RAW_CMP(raw_cons
);
2207 if (cpr
->has_more_work
)
2210 __bnxt_poll_cqs_done(bp
, bnapi
, DBR_TYPE_CQ
, true);
2211 cpr
->cp_raw_cons
= raw_cons
;
2215 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
2218 struct pci_dev
*pdev
= bp
->pdev
;
2223 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
2224 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2225 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2228 for (j
= 0; j
< max_idx
;) {
2229 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
2230 struct sk_buff
*skb
= tx_buf
->skb
;
2240 if (tx_buf
->is_push
) {
2246 dma_unmap_single(&pdev
->dev
,
2247 dma_unmap_addr(tx_buf
, mapping
),
2251 last
= tx_buf
->nr_frags
;
2253 for (k
= 0; k
< last
; k
++, j
++) {
2254 int ring_idx
= j
& bp
->tx_ring_mask
;
2255 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
2257 tx_buf
= &txr
->tx_buf_ring
[ring_idx
];
2260 dma_unmap_addr(tx_buf
, mapping
),
2261 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
2265 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
2269 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
2271 int i
, max_idx
, max_agg_idx
;
2272 struct pci_dev
*pdev
= bp
->pdev
;
2277 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
2278 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
2279 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2280 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
2284 for (j
= 0; j
< MAX_TPA
; j
++) {
2285 struct bnxt_tpa_info
*tpa_info
=
2287 u8
*data
= tpa_info
->data
;
2292 dma_unmap_single_attrs(&pdev
->dev
,
2294 bp
->rx_buf_use_size
,
2296 DMA_ATTR_WEAK_ORDERING
);
2298 tpa_info
->data
= NULL
;
2304 for (j
= 0; j
< max_idx
; j
++) {
2305 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
2306 dma_addr_t mapping
= rx_buf
->mapping
;
2307 void *data
= rx_buf
->data
;
2312 rx_buf
->data
= NULL
;
2314 if (BNXT_RX_PAGE_MODE(bp
)) {
2315 mapping
-= bp
->rx_dma_offset
;
2316 dma_unmap_page_attrs(&pdev
->dev
, mapping
,
2317 PAGE_SIZE
, bp
->rx_dir
,
2318 DMA_ATTR_WEAK_ORDERING
);
2321 dma_unmap_single_attrs(&pdev
->dev
, mapping
,
2322 bp
->rx_buf_use_size
,
2324 DMA_ATTR_WEAK_ORDERING
);
2329 for (j
= 0; j
< max_agg_idx
; j
++) {
2330 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
2331 &rxr
->rx_agg_ring
[j
];
2332 struct page
*page
= rx_agg_buf
->page
;
2337 dma_unmap_page_attrs(&pdev
->dev
, rx_agg_buf
->mapping
,
2340 DMA_ATTR_WEAK_ORDERING
);
2342 rx_agg_buf
->page
= NULL
;
2343 __clear_bit(j
, rxr
->rx_agg_bmap
);
2348 __free_page(rxr
->rx_page
);
2349 rxr
->rx_page
= NULL
;
2354 static void bnxt_free_skbs(struct bnxt
*bp
)
2356 bnxt_free_tx_skbs(bp
);
2357 bnxt_free_rx_skbs(bp
);
2360 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_mem_info
*rmem
)
2362 struct pci_dev
*pdev
= bp
->pdev
;
2365 for (i
= 0; i
< rmem
->nr_pages
; i
++) {
2366 if (!rmem
->pg_arr
[i
])
2369 dma_free_coherent(&pdev
->dev
, rmem
->page_size
,
2370 rmem
->pg_arr
[i
], rmem
->dma_arr
[i
]);
2372 rmem
->pg_arr
[i
] = NULL
;
2375 dma_free_coherent(&pdev
->dev
, rmem
->nr_pages
* 8,
2376 rmem
->pg_tbl
, rmem
->pg_tbl_map
);
2377 rmem
->pg_tbl
= NULL
;
2379 if (rmem
->vmem_size
&& *rmem
->vmem
) {
2385 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_mem_info
*rmem
)
2387 struct pci_dev
*pdev
= bp
->pdev
;
2391 if (rmem
->flags
& (BNXT_RMEM_VALID_PTE_FLAG
| BNXT_RMEM_RING_PTE_FLAG
))
2392 valid_bit
= PTU_PTE_VALID
;
2393 if (rmem
->nr_pages
> 1) {
2394 rmem
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
2402 for (i
= 0; i
< rmem
->nr_pages
; i
++) {
2403 u64 extra_bits
= valid_bit
;
2405 rmem
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
2409 if (!rmem
->pg_arr
[i
])
2412 if (rmem
->nr_pages
> 1) {
2413 if (i
== rmem
->nr_pages
- 2 &&
2414 (rmem
->flags
& BNXT_RMEM_RING_PTE_FLAG
))
2415 extra_bits
|= PTU_PTE_NEXT_TO_LAST
;
2416 else if (i
== rmem
->nr_pages
- 1 &&
2417 (rmem
->flags
& BNXT_RMEM_RING_PTE_FLAG
))
2418 extra_bits
|= PTU_PTE_LAST
;
2420 cpu_to_le64(rmem
->dma_arr
[i
] | extra_bits
);
2424 if (rmem
->vmem_size
) {
2425 *rmem
->vmem
= vzalloc(rmem
->vmem_size
);
2432 static void bnxt_free_rx_rings(struct bnxt
*bp
)
2439 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2440 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
2441 struct bnxt_ring_struct
*ring
;
2444 bpf_prog_put(rxr
->xdp_prog
);
2446 if (xdp_rxq_info_is_reg(&rxr
->xdp_rxq
))
2447 xdp_rxq_info_unreg(&rxr
->xdp_rxq
);
2452 kfree(rxr
->rx_agg_bmap
);
2453 rxr
->rx_agg_bmap
= NULL
;
2455 ring
= &rxr
->rx_ring_struct
;
2456 bnxt_free_ring(bp
, &ring
->ring_mem
);
2458 ring
= &rxr
->rx_agg_ring_struct
;
2459 bnxt_free_ring(bp
, &ring
->ring_mem
);
2463 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
2465 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
2470 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
2473 if (bp
->flags
& BNXT_FLAG_TPA
)
2476 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2477 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
2478 struct bnxt_ring_struct
*ring
;
2480 ring
= &rxr
->rx_ring_struct
;
2482 rc
= xdp_rxq_info_reg(&rxr
->xdp_rxq
, bp
->dev
, i
);
2486 rc
= bnxt_alloc_ring(bp
, &ring
->ring_mem
);
2494 ring
= &rxr
->rx_agg_ring_struct
;
2495 rc
= bnxt_alloc_ring(bp
, &ring
->ring_mem
);
2500 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
2501 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
2502 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
2503 if (!rxr
->rx_agg_bmap
)
2507 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
2508 sizeof(struct bnxt_tpa_info
),
2518 static void bnxt_free_tx_rings(struct bnxt
*bp
)
2521 struct pci_dev
*pdev
= bp
->pdev
;
2526 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2527 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2528 struct bnxt_ring_struct
*ring
;
2531 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
2532 txr
->tx_push
, txr
->tx_push_mapping
);
2533 txr
->tx_push
= NULL
;
2536 ring
= &txr
->tx_ring_struct
;
2538 bnxt_free_ring(bp
, &ring
->ring_mem
);
2542 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
2545 struct pci_dev
*pdev
= bp
->pdev
;
2547 bp
->tx_push_size
= 0;
2548 if (bp
->tx_push_thresh
) {
2551 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
2552 bp
->tx_push_thresh
);
2554 if (push_size
> 256) {
2556 bp
->tx_push_thresh
= 0;
2559 bp
->tx_push_size
= push_size
;
2562 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
2563 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2564 struct bnxt_ring_struct
*ring
;
2567 ring
= &txr
->tx_ring_struct
;
2569 rc
= bnxt_alloc_ring(bp
, &ring
->ring_mem
);
2573 ring
->grp_idx
= txr
->bnapi
->index
;
2574 if (bp
->tx_push_size
) {
2577 /* One pre-allocated DMA buffer to backup
2580 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
2582 &txr
->tx_push_mapping
,
2588 mapping
= txr
->tx_push_mapping
+
2589 sizeof(struct tx_push_bd
);
2590 txr
->data_mapping
= cpu_to_le64(mapping
);
2592 memset(txr
->tx_push
, 0, sizeof(struct tx_push_bd
));
2594 qidx
= bp
->tc_to_qidx
[j
];
2595 ring
->queue_id
= bp
->q_info
[qidx
].queue_id
;
2596 if (i
< bp
->tx_nr_rings_xdp
)
2598 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
2604 static void bnxt_free_cp_rings(struct bnxt
*bp
)
2611 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2612 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2613 struct bnxt_cp_ring_info
*cpr
;
2614 struct bnxt_ring_struct
*ring
;
2620 cpr
= &bnapi
->cp_ring
;
2621 ring
= &cpr
->cp_ring_struct
;
2623 bnxt_free_ring(bp
, &ring
->ring_mem
);
2625 for (j
= 0; j
< 2; j
++) {
2626 struct bnxt_cp_ring_info
*cpr2
= cpr
->cp_ring_arr
[j
];
2629 ring
= &cpr2
->cp_ring_struct
;
2630 bnxt_free_ring(bp
, &ring
->ring_mem
);
2632 cpr
->cp_ring_arr
[j
] = NULL
;
2638 static struct bnxt_cp_ring_info
*bnxt_alloc_cp_sub_ring(struct bnxt
*bp
)
2640 struct bnxt_ring_mem_info
*rmem
;
2641 struct bnxt_ring_struct
*ring
;
2642 struct bnxt_cp_ring_info
*cpr
;
2645 cpr
= kzalloc(sizeof(*cpr
), GFP_KERNEL
);
2649 ring
= &cpr
->cp_ring_struct
;
2650 rmem
= &ring
->ring_mem
;
2651 rmem
->nr_pages
= bp
->cp_nr_pages
;
2652 rmem
->page_size
= HW_CMPD_RING_SIZE
;
2653 rmem
->pg_arr
= (void **)cpr
->cp_desc_ring
;
2654 rmem
->dma_arr
= cpr
->cp_desc_mapping
;
2655 rmem
->flags
= BNXT_RMEM_RING_PTE_FLAG
;
2656 rc
= bnxt_alloc_ring(bp
, rmem
);
2658 bnxt_free_ring(bp
, rmem
);
2665 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
2667 bool sh
= !!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
);
2668 int i
, rc
, ulp_base_vec
, ulp_msix
;
2670 ulp_msix
= bnxt_get_ulp_msix_num(bp
);
2671 ulp_base_vec
= bnxt_get_ulp_msix_base(bp
);
2672 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2673 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2674 struct bnxt_cp_ring_info
*cpr
;
2675 struct bnxt_ring_struct
*ring
;
2680 cpr
= &bnapi
->cp_ring
;
2682 ring
= &cpr
->cp_ring_struct
;
2684 rc
= bnxt_alloc_ring(bp
, &ring
->ring_mem
);
2688 if (ulp_msix
&& i
>= ulp_base_vec
)
2689 ring
->map_idx
= i
+ ulp_msix
;
2693 if (!(bp
->flags
& BNXT_FLAG_CHIP_P5
))
2696 if (i
< bp
->rx_nr_rings
) {
2697 struct bnxt_cp_ring_info
*cpr2
=
2698 bnxt_alloc_cp_sub_ring(bp
);
2700 cpr
->cp_ring_arr
[BNXT_RX_HDL
] = cpr2
;
2703 cpr2
->bnapi
= bnapi
;
2705 if ((sh
&& i
< bp
->tx_nr_rings
) ||
2706 (!sh
&& i
>= bp
->rx_nr_rings
)) {
2707 struct bnxt_cp_ring_info
*cpr2
=
2708 bnxt_alloc_cp_sub_ring(bp
);
2710 cpr
->cp_ring_arr
[BNXT_TX_HDL
] = cpr2
;
2713 cpr2
->bnapi
= bnapi
;
2719 static void bnxt_init_ring_struct(struct bnxt
*bp
)
2723 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2724 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2725 struct bnxt_ring_mem_info
*rmem
;
2726 struct bnxt_cp_ring_info
*cpr
;
2727 struct bnxt_rx_ring_info
*rxr
;
2728 struct bnxt_tx_ring_info
*txr
;
2729 struct bnxt_ring_struct
*ring
;
2734 cpr
= &bnapi
->cp_ring
;
2735 ring
= &cpr
->cp_ring_struct
;
2736 rmem
= &ring
->ring_mem
;
2737 rmem
->nr_pages
= bp
->cp_nr_pages
;
2738 rmem
->page_size
= HW_CMPD_RING_SIZE
;
2739 rmem
->pg_arr
= (void **)cpr
->cp_desc_ring
;
2740 rmem
->dma_arr
= cpr
->cp_desc_mapping
;
2741 rmem
->vmem_size
= 0;
2743 rxr
= bnapi
->rx_ring
;
2747 ring
= &rxr
->rx_ring_struct
;
2748 rmem
= &ring
->ring_mem
;
2749 rmem
->nr_pages
= bp
->rx_nr_pages
;
2750 rmem
->page_size
= HW_RXBD_RING_SIZE
;
2751 rmem
->pg_arr
= (void **)rxr
->rx_desc_ring
;
2752 rmem
->dma_arr
= rxr
->rx_desc_mapping
;
2753 rmem
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
2754 rmem
->vmem
= (void **)&rxr
->rx_buf_ring
;
2756 ring
= &rxr
->rx_agg_ring_struct
;
2757 rmem
= &ring
->ring_mem
;
2758 rmem
->nr_pages
= bp
->rx_agg_nr_pages
;
2759 rmem
->page_size
= HW_RXBD_RING_SIZE
;
2760 rmem
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
2761 rmem
->dma_arr
= rxr
->rx_agg_desc_mapping
;
2762 rmem
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
2763 rmem
->vmem
= (void **)&rxr
->rx_agg_ring
;
2766 txr
= bnapi
->tx_ring
;
2770 ring
= &txr
->tx_ring_struct
;
2771 rmem
= &ring
->ring_mem
;
2772 rmem
->nr_pages
= bp
->tx_nr_pages
;
2773 rmem
->page_size
= HW_RXBD_RING_SIZE
;
2774 rmem
->pg_arr
= (void **)txr
->tx_desc_ring
;
2775 rmem
->dma_arr
= txr
->tx_desc_mapping
;
2776 rmem
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
2777 rmem
->vmem
= (void **)&txr
->tx_buf_ring
;
2781 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
2785 struct rx_bd
**rx_buf_ring
;
2787 rx_buf_ring
= (struct rx_bd
**)ring
->ring_mem
.pg_arr
;
2788 for (i
= 0, prod
= 0; i
< ring
->ring_mem
.nr_pages
; i
++) {
2792 rxbd
= rx_buf_ring
[i
];
2796 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
2797 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
2798 rxbd
->rx_bd_opaque
= prod
;
2803 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
2805 struct net_device
*dev
= bp
->dev
;
2806 struct bnxt_rx_ring_info
*rxr
;
2807 struct bnxt_ring_struct
*ring
;
2811 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
2812 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
2814 if (NET_IP_ALIGN
== 2)
2815 type
|= RX_BD_FLAGS_SOP
;
2817 rxr
= &bp
->rx_ring
[ring_nr
];
2818 ring
= &rxr
->rx_ring_struct
;
2819 bnxt_init_rxbd_pages(ring
, type
);
2821 if (BNXT_RX_PAGE_MODE(bp
) && bp
->xdp_prog
) {
2822 rxr
->xdp_prog
= bpf_prog_add(bp
->xdp_prog
, 1);
2823 if (IS_ERR(rxr
->xdp_prog
)) {
2824 int rc
= PTR_ERR(rxr
->xdp_prog
);
2826 rxr
->xdp_prog
= NULL
;
2830 prod
= rxr
->rx_prod
;
2831 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
2832 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2833 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
2834 ring_nr
, i
, bp
->rx_ring_size
);
2837 prod
= NEXT_RX(prod
);
2839 rxr
->rx_prod
= prod
;
2840 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2842 ring
= &rxr
->rx_agg_ring_struct
;
2843 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2845 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
2848 type
= ((u32
)BNXT_RX_PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
2849 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
2851 bnxt_init_rxbd_pages(ring
, type
);
2853 prod
= rxr
->rx_agg_prod
;
2854 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
2855 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2856 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
2857 ring_nr
, i
, bp
->rx_ring_size
);
2860 prod
= NEXT_RX_AGG(prod
);
2862 rxr
->rx_agg_prod
= prod
;
2864 if (bp
->flags
& BNXT_FLAG_TPA
) {
2869 for (i
= 0; i
< MAX_TPA
; i
++) {
2870 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
2875 rxr
->rx_tpa
[i
].data
= data
;
2876 rxr
->rx_tpa
[i
].data_ptr
= data
+ bp
->rx_offset
;
2877 rxr
->rx_tpa
[i
].mapping
= mapping
;
2880 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2888 static void bnxt_init_cp_rings(struct bnxt
*bp
)
2892 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2893 struct bnxt_cp_ring_info
*cpr
= &bp
->bnapi
[i
]->cp_ring
;
2894 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
2896 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2897 cpr
->rx_ring_coal
.coal_ticks
= bp
->rx_coal
.coal_ticks
;
2898 cpr
->rx_ring_coal
.coal_bufs
= bp
->rx_coal
.coal_bufs
;
2899 for (j
= 0; j
< 2; j
++) {
2900 struct bnxt_cp_ring_info
*cpr2
= cpr
->cp_ring_arr
[j
];
2905 ring
= &cpr2
->cp_ring_struct
;
2906 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2907 cpr2
->rx_ring_coal
.coal_ticks
= bp
->rx_coal
.coal_ticks
;
2908 cpr2
->rx_ring_coal
.coal_bufs
= bp
->rx_coal
.coal_bufs
;
2913 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2917 if (BNXT_RX_PAGE_MODE(bp
)) {
2918 bp
->rx_offset
= NET_IP_ALIGN
+ XDP_PACKET_HEADROOM
;
2919 bp
->rx_dma_offset
= XDP_PACKET_HEADROOM
;
2921 bp
->rx_offset
= BNXT_RX_OFFSET
;
2922 bp
->rx_dma_offset
= BNXT_RX_DMA_OFFSET
;
2925 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2926 rc
= bnxt_init_one_rx_ring(bp
, i
);
2934 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2938 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2941 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2942 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2943 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2945 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2951 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2953 kfree(bp
->grp_info
);
2954 bp
->grp_info
= NULL
;
2957 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2962 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2963 sizeof(struct bnxt_ring_grp_info
),
2968 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2970 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2971 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2972 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2973 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2974 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2979 static void bnxt_free_vnics(struct bnxt
*bp
)
2981 kfree(bp
->vnic_info
);
2982 bp
->vnic_info
= NULL
;
2986 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2990 #ifdef CONFIG_RFS_ACCEL
2991 if (bp
->flags
& BNXT_FLAG_RFS
)
2992 num_vnics
+= bp
->rx_nr_rings
;
2995 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
2998 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
3003 bp
->nr_vnics
= num_vnics
;
3007 static void bnxt_init_vnics(struct bnxt
*bp
)
3011 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3012 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3015 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
3016 for (j
= 0; j
< BNXT_MAX_CTX_PER_VNIC
; j
++)
3017 vnic
->fw_rss_cos_lb_ctx
[j
] = INVALID_HW_RING_ID
;
3019 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
3021 if (bp
->vnic_info
[i
].rss_hash_key
) {
3023 prandom_bytes(vnic
->rss_hash_key
,
3026 memcpy(vnic
->rss_hash_key
,
3027 bp
->vnic_info
[0].rss_hash_key
,
3033 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
3037 pages
= ring_size
/ desc_per_pg
;
3044 while (pages
& (pages
- 1))
3050 void bnxt_set_tpa_flags(struct bnxt
*bp
)
3052 bp
->flags
&= ~BNXT_FLAG_TPA
;
3053 if (bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)
3055 if (bp
->dev
->features
& NETIF_F_LRO
)
3056 bp
->flags
|= BNXT_FLAG_LRO
;
3057 else if (bp
->dev
->features
& NETIF_F_GRO_HW
)
3058 bp
->flags
|= BNXT_FLAG_GRO
;
3061 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3064 void bnxt_set_ring_params(struct bnxt
*bp
)
3066 u32 ring_size
, rx_size
, rx_space
;
3067 u32 agg_factor
= 0, agg_ring_size
= 0;
3069 /* 8 for CRC and VLAN */
3070 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
3072 rx_space
= rx_size
+ NET_SKB_PAD
+
3073 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
3075 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
3076 ring_size
= bp
->rx_ring_size
;
3077 bp
->rx_agg_ring_size
= 0;
3078 bp
->rx_agg_nr_pages
= 0;
3080 if (bp
->flags
& BNXT_FLAG_TPA
)
3081 agg_factor
= min_t(u32
, 4, 65536 / BNXT_RX_PAGE_SIZE
);
3083 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
3084 if (rx_space
> PAGE_SIZE
&& !(bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)) {
3087 bp
->flags
|= BNXT_FLAG_JUMBO
;
3088 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
3089 if (jumbo_factor
> agg_factor
)
3090 agg_factor
= jumbo_factor
;
3092 agg_ring_size
= ring_size
* agg_factor
;
3094 if (agg_ring_size
) {
3095 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
3097 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
3098 u32 tmp
= agg_ring_size
;
3100 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
3101 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
3102 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
3103 tmp
, agg_ring_size
);
3105 bp
->rx_agg_ring_size
= agg_ring_size
;
3106 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
3107 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
3108 rx_space
= rx_size
+ NET_SKB_PAD
+
3109 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
3112 bp
->rx_buf_use_size
= rx_size
;
3113 bp
->rx_buf_size
= rx_space
;
3115 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
3116 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
3118 ring_size
= bp
->tx_ring_size
;
3119 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
3120 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
3122 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
3123 bp
->cp_ring_size
= ring_size
;
3125 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
3126 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
3127 bp
->cp_nr_pages
= MAX_CP_PAGES
;
3128 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
3129 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
3130 ring_size
, bp
->cp_ring_size
);
3132 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
3133 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
3136 /* Changing allocation mode of RX rings.
3137 * TODO: Update when extending xdp_rxq_info to support allocation modes.
3139 int bnxt_set_rx_skb_mode(struct bnxt
*bp
, bool page_mode
)
3142 if (bp
->dev
->mtu
> BNXT_MAX_PAGE_MODE_MTU
)
3145 min_t(u16
, bp
->max_mtu
, BNXT_MAX_PAGE_MODE_MTU
);
3146 bp
->flags
&= ~BNXT_FLAG_AGG_RINGS
;
3147 bp
->flags
|= BNXT_FLAG_NO_AGG_RINGS
| BNXT_FLAG_RX_PAGE_MODE
;
3148 bp
->rx_dir
= DMA_BIDIRECTIONAL
;
3149 bp
->rx_skb_func
= bnxt_rx_page_skb
;
3150 /* Disable LRO or GRO_HW */
3151 netdev_update_features(bp
->dev
);
3153 bp
->dev
->max_mtu
= bp
->max_mtu
;
3154 bp
->flags
&= ~BNXT_FLAG_RX_PAGE_MODE
;
3155 bp
->rx_dir
= DMA_FROM_DEVICE
;
3156 bp
->rx_skb_func
= bnxt_rx_skb
;
3161 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
3164 struct bnxt_vnic_info
*vnic
;
3165 struct pci_dev
*pdev
= bp
->pdev
;
3170 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3171 vnic
= &bp
->vnic_info
[i
];
3173 kfree(vnic
->fw_grp_ids
);
3174 vnic
->fw_grp_ids
= NULL
;
3176 kfree(vnic
->uc_list
);
3177 vnic
->uc_list
= NULL
;
3179 if (vnic
->mc_list
) {
3180 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
3181 vnic
->mc_list
, vnic
->mc_list_mapping
);
3182 vnic
->mc_list
= NULL
;
3185 if (vnic
->rss_table
) {
3186 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
3188 vnic
->rss_table_dma_addr
);
3189 vnic
->rss_table
= NULL
;
3192 vnic
->rss_hash_key
= NULL
;
3197 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
3199 int i
, rc
= 0, size
;
3200 struct bnxt_vnic_info
*vnic
;
3201 struct pci_dev
*pdev
= bp
->pdev
;
3204 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3205 vnic
= &bp
->vnic_info
[i
];
3207 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
3208 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
3211 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
3212 if (!vnic
->uc_list
) {
3219 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
3220 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
3222 dma_alloc_coherent(&pdev
->dev
,
3224 &vnic
->mc_list_mapping
,
3226 if (!vnic
->mc_list
) {
3232 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
3233 goto vnic_skip_grps
;
3235 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3236 max_rings
= bp
->rx_nr_rings
;
3240 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
3241 if (!vnic
->fw_grp_ids
) {
3246 if ((bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
) &&
3247 !(vnic
->flags
& BNXT_VNIC_RSS_FLAG
))
3250 /* Allocate rss table and hash key */
3251 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
3252 &vnic
->rss_table_dma_addr
,
3254 if (!vnic
->rss_table
) {
3259 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
3261 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
3262 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
3270 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
3272 struct pci_dev
*pdev
= bp
->pdev
;
3274 if (bp
->hwrm_cmd_resp_addr
) {
3275 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
3276 bp
->hwrm_cmd_resp_dma_addr
);
3277 bp
->hwrm_cmd_resp_addr
= NULL
;
3281 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
3283 struct pci_dev
*pdev
= bp
->pdev
;
3285 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
3286 &bp
->hwrm_cmd_resp_dma_addr
,
3288 if (!bp
->hwrm_cmd_resp_addr
)
3294 static void bnxt_free_hwrm_short_cmd_req(struct bnxt
*bp
)
3296 if (bp
->hwrm_short_cmd_req_addr
) {
3297 struct pci_dev
*pdev
= bp
->pdev
;
3299 dma_free_coherent(&pdev
->dev
, bp
->hwrm_max_ext_req_len
,
3300 bp
->hwrm_short_cmd_req_addr
,
3301 bp
->hwrm_short_cmd_req_dma_addr
);
3302 bp
->hwrm_short_cmd_req_addr
= NULL
;
3306 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt
*bp
)
3308 struct pci_dev
*pdev
= bp
->pdev
;
3310 bp
->hwrm_short_cmd_req_addr
=
3311 dma_alloc_coherent(&pdev
->dev
, bp
->hwrm_max_ext_req_len
,
3312 &bp
->hwrm_short_cmd_req_dma_addr
,
3314 if (!bp
->hwrm_short_cmd_req_addr
)
3320 static void bnxt_free_stats(struct bnxt
*bp
)
3323 struct pci_dev
*pdev
= bp
->pdev
;
3325 bp
->flags
&= ~BNXT_FLAG_PORT_STATS
;
3326 bp
->flags
&= ~BNXT_FLAG_PORT_STATS_EXT
;
3328 if (bp
->hw_rx_port_stats
) {
3329 dma_free_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
3330 bp
->hw_rx_port_stats
,
3331 bp
->hw_rx_port_stats_map
);
3332 bp
->hw_rx_port_stats
= NULL
;
3335 if (bp
->hw_tx_port_stats_ext
) {
3336 dma_free_coherent(&pdev
->dev
, sizeof(struct tx_port_stats_ext
),
3337 bp
->hw_tx_port_stats_ext
,
3338 bp
->hw_tx_port_stats_ext_map
);
3339 bp
->hw_tx_port_stats_ext
= NULL
;
3342 if (bp
->hw_rx_port_stats_ext
) {
3343 dma_free_coherent(&pdev
->dev
, sizeof(struct rx_port_stats_ext
),
3344 bp
->hw_rx_port_stats_ext
,
3345 bp
->hw_rx_port_stats_ext_map
);
3346 bp
->hw_rx_port_stats_ext
= NULL
;
3352 size
= sizeof(struct ctx_hw_stats
);
3354 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3355 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3356 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3358 if (cpr
->hw_stats
) {
3359 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
3361 cpr
->hw_stats
= NULL
;
3366 static int bnxt_alloc_stats(struct bnxt
*bp
)
3369 struct pci_dev
*pdev
= bp
->pdev
;
3371 size
= sizeof(struct ctx_hw_stats
);
3373 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3374 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3375 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3377 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
3383 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
3386 if (BNXT_PF(bp
) && bp
->chip_num
!= CHIP_NUM_58700
) {
3387 bp
->hw_port_stats_size
= sizeof(struct rx_port_stats
) +
3388 sizeof(struct tx_port_stats
) + 1024;
3390 bp
->hw_rx_port_stats
=
3391 dma_alloc_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
3392 &bp
->hw_rx_port_stats_map
,
3394 if (!bp
->hw_rx_port_stats
)
3397 bp
->hw_tx_port_stats
= (void *)(bp
->hw_rx_port_stats
+ 1) +
3399 bp
->hw_tx_port_stats_map
= bp
->hw_rx_port_stats_map
+
3400 sizeof(struct rx_port_stats
) + 512;
3401 bp
->flags
|= BNXT_FLAG_PORT_STATS
;
3403 /* Display extended statistics only if FW supports it */
3404 if (bp
->hwrm_spec_code
< 0x10804 ||
3405 bp
->hwrm_spec_code
== 0x10900)
3408 bp
->hw_rx_port_stats_ext
=
3409 dma_zalloc_coherent(&pdev
->dev
,
3410 sizeof(struct rx_port_stats_ext
),
3411 &bp
->hw_rx_port_stats_ext_map
,
3413 if (!bp
->hw_rx_port_stats_ext
)
3416 if (bp
->hwrm_spec_code
>= 0x10902) {
3417 bp
->hw_tx_port_stats_ext
=
3418 dma_zalloc_coherent(&pdev
->dev
,
3419 sizeof(struct tx_port_stats_ext
),
3420 &bp
->hw_tx_port_stats_ext_map
,
3423 bp
->flags
|= BNXT_FLAG_PORT_STATS_EXT
;
3428 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
3435 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3436 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3437 struct bnxt_cp_ring_info
*cpr
;
3438 struct bnxt_rx_ring_info
*rxr
;
3439 struct bnxt_tx_ring_info
*txr
;
3444 cpr
= &bnapi
->cp_ring
;
3445 cpr
->cp_raw_cons
= 0;
3447 txr
= bnapi
->tx_ring
;
3453 rxr
= bnapi
->rx_ring
;
3456 rxr
->rx_agg_prod
= 0;
3457 rxr
->rx_sw_agg_prod
= 0;
3458 rxr
->rx_next_cons
= 0;
3463 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
3465 #ifdef CONFIG_RFS_ACCEL
3468 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3469 * safe to delete the hash table.
3471 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
3472 struct hlist_head
*head
;
3473 struct hlist_node
*tmp
;
3474 struct bnxt_ntuple_filter
*fltr
;
3476 head
= &bp
->ntp_fltr_hash_tbl
[i
];
3477 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
3478 hlist_del(&fltr
->hash
);
3483 kfree(bp
->ntp_fltr_bmap
);
3484 bp
->ntp_fltr_bmap
= NULL
;
3486 bp
->ntp_fltr_count
= 0;
3490 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
3492 #ifdef CONFIG_RFS_ACCEL
3495 if (!(bp
->flags
& BNXT_FLAG_RFS
))
3498 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
3499 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
3501 bp
->ntp_fltr_count
= 0;
3502 bp
->ntp_fltr_bmap
= kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
3506 if (!bp
->ntp_fltr_bmap
)
3515 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
3517 bnxt_free_vnic_attributes(bp
);
3518 bnxt_free_tx_rings(bp
);
3519 bnxt_free_rx_rings(bp
);
3520 bnxt_free_cp_rings(bp
);
3521 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
3523 bnxt_free_stats(bp
);
3524 bnxt_free_ring_grps(bp
);
3525 bnxt_free_vnics(bp
);
3526 kfree(bp
->tx_ring_map
);
3527 bp
->tx_ring_map
= NULL
;
3535 bnxt_clear_ring_indices(bp
);
3539 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
3541 int i
, j
, rc
, size
, arr_size
;
3545 /* Allocate bnapi mem pointer array and mem block for
3548 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
3550 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
3551 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
3557 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
3558 bp
->bnapi
[i
] = bnapi
;
3559 bp
->bnapi
[i
]->index
= i
;
3560 bp
->bnapi
[i
]->bp
= bp
;
3561 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
3562 struct bnxt_cp_ring_info
*cpr
=
3563 &bp
->bnapi
[i
]->cp_ring
;
3565 cpr
->cp_ring_struct
.ring_mem
.flags
=
3566 BNXT_RMEM_RING_PTE_FLAG
;
3570 bp
->rx_ring
= kcalloc(bp
->rx_nr_rings
,
3571 sizeof(struct bnxt_rx_ring_info
),
3576 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3577 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3579 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
3580 rxr
->rx_ring_struct
.ring_mem
.flags
=
3581 BNXT_RMEM_RING_PTE_FLAG
;
3582 rxr
->rx_agg_ring_struct
.ring_mem
.flags
=
3583 BNXT_RMEM_RING_PTE_FLAG
;
3585 rxr
->bnapi
= bp
->bnapi
[i
];
3586 bp
->bnapi
[i
]->rx_ring
= &bp
->rx_ring
[i
];
3589 bp
->tx_ring
= kcalloc(bp
->tx_nr_rings
,
3590 sizeof(struct bnxt_tx_ring_info
),
3595 bp
->tx_ring_map
= kcalloc(bp
->tx_nr_rings
, sizeof(u16
),
3598 if (!bp
->tx_ring_map
)
3601 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
3604 j
= bp
->rx_nr_rings
;
3606 for (i
= 0; i
< bp
->tx_nr_rings
; i
++, j
++) {
3607 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3609 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
3610 txr
->tx_ring_struct
.ring_mem
.flags
=
3611 BNXT_RMEM_RING_PTE_FLAG
;
3612 txr
->bnapi
= bp
->bnapi
[j
];
3613 bp
->bnapi
[j
]->tx_ring
= txr
;
3614 bp
->tx_ring_map
[i
] = bp
->tx_nr_rings_xdp
+ i
;
3615 if (i
>= bp
->tx_nr_rings_xdp
) {
3616 txr
->txq_index
= i
- bp
->tx_nr_rings_xdp
;
3617 bp
->bnapi
[j
]->tx_int
= bnxt_tx_int
;
3619 bp
->bnapi
[j
]->flags
|= BNXT_NAPI_FLAG_XDP
;
3620 bp
->bnapi
[j
]->tx_int
= bnxt_tx_int_xdp
;
3624 rc
= bnxt_alloc_stats(bp
);
3628 rc
= bnxt_alloc_ntp_fltrs(bp
);
3632 rc
= bnxt_alloc_vnics(bp
);
3637 bnxt_init_ring_struct(bp
);
3639 rc
= bnxt_alloc_rx_rings(bp
);
3643 rc
= bnxt_alloc_tx_rings(bp
);
3647 rc
= bnxt_alloc_cp_rings(bp
);
3651 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
3652 BNXT_VNIC_UCAST_FLAG
;
3653 rc
= bnxt_alloc_vnic_attributes(bp
);
3659 bnxt_free_mem(bp
, true);
3663 static void bnxt_disable_int(struct bnxt
*bp
)
3670 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3671 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3672 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3673 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3675 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
)
3676 bnxt_db_nq(bp
, &cpr
->cp_db
, cpr
->cp_raw_cons
);
3680 static int bnxt_cp_num_to_irq_num(struct bnxt
*bp
, int n
)
3682 struct bnxt_napi
*bnapi
= bp
->bnapi
[n
];
3683 struct bnxt_cp_ring_info
*cpr
;
3685 cpr
= &bnapi
->cp_ring
;
3686 return cpr
->cp_ring_struct
.map_idx
;
3689 static void bnxt_disable_int_sync(struct bnxt
*bp
)
3693 atomic_inc(&bp
->intr_sem
);
3695 bnxt_disable_int(bp
);
3696 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3697 int map_idx
= bnxt_cp_num_to_irq_num(bp
, i
);
3699 synchronize_irq(bp
->irq_tbl
[map_idx
].vector
);
3703 static void bnxt_enable_int(struct bnxt
*bp
)
3707 atomic_set(&bp
->intr_sem
, 0);
3708 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3709 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3710 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3712 bnxt_db_nq_arm(bp
, &cpr
->cp_db
, cpr
->cp_raw_cons
);
3716 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
3717 u16 cmpl_ring
, u16 target_id
)
3719 struct input
*req
= request
;
3721 req
->req_type
= cpu_to_le16(req_type
);
3722 req
->cmpl_ring
= cpu_to_le16(cmpl_ring
);
3723 req
->target_id
= cpu_to_le16(target_id
);
3724 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
3727 static int bnxt_hwrm_do_send_msg(struct bnxt
*bp
, void *msg
, u32 msg_len
,
3728 int timeout
, bool silent
)
3730 int i
, intr_process
, rc
, tmo_count
;
3731 struct input
*req
= msg
;
3735 u16 cp_ring_id
, len
= 0;
3736 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3737 u16 max_req_len
= BNXT_HWRM_MAX_REQ_LEN
;
3738 struct hwrm_short_input short_input
= {0};
3740 req
->seq_id
= cpu_to_le16(bp
->hwrm_cmd_seq
++);
3741 memset(resp
, 0, PAGE_SIZE
);
3742 cp_ring_id
= le16_to_cpu(req
->cmpl_ring
);
3743 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
3745 if (msg_len
> BNXT_HWRM_MAX_REQ_LEN
) {
3746 if (msg_len
> bp
->hwrm_max_ext_req_len
||
3747 !bp
->hwrm_short_cmd_req_addr
)
3751 if ((bp
->fw_cap
& BNXT_FW_CAP_SHORT_CMD
) ||
3752 msg_len
> BNXT_HWRM_MAX_REQ_LEN
) {
3753 void *short_cmd_req
= bp
->hwrm_short_cmd_req_addr
;
3756 /* Set boundary for maximum extended request length for short
3757 * cmd format. If passed up from device use the max supported
3758 * internal req length.
3760 max_msg_len
= bp
->hwrm_max_ext_req_len
;
3762 memcpy(short_cmd_req
, req
, msg_len
);
3763 if (msg_len
< max_msg_len
)
3764 memset(short_cmd_req
+ msg_len
, 0,
3765 max_msg_len
- msg_len
);
3767 short_input
.req_type
= req
->req_type
;
3768 short_input
.signature
=
3769 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD
);
3770 short_input
.size
= cpu_to_le16(msg_len
);
3771 short_input
.req_addr
=
3772 cpu_to_le64(bp
->hwrm_short_cmd_req_dma_addr
);
3774 data
= (u32
*)&short_input
;
3775 msg_len
= sizeof(short_input
);
3777 /* Sync memory write before updating doorbell */
3780 max_req_len
= BNXT_HWRM_SHORT_REQ_LEN
;
3783 /* Write request msg to hwrm channel */
3784 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
3786 for (i
= msg_len
; i
< max_req_len
; i
+= 4)
3787 writel(0, bp
->bar0
+ i
);
3789 /* currently supports only one outstanding message */
3791 bp
->hwrm_intr_seq_id
= le16_to_cpu(req
->seq_id
);
3793 /* Ring channel doorbell */
3794 writel(1, bp
->bar0
+ 0x100);
3797 timeout
= DFLT_HWRM_CMD_TIMEOUT
;
3798 /* convert timeout to usec */
3802 /* Short timeout for the first few iterations:
3803 * number of loops = number of loops for short timeout +
3804 * number of loops for standard timeout.
3806 tmo_count
= HWRM_SHORT_TIMEOUT_COUNTER
;
3807 timeout
= timeout
- HWRM_SHORT_MIN_TIMEOUT
* HWRM_SHORT_TIMEOUT_COUNTER
;
3808 tmo_count
+= DIV_ROUND_UP(timeout
, HWRM_MIN_TIMEOUT
);
3809 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
3811 /* Wait until hwrm response cmpl interrupt is processed */
3812 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
3814 /* on first few passes, just barely sleep */
3815 if (i
< HWRM_SHORT_TIMEOUT_COUNTER
)
3816 usleep_range(HWRM_SHORT_MIN_TIMEOUT
,
3817 HWRM_SHORT_MAX_TIMEOUT
);
3819 usleep_range(HWRM_MIN_TIMEOUT
,
3823 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
3824 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
3825 le16_to_cpu(req
->req_type
));
3828 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
3830 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 1;
3834 /* Check if response len is updated */
3835 for (i
= 0; i
< tmo_count
; i
++) {
3836 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
3840 /* on first few passes, just barely sleep */
3841 if (i
< DFLT_HWRM_CMD_TIMEOUT
)
3842 usleep_range(HWRM_SHORT_MIN_TIMEOUT
,
3843 HWRM_SHORT_MAX_TIMEOUT
);
3845 usleep_range(HWRM_MIN_TIMEOUT
,
3849 if (i
>= tmo_count
) {
3850 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3851 HWRM_TOTAL_TIMEOUT(i
),
3852 le16_to_cpu(req
->req_type
),
3853 le16_to_cpu(req
->seq_id
), len
);
3857 /* Last byte of resp contains valid bit */
3858 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 1;
3859 for (j
= 0; j
< HWRM_VALID_BIT_DELAY_USEC
; j
++) {
3860 /* make sure we read from updated DMA memory */
3867 if (j
>= HWRM_VALID_BIT_DELAY_USEC
) {
3868 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3869 HWRM_TOTAL_TIMEOUT(i
),
3870 le16_to_cpu(req
->req_type
),
3871 le16_to_cpu(req
->seq_id
), len
, *valid
);
3876 /* Zero valid bit for compatibility. Valid bit in an older spec
3877 * may become a new field in a newer spec. We must make sure that
3878 * a new field not implemented by old spec will read zero.
3881 rc
= le16_to_cpu(resp
->error_code
);
3883 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3884 le16_to_cpu(resp
->req_type
),
3885 le16_to_cpu(resp
->seq_id
), rc
);
3889 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
3891 return bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, false);
3894 int _hwrm_send_message_silent(struct bnxt
*bp
, void *msg
, u32 msg_len
,
3897 return bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, true);
3900 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
3904 mutex_lock(&bp
->hwrm_cmd_lock
);
3905 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
3906 mutex_unlock(&bp
->hwrm_cmd_lock
);
3910 int hwrm_send_message_silent(struct bnxt
*bp
, void *msg
, u32 msg_len
,
3915 mutex_lock(&bp
->hwrm_cmd_lock
);
3916 rc
= bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, true);
3917 mutex_unlock(&bp
->hwrm_cmd_lock
);
3921 int bnxt_hwrm_func_rgtr_async_events(struct bnxt
*bp
, unsigned long *bmap
,
3924 struct hwrm_func_drv_rgtr_input req
= {0};
3925 DECLARE_BITMAP(async_events_bmap
, 256);
3926 u32
*events
= (u32
*)async_events_bmap
;
3929 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
3932 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
3934 memset(async_events_bmap
, 0, sizeof(async_events_bmap
));
3935 for (i
= 0; i
< ARRAY_SIZE(bnxt_async_events_arr
); i
++)
3936 __set_bit(bnxt_async_events_arr
[i
], async_events_bmap
);
3938 if (bmap
&& bmap_size
) {
3939 for (i
= 0; i
< bmap_size
; i
++) {
3940 if (test_bit(i
, bmap
))
3941 __set_bit(i
, async_events_bmap
);
3945 for (i
= 0; i
< 8; i
++)
3946 req
.async_event_fwd
[i
] |= cpu_to_le32(events
[i
]);
3948 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3951 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
3953 struct hwrm_func_drv_rgtr_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3954 struct hwrm_func_drv_rgtr_input req
= {0};
3957 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
3960 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
3961 FUNC_DRV_RGTR_REQ_ENABLES_VER
);
3963 req
.os_type
= cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX
);
3964 req
.flags
= cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE
);
3965 req
.ver_maj_8b
= DRV_VER_MAJ
;
3966 req
.ver_min_8b
= DRV_VER_MIN
;
3967 req
.ver_upd_8b
= DRV_VER_UPD
;
3968 req
.ver_maj
= cpu_to_le16(DRV_VER_MAJ
);
3969 req
.ver_min
= cpu_to_le16(DRV_VER_MIN
);
3970 req
.ver_upd
= cpu_to_le16(DRV_VER_UPD
);
3976 memset(data
, 0, sizeof(data
));
3977 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++) {
3978 u16 cmd
= bnxt_vf_req_snif
[i
];
3979 unsigned int bit
, idx
;
3983 data
[idx
] |= 1 << bit
;
3986 for (i
= 0; i
< 8; i
++)
3987 req
.vf_req_fwd
[i
] = cpu_to_le32(data
[i
]);
3990 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
3993 mutex_lock(&bp
->hwrm_cmd_lock
);
3994 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3997 else if (resp
->flags
&
3998 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED
))
3999 bp
->fw_cap
|= BNXT_FW_CAP_IF_CHANGE
;
4000 mutex_unlock(&bp
->hwrm_cmd_lock
);
4004 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt
*bp
)
4006 struct hwrm_func_drv_unrgtr_input req
= {0};
4008 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_UNRGTR
, -1, -1);
4009 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4012 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
4015 struct hwrm_tunnel_dst_port_free_input req
= {0};
4017 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
4018 req
.tunnel_type
= tunnel_type
;
4020 switch (tunnel_type
) {
4021 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
4022 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
4024 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
4025 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
4031 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4033 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4038 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
4042 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
4043 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4045 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
4047 req
.tunnel_type
= tunnel_type
;
4048 req
.tunnel_dst_port_val
= port
;
4050 mutex_lock(&bp
->hwrm_cmd_lock
);
4051 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4053 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4058 switch (tunnel_type
) {
4059 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
:
4060 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
4062 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
:
4063 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
4070 mutex_unlock(&bp
->hwrm_cmd_lock
);
4074 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
4076 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
4077 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
4079 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
4080 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
4082 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
4083 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
4084 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
4085 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4088 #ifdef CONFIG_RFS_ACCEL
4089 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
4090 struct bnxt_ntuple_filter
*fltr
)
4092 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
4094 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
4095 req
.ntuple_filter_id
= fltr
->filter_id
;
4096 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4099 #define BNXT_NTP_FLTR_FLAGS \
4100 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
4101 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
4102 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
4103 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
4104 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
4105 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
4106 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
4107 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
4108 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
4109 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
4110 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
4111 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
4112 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
4113 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4115 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
4116 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4118 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
4119 struct bnxt_ntuple_filter
*fltr
)
4122 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
4123 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
4124 bp
->hwrm_cmd_resp_addr
;
4125 struct flow_keys
*keys
= &fltr
->fkeys
;
4126 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
4128 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
4129 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[fltr
->l2_fltr_idx
];
4131 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
4133 req
.ethertype
= htons(ETH_P_IP
);
4134 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
4135 req
.ip_addr_type
= CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4
;
4136 req
.ip_protocol
= keys
->basic
.ip_proto
;
4138 if (keys
->basic
.n_proto
== htons(ETH_P_IPV6
)) {
4141 req
.ethertype
= htons(ETH_P_IPV6
);
4143 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
;
4144 *(struct in6_addr
*)&req
.src_ipaddr
[0] =
4145 keys
->addrs
.v6addrs
.src
;
4146 *(struct in6_addr
*)&req
.dst_ipaddr
[0] =
4147 keys
->addrs
.v6addrs
.dst
;
4148 for (i
= 0; i
< 4; i
++) {
4149 req
.src_ipaddr_mask
[i
] = cpu_to_be32(0xffffffff);
4150 req
.dst_ipaddr_mask
[i
] = cpu_to_be32(0xffffffff);
4153 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
4154 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
4155 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
4156 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
4158 if (keys
->control
.flags
& FLOW_DIS_ENCAPSULATION
) {
4159 req
.enables
|= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG
);
4161 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
;
4164 req
.src_port
= keys
->ports
.src
;
4165 req
.src_port_mask
= cpu_to_be16(0xffff);
4166 req
.dst_port
= keys
->ports
.dst
;
4167 req
.dst_port_mask
= cpu_to_be16(0xffff);
4169 req
.dst_id
= cpu_to_le16(vnic
->fw_vnic_id
);
4170 mutex_lock(&bp
->hwrm_cmd_lock
);
4171 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4173 fltr
->filter_id
= resp
->ntuple_filter_id
;
4174 mutex_unlock(&bp
->hwrm_cmd_lock
);
4179 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
4183 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
4184 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4186 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
4187 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
);
4188 if (!BNXT_CHIP_TYPE_NITRO_A0(bp
))
4190 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
4191 req
.dst_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
4193 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
4194 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
|
4195 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
4196 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
4197 req
.l2_addr_mask
[0] = 0xff;
4198 req
.l2_addr_mask
[1] = 0xff;
4199 req
.l2_addr_mask
[2] = 0xff;
4200 req
.l2_addr_mask
[3] = 0xff;
4201 req
.l2_addr_mask
[4] = 0xff;
4202 req
.l2_addr_mask
[5] = 0xff;
4204 mutex_lock(&bp
->hwrm_cmd_lock
);
4205 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4207 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
4209 mutex_unlock(&bp
->hwrm_cmd_lock
);
4213 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
4215 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
4218 /* Any associated ntuple filters will also be cleared by firmware. */
4219 mutex_lock(&bp
->hwrm_cmd_lock
);
4220 for (i
= 0; i
< num_of_vnics
; i
++) {
4221 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
4223 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
4224 struct hwrm_cfa_l2_filter_free_input req
= {0};
4226 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
4227 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
4229 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
4231 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4234 vnic
->uc_filter_count
= 0;
4236 mutex_unlock(&bp
->hwrm_cmd_lock
);
4241 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
4243 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
4244 struct hwrm_vnic_tpa_cfg_input req
= {0};
4246 if (vnic
->fw_vnic_id
== INVALID_HW_RING_ID
)
4249 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
4252 u16 mss
= bp
->dev
->mtu
- 40;
4253 u32 nsegs
, n
, segs
= 0, flags
;
4255 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
4256 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
4257 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
4258 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
4259 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
4260 if (tpa_flags
& BNXT_FLAG_GRO
)
4261 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
4263 req
.flags
= cpu_to_le32(flags
);
4266 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
4267 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
|
4268 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
);
4270 /* Number of segs are log2 units, and first packet is not
4271 * included as part of this units.
4273 if (mss
<= BNXT_RX_PAGE_SIZE
) {
4274 n
= BNXT_RX_PAGE_SIZE
/ mss
;
4275 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
4277 n
= mss
/ BNXT_RX_PAGE_SIZE
;
4278 if (mss
& (BNXT_RX_PAGE_SIZE
- 1))
4280 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
4283 segs
= ilog2(nsegs
);
4284 req
.max_agg_segs
= cpu_to_le16(segs
);
4285 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
4287 req
.min_agg_len
= cpu_to_le32(512);
4289 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
4291 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4294 static u16
bnxt_cp_ring_from_grp(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
4296 struct bnxt_ring_grp_info
*grp_info
;
4298 grp_info
= &bp
->grp_info
[ring
->grp_idx
];
4299 return grp_info
->cp_fw_ring_id
;
4302 static u16
bnxt_cp_ring_for_rx(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
)
4304 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
4305 struct bnxt_napi
*bnapi
= rxr
->bnapi
;
4306 struct bnxt_cp_ring_info
*cpr
;
4308 cpr
= bnapi
->cp_ring
.cp_ring_arr
[BNXT_RX_HDL
];
4309 return cpr
->cp_ring_struct
.fw_ring_id
;
4311 return bnxt_cp_ring_from_grp(bp
, &rxr
->rx_ring_struct
);
4315 static u16
bnxt_cp_ring_for_tx(struct bnxt
*bp
, struct bnxt_tx_ring_info
*txr
)
4317 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
4318 struct bnxt_napi
*bnapi
= txr
->bnapi
;
4319 struct bnxt_cp_ring_info
*cpr
;
4321 cpr
= bnapi
->cp_ring
.cp_ring_arr
[BNXT_TX_HDL
];
4322 return cpr
->cp_ring_struct
.fw_ring_id
;
4324 return bnxt_cp_ring_from_grp(bp
, &txr
->tx_ring_struct
);
4328 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
4330 u32 i
, j
, max_rings
;
4331 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
4332 struct hwrm_vnic_rss_cfg_input req
= {0};
4334 if ((bp
->flags
& BNXT_FLAG_CHIP_P5
) ||
4335 vnic
->fw_rss_cos_lb_ctx
[0] == INVALID_HW_RING_ID
)
4338 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
4340 req
.hash_type
= cpu_to_le32(bp
->rss_hash_cfg
);
4341 req
.hash_mode_flags
= VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT
;
4342 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
) {
4343 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
4344 max_rings
= bp
->rx_nr_rings
- 1;
4346 max_rings
= bp
->rx_nr_rings
;
4351 /* Fill the RSS indirection table with ring group ids */
4352 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
4355 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
4358 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
4359 req
.hash_key_tbl_addr
=
4360 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
4362 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[0]);
4363 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4366 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
4368 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
4369 u32 i
, j
, k
, nr_ctxs
, max_rings
= bp
->rx_nr_rings
;
4370 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[0];
4371 struct hwrm_vnic_rss_cfg_input req
= {0};
4373 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
4374 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
4376 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4379 req
.hash_type
= cpu_to_le32(bp
->rss_hash_cfg
);
4380 req
.hash_mode_flags
= VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT
;
4381 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
4382 req
.hash_key_tbl_addr
= cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
4383 nr_ctxs
= DIV_ROUND_UP(bp
->rx_nr_rings
, 64);
4384 for (i
= 0, k
= 0; i
< nr_ctxs
; i
++) {
4385 __le16
*ring_tbl
= vnic
->rss_table
;
4388 req
.ring_table_pair_index
= i
;
4389 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[i
]);
4390 for (j
= 0; j
< 64; j
++) {
4393 ring_id
= rxr
->rx_ring_struct
.fw_ring_id
;
4394 *ring_tbl
++ = cpu_to_le16(ring_id
);
4395 ring_id
= bnxt_cp_ring_for_rx(bp
, rxr
);
4396 *ring_tbl
++ = cpu_to_le16(ring_id
);
4399 if (k
== max_rings
) {
4401 rxr
= &bp
->rx_ring
[0];
4404 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4411 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
4413 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
4414 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
4416 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
4417 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
4418 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
4419 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
4421 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
4422 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
4423 /* thresholds not implemented in firmware yet */
4424 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
4425 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
4426 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
4427 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4430 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
,
4433 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
4435 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
4436 req
.rss_cos_lb_ctx_id
=
4437 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
]);
4439 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4440 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
] = INVALID_HW_RING_ID
;
4443 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
4447 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
4448 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
4450 for (j
= 0; j
< BNXT_MAX_CTX_PER_VNIC
; j
++) {
4451 if (vnic
->fw_rss_cos_lb_ctx
[j
] != INVALID_HW_RING_ID
)
4452 bnxt_hwrm_vnic_ctx_free_one(bp
, i
, j
);
4455 bp
->rsscos_nr_ctxs
= 0;
4458 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
, u16 ctx_idx
)
4461 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
4462 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
4463 bp
->hwrm_cmd_resp_addr
;
4465 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
4468 mutex_lock(&bp
->hwrm_cmd_lock
);
4469 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4471 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
] =
4472 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
4473 mutex_unlock(&bp
->hwrm_cmd_lock
);
4478 static u32
bnxt_get_roce_vnic_mode(struct bnxt
*bp
)
4480 if (bp
->flags
& BNXT_FLAG_ROCE_MIRROR_CAP
)
4481 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE
;
4482 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE
;
4485 int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
4487 unsigned int ring
= 0, grp_idx
;
4488 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
4489 struct hwrm_vnic_cfg_input req
= {0};
4492 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
4494 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
4495 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[0];
4497 req
.default_rx_ring_id
=
4498 cpu_to_le16(rxr
->rx_ring_struct
.fw_ring_id
);
4499 req
.default_cmpl_ring_id
=
4500 cpu_to_le16(bnxt_cp_ring_for_rx(bp
, rxr
));
4502 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID
|
4503 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID
);
4506 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
);
4507 /* Only RSS support for now TBD: COS & LB */
4508 if (vnic
->fw_rss_cos_lb_ctx
[0] != INVALID_HW_RING_ID
) {
4509 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[0]);
4510 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE
|
4511 VNIC_CFG_REQ_ENABLES_MRU
);
4512 } else if (vnic
->flags
& BNXT_VNIC_RFS_NEW_RSS_FLAG
) {
4514 cpu_to_le16(bp
->vnic_info
[0].fw_rss_cos_lb_ctx
[0]);
4515 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE
|
4516 VNIC_CFG_REQ_ENABLES_MRU
);
4517 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE
);
4519 req
.rss_rule
= cpu_to_le16(0xffff);
4522 if (BNXT_CHIP_TYPE_NITRO_A0(bp
) &&
4523 (vnic
->fw_rss_cos_lb_ctx
[0] != INVALID_HW_RING_ID
)) {
4524 req
.cos_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[1]);
4525 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE
);
4527 req
.cos_rule
= cpu_to_le16(0xffff);
4530 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
4532 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
4534 else if ((vnic_id
== 1) && BNXT_CHIP_TYPE_NITRO_A0(bp
))
4535 ring
= bp
->rx_nr_rings
- 1;
4537 grp_idx
= bp
->rx_ring
[ring
].bnapi
->index
;
4538 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
4539 req
.lb_rule
= cpu_to_le16(0xffff);
4541 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
4544 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
4545 #ifdef CONFIG_BNXT_SRIOV
4547 def_vlan
= bp
->vf
.vlan
;
4549 if ((bp
->flags
& BNXT_FLAG_STRIP_VLAN
) || def_vlan
)
4550 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
4551 if (!vnic_id
&& bnxt_ulp_registered(bp
->edev
, BNXT_ROCE_ULP
))
4552 req
.flags
|= cpu_to_le32(bnxt_get_roce_vnic_mode(bp
));
4554 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4557 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
4561 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
4562 struct hwrm_vnic_free_input req
= {0};
4564 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
4566 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
4568 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4571 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
4576 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
4580 for (i
= 0; i
< bp
->nr_vnics
; i
++)
4581 bnxt_hwrm_vnic_free_one(bp
, i
);
4584 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
,
4585 unsigned int start_rx_ring_idx
,
4586 unsigned int nr_rings
)
4589 unsigned int i
, j
, grp_idx
, end_idx
= start_rx_ring_idx
+ nr_rings
;
4590 struct hwrm_vnic_alloc_input req
= {0};
4591 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4592 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
4594 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
4595 goto vnic_no_ring_grps
;
4597 /* map ring groups to this vnic */
4598 for (i
= start_rx_ring_idx
, j
= 0; i
< end_idx
; i
++, j
++) {
4599 grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
4600 if (bp
->grp_info
[grp_idx
].fw_grp_id
== INVALID_HW_RING_ID
) {
4601 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
4605 vnic
->fw_grp_ids
[j
] = bp
->grp_info
[grp_idx
].fw_grp_id
;
4609 for (i
= 0; i
< BNXT_MAX_CTX_PER_VNIC
; i
++)
4610 vnic
->fw_rss_cos_lb_ctx
[i
] = INVALID_HW_RING_ID
;
4612 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
4614 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
4616 mutex_lock(&bp
->hwrm_cmd_lock
);
4617 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4619 vnic
->fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
4620 mutex_unlock(&bp
->hwrm_cmd_lock
);
4624 static int bnxt_hwrm_vnic_qcaps(struct bnxt
*bp
)
4626 struct hwrm_vnic_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4627 struct hwrm_vnic_qcaps_input req
= {0};
4630 if (bp
->hwrm_spec_code
< 0x10600)
4633 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_QCAPS
, -1, -1);
4634 mutex_lock(&bp
->hwrm_cmd_lock
);
4635 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4637 u32 flags
= le32_to_cpu(resp
->flags
);
4639 if (!(bp
->flags
& BNXT_FLAG_CHIP_P5
) &&
4640 (flags
& VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP
))
4641 bp
->flags
|= BNXT_FLAG_NEW_RSS_CAP
;
4643 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP
)
4644 bp
->flags
|= BNXT_FLAG_ROCE_MIRROR_CAP
;
4646 mutex_unlock(&bp
->hwrm_cmd_lock
);
4650 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
4655 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
4658 mutex_lock(&bp
->hwrm_cmd_lock
);
4659 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4660 struct hwrm_ring_grp_alloc_input req
= {0};
4661 struct hwrm_ring_grp_alloc_output
*resp
=
4662 bp
->hwrm_cmd_resp_addr
;
4663 unsigned int grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
4665 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
4667 req
.cr
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
4668 req
.rr
= cpu_to_le16(bp
->grp_info
[grp_idx
].rx_fw_ring_id
);
4669 req
.ar
= cpu_to_le16(bp
->grp_info
[grp_idx
].agg_fw_ring_id
);
4670 req
.sc
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_stats_ctx
);
4672 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4677 bp
->grp_info
[grp_idx
].fw_grp_id
=
4678 le32_to_cpu(resp
->ring_group_id
);
4680 mutex_unlock(&bp
->hwrm_cmd_lock
);
4684 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
4688 struct hwrm_ring_grp_free_input req
= {0};
4690 if (!bp
->grp_info
|| (bp
->flags
& BNXT_FLAG_CHIP_P5
))
4693 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
4695 mutex_lock(&bp
->hwrm_cmd_lock
);
4696 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4697 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
4700 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
4702 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4706 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
4708 mutex_unlock(&bp
->hwrm_cmd_lock
);
4712 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
4713 struct bnxt_ring_struct
*ring
,
4714 u32 ring_type
, u32 map_index
)
4716 int rc
= 0, err
= 0;
4717 struct hwrm_ring_alloc_input req
= {0};
4718 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4719 struct bnxt_ring_mem_info
*rmem
= &ring
->ring_mem
;
4720 struct bnxt_ring_grp_info
*grp_info
;
4723 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
4726 if (rmem
->nr_pages
> 1) {
4727 req
.page_tbl_addr
= cpu_to_le64(rmem
->pg_tbl_map
);
4728 /* Page size is in log2 units */
4729 req
.page_size
= BNXT_PAGE_SHIFT
;
4730 req
.page_tbl_depth
= 1;
4732 req
.page_tbl_addr
= cpu_to_le64(rmem
->dma_arr
[0]);
4735 /* Association of ring index with doorbell index and MSIX number */
4736 req
.logical_id
= cpu_to_le16(map_index
);
4738 switch (ring_type
) {
4739 case HWRM_RING_ALLOC_TX
: {
4740 struct bnxt_tx_ring_info
*txr
;
4742 txr
= container_of(ring
, struct bnxt_tx_ring_info
,
4744 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
4745 /* Association of transmit ring with completion ring */
4746 grp_info
= &bp
->grp_info
[ring
->grp_idx
];
4747 req
.cmpl_ring_id
= cpu_to_le16(bnxt_cp_ring_for_tx(bp
, txr
));
4748 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
4749 req
.stat_ctx_id
= cpu_to_le32(grp_info
->fw_stats_ctx
);
4750 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
4753 case HWRM_RING_ALLOC_RX
:
4754 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
4755 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
4756 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
4759 /* Association of rx ring with stats context */
4760 grp_info
= &bp
->grp_info
[ring
->grp_idx
];
4761 req
.rx_buf_size
= cpu_to_le16(bp
->rx_buf_use_size
);
4762 req
.stat_ctx_id
= cpu_to_le32(grp_info
->fw_stats_ctx
);
4763 req
.enables
|= cpu_to_le32(
4764 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID
);
4765 if (NET_IP_ALIGN
== 2)
4766 flags
= RING_ALLOC_REQ_FLAGS_RX_SOP_PAD
;
4767 req
.flags
= cpu_to_le16(flags
);
4770 case HWRM_RING_ALLOC_AGG
:
4771 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
4772 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX_AGG
;
4773 /* Association of agg ring with rx ring */
4774 grp_info
= &bp
->grp_info
[ring
->grp_idx
];
4775 req
.rx_ring_id
= cpu_to_le16(grp_info
->rx_fw_ring_id
);
4776 req
.rx_buf_size
= cpu_to_le16(BNXT_RX_PAGE_SIZE
);
4777 req
.stat_ctx_id
= cpu_to_le32(grp_info
->fw_stats_ctx
);
4778 req
.enables
|= cpu_to_le32(
4779 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID
|
4780 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID
);
4782 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
4784 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
4786 case HWRM_RING_ALLOC_CMPL
:
4787 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_L2_CMPL
;
4788 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
4789 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
4790 /* Association of cp ring with nq */
4791 grp_info
= &bp
->grp_info
[map_index
];
4792 req
.nq_ring_id
= cpu_to_le16(grp_info
->cp_fw_ring_id
);
4793 req
.cq_handle
= cpu_to_le64(ring
->handle
);
4794 req
.enables
|= cpu_to_le32(
4795 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID
);
4796 } else if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
4797 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
4800 case HWRM_RING_ALLOC_NQ
:
4801 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_NQ
;
4802 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
4803 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4804 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
4807 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
4812 mutex_lock(&bp
->hwrm_cmd_lock
);
4813 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4814 err
= le16_to_cpu(resp
->error_code
);
4815 ring_id
= le16_to_cpu(resp
->ring_id
);
4816 mutex_unlock(&bp
->hwrm_cmd_lock
);
4819 netdev_err(bp
->dev
, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4820 ring_type
, rc
, err
);
4823 ring
->fw_ring_id
= ring_id
;
4827 static int bnxt_hwrm_set_async_event_cr(struct bnxt
*bp
, int idx
)
4832 struct hwrm_func_cfg_input req
= {0};
4834 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_CFG
, -1, -1);
4835 req
.fid
= cpu_to_le16(0xffff);
4836 req
.enables
= cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR
);
4837 req
.async_event_cr
= cpu_to_le16(idx
);
4838 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4840 struct hwrm_func_vf_cfg_input req
= {0};
4842 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_VF_CFG
, -1, -1);
4844 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR
);
4845 req
.async_event_cr
= cpu_to_le16(idx
);
4846 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4851 static void bnxt_set_db(struct bnxt
*bp
, struct bnxt_db_info
*db
, u32 ring_type
,
4852 u32 map_idx
, u32 xid
)
4854 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
4856 db
->doorbell
= bp
->bar1
+ 0x10000;
4858 db
->doorbell
= bp
->bar1
+ 0x4000;
4859 switch (ring_type
) {
4860 case HWRM_RING_ALLOC_TX
:
4861 db
->db_key64
= DBR_PATH_L2
| DBR_TYPE_SQ
;
4863 case HWRM_RING_ALLOC_RX
:
4864 case HWRM_RING_ALLOC_AGG
:
4865 db
->db_key64
= DBR_PATH_L2
| DBR_TYPE_SRQ
;
4867 case HWRM_RING_ALLOC_CMPL
:
4868 db
->db_key64
= DBR_PATH_L2
;
4870 case HWRM_RING_ALLOC_NQ
:
4871 db
->db_key64
= DBR_PATH_L2
;
4874 db
->db_key64
|= (u64
)xid
<< DBR_XID_SFT
;
4876 db
->doorbell
= bp
->bar1
+ map_idx
* 0x80;
4877 switch (ring_type
) {
4878 case HWRM_RING_ALLOC_TX
:
4879 db
->db_key32
= DB_KEY_TX
;
4881 case HWRM_RING_ALLOC_RX
:
4882 case HWRM_RING_ALLOC_AGG
:
4883 db
->db_key32
= DB_KEY_RX
;
4885 case HWRM_RING_ALLOC_CMPL
:
4886 db
->db_key32
= DB_KEY_CP
;
4892 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
4897 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
4898 type
= HWRM_RING_ALLOC_NQ
;
4900 type
= HWRM_RING_ALLOC_CMPL
;
4901 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4902 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4903 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4904 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
4905 u32 map_idx
= ring
->map_idx
;
4907 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, type
, map_idx
);
4910 bnxt_set_db(bp
, &cpr
->cp_db
, type
, map_idx
, ring
->fw_ring_id
);
4911 bnxt_db_nq(bp
, &cpr
->cp_db
, cpr
->cp_raw_cons
);
4912 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
4915 rc
= bnxt_hwrm_set_async_event_cr(bp
, ring
->fw_ring_id
);
4917 netdev_warn(bp
->dev
, "Failed to set async event completion ring.\n");
4921 type
= HWRM_RING_ALLOC_TX
;
4922 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4923 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
4924 struct bnxt_ring_struct
*ring
;
4927 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
4928 struct bnxt_napi
*bnapi
= txr
->bnapi
;
4929 struct bnxt_cp_ring_info
*cpr
, *cpr2
;
4930 u32 type2
= HWRM_RING_ALLOC_CMPL
;
4932 cpr
= &bnapi
->cp_ring
;
4933 cpr2
= cpr
->cp_ring_arr
[BNXT_TX_HDL
];
4934 ring
= &cpr2
->cp_ring_struct
;
4935 ring
->handle
= BNXT_TX_HDL
;
4936 map_idx
= bnapi
->index
;
4937 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, type2
, map_idx
);
4940 bnxt_set_db(bp
, &cpr2
->cp_db
, type2
, map_idx
,
4942 bnxt_db_cq(bp
, &cpr2
->cp_db
, cpr2
->cp_raw_cons
);
4944 ring
= &txr
->tx_ring_struct
;
4946 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, type
, map_idx
);
4949 bnxt_set_db(bp
, &txr
->tx_db
, type
, map_idx
, ring
->fw_ring_id
);
4952 type
= HWRM_RING_ALLOC_RX
;
4953 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4954 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4955 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
4956 struct bnxt_napi
*bnapi
= rxr
->bnapi
;
4957 u32 map_idx
= bnapi
->index
;
4959 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, type
, map_idx
);
4962 bnxt_set_db(bp
, &rxr
->rx_db
, type
, map_idx
, ring
->fw_ring_id
);
4963 bnxt_db_write(bp
, &rxr
->rx_db
, rxr
->rx_prod
);
4964 bp
->grp_info
[map_idx
].rx_fw_ring_id
= ring
->fw_ring_id
;
4965 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
4966 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4967 u32 type2
= HWRM_RING_ALLOC_CMPL
;
4968 struct bnxt_cp_ring_info
*cpr2
;
4970 cpr2
= cpr
->cp_ring_arr
[BNXT_RX_HDL
];
4971 ring
= &cpr2
->cp_ring_struct
;
4972 ring
->handle
= BNXT_RX_HDL
;
4973 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, type2
, map_idx
);
4976 bnxt_set_db(bp
, &cpr2
->cp_db
, type2
, map_idx
,
4978 bnxt_db_cq(bp
, &cpr2
->cp_db
, cpr2
->cp_raw_cons
);
4982 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
4983 type
= HWRM_RING_ALLOC_AGG
;
4984 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4985 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4986 struct bnxt_ring_struct
*ring
=
4987 &rxr
->rx_agg_ring_struct
;
4988 u32 grp_idx
= ring
->grp_idx
;
4989 u32 map_idx
= grp_idx
+ bp
->rx_nr_rings
;
4991 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, type
, map_idx
);
4995 bnxt_set_db(bp
, &rxr
->rx_agg_db
, type
, map_idx
,
4997 bnxt_db_write(bp
, &rxr
->rx_agg_db
, rxr
->rx_agg_prod
);
4998 bp
->grp_info
[grp_idx
].agg_fw_ring_id
= ring
->fw_ring_id
;
5005 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
5006 struct bnxt_ring_struct
*ring
,
5007 u32 ring_type
, int cmpl_ring_id
)
5010 struct hwrm_ring_free_input req
= {0};
5011 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5014 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, cmpl_ring_id
, -1);
5015 req
.ring_type
= ring_type
;
5016 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
5018 mutex_lock(&bp
->hwrm_cmd_lock
);
5019 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5020 error_code
= le16_to_cpu(resp
->error_code
);
5021 mutex_unlock(&bp
->hwrm_cmd_lock
);
5023 if (rc
|| error_code
) {
5024 netdev_err(bp
->dev
, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5025 ring_type
, rc
, error_code
);
5031 static void bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
5039 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
5040 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
5041 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
5044 cmpl_ring_id
= bnxt_cp_ring_for_tx(bp
, txr
);
5045 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
5046 hwrm_ring_free_send_msg(bp
, ring
,
5047 RING_FREE_REQ_RING_TYPE_TX
,
5048 close_path
? cmpl_ring_id
:
5049 INVALID_HW_RING_ID
);
5050 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
5054 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
5055 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
5056 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
5057 u32 grp_idx
= rxr
->bnapi
->index
;
5060 cmpl_ring_id
= bnxt_cp_ring_for_rx(bp
, rxr
);
5061 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
5062 hwrm_ring_free_send_msg(bp
, ring
,
5063 RING_FREE_REQ_RING_TYPE_RX
,
5064 close_path
? cmpl_ring_id
:
5065 INVALID_HW_RING_ID
);
5066 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
5067 bp
->grp_info
[grp_idx
].rx_fw_ring_id
=
5072 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
5073 type
= RING_FREE_REQ_RING_TYPE_RX_AGG
;
5075 type
= RING_FREE_REQ_RING_TYPE_RX
;
5076 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
5077 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
5078 struct bnxt_ring_struct
*ring
= &rxr
->rx_agg_ring_struct
;
5079 u32 grp_idx
= rxr
->bnapi
->index
;
5082 cmpl_ring_id
= bnxt_cp_ring_for_rx(bp
, rxr
);
5083 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
5084 hwrm_ring_free_send_msg(bp
, ring
, type
,
5085 close_path
? cmpl_ring_id
:
5086 INVALID_HW_RING_ID
);
5087 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
5088 bp
->grp_info
[grp_idx
].agg_fw_ring_id
=
5093 /* The completion rings are about to be freed. After that the
5094 * IRQ doorbell will not work anymore. So we need to disable
5097 bnxt_disable_int_sync(bp
);
5099 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
5100 type
= RING_FREE_REQ_RING_TYPE_NQ
;
5102 type
= RING_FREE_REQ_RING_TYPE_L2_CMPL
;
5103 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5104 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
5105 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5106 struct bnxt_ring_struct
*ring
;
5109 for (j
= 0; j
< 2; j
++) {
5110 struct bnxt_cp_ring_info
*cpr2
= cpr
->cp_ring_arr
[j
];
5113 ring
= &cpr2
->cp_ring_struct
;
5114 if (ring
->fw_ring_id
== INVALID_HW_RING_ID
)
5116 hwrm_ring_free_send_msg(bp
, ring
,
5117 RING_FREE_REQ_RING_TYPE_L2_CMPL
,
5118 INVALID_HW_RING_ID
);
5119 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
5122 ring
= &cpr
->cp_ring_struct
;
5123 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
5124 hwrm_ring_free_send_msg(bp
, ring
, type
,
5125 INVALID_HW_RING_ID
);
5126 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
5127 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
5132 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
5135 static int bnxt_hwrm_get_rings(struct bnxt
*bp
)
5137 struct hwrm_func_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5138 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
5139 struct hwrm_func_qcfg_input req
= {0};
5142 if (bp
->hwrm_spec_code
< 0x10601)
5145 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCFG
, -1, -1);
5146 req
.fid
= cpu_to_le16(0xffff);
5147 mutex_lock(&bp
->hwrm_cmd_lock
);
5148 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5150 mutex_unlock(&bp
->hwrm_cmd_lock
);
5154 hw_resc
->resv_tx_rings
= le16_to_cpu(resp
->alloc_tx_rings
);
5155 if (BNXT_NEW_RM(bp
)) {
5158 hw_resc
->resv_rx_rings
= le16_to_cpu(resp
->alloc_rx_rings
);
5159 hw_resc
->resv_hw_ring_grps
=
5160 le32_to_cpu(resp
->alloc_hw_ring_grps
);
5161 hw_resc
->resv_vnics
= le16_to_cpu(resp
->alloc_vnics
);
5162 cp
= le16_to_cpu(resp
->alloc_cmpl_rings
);
5163 stats
= le16_to_cpu(resp
->alloc_stat_ctx
);
5164 cp
= min_t(u16
, cp
, stats
);
5165 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
5166 int rx
= hw_resc
->resv_rx_rings
;
5167 int tx
= hw_resc
->resv_tx_rings
;
5169 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
5171 if (cp
< (rx
+ tx
)) {
5172 bnxt_trim_rings(bp
, &rx
, &tx
, cp
, false);
5173 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
5175 hw_resc
->resv_rx_rings
= rx
;
5176 hw_resc
->resv_tx_rings
= tx
;
5178 cp
= le16_to_cpu(resp
->alloc_msix
);
5179 hw_resc
->resv_hw_ring_grps
= rx
;
5181 hw_resc
->resv_cp_rings
= cp
;
5183 mutex_unlock(&bp
->hwrm_cmd_lock
);
5187 /* Caller must hold bp->hwrm_cmd_lock */
5188 int __bnxt_hwrm_get_tx_rings(struct bnxt
*bp
, u16 fid
, int *tx_rings
)
5190 struct hwrm_func_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5191 struct hwrm_func_qcfg_input req
= {0};
5194 if (bp
->hwrm_spec_code
< 0x10601)
5197 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCFG
, -1, -1);
5198 req
.fid
= cpu_to_le16(fid
);
5199 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5201 *tx_rings
= le16_to_cpu(resp
->alloc_tx_rings
);
5206 static bool bnxt_rfs_supported(struct bnxt
*bp
);
5209 __bnxt_hwrm_reserve_pf_rings(struct bnxt
*bp
, struct hwrm_func_cfg_input
*req
,
5210 int tx_rings
, int rx_rings
, int ring_grps
,
5211 int cp_rings
, int vnics
)
5215 bnxt_hwrm_cmd_hdr_init(bp
, req
, HWRM_FUNC_CFG
, -1, -1);
5216 req
->fid
= cpu_to_le16(0xffff);
5217 enables
|= tx_rings
? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS
: 0;
5218 req
->num_tx_rings
= cpu_to_le16(tx_rings
);
5219 if (BNXT_NEW_RM(bp
)) {
5220 enables
|= rx_rings
? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS
: 0;
5221 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
5222 enables
|= cp_rings
? FUNC_CFG_REQ_ENABLES_NUM_MSIX
: 0;
5223 enables
|= tx_rings
+ ring_grps
?
5224 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS
|
5225 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS
: 0;
5226 enables
|= rx_rings
?
5227 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS
: 0;
5229 enables
|= cp_rings
?
5230 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS
|
5231 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS
: 0;
5232 enables
|= ring_grps
?
5233 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS
|
5234 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS
: 0;
5236 enables
|= vnics
? FUNC_CFG_REQ_ENABLES_NUM_VNICS
: 0;
5238 req
->num_rx_rings
= cpu_to_le16(rx_rings
);
5239 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
5240 req
->num_cmpl_rings
= cpu_to_le16(tx_rings
+ ring_grps
);
5241 req
->num_msix
= cpu_to_le16(cp_rings
);
5242 req
->num_rsscos_ctxs
=
5243 cpu_to_le16(DIV_ROUND_UP(ring_grps
, 64));
5245 req
->num_cmpl_rings
= cpu_to_le16(cp_rings
);
5246 req
->num_hw_ring_grps
= cpu_to_le16(ring_grps
);
5247 req
->num_rsscos_ctxs
= cpu_to_le16(1);
5248 if (!(bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
) &&
5249 bnxt_rfs_supported(bp
))
5250 req
->num_rsscos_ctxs
=
5251 cpu_to_le16(ring_grps
+ 1);
5253 req
->num_stat_ctxs
= req
->num_cmpl_rings
;
5254 req
->num_vnics
= cpu_to_le16(vnics
);
5256 req
->enables
= cpu_to_le32(enables
);
5260 __bnxt_hwrm_reserve_vf_rings(struct bnxt
*bp
,
5261 struct hwrm_func_vf_cfg_input
*req
, int tx_rings
,
5262 int rx_rings
, int ring_grps
, int cp_rings
,
5267 bnxt_hwrm_cmd_hdr_init(bp
, req
, HWRM_FUNC_VF_CFG
, -1, -1);
5268 enables
|= tx_rings
? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS
: 0;
5269 enables
|= rx_rings
? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS
|
5270 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS
: 0;
5271 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
5272 enables
|= tx_rings
+ ring_grps
?
5273 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS
|
5274 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS
: 0;
5276 enables
|= cp_rings
?
5277 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS
|
5278 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS
: 0;
5279 enables
|= ring_grps
?
5280 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS
: 0;
5282 enables
|= vnics
? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS
: 0;
5283 enables
|= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS
;
5285 req
->num_l2_ctxs
= cpu_to_le16(BNXT_VF_MAX_L2_CTX
);
5286 req
->num_tx_rings
= cpu_to_le16(tx_rings
);
5287 req
->num_rx_rings
= cpu_to_le16(rx_rings
);
5288 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
5289 req
->num_cmpl_rings
= cpu_to_le16(tx_rings
+ ring_grps
);
5290 req
->num_rsscos_ctxs
= cpu_to_le16(DIV_ROUND_UP(ring_grps
, 64));
5292 req
->num_cmpl_rings
= cpu_to_le16(cp_rings
);
5293 req
->num_hw_ring_grps
= cpu_to_le16(ring_grps
);
5294 req
->num_rsscos_ctxs
= cpu_to_le16(BNXT_VF_MAX_RSS_CTX
);
5296 req
->num_stat_ctxs
= req
->num_cmpl_rings
;
5297 req
->num_vnics
= cpu_to_le16(vnics
);
5299 req
->enables
= cpu_to_le32(enables
);
5303 bnxt_hwrm_reserve_pf_rings(struct bnxt
*bp
, int tx_rings
, int rx_rings
,
5304 int ring_grps
, int cp_rings
, int vnics
)
5306 struct hwrm_func_cfg_input req
= {0};
5309 __bnxt_hwrm_reserve_pf_rings(bp
, &req
, tx_rings
, rx_rings
, ring_grps
,
5314 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5318 if (bp
->hwrm_spec_code
< 0x10601)
5319 bp
->hw_resc
.resv_tx_rings
= tx_rings
;
5321 rc
= bnxt_hwrm_get_rings(bp
);
5326 bnxt_hwrm_reserve_vf_rings(struct bnxt
*bp
, int tx_rings
, int rx_rings
,
5327 int ring_grps
, int cp_rings
, int vnics
)
5329 struct hwrm_func_vf_cfg_input req
= {0};
5332 if (!BNXT_NEW_RM(bp
)) {
5333 bp
->hw_resc
.resv_tx_rings
= tx_rings
;
5337 __bnxt_hwrm_reserve_vf_rings(bp
, &req
, tx_rings
, rx_rings
, ring_grps
,
5339 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5343 rc
= bnxt_hwrm_get_rings(bp
);
5347 static int bnxt_hwrm_reserve_rings(struct bnxt
*bp
, int tx
, int rx
, int grp
,
5351 return bnxt_hwrm_reserve_pf_rings(bp
, tx
, rx
, grp
, cp
, vnic
);
5353 return bnxt_hwrm_reserve_vf_rings(bp
, tx
, rx
, grp
, cp
, vnic
);
5356 static int bnxt_cp_rings_in_use(struct bnxt
*bp
)
5358 int cp
= bp
->cp_nr_rings
;
5359 int ulp_msix
, ulp_base
;
5361 ulp_msix
= bnxt_get_ulp_msix_num(bp
);
5363 ulp_base
= bnxt_get_ulp_msix_base(bp
);
5365 if ((ulp_base
+ ulp_msix
) > cp
)
5366 cp
= ulp_base
+ ulp_msix
;
5371 static bool bnxt_need_reserve_rings(struct bnxt
*bp
)
5373 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
5374 int cp
= bnxt_cp_rings_in_use(bp
);
5375 int rx
= bp
->rx_nr_rings
;
5376 int vnic
= 1, grp
= rx
;
5378 if (bp
->hwrm_spec_code
< 0x10601)
5381 if (hw_resc
->resv_tx_rings
!= bp
->tx_nr_rings
)
5384 if ((bp
->flags
& BNXT_FLAG_RFS
) && !(bp
->flags
& BNXT_FLAG_CHIP_P5
))
5386 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
5388 if (BNXT_NEW_RM(bp
) &&
5389 (hw_resc
->resv_rx_rings
!= rx
|| hw_resc
->resv_cp_rings
!= cp
||
5390 hw_resc
->resv_vnics
!= vnic
||
5391 (hw_resc
->resv_hw_ring_grps
!= grp
&&
5392 !(bp
->flags
& BNXT_FLAG_CHIP_P5
))))
5397 static int __bnxt_reserve_rings(struct bnxt
*bp
)
5399 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
5400 int cp
= bnxt_cp_rings_in_use(bp
);
5401 int tx
= bp
->tx_nr_rings
;
5402 int rx
= bp
->rx_nr_rings
;
5403 int grp
, rx_rings
, rc
;
5407 if (!bnxt_need_reserve_rings(bp
))
5410 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
5412 if ((bp
->flags
& BNXT_FLAG_RFS
) && !(bp
->flags
& BNXT_FLAG_CHIP_P5
))
5414 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
5416 grp
= bp
->rx_nr_rings
;
5418 rc
= bnxt_hwrm_reserve_rings(bp
, tx
, rx
, grp
, cp
, vnic
);
5422 tx
= hw_resc
->resv_tx_rings
;
5423 if (BNXT_NEW_RM(bp
)) {
5424 rx
= hw_resc
->resv_rx_rings
;
5425 cp
= hw_resc
->resv_cp_rings
;
5426 grp
= hw_resc
->resv_hw_ring_grps
;
5427 vnic
= hw_resc
->resv_vnics
;
5431 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
5435 if (netif_running(bp
->dev
))
5438 bp
->flags
&= ~BNXT_FLAG_AGG_RINGS
;
5439 bp
->flags
|= BNXT_FLAG_NO_AGG_RINGS
;
5440 bp
->dev
->hw_features
&= ~NETIF_F_LRO
;
5441 bp
->dev
->features
&= ~NETIF_F_LRO
;
5442 bnxt_set_ring_params(bp
);
5445 rx_rings
= min_t(int, rx_rings
, grp
);
5446 rc
= bnxt_trim_rings(bp
, &rx_rings
, &tx
, cp
, sh
);
5447 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
5449 cp
= sh
? max_t(int, tx
, rx_rings
) : tx
+ rx_rings
;
5450 bp
->tx_nr_rings
= tx
;
5451 bp
->rx_nr_rings
= rx_rings
;
5452 bp
->cp_nr_rings
= cp
;
5454 if (!tx
|| !rx
|| !cp
|| !grp
|| !vnic
)
5460 static int bnxt_hwrm_check_vf_rings(struct bnxt
*bp
, int tx_rings
, int rx_rings
,
5461 int ring_grps
, int cp_rings
, int vnics
)
5463 struct hwrm_func_vf_cfg_input req
= {0};
5467 if (!BNXT_NEW_RM(bp
))
5470 __bnxt_hwrm_reserve_vf_rings(bp
, &req
, tx_rings
, rx_rings
, ring_grps
,
5472 flags
= FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST
|
5473 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST
|
5474 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST
|
5475 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST
|
5476 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST
|
5477 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST
;
5478 if (!(bp
->flags
& BNXT_FLAG_CHIP_P5
))
5479 flags
|= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST
;
5481 req
.flags
= cpu_to_le32(flags
);
5482 rc
= hwrm_send_message_silent(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5488 static int bnxt_hwrm_check_pf_rings(struct bnxt
*bp
, int tx_rings
, int rx_rings
,
5489 int ring_grps
, int cp_rings
, int vnics
)
5491 struct hwrm_func_cfg_input req
= {0};
5495 __bnxt_hwrm_reserve_pf_rings(bp
, &req
, tx_rings
, rx_rings
, ring_grps
,
5497 flags
= FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST
;
5498 if (BNXT_NEW_RM(bp
)) {
5499 flags
|= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST
|
5500 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST
|
5501 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST
|
5502 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST
;
5503 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
5504 flags
|= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST
;
5506 flags
|= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST
;
5509 req
.flags
= cpu_to_le32(flags
);
5510 rc
= hwrm_send_message_silent(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5516 static int bnxt_hwrm_check_rings(struct bnxt
*bp
, int tx_rings
, int rx_rings
,
5517 int ring_grps
, int cp_rings
, int vnics
)
5519 if (bp
->hwrm_spec_code
< 0x10801)
5523 return bnxt_hwrm_check_pf_rings(bp
, tx_rings
, rx_rings
,
5524 ring_grps
, cp_rings
, vnics
);
5526 return bnxt_hwrm_check_vf_rings(bp
, tx_rings
, rx_rings
, ring_grps
,
5530 static void bnxt_hwrm_coal_params_qcaps(struct bnxt
*bp
)
5532 struct hwrm_ring_aggint_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5533 struct bnxt_coal_cap
*coal_cap
= &bp
->coal_cap
;
5534 struct hwrm_ring_aggint_qcaps_input req
= {0};
5537 coal_cap
->cmpl_params
= BNXT_LEGACY_COAL_CMPL_PARAMS
;
5538 coal_cap
->num_cmpl_dma_aggr_max
= 63;
5539 coal_cap
->num_cmpl_dma_aggr_during_int_max
= 63;
5540 coal_cap
->cmpl_aggr_dma_tmr_max
= 65535;
5541 coal_cap
->cmpl_aggr_dma_tmr_during_int_max
= 65535;
5542 coal_cap
->int_lat_tmr_min_max
= 65535;
5543 coal_cap
->int_lat_tmr_max_max
= 65535;
5544 coal_cap
->num_cmpl_aggr_int_max
= 65535;
5545 coal_cap
->timer_units
= 80;
5547 if (bp
->hwrm_spec_code
< 0x10902)
5550 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_AGGINT_QCAPS
, -1, -1);
5551 mutex_lock(&bp
->hwrm_cmd_lock
);
5552 rc
= _hwrm_send_message_silent(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5554 coal_cap
->cmpl_params
= le32_to_cpu(resp
->cmpl_params
);
5555 coal_cap
->nq_params
= le32_to_cpu(resp
->nq_params
);
5556 coal_cap
->num_cmpl_dma_aggr_max
=
5557 le16_to_cpu(resp
->num_cmpl_dma_aggr_max
);
5558 coal_cap
->num_cmpl_dma_aggr_during_int_max
=
5559 le16_to_cpu(resp
->num_cmpl_dma_aggr_during_int_max
);
5560 coal_cap
->cmpl_aggr_dma_tmr_max
=
5561 le16_to_cpu(resp
->cmpl_aggr_dma_tmr_max
);
5562 coal_cap
->cmpl_aggr_dma_tmr_during_int_max
=
5563 le16_to_cpu(resp
->cmpl_aggr_dma_tmr_during_int_max
);
5564 coal_cap
->int_lat_tmr_min_max
=
5565 le16_to_cpu(resp
->int_lat_tmr_min_max
);
5566 coal_cap
->int_lat_tmr_max_max
=
5567 le16_to_cpu(resp
->int_lat_tmr_max_max
);
5568 coal_cap
->num_cmpl_aggr_int_max
=
5569 le16_to_cpu(resp
->num_cmpl_aggr_int_max
);
5570 coal_cap
->timer_units
= le16_to_cpu(resp
->timer_units
);
5572 mutex_unlock(&bp
->hwrm_cmd_lock
);
5575 static u16
bnxt_usec_to_coal_tmr(struct bnxt
*bp
, u16 usec
)
5577 struct bnxt_coal_cap
*coal_cap
= &bp
->coal_cap
;
5579 return usec
* 1000 / coal_cap
->timer_units
;
5582 static void bnxt_hwrm_set_coal_params(struct bnxt
*bp
,
5583 struct bnxt_coal
*hw_coal
,
5584 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input
*req
)
5586 struct bnxt_coal_cap
*coal_cap
= &bp
->coal_cap
;
5587 u32 cmpl_params
= coal_cap
->cmpl_params
;
5588 u16 val
, tmr
, max
, flags
= 0;
5590 max
= hw_coal
->bufs_per_record
* 128;
5591 if (hw_coal
->budget
)
5592 max
= hw_coal
->bufs_per_record
* hw_coal
->budget
;
5593 max
= min_t(u16
, max
, coal_cap
->num_cmpl_aggr_int_max
);
5595 val
= clamp_t(u16
, hw_coal
->coal_bufs
, 1, max
);
5596 req
->num_cmpl_aggr_int
= cpu_to_le16(val
);
5598 val
= min_t(u16
, val
, coal_cap
->num_cmpl_dma_aggr_max
);
5599 req
->num_cmpl_dma_aggr
= cpu_to_le16(val
);
5601 val
= clamp_t(u16
, hw_coal
->coal_bufs_irq
, 1,
5602 coal_cap
->num_cmpl_dma_aggr_during_int_max
);
5603 req
->num_cmpl_dma_aggr_during_int
= cpu_to_le16(val
);
5605 tmr
= bnxt_usec_to_coal_tmr(bp
, hw_coal
->coal_ticks
);
5606 tmr
= clamp_t(u16
, tmr
, 1, coal_cap
->int_lat_tmr_max_max
);
5607 req
->int_lat_tmr_max
= cpu_to_le16(tmr
);
5609 /* min timer set to 1/2 of interrupt timer */
5610 if (cmpl_params
& RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN
) {
5612 val
= clamp_t(u16
, val
, 1, coal_cap
->int_lat_tmr_min_max
);
5613 req
->int_lat_tmr_min
= cpu_to_le16(val
);
5614 req
->enables
|= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE
);
5617 /* buf timer set to 1/4 of interrupt timer */
5618 val
= clamp_t(u16
, tmr
/ 4, 1, coal_cap
->cmpl_aggr_dma_tmr_max
);
5619 req
->cmpl_aggr_dma_tmr
= cpu_to_le16(val
);
5622 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT
) {
5623 tmr
= bnxt_usec_to_coal_tmr(bp
, hw_coal
->coal_ticks_irq
);
5624 val
= clamp_t(u16
, tmr
, 1,
5625 coal_cap
->cmpl_aggr_dma_tmr_during_int_max
);
5626 req
->cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(tmr
);
5628 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE
);
5631 if (cmpl_params
& RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET
)
5632 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
5633 if ((cmpl_params
& RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE
) &&
5634 hw_coal
->idle_thresh
&& hw_coal
->coal_ticks
< hw_coal
->idle_thresh
)
5635 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
5636 req
->flags
= cpu_to_le16(flags
);
5637 req
->enables
|= cpu_to_le16(BNXT_COAL_CMPL_ENABLES
);
5640 /* Caller holds bp->hwrm_cmd_lock */
5641 static int __bnxt_hwrm_set_coal_nq(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
5642 struct bnxt_coal
*hw_coal
)
5644 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req
= {0};
5645 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5646 struct bnxt_coal_cap
*coal_cap
= &bp
->coal_cap
;
5647 u32 nq_params
= coal_cap
->nq_params
;
5650 if (!(nq_params
& RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN
))
5653 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
,
5655 req
.ring_id
= cpu_to_le16(cpr
->cp_ring_struct
.fw_ring_id
);
5657 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ
);
5659 tmr
= bnxt_usec_to_coal_tmr(bp
, hw_coal
->coal_ticks
) / 2;
5660 tmr
= clamp_t(u16
, tmr
, 1, coal_cap
->int_lat_tmr_min_max
);
5661 req
.int_lat_tmr_min
= cpu_to_le16(tmr
);
5662 req
.enables
|= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE
);
5663 return _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5666 int bnxt_hwrm_set_ring_coal(struct bnxt
*bp
, struct bnxt_napi
*bnapi
)
5668 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx
= {0};
5669 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5670 struct bnxt_coal coal
;
5672 /* Tick values in micro seconds.
5673 * 1 coal_buf x bufs_per_record = 1 completion record.
5675 memcpy(&coal
, &bp
->rx_coal
, sizeof(struct bnxt_coal
));
5677 coal
.coal_ticks
= cpr
->rx_ring_coal
.coal_ticks
;
5678 coal
.coal_bufs
= cpr
->rx_ring_coal
.coal_bufs
;
5680 if (!bnapi
->rx_ring
)
5683 bnxt_hwrm_cmd_hdr_init(bp
, &req_rx
,
5684 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
5686 bnxt_hwrm_set_coal_params(bp
, &coal
, &req_rx
);
5688 req_rx
.ring_id
= cpu_to_le16(bnxt_cp_ring_for_rx(bp
, bnapi
->rx_ring
));
5690 return hwrm_send_message(bp
, &req_rx
, sizeof(req_rx
),
5694 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
5697 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx
= {0},
5700 bnxt_hwrm_cmd_hdr_init(bp
, &req_rx
,
5701 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
5702 bnxt_hwrm_cmd_hdr_init(bp
, &req_tx
,
5703 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
5705 bnxt_hwrm_set_coal_params(bp
, &bp
->rx_coal
, &req_rx
);
5706 bnxt_hwrm_set_coal_params(bp
, &bp
->tx_coal
, &req_tx
);
5708 mutex_lock(&bp
->hwrm_cmd_lock
);
5709 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5710 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
5711 struct bnxt_coal
*hw_coal
;
5715 if (!bnapi
->rx_ring
) {
5716 ring_id
= bnxt_cp_ring_for_tx(bp
, bnapi
->tx_ring
);
5719 ring_id
= bnxt_cp_ring_for_rx(bp
, bnapi
->rx_ring
);
5721 req
->ring_id
= cpu_to_le16(ring_id
);
5723 rc
= _hwrm_send_message(bp
, req
, sizeof(*req
),
5728 if (!(bp
->flags
& BNXT_FLAG_CHIP_P5
))
5731 if (bnapi
->rx_ring
&& bnapi
->tx_ring
) {
5733 ring_id
= bnxt_cp_ring_for_tx(bp
, bnapi
->tx_ring
);
5734 req
->ring_id
= cpu_to_le16(ring_id
);
5735 rc
= _hwrm_send_message(bp
, req
, sizeof(*req
),
5741 hw_coal
= &bp
->rx_coal
;
5743 hw_coal
= &bp
->tx_coal
;
5744 __bnxt_hwrm_set_coal_nq(bp
, bnapi
, hw_coal
);
5746 mutex_unlock(&bp
->hwrm_cmd_lock
);
5750 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
5753 struct hwrm_stat_ctx_free_input req
= {0};
5758 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
5761 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
5763 mutex_lock(&bp
->hwrm_cmd_lock
);
5764 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5765 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
5766 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5768 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
5769 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
5771 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
5776 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
5779 mutex_unlock(&bp
->hwrm_cmd_lock
);
5783 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
5786 struct hwrm_stat_ctx_alloc_input req
= {0};
5787 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5789 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
5792 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
5794 req
.update_period_ms
= cpu_to_le32(bp
->stats_coal_ticks
/ 1000);
5796 mutex_lock(&bp
->hwrm_cmd_lock
);
5797 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5798 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
5799 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5801 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
5803 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
5808 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
5810 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
5812 mutex_unlock(&bp
->hwrm_cmd_lock
);
5816 static int bnxt_hwrm_func_qcfg(struct bnxt
*bp
)
5818 struct hwrm_func_qcfg_input req
= {0};
5819 struct hwrm_func_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5823 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCFG
, -1, -1);
5824 req
.fid
= cpu_to_le16(0xffff);
5825 mutex_lock(&bp
->hwrm_cmd_lock
);
5826 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5828 goto func_qcfg_exit
;
5830 #ifdef CONFIG_BNXT_SRIOV
5832 struct bnxt_vf_info
*vf
= &bp
->vf
;
5834 vf
->vlan
= le16_to_cpu(resp
->vlan
) & VLAN_VID_MASK
;
5837 flags
= le16_to_cpu(resp
->flags
);
5838 if (flags
& (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED
|
5839 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED
)) {
5840 bp
->fw_cap
|= BNXT_FW_CAP_LLDP_AGENT
;
5841 if (flags
& FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED
)
5842 bp
->fw_cap
|= BNXT_FW_CAP_DCBX_AGENT
;
5844 if (BNXT_PF(bp
) && (flags
& FUNC_QCFG_RESP_FLAGS_MULTI_HOST
))
5845 bp
->flags
|= BNXT_FLAG_MULTI_HOST
;
5847 switch (resp
->port_partition_type
) {
5848 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0
:
5849 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5
:
5850 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0
:
5851 bp
->port_partition_type
= resp
->port_partition_type
;
5854 if (bp
->hwrm_spec_code
< 0x10707 ||
5855 resp
->evb_mode
== FUNC_QCFG_RESP_EVB_MODE_VEB
)
5856 bp
->br_mode
= BRIDGE_MODE_VEB
;
5857 else if (resp
->evb_mode
== FUNC_QCFG_RESP_EVB_MODE_VEPA
)
5858 bp
->br_mode
= BRIDGE_MODE_VEPA
;
5860 bp
->br_mode
= BRIDGE_MODE_UNDEF
;
5862 bp
->max_mtu
= le16_to_cpu(resp
->max_mtu_configured
);
5864 bp
->max_mtu
= BNXT_MAX_MTU
;
5867 mutex_unlock(&bp
->hwrm_cmd_lock
);
5871 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt
*bp
)
5873 struct hwrm_func_backing_store_qcaps_input req
= {0};
5874 struct hwrm_func_backing_store_qcaps_output
*resp
=
5875 bp
->hwrm_cmd_resp_addr
;
5878 if (bp
->hwrm_spec_code
< 0x10902 || BNXT_VF(bp
) || bp
->ctx
)
5881 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_BACKING_STORE_QCAPS
, -1, -1);
5882 mutex_lock(&bp
->hwrm_cmd_lock
);
5883 rc
= _hwrm_send_message_silent(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5885 struct bnxt_ctx_pg_info
*ctx_pg
;
5886 struct bnxt_ctx_mem_info
*ctx
;
5889 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
5894 ctx_pg
= kzalloc(sizeof(*ctx_pg
) * (bp
->max_q
+ 1), GFP_KERNEL
);
5900 for (i
= 0; i
< bp
->max_q
+ 1; i
++, ctx_pg
++)
5901 ctx
->tqm_mem
[i
] = ctx_pg
;
5904 ctx
->qp_max_entries
= le32_to_cpu(resp
->qp_max_entries
);
5905 ctx
->qp_min_qp1_entries
= le16_to_cpu(resp
->qp_min_qp1_entries
);
5906 ctx
->qp_max_l2_entries
= le16_to_cpu(resp
->qp_max_l2_entries
);
5907 ctx
->qp_entry_size
= le16_to_cpu(resp
->qp_entry_size
);
5908 ctx
->srq_max_l2_entries
= le16_to_cpu(resp
->srq_max_l2_entries
);
5909 ctx
->srq_max_entries
= le32_to_cpu(resp
->srq_max_entries
);
5910 ctx
->srq_entry_size
= le16_to_cpu(resp
->srq_entry_size
);
5911 ctx
->cq_max_l2_entries
= le16_to_cpu(resp
->cq_max_l2_entries
);
5912 ctx
->cq_max_entries
= le32_to_cpu(resp
->cq_max_entries
);
5913 ctx
->cq_entry_size
= le16_to_cpu(resp
->cq_entry_size
);
5914 ctx
->vnic_max_vnic_entries
=
5915 le16_to_cpu(resp
->vnic_max_vnic_entries
);
5916 ctx
->vnic_max_ring_table_entries
=
5917 le16_to_cpu(resp
->vnic_max_ring_table_entries
);
5918 ctx
->vnic_entry_size
= le16_to_cpu(resp
->vnic_entry_size
);
5919 ctx
->stat_max_entries
= le32_to_cpu(resp
->stat_max_entries
);
5920 ctx
->stat_entry_size
= le16_to_cpu(resp
->stat_entry_size
);
5921 ctx
->tqm_entry_size
= le16_to_cpu(resp
->tqm_entry_size
);
5922 ctx
->tqm_min_entries_per_ring
=
5923 le32_to_cpu(resp
->tqm_min_entries_per_ring
);
5924 ctx
->tqm_max_entries_per_ring
=
5925 le32_to_cpu(resp
->tqm_max_entries_per_ring
);
5926 ctx
->tqm_entries_multiple
= resp
->tqm_entries_multiple
;
5927 if (!ctx
->tqm_entries_multiple
)
5928 ctx
->tqm_entries_multiple
= 1;
5929 ctx
->mrav_max_entries
= le32_to_cpu(resp
->mrav_max_entries
);
5930 ctx
->mrav_entry_size
= le16_to_cpu(resp
->mrav_entry_size
);
5931 ctx
->tim_entry_size
= le16_to_cpu(resp
->tim_entry_size
);
5932 ctx
->tim_max_entries
= le32_to_cpu(resp
->tim_max_entries
);
5937 mutex_unlock(&bp
->hwrm_cmd_lock
);
5941 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info
*rmem
, u8
*pg_attr
,
5946 if (BNXT_PAGE_SHIFT
== 13)
5948 else if (BNXT_PAGE_SIZE
== 16)
5952 if (rmem
->nr_pages
> 1) {
5954 *pg_dir
= cpu_to_le64(rmem
->pg_tbl_map
);
5956 *pg_dir
= cpu_to_le64(rmem
->dma_arr
[0]);
5960 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \
5961 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \
5962 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \
5963 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \
5964 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \
5965 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
5967 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt
*bp
, u32 enables
)
5969 struct hwrm_func_backing_store_cfg_input req
= {0};
5970 struct bnxt_ctx_mem_info
*ctx
= bp
->ctx
;
5971 struct bnxt_ctx_pg_info
*ctx_pg
;
5972 __le32
*num_entries
;
5981 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_BACKING_STORE_CFG
, -1, -1);
5982 req
.enables
= cpu_to_le32(enables
);
5984 if (enables
& FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP
) {
5985 ctx_pg
= &ctx
->qp_mem
;
5986 req
.qp_num_entries
= cpu_to_le32(ctx_pg
->entries
);
5987 req
.qp_num_qp1_entries
= cpu_to_le16(ctx
->qp_min_qp1_entries
);
5988 req
.qp_num_l2_entries
= cpu_to_le16(ctx
->qp_max_l2_entries
);
5989 req
.qp_entry_size
= cpu_to_le16(ctx
->qp_entry_size
);
5990 bnxt_hwrm_set_pg_attr(&ctx_pg
->ring_mem
,
5991 &req
.qpc_pg_size_qpc_lvl
,
5994 if (enables
& FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ
) {
5995 ctx_pg
= &ctx
->srq_mem
;
5996 req
.srq_num_entries
= cpu_to_le32(ctx_pg
->entries
);
5997 req
.srq_num_l2_entries
= cpu_to_le16(ctx
->srq_max_l2_entries
);
5998 req
.srq_entry_size
= cpu_to_le16(ctx
->srq_entry_size
);
5999 bnxt_hwrm_set_pg_attr(&ctx_pg
->ring_mem
,
6000 &req
.srq_pg_size_srq_lvl
,
6003 if (enables
& FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ
) {
6004 ctx_pg
= &ctx
->cq_mem
;
6005 req
.cq_num_entries
= cpu_to_le32(ctx_pg
->entries
);
6006 req
.cq_num_l2_entries
= cpu_to_le16(ctx
->cq_max_l2_entries
);
6007 req
.cq_entry_size
= cpu_to_le16(ctx
->cq_entry_size
);
6008 bnxt_hwrm_set_pg_attr(&ctx_pg
->ring_mem
, &req
.cq_pg_size_cq_lvl
,
6011 if (enables
& FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC
) {
6012 ctx_pg
= &ctx
->vnic_mem
;
6013 req
.vnic_num_vnic_entries
=
6014 cpu_to_le16(ctx
->vnic_max_vnic_entries
);
6015 req
.vnic_num_ring_table_entries
=
6016 cpu_to_le16(ctx
->vnic_max_ring_table_entries
);
6017 req
.vnic_entry_size
= cpu_to_le16(ctx
->vnic_entry_size
);
6018 bnxt_hwrm_set_pg_attr(&ctx_pg
->ring_mem
,
6019 &req
.vnic_pg_size_vnic_lvl
,
6020 &req
.vnic_page_dir
);
6022 if (enables
& FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT
) {
6023 ctx_pg
= &ctx
->stat_mem
;
6024 req
.stat_num_entries
= cpu_to_le32(ctx
->stat_max_entries
);
6025 req
.stat_entry_size
= cpu_to_le16(ctx
->stat_entry_size
);
6026 bnxt_hwrm_set_pg_attr(&ctx_pg
->ring_mem
,
6027 &req
.stat_pg_size_stat_lvl
,
6028 &req
.stat_page_dir
);
6030 for (i
= 0, num_entries
= &req
.tqm_sp_num_entries
,
6031 pg_attr
= &req
.tqm_sp_pg_size_tqm_sp_lvl
,
6032 pg_dir
= &req
.tqm_sp_page_dir
,
6033 ena
= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP
;
6034 i
< 9; i
++, num_entries
++, pg_attr
++, pg_dir
++, ena
<<= 1) {
6035 if (!(enables
& ena
))
6038 req
.tqm_entry_size
= cpu_to_le16(ctx
->tqm_entry_size
);
6039 ctx_pg
= ctx
->tqm_mem
[i
];
6040 *num_entries
= cpu_to_le32(ctx_pg
->entries
);
6041 bnxt_hwrm_set_pg_attr(&ctx_pg
->ring_mem
, pg_attr
, pg_dir
);
6043 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6049 static int bnxt_alloc_ctx_mem_blk(struct bnxt
*bp
,
6050 struct bnxt_ctx_pg_info
*ctx_pg
, u32 mem_size
)
6052 struct bnxt_ring_mem_info
*rmem
= &ctx_pg
->ring_mem
;
6057 rmem
->nr_pages
= DIV_ROUND_UP(mem_size
, BNXT_PAGE_SIZE
);
6058 if (rmem
->nr_pages
> MAX_CTX_PAGES
) {
6062 rmem
->page_size
= BNXT_PAGE_SIZE
;
6063 rmem
->pg_arr
= ctx_pg
->ctx_pg_arr
;
6064 rmem
->dma_arr
= ctx_pg
->ctx_dma_arr
;
6065 rmem
->flags
= BNXT_RMEM_VALID_PTE_FLAG
;
6066 return bnxt_alloc_ring(bp
, rmem
);
6069 static void bnxt_free_ctx_mem(struct bnxt
*bp
)
6071 struct bnxt_ctx_mem_info
*ctx
= bp
->ctx
;
6077 if (ctx
->tqm_mem
[0]) {
6078 for (i
= 0; i
< bp
->max_q
+ 1; i
++)
6079 bnxt_free_ring(bp
, &ctx
->tqm_mem
[i
]->ring_mem
);
6080 kfree(ctx
->tqm_mem
[0]);
6081 ctx
->tqm_mem
[0] = NULL
;
6084 bnxt_free_ring(bp
, &ctx
->stat_mem
.ring_mem
);
6085 bnxt_free_ring(bp
, &ctx
->vnic_mem
.ring_mem
);
6086 bnxt_free_ring(bp
, &ctx
->cq_mem
.ring_mem
);
6087 bnxt_free_ring(bp
, &ctx
->srq_mem
.ring_mem
);
6088 bnxt_free_ring(bp
, &ctx
->qp_mem
.ring_mem
);
6089 ctx
->flags
&= ~BNXT_CTX_FLAG_INITED
;
6092 static int bnxt_alloc_ctx_mem(struct bnxt
*bp
)
6094 struct bnxt_ctx_pg_info
*ctx_pg
;
6095 struct bnxt_ctx_mem_info
*ctx
;
6096 u32 mem_size
, ena
, entries
;
6099 rc
= bnxt_hwrm_func_backing_store_qcaps(bp
);
6101 netdev_err(bp
->dev
, "Failed querying context mem capability, rc = %d.\n",
6106 if (!ctx
|| (ctx
->flags
& BNXT_CTX_FLAG_INITED
))
6109 ctx_pg
= &ctx
->qp_mem
;
6110 ctx_pg
->entries
= ctx
->qp_min_qp1_entries
+ ctx
->qp_max_l2_entries
;
6111 mem_size
= ctx
->qp_entry_size
* ctx_pg
->entries
;
6112 rc
= bnxt_alloc_ctx_mem_blk(bp
, ctx_pg
, mem_size
);
6116 ctx_pg
= &ctx
->srq_mem
;
6117 ctx_pg
->entries
= ctx
->srq_max_l2_entries
;
6118 mem_size
= ctx
->srq_entry_size
* ctx_pg
->entries
;
6119 rc
= bnxt_alloc_ctx_mem_blk(bp
, ctx_pg
, mem_size
);
6123 ctx_pg
= &ctx
->cq_mem
;
6124 ctx_pg
->entries
= ctx
->cq_max_l2_entries
;
6125 mem_size
= ctx
->cq_entry_size
* ctx_pg
->entries
;
6126 rc
= bnxt_alloc_ctx_mem_blk(bp
, ctx_pg
, mem_size
);
6130 ctx_pg
= &ctx
->vnic_mem
;
6131 ctx_pg
->entries
= ctx
->vnic_max_vnic_entries
+
6132 ctx
->vnic_max_ring_table_entries
;
6133 mem_size
= ctx
->vnic_entry_size
* ctx_pg
->entries
;
6134 rc
= bnxt_alloc_ctx_mem_blk(bp
, ctx_pg
, mem_size
);
6138 ctx_pg
= &ctx
->stat_mem
;
6139 ctx_pg
->entries
= ctx
->stat_max_entries
;
6140 mem_size
= ctx
->stat_entry_size
* ctx_pg
->entries
;
6141 rc
= bnxt_alloc_ctx_mem_blk(bp
, ctx_pg
, mem_size
);
6145 entries
= ctx
->qp_max_l2_entries
;
6146 entries
= roundup(entries
, ctx
->tqm_entries_multiple
);
6147 entries
= clamp_t(u32
, entries
, ctx
->tqm_min_entries_per_ring
,
6148 ctx
->tqm_max_entries_per_ring
);
6149 for (i
= 0, ena
= 0; i
< bp
->max_q
+ 1; i
++) {
6150 ctx_pg
= ctx
->tqm_mem
[i
];
6151 ctx_pg
->entries
= entries
;
6152 mem_size
= ctx
->tqm_entry_size
* entries
;
6153 rc
= bnxt_alloc_ctx_mem_blk(bp
, ctx_pg
, mem_size
);
6156 ena
|= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP
<< i
;
6158 ena
|= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES
;
6159 rc
= bnxt_hwrm_func_backing_store_cfg(bp
, ena
);
6161 netdev_err(bp
->dev
, "Failed configuring context mem, rc = %d.\n",
6164 ctx
->flags
|= BNXT_CTX_FLAG_INITED
;
6169 int bnxt_hwrm_func_resc_qcaps(struct bnxt
*bp
, bool all
)
6171 struct hwrm_func_resource_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
6172 struct hwrm_func_resource_qcaps_input req
= {0};
6173 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
6176 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESOURCE_QCAPS
, -1, -1);
6177 req
.fid
= cpu_to_le16(0xffff);
6179 mutex_lock(&bp
->hwrm_cmd_lock
);
6180 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6183 goto hwrm_func_resc_qcaps_exit
;
6186 hw_resc
->max_tx_sch_inputs
= le16_to_cpu(resp
->max_tx_scheduler_inputs
);
6188 goto hwrm_func_resc_qcaps_exit
;
6190 hw_resc
->min_rsscos_ctxs
= le16_to_cpu(resp
->min_rsscos_ctx
);
6191 hw_resc
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
6192 hw_resc
->min_cp_rings
= le16_to_cpu(resp
->min_cmpl_rings
);
6193 hw_resc
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
6194 hw_resc
->min_tx_rings
= le16_to_cpu(resp
->min_tx_rings
);
6195 hw_resc
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
6196 hw_resc
->min_rx_rings
= le16_to_cpu(resp
->min_rx_rings
);
6197 hw_resc
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
6198 hw_resc
->min_hw_ring_grps
= le16_to_cpu(resp
->min_hw_ring_grps
);
6199 hw_resc
->max_hw_ring_grps
= le16_to_cpu(resp
->max_hw_ring_grps
);
6200 hw_resc
->min_l2_ctxs
= le16_to_cpu(resp
->min_l2_ctxs
);
6201 hw_resc
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
6202 hw_resc
->min_vnics
= le16_to_cpu(resp
->min_vnics
);
6203 hw_resc
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
6204 hw_resc
->min_stat_ctxs
= le16_to_cpu(resp
->min_stat_ctx
);
6205 hw_resc
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
6207 if (bp
->flags
& BNXT_FLAG_CHIP_P5
) {
6208 u16 max_msix
= le16_to_cpu(resp
->max_msix
);
6210 hw_resc
->max_irqs
= min_t(u16
, hw_resc
->max_irqs
, max_msix
);
6211 hw_resc
->max_hw_ring_grps
= hw_resc
->max_rx_rings
;
6215 struct bnxt_pf_info
*pf
= &bp
->pf
;
6217 pf
->vf_resv_strategy
=
6218 le16_to_cpu(resp
->vf_reservation_strategy
);
6219 if (pf
->vf_resv_strategy
> BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC
)
6220 pf
->vf_resv_strategy
= BNXT_VF_RESV_STRATEGY_MAXIMAL
;
6222 hwrm_func_resc_qcaps_exit
:
6223 mutex_unlock(&bp
->hwrm_cmd_lock
);
6227 static int __bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
6230 struct hwrm_func_qcaps_input req
= {0};
6231 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
6232 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
6235 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
6236 req
.fid
= cpu_to_le16(0xffff);
6238 mutex_lock(&bp
->hwrm_cmd_lock
);
6239 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6241 goto hwrm_func_qcaps_exit
;
6243 flags
= le32_to_cpu(resp
->flags
);
6244 if (flags
& FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED
)
6245 bp
->flags
|= BNXT_FLAG_ROCEV1_CAP
;
6246 if (flags
& FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED
)
6247 bp
->flags
|= BNXT_FLAG_ROCEV2_CAP
;
6249 bp
->tx_push_thresh
= 0;
6250 if (flags
& FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
)
6251 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
6253 hw_resc
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
6254 hw_resc
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
6255 hw_resc
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
6256 hw_resc
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
6257 hw_resc
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
6258 if (!hw_resc
->max_hw_ring_grps
)
6259 hw_resc
->max_hw_ring_grps
= hw_resc
->max_tx_rings
;
6260 hw_resc
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
6261 hw_resc
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
6262 hw_resc
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
6265 struct bnxt_pf_info
*pf
= &bp
->pf
;
6267 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
6268 pf
->port_id
= le16_to_cpu(resp
->port_id
);
6269 bp
->dev
->dev_port
= pf
->port_id
;
6270 memcpy(pf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
6271 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
6272 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
6273 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
6274 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
6275 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
6276 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
6277 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
6278 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
6279 if (flags
& FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED
)
6280 bp
->flags
|= BNXT_FLAG_WOL_CAP
;
6282 #ifdef CONFIG_BNXT_SRIOV
6283 struct bnxt_vf_info
*vf
= &bp
->vf
;
6285 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
6286 memcpy(vf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
6290 hwrm_func_qcaps_exit
:
6291 mutex_unlock(&bp
->hwrm_cmd_lock
);
6295 static int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
6299 rc
= __bnxt_hwrm_func_qcaps(bp
);
6302 if (bp
->hwrm_spec_code
>= 0x10803) {
6303 rc
= bnxt_alloc_ctx_mem(bp
);
6306 rc
= bnxt_hwrm_func_resc_qcaps(bp
, true);
6308 bp
->fw_cap
|= BNXT_FW_CAP_NEW_RM
;
6313 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
6315 struct hwrm_func_reset_input req
= {0};
6317 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
6320 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
6323 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
6326 struct hwrm_queue_qportcfg_input req
= {0};
6327 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
6331 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
6333 mutex_lock(&bp
->hwrm_cmd_lock
);
6334 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6338 if (!resp
->max_configurable_queues
) {
6342 bp
->max_tc
= resp
->max_configurable_queues
;
6343 bp
->max_lltc
= resp
->max_configurable_lossless_queues
;
6344 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
6345 bp
->max_tc
= BNXT_MAX_QUEUE
;
6347 no_rdma
= !(bp
->flags
& BNXT_FLAG_ROCE_CAP
);
6348 qptr
= &resp
->queue_id0
;
6349 for (i
= 0, j
= 0; i
< bp
->max_tc
; i
++) {
6350 bp
->q_info
[j
].queue_id
= *qptr
;
6351 bp
->q_ids
[i
] = *qptr
++;
6352 bp
->q_info
[j
].queue_profile
= *qptr
++;
6353 bp
->tc_to_qidx
[j
] = j
;
6354 if (!BNXT_CNPQ(bp
->q_info
[j
].queue_profile
) ||
6355 (no_rdma
&& BNXT_PF(bp
)))
6358 bp
->max_q
= bp
->max_tc
;
6359 bp
->max_tc
= max_t(u8
, j
, 1);
6361 if (resp
->queue_cfg_info
& QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG
)
6364 if (bp
->max_lltc
> bp
->max_tc
)
6365 bp
->max_lltc
= bp
->max_tc
;
6368 mutex_unlock(&bp
->hwrm_cmd_lock
);
6372 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
6375 struct hwrm_ver_get_input req
= {0};
6376 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
6379 bp
->hwrm_max_req_len
= HWRM_MAX_REQ_LEN
;
6380 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
6381 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
6382 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
6383 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
6384 mutex_lock(&bp
->hwrm_cmd_lock
);
6385 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6387 goto hwrm_ver_get_exit
;
6389 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
6391 bp
->hwrm_spec_code
= resp
->hwrm_intf_maj_8b
<< 16 |
6392 resp
->hwrm_intf_min_8b
<< 8 |
6393 resp
->hwrm_intf_upd_8b
;
6394 if (resp
->hwrm_intf_maj_8b
< 1) {
6395 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
6396 resp
->hwrm_intf_maj_8b
, resp
->hwrm_intf_min_8b
,
6397 resp
->hwrm_intf_upd_8b
);
6398 netdev_warn(bp
->dev
, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
6400 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "%d.%d.%d.%d",
6401 resp
->hwrm_fw_maj_8b
, resp
->hwrm_fw_min_8b
,
6402 resp
->hwrm_fw_bld_8b
, resp
->hwrm_fw_rsvd_8b
);
6404 bp
->hwrm_cmd_timeout
= le16_to_cpu(resp
->def_req_timeout
);
6405 if (!bp
->hwrm_cmd_timeout
)
6406 bp
->hwrm_cmd_timeout
= DFLT_HWRM_CMD_TIMEOUT
;
6408 if (resp
->hwrm_intf_maj_8b
>= 1) {
6409 bp
->hwrm_max_req_len
= le16_to_cpu(resp
->max_req_win_len
);
6410 bp
->hwrm_max_ext_req_len
= le16_to_cpu(resp
->max_ext_req_len
);
6412 if (bp
->hwrm_max_ext_req_len
< HWRM_MAX_REQ_LEN
)
6413 bp
->hwrm_max_ext_req_len
= HWRM_MAX_REQ_LEN
;
6415 bp
->chip_num
= le16_to_cpu(resp
->chip_num
);
6416 if (bp
->chip_num
== CHIP_NUM_58700
&& !resp
->chip_rev
&&
6418 bp
->flags
|= BNXT_FLAG_CHIP_NITRO_A0
;
6420 dev_caps_cfg
= le32_to_cpu(resp
->dev_caps_cfg
);
6421 if ((dev_caps_cfg
& VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED
) &&
6422 (dev_caps_cfg
& VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED
))
6423 bp
->fw_cap
|= BNXT_FW_CAP_SHORT_CMD
;
6426 mutex_unlock(&bp
->hwrm_cmd_lock
);
6430 int bnxt_hwrm_fw_set_time(struct bnxt
*bp
)
6432 struct hwrm_fw_set_time_input req
= {0};
6434 time64_t now
= ktime_get_real_seconds();
6436 if ((BNXT_VF(bp
) && bp
->hwrm_spec_code
< 0x10901) ||
6437 bp
->hwrm_spec_code
< 0x10400)
6440 time64_to_tm(now
, 0, &tm
);
6441 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FW_SET_TIME
, -1, -1);
6442 req
.year
= cpu_to_le16(1900 + tm
.tm_year
);
6443 req
.month
= 1 + tm
.tm_mon
;
6444 req
.day
= tm
.tm_mday
;
6445 req
.hour
= tm
.tm_hour
;
6446 req
.minute
= tm
.tm_min
;
6447 req
.second
= tm
.tm_sec
;
6448 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6451 static int bnxt_hwrm_port_qstats(struct bnxt
*bp
)
6454 struct bnxt_pf_info
*pf
= &bp
->pf
;
6455 struct hwrm_port_qstats_input req
= {0};
6457 if (!(bp
->flags
& BNXT_FLAG_PORT_STATS
))
6460 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_QSTATS
, -1, -1);
6461 req
.port_id
= cpu_to_le16(pf
->port_id
);
6462 req
.tx_stat_host_addr
= cpu_to_le64(bp
->hw_tx_port_stats_map
);
6463 req
.rx_stat_host_addr
= cpu_to_le64(bp
->hw_rx_port_stats_map
);
6464 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6468 static int bnxt_hwrm_port_qstats_ext(struct bnxt
*bp
)
6470 struct hwrm_port_qstats_ext_output
*resp
= bp
->hwrm_cmd_resp_addr
;
6471 struct hwrm_port_qstats_ext_input req
= {0};
6472 struct bnxt_pf_info
*pf
= &bp
->pf
;
6475 if (!(bp
->flags
& BNXT_FLAG_PORT_STATS_EXT
))
6478 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_QSTATS_EXT
, -1, -1);
6479 req
.port_id
= cpu_to_le16(pf
->port_id
);
6480 req
.rx_stat_size
= cpu_to_le16(sizeof(struct rx_port_stats_ext
));
6481 req
.rx_stat_host_addr
= cpu_to_le64(bp
->hw_rx_port_stats_ext_map
);
6482 req
.tx_stat_size
= cpu_to_le16(sizeof(struct tx_port_stats_ext
));
6483 req
.tx_stat_host_addr
= cpu_to_le64(bp
->hw_tx_port_stats_ext_map
);
6484 mutex_lock(&bp
->hwrm_cmd_lock
);
6485 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6487 bp
->fw_rx_stats_ext_size
= le16_to_cpu(resp
->rx_stat_size
) / 8;
6488 bp
->fw_tx_stats_ext_size
= le16_to_cpu(resp
->tx_stat_size
) / 8;
6490 bp
->fw_rx_stats_ext_size
= 0;
6491 bp
->fw_tx_stats_ext_size
= 0;
6493 mutex_unlock(&bp
->hwrm_cmd_lock
);
6497 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
6499 if (bp
->vxlan_port_cnt
) {
6500 bnxt_hwrm_tunnel_dst_port_free(
6501 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
6503 bp
->vxlan_port_cnt
= 0;
6504 if (bp
->nge_port_cnt
) {
6505 bnxt_hwrm_tunnel_dst_port_free(
6506 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
6508 bp
->nge_port_cnt
= 0;
6511 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
6517 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
6518 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
6519 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
6521 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
6529 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
6533 for (i
= 0; i
< bp
->nr_vnics
; i
++)
6534 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
6537 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
6540 if (bp
->vnic_info
) {
6541 bnxt_hwrm_clear_vnic_filter(bp
);
6542 /* clear all RSS setting before free vnic ctx */
6543 bnxt_hwrm_clear_vnic_rss(bp
);
6544 bnxt_hwrm_vnic_ctx_free(bp
);
6545 /* before free the vnic, undo the vnic tpa settings */
6546 if (bp
->flags
& BNXT_FLAG_TPA
)
6547 bnxt_set_tpa(bp
, false);
6548 bnxt_hwrm_vnic_free(bp
);
6550 bnxt_hwrm_ring_free(bp
, close_path
);
6551 bnxt_hwrm_ring_grp_free(bp
);
6553 bnxt_hwrm_stat_ctx_free(bp
);
6554 bnxt_hwrm_free_tunnel_ports(bp
);
6558 static int bnxt_hwrm_set_br_mode(struct bnxt
*bp
, u16 br_mode
)
6560 struct hwrm_func_cfg_input req
= {0};
6563 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_CFG
, -1, -1);
6564 req
.fid
= cpu_to_le16(0xffff);
6565 req
.enables
= cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE
);
6566 if (br_mode
== BRIDGE_MODE_VEB
)
6567 req
.evb_mode
= FUNC_CFG_REQ_EVB_MODE_VEB
;
6568 else if (br_mode
== BRIDGE_MODE_VEPA
)
6569 req
.evb_mode
= FUNC_CFG_REQ_EVB_MODE_VEPA
;
6572 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6578 static int bnxt_hwrm_set_cache_line_size(struct bnxt
*bp
, int size
)
6580 struct hwrm_func_cfg_input req
= {0};
6583 if (BNXT_VF(bp
) || bp
->hwrm_spec_code
< 0x10803)
6586 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_CFG
, -1, -1);
6587 req
.fid
= cpu_to_le16(0xffff);
6588 req
.enables
= cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE
);
6589 req
.options
= FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64
;
6591 req
.options
= FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
;
6593 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6599 static int __bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
6601 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
6604 if (vnic
->flags
& BNXT_VNIC_RFS_NEW_RSS_FLAG
)
6607 /* allocate context for vnic */
6608 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
, 0);
6610 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
6612 goto vnic_setup_err
;
6614 bp
->rsscos_nr_ctxs
++;
6616 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
6617 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
, 1);
6619 netdev_err(bp
->dev
, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
6621 goto vnic_setup_err
;
6623 bp
->rsscos_nr_ctxs
++;
6627 /* configure default vnic, ring grp */
6628 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
6630 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
6632 goto vnic_setup_err
;
6635 /* Enable RSS hashing on vnic */
6636 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
6638 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
6640 goto vnic_setup_err
;
6643 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
6644 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
6646 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
6655 static int __bnxt_setup_vnic_p5(struct bnxt
*bp
, u16 vnic_id
)
6659 nr_ctxs
= DIV_ROUND_UP(bp
->rx_nr_rings
, 64);
6660 for (i
= 0; i
< nr_ctxs
; i
++) {
6661 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
, i
);
6663 netdev_err(bp
->dev
, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
6667 bp
->rsscos_nr_ctxs
++;
6672 rc
= bnxt_hwrm_vnic_set_rss_p5(bp
, vnic_id
, true);
6674 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %d\n",
6678 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
6680 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
6684 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
6685 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
6687 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
6694 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
6696 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
6697 return __bnxt_setup_vnic_p5(bp
, vnic_id
);
6699 return __bnxt_setup_vnic(bp
, vnic_id
);
6702 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
6704 #ifdef CONFIG_RFS_ACCEL
6707 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
6708 struct bnxt_vnic_info
*vnic
;
6709 u16 vnic_id
= i
+ 1;
6712 if (vnic_id
>= bp
->nr_vnics
)
6715 vnic
= &bp
->vnic_info
[vnic_id
];
6716 vnic
->flags
|= BNXT_VNIC_RFS_FLAG
;
6717 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
6718 vnic
->flags
|= BNXT_VNIC_RFS_NEW_RSS_FLAG
;
6719 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, 1);
6721 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
6725 rc
= bnxt_setup_vnic(bp
, vnic_id
);
6735 /* Allow PF and VF with default VLAN to be in promiscuous mode */
6736 static bool bnxt_promisc_ok(struct bnxt
*bp
)
6738 #ifdef CONFIG_BNXT_SRIOV
6739 if (BNXT_VF(bp
) && !bp
->vf
.vlan
)
6745 static int bnxt_setup_nitroa0_vnic(struct bnxt
*bp
)
6747 unsigned int rc
= 0;
6749 rc
= bnxt_hwrm_vnic_alloc(bp
, 1, bp
->rx_nr_rings
- 1, 1);
6751 netdev_err(bp
->dev
, "Cannot allocate special vnic for NS2 A0: %x\n",
6756 rc
= bnxt_hwrm_vnic_cfg(bp
, 1);
6758 netdev_err(bp
->dev
, "Cannot allocate special vnic for NS2 A0: %x\n",
6765 static int bnxt_cfg_rx_mode(struct bnxt
*);
6766 static bool bnxt_mc_list_updated(struct bnxt
*, u32
*);
6768 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
6770 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6772 unsigned int rx_nr_rings
= bp
->rx_nr_rings
;
6775 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
6777 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
6783 rc
= bnxt_hwrm_ring_alloc(bp
);
6785 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
6789 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
6791 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
6795 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
6798 /* default vnic 0 */
6799 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, rx_nr_rings
);
6801 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
6805 rc
= bnxt_setup_vnic(bp
, 0);
6809 if (bp
->flags
& BNXT_FLAG_RFS
) {
6810 rc
= bnxt_alloc_rfs_vnics(bp
);
6815 if (bp
->flags
& BNXT_FLAG_TPA
) {
6816 rc
= bnxt_set_tpa(bp
, true);
6822 bnxt_update_vf_mac(bp
);
6824 /* Filter for default vnic 0 */
6825 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
6827 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
6830 vnic
->uc_filter_count
= 1;
6833 if (bp
->dev
->flags
& IFF_BROADCAST
)
6834 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
6836 if ((bp
->dev
->flags
& IFF_PROMISC
) && bnxt_promisc_ok(bp
))
6837 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
6839 if (bp
->dev
->flags
& IFF_ALLMULTI
) {
6840 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
6841 vnic
->mc_list_count
= 0;
6845 bnxt_mc_list_updated(bp
, &mask
);
6846 vnic
->rx_mask
|= mask
;
6849 rc
= bnxt_cfg_rx_mode(bp
);
6853 rc
= bnxt_hwrm_set_coal(bp
);
6855 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
6858 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
6859 rc
= bnxt_setup_nitroa0_vnic(bp
);
6861 netdev_err(bp
->dev
, "Special vnic setup failure for NS2 A0 rc: %x\n",
6866 bnxt_hwrm_func_qcfg(bp
);
6867 netdev_update_features(bp
->dev
);
6873 bnxt_hwrm_resource_free(bp
, 0, true);
6878 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
6880 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
6884 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
6886 bnxt_init_cp_rings(bp
);
6887 bnxt_init_rx_rings(bp
);
6888 bnxt_init_tx_rings(bp
);
6889 bnxt_init_ring_grps(bp
, irq_re_init
);
6890 bnxt_init_vnics(bp
);
6892 return bnxt_init_chip(bp
, irq_re_init
);
6895 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
6898 struct net_device
*dev
= bp
->dev
;
6900 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
-
6901 bp
->tx_nr_rings_xdp
);
6905 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
6909 #ifdef CONFIG_RFS_ACCEL
6910 if (bp
->flags
& BNXT_FLAG_RFS
)
6911 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
6917 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
6920 int _rx
= *rx
, _tx
= *tx
;
6923 *rx
= min_t(int, _rx
, max
);
6924 *tx
= min_t(int, _tx
, max
);
6929 while (_rx
+ _tx
> max
) {
6930 if (_rx
> _tx
&& _rx
> 1)
6941 static void bnxt_setup_msix(struct bnxt
*bp
)
6943 const int len
= sizeof(bp
->irq_tbl
[0].name
);
6944 struct net_device
*dev
= bp
->dev
;
6947 tcs
= netdev_get_num_tc(dev
);
6951 for (i
= 0; i
< tcs
; i
++) {
6952 count
= bp
->tx_nr_rings_per_tc
;
6954 netdev_set_tc_queue(dev
, i
, count
, off
);
6958 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
6959 int map_idx
= bnxt_cp_num_to_irq_num(bp
, i
);
6962 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
6964 else if (i
< bp
->rx_nr_rings
)
6969 snprintf(bp
->irq_tbl
[map_idx
].name
, len
, "%s-%s-%d", dev
->name
,
6971 bp
->irq_tbl
[map_idx
].handler
= bnxt_msix
;
6975 static void bnxt_setup_inta(struct bnxt
*bp
)
6977 const int len
= sizeof(bp
->irq_tbl
[0].name
);
6979 if (netdev_get_num_tc(bp
->dev
))
6980 netdev_reset_tc(bp
->dev
);
6982 snprintf(bp
->irq_tbl
[0].name
, len
, "%s-%s-%d", bp
->dev
->name
, "TxRx",
6984 bp
->irq_tbl
[0].handler
= bnxt_inta
;
6987 static int bnxt_setup_int_mode(struct bnxt
*bp
)
6991 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
6992 bnxt_setup_msix(bp
);
6994 bnxt_setup_inta(bp
);
6996 rc
= bnxt_set_real_num_queues(bp
);
7000 #ifdef CONFIG_RFS_ACCEL
7001 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt
*bp
)
7003 return bp
->hw_resc
.max_rsscos_ctxs
;
7006 static unsigned int bnxt_get_max_func_vnics(struct bnxt
*bp
)
7008 return bp
->hw_resc
.max_vnics
;
7012 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt
*bp
)
7014 return bp
->hw_resc
.max_stat_ctxs
;
7017 void bnxt_set_max_func_stat_ctxs(struct bnxt
*bp
, unsigned int max
)
7019 bp
->hw_resc
.max_stat_ctxs
= max
;
7022 unsigned int bnxt_get_max_func_cp_rings(struct bnxt
*bp
)
7024 return bp
->hw_resc
.max_cp_rings
;
7027 unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt
*bp
)
7029 return bp
->hw_resc
.max_cp_rings
- bnxt_get_ulp_msix_num(bp
);
7032 static unsigned int bnxt_get_max_func_irqs(struct bnxt
*bp
)
7034 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
7036 return min_t(unsigned int, hw_resc
->max_irqs
, hw_resc
->max_cp_rings
);
7039 static void bnxt_set_max_func_irqs(struct bnxt
*bp
, unsigned int max_irqs
)
7041 bp
->hw_resc
.max_irqs
= max_irqs
;
7044 int bnxt_get_avail_msix(struct bnxt
*bp
, int num
)
7046 int max_cp
= bnxt_get_max_func_cp_rings(bp
);
7047 int max_irq
= bnxt_get_max_func_irqs(bp
);
7048 int total_req
= bp
->cp_nr_rings
+ num
;
7049 int max_idx
, avail_msix
;
7051 max_idx
= min_t(int, bp
->total_irqs
, max_cp
);
7052 avail_msix
= max_idx
- bp
->cp_nr_rings
;
7053 if (!BNXT_NEW_RM(bp
) || avail_msix
>= num
)
7056 if (max_irq
< total_req
) {
7057 num
= max_irq
- bp
->cp_nr_rings
;
7064 static int bnxt_get_num_msix(struct bnxt
*bp
)
7066 if (!BNXT_NEW_RM(bp
))
7067 return bnxt_get_max_func_irqs(bp
);
7069 return bnxt_cp_rings_in_use(bp
);
7072 static int bnxt_init_msix(struct bnxt
*bp
)
7074 int i
, total_vecs
, max
, rc
= 0, min
= 1, ulp_msix
;
7075 struct msix_entry
*msix_ent
;
7077 total_vecs
= bnxt_get_num_msix(bp
);
7078 max
= bnxt_get_max_func_irqs(bp
);
7079 if (total_vecs
> max
)
7085 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
7089 for (i
= 0; i
< total_vecs
; i
++) {
7090 msix_ent
[i
].entry
= i
;
7091 msix_ent
[i
].vector
= 0;
7094 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
7097 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, min
, total_vecs
);
7098 ulp_msix
= bnxt_get_ulp_msix_num(bp
);
7099 if (total_vecs
< 0 || total_vecs
< ulp_msix
) {
7101 goto msix_setup_exit
;
7104 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
7106 for (i
= 0; i
< total_vecs
; i
++)
7107 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
7109 bp
->total_irqs
= total_vecs
;
7110 /* Trim rings based upon num of vectors allocated */
7111 rc
= bnxt_trim_rings(bp
, &bp
->rx_nr_rings
, &bp
->tx_nr_rings
,
7112 total_vecs
- ulp_msix
, min
== 1);
7114 goto msix_setup_exit
;
7116 bp
->cp_nr_rings
= (min
== 1) ?
7117 max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
7118 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
7122 goto msix_setup_exit
;
7124 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
7129 netdev_err(bp
->dev
, "bnxt_init_msix err: %x\n", rc
);
7132 pci_disable_msix(bp
->pdev
);
7137 static int bnxt_init_inta(struct bnxt
*bp
)
7139 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
7144 bp
->rx_nr_rings
= 1;
7145 bp
->tx_nr_rings
= 1;
7146 bp
->cp_nr_rings
= 1;
7147 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
7148 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
7152 static int bnxt_init_int_mode(struct bnxt
*bp
)
7156 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
7157 rc
= bnxt_init_msix(bp
);
7159 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
) && BNXT_PF(bp
)) {
7160 /* fallback to INTA */
7161 rc
= bnxt_init_inta(bp
);
7166 static void bnxt_clear_int_mode(struct bnxt
*bp
)
7168 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
7169 pci_disable_msix(bp
->pdev
);
7173 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
7176 int bnxt_reserve_rings(struct bnxt
*bp
)
7178 int tcs
= netdev_get_num_tc(bp
->dev
);
7181 if (!bnxt_need_reserve_rings(bp
))
7184 rc
= __bnxt_reserve_rings(bp
);
7186 netdev_err(bp
->dev
, "ring reservation failure rc: %d\n", rc
);
7189 if (BNXT_NEW_RM(bp
) && (bnxt_get_num_msix(bp
) != bp
->total_irqs
)) {
7190 bnxt_ulp_irq_stop(bp
);
7191 bnxt_clear_int_mode(bp
);
7192 rc
= bnxt_init_int_mode(bp
);
7193 bnxt_ulp_irq_restart(bp
, rc
);
7197 if (tcs
&& (bp
->tx_nr_rings_per_tc
* tcs
!= bp
->tx_nr_rings
)) {
7198 netdev_err(bp
->dev
, "tx ring reservation failure\n");
7199 netdev_reset_tc(bp
->dev
);
7200 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
7203 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
7207 static void bnxt_free_irq(struct bnxt
*bp
)
7209 struct bnxt_irq
*irq
;
7212 #ifdef CONFIG_RFS_ACCEL
7213 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
7214 bp
->dev
->rx_cpu_rmap
= NULL
;
7216 if (!bp
->irq_tbl
|| !bp
->bnapi
)
7219 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
7220 int map_idx
= bnxt_cp_num_to_irq_num(bp
, i
);
7222 irq
= &bp
->irq_tbl
[map_idx
];
7223 if (irq
->requested
) {
7224 if (irq
->have_cpumask
) {
7225 irq_set_affinity_hint(irq
->vector
, NULL
);
7226 free_cpumask_var(irq
->cpu_mask
);
7227 irq
->have_cpumask
= 0;
7229 free_irq(irq
->vector
, bp
->bnapi
[i
]);
7236 static int bnxt_request_irq(struct bnxt
*bp
)
7239 unsigned long flags
= 0;
7240 #ifdef CONFIG_RFS_ACCEL
7241 struct cpu_rmap
*rmap
;
7244 rc
= bnxt_setup_int_mode(bp
);
7246 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
7250 #ifdef CONFIG_RFS_ACCEL
7251 rmap
= bp
->dev
->rx_cpu_rmap
;
7253 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
7254 flags
= IRQF_SHARED
;
7256 for (i
= 0, j
= 0; i
< bp
->cp_nr_rings
; i
++) {
7257 int map_idx
= bnxt_cp_num_to_irq_num(bp
, i
);
7258 struct bnxt_irq
*irq
= &bp
->irq_tbl
[map_idx
];
7260 #ifdef CONFIG_RFS_ACCEL
7261 if (rmap
&& bp
->bnapi
[i
]->rx_ring
) {
7262 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
7264 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
7269 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
7276 if (zalloc_cpumask_var(&irq
->cpu_mask
, GFP_KERNEL
)) {
7277 int numa_node
= dev_to_node(&bp
->pdev
->dev
);
7279 irq
->have_cpumask
= 1;
7280 cpumask_set_cpu(cpumask_local_spread(i
, numa_node
),
7282 rc
= irq_set_affinity_hint(irq
->vector
, irq
->cpu_mask
);
7284 netdev_warn(bp
->dev
,
7285 "Set affinity failed, IRQ = %d\n",
7294 static void bnxt_del_napi(struct bnxt
*bp
)
7301 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
7302 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
7304 napi_hash_del(&bnapi
->napi
);
7305 netif_napi_del(&bnapi
->napi
);
7307 /* We called napi_hash_del() before netif_napi_del(), we need
7308 * to respect an RCU grace period before freeing napi structures.
7313 static void bnxt_init_napi(struct bnxt
*bp
)
7316 unsigned int cp_nr_rings
= bp
->cp_nr_rings
;
7317 struct bnxt_napi
*bnapi
;
7319 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
7320 int (*poll_fn
)(struct napi_struct
*, int) = bnxt_poll
;
7322 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
7323 poll_fn
= bnxt_poll_p5
;
7324 else if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
7326 for (i
= 0; i
< cp_nr_rings
; i
++) {
7327 bnapi
= bp
->bnapi
[i
];
7328 netif_napi_add(bp
->dev
, &bnapi
->napi
, poll_fn
, 64);
7330 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
7331 bnapi
= bp
->bnapi
[cp_nr_rings
];
7332 netif_napi_add(bp
->dev
, &bnapi
->napi
,
7333 bnxt_poll_nitroa0
, 64);
7336 bnapi
= bp
->bnapi
[0];
7337 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
7341 static void bnxt_disable_napi(struct bnxt
*bp
)
7348 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
7349 struct bnxt_cp_ring_info
*cpr
= &bp
->bnapi
[i
]->cp_ring
;
7351 if (bp
->bnapi
[i
]->rx_ring
)
7352 cancel_work_sync(&cpr
->dim
.work
);
7354 napi_disable(&bp
->bnapi
[i
]->napi
);
7358 static void bnxt_enable_napi(struct bnxt
*bp
)
7362 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
7363 struct bnxt_cp_ring_info
*cpr
= &bp
->bnapi
[i
]->cp_ring
;
7364 bp
->bnapi
[i
]->in_reset
= false;
7366 if (bp
->bnapi
[i
]->rx_ring
) {
7367 INIT_WORK(&cpr
->dim
.work
, bnxt_dim_work
);
7368 cpr
->dim
.mode
= NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE
;
7370 napi_enable(&bp
->bnapi
[i
]->napi
);
7374 void bnxt_tx_disable(struct bnxt
*bp
)
7377 struct bnxt_tx_ring_info
*txr
;
7380 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
7381 txr
= &bp
->tx_ring
[i
];
7382 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
7385 /* Stop all TX queues */
7386 netif_tx_disable(bp
->dev
);
7387 netif_carrier_off(bp
->dev
);
7390 void bnxt_tx_enable(struct bnxt
*bp
)
7393 struct bnxt_tx_ring_info
*txr
;
7395 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
7396 txr
= &bp
->tx_ring
[i
];
7399 netif_tx_wake_all_queues(bp
->dev
);
7400 if (bp
->link_info
.link_up
)
7401 netif_carrier_on(bp
->dev
);
7404 static void bnxt_report_link(struct bnxt
*bp
)
7406 if (bp
->link_info
.link_up
) {
7408 const char *flow_ctrl
;
7412 netif_carrier_on(bp
->dev
);
7413 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
7417 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
7418 flow_ctrl
= "ON - receive & transmit";
7419 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
7420 flow_ctrl
= "ON - transmit";
7421 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
7422 flow_ctrl
= "ON - receive";
7425 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
7426 netdev_info(bp
->dev
, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
7427 speed
, duplex
, flow_ctrl
);
7428 if (bp
->flags
& BNXT_FLAG_EEE_CAP
)
7429 netdev_info(bp
->dev
, "EEE is %s\n",
7430 bp
->eee
.eee_active
? "active" :
7432 fec
= bp
->link_info
.fec_cfg
;
7433 if (!(fec
& PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
))
7434 netdev_info(bp
->dev
, "FEC autoneg %s encodings: %s\n",
7435 (fec
& BNXT_FEC_AUTONEG
) ? "on" : "off",
7436 (fec
& BNXT_FEC_ENC_BASE_R
) ? "BaseR" :
7437 (fec
& BNXT_FEC_ENC_RS
) ? "RS" : "None");
7439 netif_carrier_off(bp
->dev
);
7440 netdev_err(bp
->dev
, "NIC Link is Down\n");
7444 static int bnxt_hwrm_phy_qcaps(struct bnxt
*bp
)
7447 struct hwrm_port_phy_qcaps_input req
= {0};
7448 struct hwrm_port_phy_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
7449 struct bnxt_link_info
*link_info
= &bp
->link_info
;
7451 if (bp
->hwrm_spec_code
< 0x10201)
7454 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCAPS
, -1, -1);
7456 mutex_lock(&bp
->hwrm_cmd_lock
);
7457 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
7459 goto hwrm_phy_qcaps_exit
;
7461 if (resp
->flags
& PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
) {
7462 struct ethtool_eee
*eee
= &bp
->eee
;
7463 u16 fw_speeds
= le16_to_cpu(resp
->supported_speeds_eee_mode
);
7465 bp
->flags
|= BNXT_FLAG_EEE_CAP
;
7466 eee
->supported
= _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
7467 bp
->lpi_tmr_lo
= le32_to_cpu(resp
->tx_lpi_timer_low
) &
7468 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK
;
7469 bp
->lpi_tmr_hi
= le32_to_cpu(resp
->valid_tx_lpi_timer_high
) &
7470 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK
;
7472 if (resp
->flags
& PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
) {
7474 bp
->test_info
->flags
|= BNXT_TEST_FL_EXT_LPBK
;
7476 if (resp
->supported_speeds_auto_mode
)
7477 link_info
->support_auto_speeds
=
7478 le16_to_cpu(resp
->supported_speeds_auto_mode
);
7480 bp
->port_count
= resp
->port_cnt
;
7482 hwrm_phy_qcaps_exit
:
7483 mutex_unlock(&bp
->hwrm_cmd_lock
);
7487 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
7490 struct bnxt_link_info
*link_info
= &bp
->link_info
;
7491 struct hwrm_port_phy_qcfg_input req
= {0};
7492 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
7493 u8 link_up
= link_info
->link_up
;
7496 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
7498 mutex_lock(&bp
->hwrm_cmd_lock
);
7499 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
7501 mutex_unlock(&bp
->hwrm_cmd_lock
);
7505 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
7506 link_info
->phy_link_status
= resp
->link
;
7507 link_info
->duplex
= resp
->duplex_cfg
;
7508 if (bp
->hwrm_spec_code
>= 0x10800)
7509 link_info
->duplex
= resp
->duplex_state
;
7510 link_info
->pause
= resp
->pause
;
7511 link_info
->auto_mode
= resp
->auto_mode
;
7512 link_info
->auto_pause_setting
= resp
->auto_pause
;
7513 link_info
->lp_pause
= resp
->link_partner_adv_pause
;
7514 link_info
->force_pause_setting
= resp
->force_pause
;
7515 link_info
->duplex_setting
= resp
->duplex_cfg
;
7516 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
7517 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
7519 link_info
->link_speed
= 0;
7520 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
7521 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
7522 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
7523 link_info
->lp_auto_link_speeds
=
7524 le16_to_cpu(resp
->link_partner_adv_speeds
);
7525 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
7526 link_info
->phy_ver
[0] = resp
->phy_maj
;
7527 link_info
->phy_ver
[1] = resp
->phy_min
;
7528 link_info
->phy_ver
[2] = resp
->phy_bld
;
7529 link_info
->media_type
= resp
->media_type
;
7530 link_info
->phy_type
= resp
->phy_type
;
7531 link_info
->transceiver
= resp
->xcvr_pkg_type
;
7532 link_info
->phy_addr
= resp
->eee_config_phy_addr
&
7533 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK
;
7534 link_info
->module_status
= resp
->module_status
;
7536 if (bp
->flags
& BNXT_FLAG_EEE_CAP
) {
7537 struct ethtool_eee
*eee
= &bp
->eee
;
7540 eee
->eee_active
= 0;
7541 if (resp
->eee_config_phy_addr
&
7542 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE
) {
7543 eee
->eee_active
= 1;
7544 fw_speeds
= le16_to_cpu(
7545 resp
->link_partner_adv_eee_link_speed_mask
);
7546 eee
->lp_advertised
=
7547 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
7550 /* Pull initial EEE config */
7551 if (!chng_link_state
) {
7552 if (resp
->eee_config_phy_addr
&
7553 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED
)
7554 eee
->eee_enabled
= 1;
7556 fw_speeds
= le16_to_cpu(resp
->adv_eee_link_speed_mask
);
7558 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
7560 if (resp
->eee_config_phy_addr
&
7561 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI
) {
7564 eee
->tx_lpi_enabled
= 1;
7565 tmr
= resp
->xcvr_identifier_type_tx_lpi_timer
;
7566 eee
->tx_lpi_timer
= le32_to_cpu(tmr
) &
7567 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK
;
7572 link_info
->fec_cfg
= PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
;
7573 if (bp
->hwrm_spec_code
>= 0x10504)
7574 link_info
->fec_cfg
= le16_to_cpu(resp
->fec_cfg
);
7576 /* TODO: need to add more logic to report VF link */
7577 if (chng_link_state
) {
7578 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
7579 link_info
->link_up
= 1;
7581 link_info
->link_up
= 0;
7582 if (link_up
!= link_info
->link_up
)
7583 bnxt_report_link(bp
);
7585 /* alwasy link down if not require to update link state */
7586 link_info
->link_up
= 0;
7588 mutex_unlock(&bp
->hwrm_cmd_lock
);
7590 if (!BNXT_SINGLE_PF(bp
))
7593 diff
= link_info
->support_auto_speeds
^ link_info
->advertising
;
7594 if ((link_info
->support_auto_speeds
| diff
) !=
7595 link_info
->support_auto_speeds
) {
7596 /* An advertised speed is no longer supported, so we need to
7597 * update the advertisement settings. Caller holds RTNL
7598 * so we can modify link settings.
7600 link_info
->advertising
= link_info
->support_auto_speeds
;
7601 if (link_info
->autoneg
& BNXT_AUTONEG_SPEED
)
7602 bnxt_hwrm_set_link_setting(bp
, true, false);
7607 static void bnxt_get_port_module_status(struct bnxt
*bp
)
7609 struct bnxt_link_info
*link_info
= &bp
->link_info
;
7610 struct hwrm_port_phy_qcfg_output
*resp
= &link_info
->phy_qcfg_resp
;
7613 if (bnxt_update_link(bp
, true))
7616 module_status
= link_info
->module_status
;
7617 switch (module_status
) {
7618 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
:
7619 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
:
7620 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG
:
7621 netdev_warn(bp
->dev
, "Unqualified SFP+ module detected on port %d\n",
7623 if (bp
->hwrm_spec_code
>= 0x10201) {
7624 netdev_warn(bp
->dev
, "Module part number %s\n",
7625 resp
->phy_vendor_partnumber
);
7627 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
)
7628 netdev_warn(bp
->dev
, "TX is disabled\n");
7629 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
)
7630 netdev_warn(bp
->dev
, "SFP+ module is shutdown\n");
7635 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
7637 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
7638 if (bp
->hwrm_spec_code
>= 0x10201)
7640 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
;
7641 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
7642 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
7643 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
7644 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX
;
7646 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
7648 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
7649 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
7650 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
7651 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
7653 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
7654 if (bp
->hwrm_spec_code
>= 0x10201) {
7655 req
->auto_pause
= req
->force_pause
;
7656 req
->enables
|= cpu_to_le32(
7657 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
7662 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
7663 struct hwrm_port_phy_cfg_input
*req
)
7665 u8 autoneg
= bp
->link_info
.autoneg
;
7666 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
7667 u16 advertising
= bp
->link_info
.advertising
;
7669 if (autoneg
& BNXT_AUTONEG_SPEED
) {
7671 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
;
7673 req
->enables
|= cpu_to_le32(
7674 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
7675 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
7677 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
7679 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
7681 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
7682 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
7685 /* tell chimp that the setting takes effect immediately */
7686 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
7689 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
7691 struct hwrm_port_phy_cfg_input req
= {0};
7694 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
7695 bnxt_hwrm_set_pause_common(bp
, &req
);
7697 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
7698 bp
->link_info
.force_link_chng
)
7699 bnxt_hwrm_set_link_common(bp
, &req
);
7701 mutex_lock(&bp
->hwrm_cmd_lock
);
7702 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
7703 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
7704 /* since changing of pause setting doesn't trigger any link
7705 * change event, the driver needs to update the current pause
7706 * result upon successfully return of the phy_cfg command
7708 bp
->link_info
.pause
=
7709 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
7710 bp
->link_info
.auto_pause_setting
= 0;
7711 if (!bp
->link_info
.force_link_chng
)
7712 bnxt_report_link(bp
);
7714 bp
->link_info
.force_link_chng
= false;
7715 mutex_unlock(&bp
->hwrm_cmd_lock
);
7719 static void bnxt_hwrm_set_eee(struct bnxt
*bp
,
7720 struct hwrm_port_phy_cfg_input
*req
)
7722 struct ethtool_eee
*eee
= &bp
->eee
;
7724 if (eee
->eee_enabled
) {
7726 u32 flags
= PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE
;
7728 if (eee
->tx_lpi_enabled
)
7729 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE
;
7731 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE
;
7733 req
->flags
|= cpu_to_le32(flags
);
7734 eee_speeds
= bnxt_get_fw_auto_link_speeds(eee
->advertised
);
7735 req
->eee_link_speed_mask
= cpu_to_le16(eee_speeds
);
7736 req
->tx_lpi_timer
= cpu_to_le32(eee
->tx_lpi_timer
);
7738 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE
);
7742 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
, bool set_eee
)
7744 struct hwrm_port_phy_cfg_input req
= {0};
7746 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
7748 bnxt_hwrm_set_pause_common(bp
, &req
);
7750 bnxt_hwrm_set_link_common(bp
, &req
);
7753 bnxt_hwrm_set_eee(bp
, &req
);
7754 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
7757 static int bnxt_hwrm_shutdown_link(struct bnxt
*bp
)
7759 struct hwrm_port_phy_cfg_input req
= {0};
7761 if (!BNXT_SINGLE_PF(bp
))
7764 if (pci_num_vf(bp
->pdev
))
7767 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
7768 req
.flags
= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN
);
7769 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
7772 static int bnxt_hwrm_if_change(struct bnxt
*bp
, bool up
)
7774 struct hwrm_func_drv_if_change_output
*resp
= bp
->hwrm_cmd_resp_addr
;
7775 struct hwrm_func_drv_if_change_input req
= {0};
7776 bool resc_reinit
= false;
7779 if (!(bp
->fw_cap
& BNXT_FW_CAP_IF_CHANGE
))
7782 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_IF_CHANGE
, -1, -1);
7784 req
.flags
= cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP
);
7785 mutex_lock(&bp
->hwrm_cmd_lock
);
7786 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
7787 if (!rc
&& (resp
->flags
&
7788 cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE
)))
7790 mutex_unlock(&bp
->hwrm_cmd_lock
);
7792 if (up
&& resc_reinit
&& BNXT_NEW_RM(bp
)) {
7793 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
7795 rc
= bnxt_hwrm_func_resc_qcaps(bp
, true);
7796 hw_resc
->resv_cp_rings
= 0;
7797 hw_resc
->resv_tx_rings
= 0;
7798 hw_resc
->resv_rx_rings
= 0;
7799 hw_resc
->resv_hw_ring_grps
= 0;
7800 hw_resc
->resv_vnics
= 0;
7801 bp
->tx_nr_rings
= 0;
7802 bp
->rx_nr_rings
= 0;
7807 static int bnxt_hwrm_port_led_qcaps(struct bnxt
*bp
)
7809 struct hwrm_port_led_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
7810 struct hwrm_port_led_qcaps_input req
= {0};
7811 struct bnxt_pf_info
*pf
= &bp
->pf
;
7814 if (BNXT_VF(bp
) || bp
->hwrm_spec_code
< 0x10601)
7817 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_LED_QCAPS
, -1, -1);
7818 req
.port_id
= cpu_to_le16(pf
->port_id
);
7819 mutex_lock(&bp
->hwrm_cmd_lock
);
7820 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
7822 mutex_unlock(&bp
->hwrm_cmd_lock
);
7825 if (resp
->num_leds
> 0 && resp
->num_leds
< BNXT_MAX_LED
) {
7828 bp
->num_leds
= resp
->num_leds
;
7829 memcpy(bp
->leds
, &resp
->led0_id
, sizeof(bp
->leds
[0]) *
7831 for (i
= 0; i
< bp
->num_leds
; i
++) {
7832 struct bnxt_led_info
*led
= &bp
->leds
[i
];
7833 __le16 caps
= led
->led_state_caps
;
7835 if (!led
->led_group_id
||
7836 !BNXT_LED_ALT_BLINK_CAP(caps
)) {
7842 mutex_unlock(&bp
->hwrm_cmd_lock
);
7846 int bnxt_hwrm_alloc_wol_fltr(struct bnxt
*bp
)
7848 struct hwrm_wol_filter_alloc_input req
= {0};
7849 struct hwrm_wol_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
7852 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_WOL_FILTER_ALLOC
, -1, -1);
7853 req
.port_id
= cpu_to_le16(bp
->pf
.port_id
);
7854 req
.wol_type
= WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT
;
7855 req
.enables
= cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS
);
7856 memcpy(req
.mac_address
, bp
->dev
->dev_addr
, ETH_ALEN
);
7857 mutex_lock(&bp
->hwrm_cmd_lock
);
7858 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
7860 bp
->wol_filter_id
= resp
->wol_filter_id
;
7861 mutex_unlock(&bp
->hwrm_cmd_lock
);
7865 int bnxt_hwrm_free_wol_fltr(struct bnxt
*bp
)
7867 struct hwrm_wol_filter_free_input req
= {0};
7870 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_WOL_FILTER_FREE
, -1, -1);
7871 req
.port_id
= cpu_to_le16(bp
->pf
.port_id
);
7872 req
.enables
= cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID
);
7873 req
.wol_filter_id
= bp
->wol_filter_id
;
7874 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
7878 static u16
bnxt_hwrm_get_wol_fltrs(struct bnxt
*bp
, u16 handle
)
7880 struct hwrm_wol_filter_qcfg_input req
= {0};
7881 struct hwrm_wol_filter_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
7882 u16 next_handle
= 0;
7885 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_WOL_FILTER_QCFG
, -1, -1);
7886 req
.port_id
= cpu_to_le16(bp
->pf
.port_id
);
7887 req
.handle
= cpu_to_le16(handle
);
7888 mutex_lock(&bp
->hwrm_cmd_lock
);
7889 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
7891 next_handle
= le16_to_cpu(resp
->next_handle
);
7892 if (next_handle
!= 0) {
7893 if (resp
->wol_type
==
7894 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT
) {
7896 bp
->wol_filter_id
= resp
->wol_filter_id
;
7900 mutex_unlock(&bp
->hwrm_cmd_lock
);
7904 static void bnxt_get_wol_settings(struct bnxt
*bp
)
7908 if (!BNXT_PF(bp
) || !(bp
->flags
& BNXT_FLAG_WOL_CAP
))
7912 handle
= bnxt_hwrm_get_wol_fltrs(bp
, handle
);
7913 } while (handle
&& handle
!= 0xffff);
7916 #ifdef CONFIG_BNXT_HWMON
7917 static ssize_t
bnxt_show_temp(struct device
*dev
,
7918 struct device_attribute
*devattr
, char *buf
)
7920 struct hwrm_temp_monitor_query_input req
= {0};
7921 struct hwrm_temp_monitor_query_output
*resp
;
7922 struct bnxt
*bp
= dev_get_drvdata(dev
);
7925 resp
= bp
->hwrm_cmd_resp_addr
;
7926 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TEMP_MONITOR_QUERY
, -1, -1);
7927 mutex_lock(&bp
->hwrm_cmd_lock
);
7928 if (!_hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
))
7929 temp
= resp
->temp
* 1000; /* display millidegree */
7930 mutex_unlock(&bp
->hwrm_cmd_lock
);
7932 return sprintf(buf
, "%u\n", temp
);
7934 static SENSOR_DEVICE_ATTR(temp1_input
, 0444, bnxt_show_temp
, NULL
, 0);
7936 static struct attribute
*bnxt_attrs
[] = {
7937 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
7940 ATTRIBUTE_GROUPS(bnxt
);
7942 static void bnxt_hwmon_close(struct bnxt
*bp
)
7944 if (bp
->hwmon_dev
) {
7945 hwmon_device_unregister(bp
->hwmon_dev
);
7946 bp
->hwmon_dev
= NULL
;
7950 static void bnxt_hwmon_open(struct bnxt
*bp
)
7952 struct pci_dev
*pdev
= bp
->pdev
;
7954 bp
->hwmon_dev
= hwmon_device_register_with_groups(&pdev
->dev
,
7955 DRV_MODULE_NAME
, bp
,
7957 if (IS_ERR(bp
->hwmon_dev
)) {
7958 bp
->hwmon_dev
= NULL
;
7959 dev_warn(&pdev
->dev
, "Cannot register hwmon device\n");
7963 static void bnxt_hwmon_close(struct bnxt
*bp
)
7967 static void bnxt_hwmon_open(struct bnxt
*bp
)
7972 static bool bnxt_eee_config_ok(struct bnxt
*bp
)
7974 struct ethtool_eee
*eee
= &bp
->eee
;
7975 struct bnxt_link_info
*link_info
= &bp
->link_info
;
7977 if (!(bp
->flags
& BNXT_FLAG_EEE_CAP
))
7980 if (eee
->eee_enabled
) {
7982 _bnxt_fw_to_ethtool_adv_spds(link_info
->advertising
, 0);
7984 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
7985 eee
->eee_enabled
= 0;
7988 if (eee
->advertised
& ~advertising
) {
7989 eee
->advertised
= advertising
& eee
->supported
;
7996 static int bnxt_update_phy_setting(struct bnxt
*bp
)
7999 bool update_link
= false;
8000 bool update_pause
= false;
8001 bool update_eee
= false;
8002 struct bnxt_link_info
*link_info
= &bp
->link_info
;
8004 rc
= bnxt_update_link(bp
, true);
8006 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
8010 if (!BNXT_SINGLE_PF(bp
))
8013 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
8014 (link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
) !=
8015 link_info
->req_flow_ctrl
)
8016 update_pause
= true;
8017 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
8018 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
8019 update_pause
= true;
8020 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
8021 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
8023 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
8025 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
8028 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
8030 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
8034 /* The last close may have shutdown the link, so need to call
8035 * PHY_CFG to bring it back up.
8037 if (!netif_carrier_ok(bp
->dev
))
8040 if (!bnxt_eee_config_ok(bp
))
8044 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
, update_eee
);
8045 else if (update_pause
)
8046 rc
= bnxt_hwrm_set_pause(bp
);
8048 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
8056 /* Common routine to pre-map certain register block to different GRC window.
8057 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
8058 * in PF and 3 windows in VF that can be customized to map in different
8061 static void bnxt_preset_reg_win(struct bnxt
*bp
)
8064 /* CAG registers map to GRC window #4 */
8065 writel(BNXT_CAG_REG_BASE
,
8066 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
8070 static int bnxt_init_dflt_ring_mode(struct bnxt
*bp
);
8072 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
8076 bnxt_preset_reg_win(bp
);
8077 netif_carrier_off(bp
->dev
);
8079 /* Reserve rings now if none were reserved at driver probe. */
8080 rc
= bnxt_init_dflt_ring_mode(bp
);
8082 netdev_err(bp
->dev
, "Failed to reserve default rings at open\n");
8086 rc
= bnxt_reserve_rings(bp
);
8089 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
8090 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
8091 /* disable RFS if falling back to INTA */
8092 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
8093 bp
->flags
&= ~BNXT_FLAG_RFS
;
8096 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
8098 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
8099 goto open_err_free_mem
;
8104 rc
= bnxt_request_irq(bp
);
8106 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
8111 bnxt_enable_napi(bp
);
8112 bnxt_debug_dev_init(bp
);
8114 rc
= bnxt_init_nic(bp
, irq_re_init
);
8116 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
8121 mutex_lock(&bp
->link_lock
);
8122 rc
= bnxt_update_phy_setting(bp
);
8123 mutex_unlock(&bp
->link_lock
);
8125 netdev_warn(bp
->dev
, "failed to update phy settings\n");
8126 if (BNXT_SINGLE_PF(bp
)) {
8127 bp
->link_info
.phy_retry
= true;
8128 bp
->link_info
.phy_retry_expires
=
8135 udp_tunnel_get_rx_info(bp
->dev
);
8137 set_bit(BNXT_STATE_OPEN
, &bp
->state
);
8138 bnxt_enable_int(bp
);
8139 /* Enable TX queues */
8141 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
8142 /* Poll link status and check for SFP+ module status */
8143 bnxt_get_port_module_status(bp
);
8145 /* VF-reps may need to be re-opened after the PF is re-opened */
8147 bnxt_vf_reps_open(bp
);
8151 bnxt_debug_dev_exit(bp
);
8152 bnxt_disable_napi(bp
);
8160 bnxt_free_mem(bp
, true);
8164 /* rtnl_lock held */
8165 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
8169 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
8171 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
8177 /* rtnl_lock held, open the NIC half way by allocating all resources, but
8178 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
8181 int bnxt_half_open_nic(struct bnxt
*bp
)
8185 rc
= bnxt_alloc_mem(bp
, false);
8187 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
8190 rc
= bnxt_init_nic(bp
, false);
8192 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
8199 bnxt_free_mem(bp
, false);
8204 /* rtnl_lock held, this call can only be made after a previous successful
8205 * call to bnxt_half_open_nic().
8207 void bnxt_half_close_nic(struct bnxt
*bp
)
8209 bnxt_hwrm_resource_free(bp
, false, false);
8211 bnxt_free_mem(bp
, false);
8214 static int bnxt_open(struct net_device
*dev
)
8216 struct bnxt
*bp
= netdev_priv(dev
);
8219 bnxt_hwrm_if_change(bp
, true);
8220 rc
= __bnxt_open_nic(bp
, true, true);
8222 bnxt_hwrm_if_change(bp
, false);
8224 bnxt_hwmon_open(bp
);
8229 static bool bnxt_drv_busy(struct bnxt
*bp
)
8231 return (test_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
) ||
8232 test_bit(BNXT_STATE_READ_STATS
, &bp
->state
));
8235 static void __bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
,
8238 /* Close the VF-reps before closing PF */
8240 bnxt_vf_reps_close(bp
);
8242 /* Change device state to avoid TX queue wake up's */
8243 bnxt_tx_disable(bp
);
8245 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
8246 smp_mb__after_atomic();
8247 while (bnxt_drv_busy(bp
))
8250 /* Flush rings and and disable interrupts */
8251 bnxt_shutdown_nic(bp
, irq_re_init
);
8253 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
8255 bnxt_debug_dev_exit(bp
);
8256 bnxt_disable_napi(bp
);
8257 del_timer_sync(&bp
->timer
);
8264 bnxt_free_mem(bp
, irq_re_init
);
8267 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
8271 #ifdef CONFIG_BNXT_SRIOV
8272 if (bp
->sriov_cfg
) {
8273 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
8275 BNXT_SRIOV_CFG_WAIT_TMO
);
8277 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
8280 __bnxt_close_nic(bp
, irq_re_init
, link_re_init
);
8284 static int bnxt_close(struct net_device
*dev
)
8286 struct bnxt
*bp
= netdev_priv(dev
);
8288 bnxt_hwmon_close(bp
);
8289 bnxt_close_nic(bp
, true, true);
8290 bnxt_hwrm_shutdown_link(bp
);
8291 bnxt_hwrm_if_change(bp
, false);
8295 /* rtnl_lock held */
8296 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
8302 if (!netif_running(dev
))
8309 if (!netif_running(dev
))
8322 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
8325 struct bnxt
*bp
= netdev_priv(dev
);
8327 set_bit(BNXT_STATE_READ_STATS
, &bp
->state
);
8328 /* Make sure bnxt_close_nic() sees that we are reading stats before
8329 * we check the BNXT_STATE_OPEN flag.
8331 smp_mb__after_atomic();
8332 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
8333 clear_bit(BNXT_STATE_READ_STATS
, &bp
->state
);
8337 /* TODO check if we need to synchronize with bnxt_close path */
8338 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
8339 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
8340 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
8341 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
8343 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
8344 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
8345 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
8347 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
8348 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
8349 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
8351 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
8352 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
8353 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
8355 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
8356 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
8357 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
8359 stats
->rx_missed_errors
+=
8360 le64_to_cpu(hw_stats
->rx_discard_pkts
);
8362 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
8364 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
8367 if (bp
->flags
& BNXT_FLAG_PORT_STATS
) {
8368 struct rx_port_stats
*rx
= bp
->hw_rx_port_stats
;
8369 struct tx_port_stats
*tx
= bp
->hw_tx_port_stats
;
8371 stats
->rx_crc_errors
= le64_to_cpu(rx
->rx_fcs_err_frames
);
8372 stats
->rx_frame_errors
= le64_to_cpu(rx
->rx_align_err_frames
);
8373 stats
->rx_length_errors
= le64_to_cpu(rx
->rx_undrsz_frames
) +
8374 le64_to_cpu(rx
->rx_ovrsz_frames
) +
8375 le64_to_cpu(rx
->rx_runt_frames
);
8376 stats
->rx_errors
= le64_to_cpu(rx
->rx_false_carrier_frames
) +
8377 le64_to_cpu(rx
->rx_jbr_frames
);
8378 stats
->collisions
= le64_to_cpu(tx
->tx_total_collisions
);
8379 stats
->tx_fifo_errors
= le64_to_cpu(tx
->tx_fifo_underruns
);
8380 stats
->tx_errors
= le64_to_cpu(tx
->tx_err
);
8382 clear_bit(BNXT_STATE_READ_STATS
, &bp
->state
);
8385 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
8387 struct net_device
*dev
= bp
->dev
;
8388 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
8389 struct netdev_hw_addr
*ha
;
8392 bool update
= false;
8395 netdev_for_each_mc_addr(ha
, dev
) {
8396 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
8397 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
8398 vnic
->mc_list_count
= 0;
8402 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
8403 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
8410 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
8412 if (mc_count
!= vnic
->mc_list_count
) {
8413 vnic
->mc_list_count
= mc_count
;
8419 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
8421 struct net_device
*dev
= bp
->dev
;
8422 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
8423 struct netdev_hw_addr
*ha
;
8426 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
8429 netdev_for_each_uc_addr(ha
, dev
) {
8430 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
8438 static void bnxt_set_rx_mode(struct net_device
*dev
)
8440 struct bnxt
*bp
= netdev_priv(dev
);
8441 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
8442 u32 mask
= vnic
->rx_mask
;
8443 bool mc_update
= false;
8446 if (!netif_running(dev
))
8449 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
8450 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
8451 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
|
8452 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
);
8454 if ((dev
->flags
& IFF_PROMISC
) && bnxt_promisc_ok(bp
))
8455 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
8457 uc_update
= bnxt_uc_list_updated(bp
);
8459 if (dev
->flags
& IFF_BROADCAST
)
8460 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
8461 if (dev
->flags
& IFF_ALLMULTI
) {
8462 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
8463 vnic
->mc_list_count
= 0;
8465 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
8468 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
8469 vnic
->rx_mask
= mask
;
8471 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
8472 bnxt_queue_sp_work(bp
);
8476 static int bnxt_cfg_rx_mode(struct bnxt
*bp
)
8478 struct net_device
*dev
= bp
->dev
;
8479 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
8480 struct netdev_hw_addr
*ha
;
8484 netif_addr_lock_bh(dev
);
8485 uc_update
= bnxt_uc_list_updated(bp
);
8486 netif_addr_unlock_bh(dev
);
8491 mutex_lock(&bp
->hwrm_cmd_lock
);
8492 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
8493 struct hwrm_cfa_l2_filter_free_input req
= {0};
8495 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
8498 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
8500 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
8503 mutex_unlock(&bp
->hwrm_cmd_lock
);
8505 vnic
->uc_filter_count
= 1;
8507 netif_addr_lock_bh(dev
);
8508 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
8509 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
8511 netdev_for_each_uc_addr(ha
, dev
) {
8512 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
8514 vnic
->uc_filter_count
++;
8517 netif_addr_unlock_bh(dev
);
8519 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
8520 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
8522 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
8524 vnic
->uc_filter_count
= i
;
8530 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
8532 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
8538 static bool bnxt_can_reserve_rings(struct bnxt
*bp
)
8540 #ifdef CONFIG_BNXT_SRIOV
8541 if (BNXT_NEW_RM(bp
) && BNXT_VF(bp
)) {
8542 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
8544 /* No minimum rings were provisioned by the PF. Don't
8545 * reserve rings by default when device is down.
8547 if (hw_resc
->min_tx_rings
|| hw_resc
->resv_tx_rings
)
8550 if (!netif_running(bp
->dev
))
8557 /* If the chip and firmware supports RFS */
8558 static bool bnxt_rfs_supported(struct bnxt
*bp
)
8560 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
8562 if (BNXT_PF(bp
) && !BNXT_CHIP_TYPE_NITRO_A0(bp
))
8564 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
8569 /* If runtime conditions support RFS */
8570 static bool bnxt_rfs_capable(struct bnxt
*bp
)
8572 #ifdef CONFIG_RFS_ACCEL
8573 int vnics
, max_vnics
, max_rss_ctxs
;
8575 if (bp
->flags
& BNXT_FLAG_CHIP_P5
)
8577 if (!(bp
->flags
& BNXT_FLAG_MSIX_CAP
) || !bnxt_can_reserve_rings(bp
))
8580 vnics
= 1 + bp
->rx_nr_rings
;
8581 max_vnics
= bnxt_get_max_func_vnics(bp
);
8582 max_rss_ctxs
= bnxt_get_max_func_rss_ctxs(bp
);
8584 /* RSS contexts not a limiting factor */
8585 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
8586 max_rss_ctxs
= max_vnics
;
8587 if (vnics
> max_vnics
|| vnics
> max_rss_ctxs
) {
8588 if (bp
->rx_nr_rings
> 1)
8589 netdev_warn(bp
->dev
,
8590 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
8591 min(max_rss_ctxs
- 1, max_vnics
- 1));
8595 if (!BNXT_NEW_RM(bp
))
8598 if (vnics
== bp
->hw_resc
.resv_vnics
)
8601 bnxt_hwrm_reserve_rings(bp
, 0, 0, 0, 0, vnics
);
8602 if (vnics
<= bp
->hw_resc
.resv_vnics
)
8605 netdev_warn(bp
->dev
, "Unable to reserve resources to support NTUPLE filters.\n");
8606 bnxt_hwrm_reserve_rings(bp
, 0, 0, 0, 0, 1);
8613 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
8614 netdev_features_t features
)
8616 struct bnxt
*bp
= netdev_priv(dev
);
8618 if ((features
& NETIF_F_NTUPLE
) && !bnxt_rfs_capable(bp
))
8619 features
&= ~NETIF_F_NTUPLE
;
8621 if (bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)
8622 features
&= ~(NETIF_F_LRO
| NETIF_F_GRO_HW
);
8624 if (!(features
& NETIF_F_GRO
))
8625 features
&= ~NETIF_F_GRO_HW
;
8627 if (features
& NETIF_F_GRO_HW
)
8628 features
&= ~NETIF_F_LRO
;
8630 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
8631 * turned on or off together.
8633 if ((features
& (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) !=
8634 (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) {
8635 if (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)
8636 features
&= ~(NETIF_F_HW_VLAN_CTAG_RX
|
8637 NETIF_F_HW_VLAN_STAG_RX
);
8639 features
|= NETIF_F_HW_VLAN_CTAG_RX
|
8640 NETIF_F_HW_VLAN_STAG_RX
;
8642 #ifdef CONFIG_BNXT_SRIOV
8645 features
&= ~(NETIF_F_HW_VLAN_CTAG_RX
|
8646 NETIF_F_HW_VLAN_STAG_RX
);
8653 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
8655 struct bnxt
*bp
= netdev_priv(dev
);
8656 u32 flags
= bp
->flags
;
8659 bool re_init
= false;
8660 bool update_tpa
= false;
8662 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
8663 if (features
& NETIF_F_GRO_HW
)
8664 flags
|= BNXT_FLAG_GRO
;
8665 else if (features
& NETIF_F_LRO
)
8666 flags
|= BNXT_FLAG_LRO
;
8668 if (bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)
8669 flags
&= ~BNXT_FLAG_TPA
;
8671 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
8672 flags
|= BNXT_FLAG_STRIP_VLAN
;
8674 if (features
& NETIF_F_NTUPLE
)
8675 flags
|= BNXT_FLAG_RFS
;
8677 changes
= flags
^ bp
->flags
;
8678 if (changes
& BNXT_FLAG_TPA
) {
8680 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
8681 (flags
& BNXT_FLAG_TPA
) == 0)
8685 if (changes
& ~BNXT_FLAG_TPA
)
8688 if (flags
!= bp
->flags
) {
8689 u32 old_flags
= bp
->flags
;
8693 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
8695 bnxt_set_ring_params(bp
);
8700 bnxt_close_nic(bp
, false, false);
8702 bnxt_set_ring_params(bp
);
8704 return bnxt_open_nic(bp
, false, false);
8707 rc
= bnxt_set_tpa(bp
,
8708 (flags
& BNXT_FLAG_TPA
) ?
8711 bp
->flags
= old_flags
;
8717 static void bnxt_dump_tx_sw_state(struct bnxt_napi
*bnapi
)
8719 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
8720 int i
= bnapi
->index
;
8725 netdev_info(bnapi
->bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
8726 i
, txr
->tx_ring_struct
.fw_ring_id
, txr
->tx_prod
,
8730 static void bnxt_dump_rx_sw_state(struct bnxt_napi
*bnapi
)
8732 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
8733 int i
= bnapi
->index
;
8738 netdev_info(bnapi
->bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
8739 i
, rxr
->rx_ring_struct
.fw_ring_id
, rxr
->rx_prod
,
8740 rxr
->rx_agg_ring_struct
.fw_ring_id
, rxr
->rx_agg_prod
,
8741 rxr
->rx_sw_agg_prod
);
8744 static void bnxt_dump_cp_sw_state(struct bnxt_napi
*bnapi
)
8746 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
8747 int i
= bnapi
->index
;
8749 netdev_info(bnapi
->bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
8750 i
, cpr
->cp_ring_struct
.fw_ring_id
, cpr
->cp_raw_cons
);
8753 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
8756 struct bnxt_napi
*bnapi
;
8758 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
8759 bnapi
= bp
->bnapi
[i
];
8760 if (netif_msg_drv(bp
)) {
8761 bnxt_dump_tx_sw_state(bnapi
);
8762 bnxt_dump_rx_sw_state(bnapi
);
8763 bnxt_dump_cp_sw_state(bnapi
);
8768 static void bnxt_reset_task(struct bnxt
*bp
, bool silent
)
8771 bnxt_dbg_dump_states(bp
);
8772 if (netif_running(bp
->dev
)) {
8777 bnxt_close_nic(bp
, false, false);
8778 rc
= bnxt_open_nic(bp
, false, false);
8784 static void bnxt_tx_timeout(struct net_device
*dev
)
8786 struct bnxt
*bp
= netdev_priv(dev
);
8788 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
8789 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
8790 bnxt_queue_sp_work(bp
);
8793 static void bnxt_timer(struct timer_list
*t
)
8795 struct bnxt
*bp
= from_timer(bp
, t
, timer
);
8796 struct net_device
*dev
= bp
->dev
;
8798 if (!netif_running(dev
))
8801 if (atomic_read(&bp
->intr_sem
) != 0)
8802 goto bnxt_restart_timer
;
8804 if (bp
->link_info
.link_up
&& (bp
->flags
& BNXT_FLAG_PORT_STATS
) &&
8805 bp
->stats_coal_ticks
) {
8806 set_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
);
8807 bnxt_queue_sp_work(bp
);
8810 if (bnxt_tc_flower_enabled(bp
)) {
8811 set_bit(BNXT_FLOW_STATS_SP_EVENT
, &bp
->sp_event
);
8812 bnxt_queue_sp_work(bp
);
8815 if (bp
->link_info
.phy_retry
) {
8816 if (time_after(jiffies
, bp
->link_info
.phy_retry_expires
)) {
8817 bp
->link_info
.phy_retry
= 0;
8818 netdev_warn(bp
->dev
, "failed to update phy settings after maximum retries.\n");
8820 set_bit(BNXT_UPDATE_PHY_SP_EVENT
, &bp
->sp_event
);
8821 bnxt_queue_sp_work(bp
);
8825 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
8828 static void bnxt_rtnl_lock_sp(struct bnxt
*bp
)
8830 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
8831 * set. If the device is being closed, bnxt_close() may be holding
8832 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
8833 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
8835 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
8839 static void bnxt_rtnl_unlock_sp(struct bnxt
*bp
)
8841 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
8845 /* Only called from bnxt_sp_task() */
8846 static void bnxt_reset(struct bnxt
*bp
, bool silent
)
8848 bnxt_rtnl_lock_sp(bp
);
8849 if (test_bit(BNXT_STATE_OPEN
, &bp
->state
))
8850 bnxt_reset_task(bp
, silent
);
8851 bnxt_rtnl_unlock_sp(bp
);
8854 static void bnxt_cfg_ntp_filters(struct bnxt
*);
8856 static void bnxt_sp_task(struct work_struct
*work
)
8858 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
8860 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
8861 smp_mb__after_atomic();
8862 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
8863 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
8867 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
8868 bnxt_cfg_rx_mode(bp
);
8870 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
8871 bnxt_cfg_ntp_filters(bp
);
8872 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
8873 bnxt_hwrm_exec_fwd_req(bp
);
8874 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
8875 bnxt_hwrm_tunnel_dst_port_alloc(
8877 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
8879 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
8880 bnxt_hwrm_tunnel_dst_port_free(
8881 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
8883 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
8884 bnxt_hwrm_tunnel_dst_port_alloc(
8886 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
8888 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
8889 bnxt_hwrm_tunnel_dst_port_free(
8890 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
8892 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
)) {
8893 bnxt_hwrm_port_qstats(bp
);
8894 bnxt_hwrm_port_qstats_ext(bp
);
8897 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
8900 mutex_lock(&bp
->link_lock
);
8901 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT
,
8903 bnxt_hwrm_phy_qcaps(bp
);
8905 rc
= bnxt_update_link(bp
, true);
8906 mutex_unlock(&bp
->link_lock
);
8908 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
8911 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT
, &bp
->sp_event
)) {
8914 mutex_lock(&bp
->link_lock
);
8915 rc
= bnxt_update_phy_setting(bp
);
8916 mutex_unlock(&bp
->link_lock
);
8918 netdev_warn(bp
->dev
, "update phy settings retry failed\n");
8920 bp
->link_info
.phy_retry
= false;
8921 netdev_info(bp
->dev
, "update phy settings retry succeeded\n");
8924 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
)) {
8925 mutex_lock(&bp
->link_lock
);
8926 bnxt_get_port_module_status(bp
);
8927 mutex_unlock(&bp
->link_lock
);
8930 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT
, &bp
->sp_event
))
8931 bnxt_tc_flow_stats_work(bp
);
8933 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
8934 * must be the last functions to be called before exiting.
8936 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
))
8937 bnxt_reset(bp
, false);
8939 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT
, &bp
->sp_event
))
8940 bnxt_reset(bp
, true);
8942 smp_mb__before_atomic();
8943 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
8946 /* Under rtnl_lock */
8947 int bnxt_check_rings(struct bnxt
*bp
, int tx
, int rx
, bool sh
, int tcs
,
8950 int max_rx
, max_tx
, tx_sets
= 1;
8951 int tx_rings_needed
;
8958 rc
= bnxt_get_max_rings(bp
, &max_rx
, &max_tx
, sh
);
8965 tx_rings_needed
= tx
* tx_sets
+ tx_xdp
;
8966 if (max_tx
< tx_rings_needed
)
8970 if (bp
->flags
& BNXT_FLAG_RFS
)
8973 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
8975 cp
= sh
? max_t(int, tx_rings_needed
, rx
) : tx_rings_needed
+ rx
;
8976 if (BNXT_NEW_RM(bp
))
8977 cp
+= bnxt_get_ulp_msix_num(bp
);
8978 return bnxt_hwrm_check_rings(bp
, tx_rings_needed
, rx_rings
, rx
, cp
,
8982 static void bnxt_unmap_bars(struct bnxt
*bp
, struct pci_dev
*pdev
)
8985 pci_iounmap(pdev
, bp
->bar2
);
8990 pci_iounmap(pdev
, bp
->bar1
);
8995 pci_iounmap(pdev
, bp
->bar0
);
9000 static void bnxt_cleanup_pci(struct bnxt
*bp
)
9002 bnxt_unmap_bars(bp
, bp
->pdev
);
9003 pci_release_regions(bp
->pdev
);
9004 pci_disable_device(bp
->pdev
);
9007 static void bnxt_init_dflt_coal(struct bnxt
*bp
)
9009 struct bnxt_coal
*coal
;
9011 /* Tick values in micro seconds.
9012 * 1 coal_buf x bufs_per_record = 1 completion record.
9014 coal
= &bp
->rx_coal
;
9015 coal
->coal_ticks
= 14;
9016 coal
->coal_bufs
= 30;
9017 coal
->coal_ticks_irq
= 1;
9018 coal
->coal_bufs_irq
= 2;
9019 coal
->idle_thresh
= 50;
9020 coal
->bufs_per_record
= 2;
9021 coal
->budget
= 64; /* NAPI budget */
9023 coal
= &bp
->tx_coal
;
9024 coal
->coal_ticks
= 28;
9025 coal
->coal_bufs
= 30;
9026 coal
->coal_ticks_irq
= 2;
9027 coal
->coal_bufs_irq
= 2;
9028 coal
->bufs_per_record
= 1;
9030 bp
->stats_coal_ticks
= BNXT_DEF_STATS_COAL_TICKS
;
9033 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
9036 struct bnxt
*bp
= netdev_priv(dev
);
9038 SET_NETDEV_DEV(dev
, &pdev
->dev
);
9040 /* enable device (incl. PCI PM wakeup), and bus-mastering */
9041 rc
= pci_enable_device(pdev
);
9043 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
9047 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
9049 "Cannot find PCI device base address, aborting\n");
9051 goto init_err_disable
;
9054 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
9056 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
9057 goto init_err_disable
;
9060 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
9061 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
9062 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
9063 goto init_err_disable
;
9066 pci_set_master(pdev
);
9071 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
9073 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
9075 goto init_err_release
;
9078 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
9080 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
9082 goto init_err_release
;
9085 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
9087 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
9089 goto init_err_release
;
9092 pci_enable_pcie_error_reporting(pdev
);
9094 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
9096 spin_lock_init(&bp
->ntp_fltr_lock
);
9097 #if BITS_PER_LONG == 32
9098 spin_lock_init(&bp
->db_lock
);
9101 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
9102 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
9104 bnxt_init_dflt_coal(bp
);
9106 timer_setup(&bp
->timer
, bnxt_timer
, 0);
9107 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
9109 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
9113 bnxt_unmap_bars(bp
, pdev
);
9114 pci_release_regions(pdev
);
9117 pci_disable_device(pdev
);
9123 /* rtnl_lock held */
9124 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
9126 struct sockaddr
*addr
= p
;
9127 struct bnxt
*bp
= netdev_priv(dev
);
9130 if (!is_valid_ether_addr(addr
->sa_data
))
9131 return -EADDRNOTAVAIL
;
9133 if (ether_addr_equal(addr
->sa_data
, dev
->dev_addr
))
9136 rc
= bnxt_approve_mac(bp
, addr
->sa_data
, true);
9140 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
9141 if (netif_running(dev
)) {
9142 bnxt_close_nic(bp
, false, false);
9143 rc
= bnxt_open_nic(bp
, false, false);
9149 /* rtnl_lock held */
9150 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
9152 struct bnxt
*bp
= netdev_priv(dev
);
9154 if (netif_running(dev
))
9155 bnxt_close_nic(bp
, false, false);
9158 bnxt_set_ring_params(bp
);
9160 if (netif_running(dev
))
9161 return bnxt_open_nic(bp
, false, false);
9166 int bnxt_setup_mq_tc(struct net_device
*dev
, u8 tc
)
9168 struct bnxt
*bp
= netdev_priv(dev
);
9172 if (tc
> bp
->max_tc
) {
9173 netdev_err(dev
, "Too many traffic classes requested: %d. Max supported is %d.\n",
9178 if (netdev_get_num_tc(dev
) == tc
)
9181 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
9184 rc
= bnxt_check_rings(bp
, bp
->tx_nr_rings_per_tc
, bp
->rx_nr_rings
,
9185 sh
, tc
, bp
->tx_nr_rings_xdp
);
9189 /* Needs to close the device and do hw resource re-allocations */
9190 if (netif_running(bp
->dev
))
9191 bnxt_close_nic(bp
, true, false);
9194 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
9195 netdev_set_num_tc(dev
, tc
);
9197 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
9198 netdev_reset_tc(dev
);
9200 bp
->tx_nr_rings
+= bp
->tx_nr_rings_xdp
;
9201 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
9202 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
9203 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
9205 if (netif_running(bp
->dev
))
9206 return bnxt_open_nic(bp
, true, false);
9211 static int bnxt_setup_tc_block_cb(enum tc_setup_type type
, void *type_data
,
9214 struct bnxt
*bp
= cb_priv
;
9216 if (!bnxt_tc_flower_enabled(bp
) ||
9217 !tc_cls_can_offload_and_chain0(bp
->dev
, type_data
))
9221 case TC_SETUP_CLSFLOWER
:
9222 return bnxt_tc_setup_flower(bp
, bp
->pf
.fw_fid
, type_data
);
9228 static int bnxt_setup_tc_block(struct net_device
*dev
,
9229 struct tc_block_offload
*f
)
9231 struct bnxt
*bp
= netdev_priv(dev
);
9233 if (f
->binder_type
!= TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS
)
9236 switch (f
->command
) {
9238 return tcf_block_cb_register(f
->block
, bnxt_setup_tc_block_cb
,
9240 case TC_BLOCK_UNBIND
:
9241 tcf_block_cb_unregister(f
->block
, bnxt_setup_tc_block_cb
, bp
);
9248 static int bnxt_setup_tc(struct net_device
*dev
, enum tc_setup_type type
,
9252 case TC_SETUP_BLOCK
:
9253 return bnxt_setup_tc_block(dev
, type_data
);
9254 case TC_SETUP_QDISC_MQPRIO
: {
9255 struct tc_mqprio_qopt
*mqprio
= type_data
;
9257 mqprio
->hw
= TC_MQPRIO_HW_OFFLOAD_TCS
;
9259 return bnxt_setup_mq_tc(dev
, mqprio
->num_tc
);
9266 #ifdef CONFIG_RFS_ACCEL
9267 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
9268 struct bnxt_ntuple_filter
*f2
)
9270 struct flow_keys
*keys1
= &f1
->fkeys
;
9271 struct flow_keys
*keys2
= &f2
->fkeys
;
9273 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
9274 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
9275 keys1
->ports
.ports
== keys2
->ports
.ports
&&
9276 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
9277 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
9278 keys1
->control
.flags
== keys2
->control
.flags
&&
9279 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
) &&
9280 ether_addr_equal(f1
->dst_mac_addr
, f2
->dst_mac_addr
))
9286 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
9287 u16 rxq_index
, u32 flow_id
)
9289 struct bnxt
*bp
= netdev_priv(dev
);
9290 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
9291 struct flow_keys
*fkeys
;
9292 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
9293 int rc
= 0, idx
, bit_id
, l2_idx
= 0;
9294 struct hlist_head
*head
;
9296 if (!ether_addr_equal(dev
->dev_addr
, eth
->h_dest
)) {
9297 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
9300 netif_addr_lock_bh(dev
);
9301 for (j
= 0; j
< vnic
->uc_filter_count
; j
++, off
+= ETH_ALEN
) {
9302 if (ether_addr_equal(eth
->h_dest
,
9303 vnic
->uc_list
+ off
)) {
9308 netif_addr_unlock_bh(dev
);
9312 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
9316 fkeys
= &new_fltr
->fkeys
;
9317 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
9318 rc
= -EPROTONOSUPPORT
;
9322 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
) &&
9323 fkeys
->basic
.n_proto
!= htons(ETH_P_IPV6
)) ||
9324 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
9325 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
9326 rc
= -EPROTONOSUPPORT
;
9329 if (fkeys
->basic
.n_proto
== htons(ETH_P_IPV6
) &&
9330 bp
->hwrm_spec_code
< 0x10601) {
9331 rc
= -EPROTONOSUPPORT
;
9334 if ((fkeys
->control
.flags
& FLOW_DIS_ENCAPSULATION
) &&
9335 bp
->hwrm_spec_code
< 0x10601) {
9336 rc
= -EPROTONOSUPPORT
;
9340 memcpy(new_fltr
->dst_mac_addr
, eth
->h_dest
, ETH_ALEN
);
9341 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
9343 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
9344 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
9346 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
9347 if (bnxt_fltr_match(fltr
, new_fltr
)) {
9355 spin_lock_bh(&bp
->ntp_fltr_lock
);
9356 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
9357 BNXT_NTP_FLTR_MAX_FLTR
, 0);
9359 spin_unlock_bh(&bp
->ntp_fltr_lock
);
9364 new_fltr
->sw_id
= (u16
)bit_id
;
9365 new_fltr
->flow_id
= flow_id
;
9366 new_fltr
->l2_fltr_idx
= l2_idx
;
9367 new_fltr
->rxq
= rxq_index
;
9368 hlist_add_head_rcu(&new_fltr
->hash
, head
);
9369 bp
->ntp_fltr_count
++;
9370 spin_unlock_bh(&bp
->ntp_fltr_lock
);
9372 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
9373 bnxt_queue_sp_work(bp
);
9375 return new_fltr
->sw_id
;
9382 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
9386 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
9387 struct hlist_head
*head
;
9388 struct hlist_node
*tmp
;
9389 struct bnxt_ntuple_filter
*fltr
;
9392 head
= &bp
->ntp_fltr_hash_tbl
[i
];
9393 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
9396 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
9397 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
9400 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
9405 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
9410 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
9414 spin_lock_bh(&bp
->ntp_fltr_lock
);
9415 hlist_del_rcu(&fltr
->hash
);
9416 bp
->ntp_fltr_count
--;
9417 spin_unlock_bh(&bp
->ntp_fltr_lock
);
9419 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
9424 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
))
9425 netdev_info(bp
->dev
, "Receive PF driver unload event!");
9430 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
9434 #endif /* CONFIG_RFS_ACCEL */
9436 static void bnxt_udp_tunnel_add(struct net_device
*dev
,
9437 struct udp_tunnel_info
*ti
)
9439 struct bnxt
*bp
= netdev_priv(dev
);
9441 if (ti
->sa_family
!= AF_INET6
&& ti
->sa_family
!= AF_INET
)
9444 if (!netif_running(dev
))
9448 case UDP_TUNNEL_TYPE_VXLAN
:
9449 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= ti
->port
)
9452 bp
->vxlan_port_cnt
++;
9453 if (bp
->vxlan_port_cnt
== 1) {
9454 bp
->vxlan_port
= ti
->port
;
9455 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
9456 bnxt_queue_sp_work(bp
);
9459 case UDP_TUNNEL_TYPE_GENEVE
:
9460 if (bp
->nge_port_cnt
&& bp
->nge_port
!= ti
->port
)
9464 if (bp
->nge_port_cnt
== 1) {
9465 bp
->nge_port
= ti
->port
;
9466 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
9473 bnxt_queue_sp_work(bp
);
9476 static void bnxt_udp_tunnel_del(struct net_device
*dev
,
9477 struct udp_tunnel_info
*ti
)
9479 struct bnxt
*bp
= netdev_priv(dev
);
9481 if (ti
->sa_family
!= AF_INET6
&& ti
->sa_family
!= AF_INET
)
9484 if (!netif_running(dev
))
9488 case UDP_TUNNEL_TYPE_VXLAN
:
9489 if (!bp
->vxlan_port_cnt
|| bp
->vxlan_port
!= ti
->port
)
9491 bp
->vxlan_port_cnt
--;
9493 if (bp
->vxlan_port_cnt
!= 0)
9496 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
9498 case UDP_TUNNEL_TYPE_GENEVE
:
9499 if (!bp
->nge_port_cnt
|| bp
->nge_port
!= ti
->port
)
9503 if (bp
->nge_port_cnt
!= 0)
9506 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
9512 bnxt_queue_sp_work(bp
);
9515 static int bnxt_bridge_getlink(struct sk_buff
*skb
, u32 pid
, u32 seq
,
9516 struct net_device
*dev
, u32 filter_mask
,
9519 struct bnxt
*bp
= netdev_priv(dev
);
9521 return ndo_dflt_bridge_getlink(skb
, pid
, seq
, dev
, bp
->br_mode
, 0, 0,
9522 nlflags
, filter_mask
, NULL
);
9525 static int bnxt_bridge_setlink(struct net_device
*dev
, struct nlmsghdr
*nlh
,
9528 struct bnxt
*bp
= netdev_priv(dev
);
9529 struct nlattr
*attr
, *br_spec
;
9532 if (bp
->hwrm_spec_code
< 0x10708 || !BNXT_SINGLE_PF(bp
))
9535 br_spec
= nlmsg_find_attr(nlh
, sizeof(struct ifinfomsg
), IFLA_AF_SPEC
);
9539 nla_for_each_nested(attr
, br_spec
, rem
) {
9542 if (nla_type(attr
) != IFLA_BRIDGE_MODE
)
9545 if (nla_len(attr
) < sizeof(mode
))
9548 mode
= nla_get_u16(attr
);
9549 if (mode
== bp
->br_mode
)
9552 rc
= bnxt_hwrm_set_br_mode(bp
, mode
);
9560 static int bnxt_get_phys_port_name(struct net_device
*dev
, char *buf
,
9563 struct bnxt
*bp
= netdev_priv(dev
);
9566 /* The PF and it's VF-reps only support the switchdev framework */
9570 rc
= snprintf(buf
, len
, "p%d", bp
->pf
.port_id
);
9577 int bnxt_port_attr_get(struct bnxt
*bp
, struct switchdev_attr
*attr
)
9579 if (bp
->eswitch_mode
!= DEVLINK_ESWITCH_MODE_SWITCHDEV
)
9582 /* The PF and it's VF-reps only support the switchdev framework */
9587 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID
:
9588 attr
->u
.ppid
.id_len
= sizeof(bp
->switch_id
);
9589 memcpy(attr
->u
.ppid
.id
, bp
->switch_id
, attr
->u
.ppid
.id_len
);
9597 static int bnxt_swdev_port_attr_get(struct net_device
*dev
,
9598 struct switchdev_attr
*attr
)
9600 return bnxt_port_attr_get(netdev_priv(dev
), attr
);
9603 static const struct switchdev_ops bnxt_switchdev_ops
= {
9604 .switchdev_port_attr_get
= bnxt_swdev_port_attr_get
9607 static const struct net_device_ops bnxt_netdev_ops
= {
9608 .ndo_open
= bnxt_open
,
9609 .ndo_start_xmit
= bnxt_start_xmit
,
9610 .ndo_stop
= bnxt_close
,
9611 .ndo_get_stats64
= bnxt_get_stats64
,
9612 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
9613 .ndo_do_ioctl
= bnxt_ioctl
,
9614 .ndo_validate_addr
= eth_validate_addr
,
9615 .ndo_set_mac_address
= bnxt_change_mac_addr
,
9616 .ndo_change_mtu
= bnxt_change_mtu
,
9617 .ndo_fix_features
= bnxt_fix_features
,
9618 .ndo_set_features
= bnxt_set_features
,
9619 .ndo_tx_timeout
= bnxt_tx_timeout
,
9620 #ifdef CONFIG_BNXT_SRIOV
9621 .ndo_get_vf_config
= bnxt_get_vf_config
,
9622 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
9623 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
9624 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
9625 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
9626 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
9627 .ndo_set_vf_trust
= bnxt_set_vf_trust
,
9629 .ndo_setup_tc
= bnxt_setup_tc
,
9630 #ifdef CONFIG_RFS_ACCEL
9631 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
9633 .ndo_udp_tunnel_add
= bnxt_udp_tunnel_add
,
9634 .ndo_udp_tunnel_del
= bnxt_udp_tunnel_del
,
9635 .ndo_bpf
= bnxt_xdp
,
9636 .ndo_bridge_getlink
= bnxt_bridge_getlink
,
9637 .ndo_bridge_setlink
= bnxt_bridge_setlink
,
9638 .ndo_get_phys_port_name
= bnxt_get_phys_port_name
9641 static void bnxt_remove_one(struct pci_dev
*pdev
)
9643 struct net_device
*dev
= pci_get_drvdata(pdev
);
9644 struct bnxt
*bp
= netdev_priv(dev
);
9647 bnxt_sriov_disable(bp
);
9648 bnxt_dl_unregister(bp
);
9651 pci_disable_pcie_error_reporting(pdev
);
9652 unregister_netdev(dev
);
9653 bnxt_shutdown_tc(bp
);
9654 bnxt_cancel_sp_work(bp
);
9657 bnxt_clear_int_mode(bp
);
9658 bnxt_hwrm_func_drv_unrgtr(bp
);
9659 bnxt_free_hwrm_resources(bp
);
9660 bnxt_free_hwrm_short_cmd_req(bp
);
9661 bnxt_ethtool_free(bp
);
9665 bnxt_free_ctx_mem(bp
);
9668 bnxt_cleanup_pci(bp
);
9672 static int bnxt_probe_phy(struct bnxt
*bp
)
9675 struct bnxt_link_info
*link_info
= &bp
->link_info
;
9677 rc
= bnxt_hwrm_phy_qcaps(bp
);
9679 netdev_err(bp
->dev
, "Probe phy can't get phy capabilities (rc: %x)\n",
9683 mutex_init(&bp
->link_lock
);
9685 rc
= bnxt_update_link(bp
, false);
9687 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
9692 /* Older firmware does not have supported_auto_speeds, so assume
9693 * that all supported speeds can be autonegotiated.
9695 if (link_info
->auto_link_speeds
&& !link_info
->support_auto_speeds
)
9696 link_info
->support_auto_speeds
= link_info
->support_speeds
;
9698 /*initialize the ethool setting copy with NVM settings */
9699 if (BNXT_AUTO_MODE(link_info
->auto_mode
)) {
9700 link_info
->autoneg
= BNXT_AUTONEG_SPEED
;
9701 if (bp
->hwrm_spec_code
>= 0x10201) {
9702 if (link_info
->auto_pause_setting
&
9703 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
)
9704 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
9706 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
9708 link_info
->advertising
= link_info
->auto_link_speeds
;
9710 link_info
->req_link_speed
= link_info
->force_link_speed
;
9711 link_info
->req_duplex
= link_info
->duplex_setting
;
9713 if (link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
)
9714 link_info
->req_flow_ctrl
=
9715 link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
;
9717 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
9721 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
9725 if (!pdev
->msix_cap
)
9728 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
9729 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
9732 static void _bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
9735 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
9736 int max_ring_grps
= 0;
9738 *max_tx
= hw_resc
->max_tx_rings
;
9739 *max_rx
= hw_resc
->max_rx_rings
;
9740 *max_cp
= min_t(int, bnxt_get_max_func_cp_rings_for_en(bp
),
9741 hw_resc
->max_irqs
- bnxt_get_ulp_msix_num(bp
));
9742 *max_cp
= min_t(int, *max_cp
, hw_resc
->max_stat_ctxs
);
9743 max_ring_grps
= hw_resc
->max_hw_ring_grps
;
9744 if (BNXT_CHIP_TYPE_NITRO_A0(bp
) && BNXT_PF(bp
)) {
9748 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
9750 *max_rx
= min_t(int, *max_rx
, max_ring_grps
);
9753 int bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
, bool shared
)
9757 _bnxt_get_max_rings(bp
, &rx
, &tx
, &cp
);
9760 if (!rx
|| !tx
|| !cp
)
9763 return bnxt_trim_rings(bp
, max_rx
, max_tx
, cp
, shared
);
9766 static int bnxt_get_dflt_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
9771 rc
= bnxt_get_max_rings(bp
, max_rx
, max_tx
, shared
);
9772 if (rc
&& (bp
->flags
& BNXT_FLAG_AGG_RINGS
)) {
9773 /* Not enough rings, try disabling agg rings. */
9774 bp
->flags
&= ~BNXT_FLAG_AGG_RINGS
;
9775 rc
= bnxt_get_max_rings(bp
, max_rx
, max_tx
, shared
);
9777 /* set BNXT_FLAG_AGG_RINGS back for consistency */
9778 bp
->flags
|= BNXT_FLAG_AGG_RINGS
;
9781 bp
->flags
|= BNXT_FLAG_NO_AGG_RINGS
;
9782 bp
->dev
->hw_features
&= ~(NETIF_F_LRO
| NETIF_F_GRO_HW
);
9783 bp
->dev
->features
&= ~(NETIF_F_LRO
| NETIF_F_GRO_HW
);
9784 bnxt_set_ring_params(bp
);
9787 if (bp
->flags
& BNXT_FLAG_ROCE_CAP
) {
9788 int max_cp
, max_stat
, max_irq
;
9790 /* Reserve minimum resources for RoCE */
9791 max_cp
= bnxt_get_max_func_cp_rings(bp
);
9792 max_stat
= bnxt_get_max_func_stat_ctxs(bp
);
9793 max_irq
= bnxt_get_max_func_irqs(bp
);
9794 if (max_cp
<= BNXT_MIN_ROCE_CP_RINGS
||
9795 max_irq
<= BNXT_MIN_ROCE_CP_RINGS
||
9796 max_stat
<= BNXT_MIN_ROCE_STAT_CTXS
)
9799 max_cp
-= BNXT_MIN_ROCE_CP_RINGS
;
9800 max_irq
-= BNXT_MIN_ROCE_CP_RINGS
;
9801 max_stat
-= BNXT_MIN_ROCE_STAT_CTXS
;
9802 max_cp
= min_t(int, max_cp
, max_irq
);
9803 max_cp
= min_t(int, max_cp
, max_stat
);
9804 rc
= bnxt_trim_rings(bp
, max_rx
, max_tx
, max_cp
, shared
);
9811 /* In initial default shared ring setting, each shared ring must have a
9814 static void bnxt_trim_dflt_sh_rings(struct bnxt
*bp
)
9816 bp
->cp_nr_rings
= min_t(int, bp
->tx_nr_rings_per_tc
, bp
->rx_nr_rings
);
9817 bp
->rx_nr_rings
= bp
->cp_nr_rings
;
9818 bp
->tx_nr_rings_per_tc
= bp
->cp_nr_rings
;
9819 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
9822 static int bnxt_set_dflt_rings(struct bnxt
*bp
, bool sh
)
9824 int dflt_rings
, max_rx_rings
, max_tx_rings
, rc
;
9826 if (!bnxt_can_reserve_rings(bp
))
9830 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
9831 dflt_rings
= netif_get_num_default_rss_queues();
9832 /* Reduce default rings on multi-port cards so that total default
9833 * rings do not exceed CPU count.
9835 if (bp
->port_count
> 1) {
9837 max_t(int, num_online_cpus() / bp
->port_count
, 1);
9839 dflt_rings
= min_t(int, dflt_rings
, max_rings
);
9841 rc
= bnxt_get_dflt_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
9844 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
9845 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
9847 bnxt_trim_dflt_sh_rings(bp
);
9849 bp
->cp_nr_rings
= bp
->tx_nr_rings_per_tc
+ bp
->rx_nr_rings
;
9850 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
9852 rc
= __bnxt_reserve_rings(bp
);
9854 netdev_warn(bp
->dev
, "Unable to reserve tx rings\n");
9855 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
9857 bnxt_trim_dflt_sh_rings(bp
);
9859 /* Rings may have been trimmed, re-reserve the trimmed rings. */
9860 if (bnxt_need_reserve_rings(bp
)) {
9861 rc
= __bnxt_reserve_rings(bp
);
9863 netdev_warn(bp
->dev
, "2nd rings reservation failed.\n");
9864 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
9866 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
9867 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
9874 static int bnxt_init_dflt_ring_mode(struct bnxt
*bp
)
9878 if (bp
->tx_nr_rings
)
9881 bnxt_ulp_irq_stop(bp
);
9882 bnxt_clear_int_mode(bp
);
9883 rc
= bnxt_set_dflt_rings(bp
, true);
9885 netdev_err(bp
->dev
, "Not enough rings available.\n");
9886 goto init_dflt_ring_err
;
9888 rc
= bnxt_init_int_mode(bp
);
9890 goto init_dflt_ring_err
;
9892 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
9893 if (bnxt_rfs_supported(bp
) && bnxt_rfs_capable(bp
)) {
9894 bp
->flags
|= BNXT_FLAG_RFS
;
9895 bp
->dev
->features
|= NETIF_F_NTUPLE
;
9898 bnxt_ulp_irq_restart(bp
, rc
);
9902 int bnxt_restore_pf_fw_resources(struct bnxt
*bp
)
9907 bnxt_hwrm_func_qcaps(bp
);
9909 if (netif_running(bp
->dev
))
9910 __bnxt_close_nic(bp
, true, false);
9912 bnxt_ulp_irq_stop(bp
);
9913 bnxt_clear_int_mode(bp
);
9914 rc
= bnxt_init_int_mode(bp
);
9915 bnxt_ulp_irq_restart(bp
, rc
);
9917 if (netif_running(bp
->dev
)) {
9921 rc
= bnxt_open_nic(bp
, true, false);
9927 static int bnxt_init_mac_addr(struct bnxt
*bp
)
9932 memcpy(bp
->dev
->dev_addr
, bp
->pf
.mac_addr
, ETH_ALEN
);
9934 #ifdef CONFIG_BNXT_SRIOV
9935 struct bnxt_vf_info
*vf
= &bp
->vf
;
9936 bool strict_approval
= true;
9938 if (is_valid_ether_addr(vf
->mac_addr
)) {
9939 /* overwrite netdev dev_addr with admin VF MAC */
9940 memcpy(bp
->dev
->dev_addr
, vf
->mac_addr
, ETH_ALEN
);
9941 /* Older PF driver or firmware may not approve this
9944 strict_approval
= false;
9946 eth_hw_addr_random(bp
->dev
);
9948 rc
= bnxt_approve_mac(bp
, bp
->dev
->dev_addr
, strict_approval
);
9954 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
9956 static int version_printed
;
9957 struct net_device
*dev
;
9961 if (pci_is_bridge(pdev
))
9964 if (version_printed
++ == 0)
9965 pr_info("%s", version
);
9967 max_irqs
= bnxt_get_max_irq(pdev
);
9968 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
9972 bp
= netdev_priv(dev
);
9973 bnxt_set_max_func_irqs(bp
, max_irqs
);
9975 if (bnxt_vf_pciid(ent
->driver_data
))
9976 bp
->flags
|= BNXT_FLAG_VF
;
9979 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
9981 rc
= bnxt_init_board(pdev
, dev
);
9985 dev
->netdev_ops
= &bnxt_netdev_ops
;
9986 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
9987 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
9988 SWITCHDEV_SET_OPS(dev
, &bnxt_switchdev_ops
);
9989 pci_set_drvdata(pdev
, dev
);
9991 rc
= bnxt_alloc_hwrm_resources(bp
);
9993 goto init_err_pci_clean
;
9995 mutex_init(&bp
->hwrm_cmd_lock
);
9996 rc
= bnxt_hwrm_ver_get(bp
);
9998 goto init_err_pci_clean
;
10000 if ((bp
->fw_cap
& BNXT_FW_CAP_SHORT_CMD
) ||
10001 bp
->hwrm_max_ext_req_len
> BNXT_HWRM_MAX_REQ_LEN
) {
10002 rc
= bnxt_alloc_hwrm_short_cmd_req(bp
);
10004 goto init_err_pci_clean
;
10007 if (BNXT_CHIP_P5(bp
))
10008 bp
->flags
|= BNXT_FLAG_CHIP_P5
;
10010 rc
= bnxt_hwrm_func_reset(bp
);
10012 goto init_err_pci_clean
;
10014 bnxt_hwrm_fw_set_time(bp
);
10016 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
10017 NETIF_F_TSO
| NETIF_F_TSO6
|
10018 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
10019 NETIF_F_GSO_IPXIP4
|
10020 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
10021 NETIF_F_GSO_PARTIAL
| NETIF_F_RXHASH
|
10022 NETIF_F_RXCSUM
| NETIF_F_GRO
;
10024 if (BNXT_SUPPORTS_TPA(bp
))
10025 dev
->hw_features
|= NETIF_F_LRO
;
10027 dev
->hw_enc_features
=
10028 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
10029 NETIF_F_TSO
| NETIF_F_TSO6
|
10030 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
10031 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
10032 NETIF_F_GSO_IPXIP4
| NETIF_F_GSO_PARTIAL
;
10033 dev
->gso_partial_features
= NETIF_F_GSO_UDP_TUNNEL_CSUM
|
10034 NETIF_F_GSO_GRE_CSUM
;
10035 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
10036 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
10037 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
10038 if (BNXT_SUPPORTS_TPA(bp
))
10039 dev
->hw_features
|= NETIF_F_GRO_HW
;
10040 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
10041 if (dev
->features
& NETIF_F_GRO_HW
)
10042 dev
->features
&= ~NETIF_F_LRO
;
10043 dev
->priv_flags
|= IFF_UNICAST_FLT
;
10045 #ifdef CONFIG_BNXT_SRIOV
10046 init_waitqueue_head(&bp
->sriov_cfg_wait
);
10047 mutex_init(&bp
->sriov_lock
);
10049 if (BNXT_SUPPORTS_TPA(bp
)) {
10050 bp
->gro_func
= bnxt_gro_func_5730x
;
10051 if (BNXT_CHIP_P4(bp
))
10052 bp
->gro_func
= bnxt_gro_func_5731x
;
10054 if (!BNXT_CHIP_P4_PLUS(bp
))
10055 bp
->flags
|= BNXT_FLAG_DOUBLE_DB
;
10057 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
10059 goto init_err_pci_clean
;
10061 rc
= bnxt_hwrm_func_rgtr_async_events(bp
, NULL
, 0);
10063 goto init_err_pci_clean
;
10065 bp
->ulp_probe
= bnxt_ulp_probe
;
10067 rc
= bnxt_hwrm_queue_qportcfg(bp
);
10069 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
10072 goto init_err_pci_clean
;
10074 /* Get the MAX capabilities for this function */
10075 rc
= bnxt_hwrm_func_qcaps(bp
);
10077 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
10080 goto init_err_pci_clean
;
10082 rc
= bnxt_init_mac_addr(bp
);
10084 dev_err(&pdev
->dev
, "Unable to initialize mac address.\n");
10085 rc
= -EADDRNOTAVAIL
;
10086 goto init_err_pci_clean
;
10089 bnxt_hwrm_func_qcfg(bp
);
10090 bnxt_hwrm_vnic_qcaps(bp
);
10091 bnxt_hwrm_port_led_qcaps(bp
);
10092 bnxt_ethtool_init(bp
);
10095 /* MTU range: 60 - FW defined max */
10096 dev
->min_mtu
= ETH_ZLEN
;
10097 dev
->max_mtu
= bp
->max_mtu
;
10099 rc
= bnxt_probe_phy(bp
);
10101 goto init_err_pci_clean
;
10103 bnxt_set_rx_skb_mode(bp
, false);
10104 bnxt_set_tpa_flags(bp
);
10105 bnxt_set_ring_params(bp
);
10106 rc
= bnxt_set_dflt_rings(bp
, true);
10108 netdev_err(bp
->dev
, "Not enough rings available.\n");
10110 goto init_err_pci_clean
;
10113 /* Default RSS hash cfg. */
10114 bp
->rss_hash_cfg
= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4
|
10115 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4
|
10116 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6
|
10117 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6
;
10118 if (BNXT_CHIP_P4(bp
) && bp
->hwrm_spec_code
>= 0x10501) {
10119 bp
->flags
|= BNXT_FLAG_UDP_RSS_CAP
;
10120 bp
->rss_hash_cfg
|= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4
|
10121 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6
;
10124 if (bnxt_rfs_supported(bp
)) {
10125 dev
->hw_features
|= NETIF_F_NTUPLE
;
10126 if (bnxt_rfs_capable(bp
)) {
10127 bp
->flags
|= BNXT_FLAG_RFS
;
10128 dev
->features
|= NETIF_F_NTUPLE
;
10132 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
10133 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
10135 rc
= bnxt_init_int_mode(bp
);
10137 goto init_err_pci_clean
;
10139 /* No TC has been set yet and rings may have been trimmed due to
10140 * limited MSIX, so we re-initialize the TX rings per TC.
10142 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
10144 bnxt_get_wol_settings(bp
);
10145 if (bp
->flags
& BNXT_FLAG_WOL_CAP
)
10146 device_set_wakeup_enable(&pdev
->dev
, bp
->wol
);
10148 device_set_wakeup_capable(&pdev
->dev
, false);
10150 bnxt_hwrm_set_cache_line_size(bp
, cache_line_size());
10152 bnxt_hwrm_coal_params_qcaps(bp
);
10157 create_singlethread_workqueue("bnxt_pf_wq");
10159 dev_err(&pdev
->dev
, "Unable to create workqueue.\n");
10160 goto init_err_pci_clean
;
10166 rc
= register_netdev(dev
);
10168 goto init_err_cleanup_tc
;
10171 bnxt_dl_register(bp
);
10173 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
10174 board_info
[ent
->driver_data
].name
,
10175 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
10176 pcie_print_link_status(pdev
);
10180 init_err_cleanup_tc
:
10181 bnxt_shutdown_tc(bp
);
10182 bnxt_clear_int_mode(bp
);
10184 init_err_pci_clean
:
10185 bnxt_free_hwrm_resources(bp
);
10186 bnxt_free_ctx_mem(bp
);
10189 bnxt_cleanup_pci(bp
);
10196 static void bnxt_shutdown(struct pci_dev
*pdev
)
10198 struct net_device
*dev
= pci_get_drvdata(pdev
);
10205 bp
= netdev_priv(dev
);
10207 goto shutdown_exit
;
10209 if (netif_running(dev
))
10212 bnxt_ulp_shutdown(bp
);
10214 if (system_state
== SYSTEM_POWER_OFF
) {
10215 bnxt_clear_int_mode(bp
);
10216 pci_wake_from_d3(pdev
, bp
->wol
);
10217 pci_set_power_state(pdev
, PCI_D3hot
);
10224 #ifdef CONFIG_PM_SLEEP
10225 static int bnxt_suspend(struct device
*device
)
10227 struct pci_dev
*pdev
= to_pci_dev(device
);
10228 struct net_device
*dev
= pci_get_drvdata(pdev
);
10229 struct bnxt
*bp
= netdev_priv(dev
);
10233 if (netif_running(dev
)) {
10234 netif_device_detach(dev
);
10235 rc
= bnxt_close(dev
);
10237 bnxt_hwrm_func_drv_unrgtr(bp
);
10242 static int bnxt_resume(struct device
*device
)
10244 struct pci_dev
*pdev
= to_pci_dev(device
);
10245 struct net_device
*dev
= pci_get_drvdata(pdev
);
10246 struct bnxt
*bp
= netdev_priv(dev
);
10250 if (bnxt_hwrm_ver_get(bp
) || bnxt_hwrm_func_drv_rgtr(bp
)) {
10254 rc
= bnxt_hwrm_func_reset(bp
);
10259 bnxt_get_wol_settings(bp
);
10260 if (netif_running(dev
)) {
10261 rc
= bnxt_open(dev
);
10263 netif_device_attach(dev
);
10271 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops
, bnxt_suspend
, bnxt_resume
);
10272 #define BNXT_PM_OPS (&bnxt_pm_ops)
10276 #define BNXT_PM_OPS NULL
10278 #endif /* CONFIG_PM_SLEEP */
10281 * bnxt_io_error_detected - called when PCI error is detected
10282 * @pdev: Pointer to PCI device
10283 * @state: The current pci connection state
10285 * This function is called after a PCI bus error affecting
10286 * this device has been detected.
10288 static pci_ers_result_t
bnxt_io_error_detected(struct pci_dev
*pdev
,
10289 pci_channel_state_t state
)
10291 struct net_device
*netdev
= pci_get_drvdata(pdev
);
10292 struct bnxt
*bp
= netdev_priv(netdev
);
10294 netdev_info(netdev
, "PCI I/O error detected\n");
10297 netif_device_detach(netdev
);
10301 if (state
== pci_channel_io_perm_failure
) {
10303 return PCI_ERS_RESULT_DISCONNECT
;
10306 if (netif_running(netdev
))
10307 bnxt_close(netdev
);
10309 pci_disable_device(pdev
);
10312 /* Request a slot slot reset. */
10313 return PCI_ERS_RESULT_NEED_RESET
;
10317 * bnxt_io_slot_reset - called after the pci bus has been reset.
10318 * @pdev: Pointer to PCI device
10320 * Restart the card from scratch, as if from a cold-boot.
10321 * At this point, the card has exprienced a hard reset,
10322 * followed by fixups by BIOS, and has its config space
10323 * set up identically to what it was at cold boot.
10325 static pci_ers_result_t
bnxt_io_slot_reset(struct pci_dev
*pdev
)
10327 struct net_device
*netdev
= pci_get_drvdata(pdev
);
10328 struct bnxt
*bp
= netdev_priv(netdev
);
10330 pci_ers_result_t result
= PCI_ERS_RESULT_DISCONNECT
;
10332 netdev_info(bp
->dev
, "PCI Slot Reset\n");
10336 if (pci_enable_device(pdev
)) {
10337 dev_err(&pdev
->dev
,
10338 "Cannot re-enable PCI device after reset.\n");
10340 pci_set_master(pdev
);
10342 err
= bnxt_hwrm_func_reset(bp
);
10343 if (!err
&& netif_running(netdev
))
10344 err
= bnxt_open(netdev
);
10347 result
= PCI_ERS_RESULT_RECOVERED
;
10348 bnxt_ulp_start(bp
);
10352 if (result
!= PCI_ERS_RESULT_RECOVERED
&& netif_running(netdev
))
10357 return PCI_ERS_RESULT_RECOVERED
;
10361 * bnxt_io_resume - called when traffic can start flowing again.
10362 * @pdev: Pointer to PCI device
10364 * This callback is called when the error recovery driver tells
10365 * us that its OK to resume normal operation.
10367 static void bnxt_io_resume(struct pci_dev
*pdev
)
10369 struct net_device
*netdev
= pci_get_drvdata(pdev
);
10373 netif_device_attach(netdev
);
10378 static const struct pci_error_handlers bnxt_err_handler
= {
10379 .error_detected
= bnxt_io_error_detected
,
10380 .slot_reset
= bnxt_io_slot_reset
,
10381 .resume
= bnxt_io_resume
10384 static struct pci_driver bnxt_pci_driver
= {
10385 .name
= DRV_MODULE_NAME
,
10386 .id_table
= bnxt_pci_tbl
,
10387 .probe
= bnxt_init_one
,
10388 .remove
= bnxt_remove_one
,
10389 .shutdown
= bnxt_shutdown
,
10390 .driver
.pm
= BNXT_PM_OPS
,
10391 .err_handler
= &bnxt_err_handler
,
10392 #if defined(CONFIG_BNXT_SRIOV)
10393 .sriov_configure
= bnxt_sriov_configure
,
10397 static int __init
bnxt_init(void)
10400 return pci_register_driver(&bnxt_pci_driver
);
10403 static void __exit
bnxt_exit(void)
10405 pci_unregister_driver(&bnxt_pci_driver
);
10407 destroy_workqueue(bnxt_pf_wq
);
10411 module_init(bnxt_init
);
10412 module_exit(bnxt_exit
);