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Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
[people/ms/linux.git] / drivers / net / ethernet / cavium / thunder / nic_main.c
1 /*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/etherdevice.h>
13 #include <linux/of.h>
14
15 #include "nic_reg.h"
16 #include "nic.h"
17 #include "q_struct.h"
18 #include "thunder_bgx.h"
19
20 #define DRV_NAME "thunder-nic"
21 #define DRV_VERSION "1.0"
22
23 struct nicpf {
24 struct pci_dev *pdev;
25 u8 node;
26 unsigned int flags;
27 u8 num_vf_en; /* No of VF enabled */
28 bool vf_enabled[MAX_NUM_VFS_SUPPORTED];
29 void __iomem *reg_base; /* Register start address */
30 u8 num_sqs_en; /* Secondary qsets enabled */
31 u64 nicvf[MAX_NUM_VFS_SUPPORTED];
32 u8 vf_sqs[MAX_NUM_VFS_SUPPORTED][MAX_SQS_PER_VF];
33 u8 pqs_vf[MAX_NUM_VFS_SUPPORTED];
34 bool sqs_used[MAX_NUM_VFS_SUPPORTED];
35 struct pkind_cfg pkind;
36 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) (((bgx & 0xF) << 4) | (lmac & 0xF))
37 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) ((map >> 4) & 0xF)
38 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) (map & 0xF)
39 u8 vf_lmac_map[MAX_LMAC];
40 struct delayed_work dwork;
41 struct workqueue_struct *check_link;
42 u8 link[MAX_LMAC];
43 u8 duplex[MAX_LMAC];
44 u32 speed[MAX_LMAC];
45 u16 cpi_base[MAX_NUM_VFS_SUPPORTED];
46 u16 rssi_base[MAX_NUM_VFS_SUPPORTED];
47 u16 rss_ind_tbl_size;
48 bool mbx_lock[MAX_NUM_VFS_SUPPORTED];
49
50 /* MSI-X */
51 bool msix_enabled;
52 u8 num_vec;
53 struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS];
54 bool irq_allocated[NIC_PF_MSIX_VECTORS];
55 };
56
57 static inline bool pass1_silicon(struct nicpf *nic)
58 {
59 return nic->pdev->revision < 8;
60 }
61
62 /* Supported devices */
63 static const struct pci_device_id nic_id_table[] = {
64 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) },
65 { 0, } /* end of table */
66 };
67
68 MODULE_AUTHOR("Sunil Goutham");
69 MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver");
70 MODULE_LICENSE("GPL v2");
71 MODULE_VERSION(DRV_VERSION);
72 MODULE_DEVICE_TABLE(pci, nic_id_table);
73
74 /* The Cavium ThunderX network controller can *only* be found in SoCs
75 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
76 * registers on this platform are implicitly strongly ordered with respect
77 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
78 * with no memory barriers in this driver. The readq()/writeq() functions add
79 * explicit ordering operation which in this case are redundant, and only
80 * add overhead.
81 */
82
83 /* Register read/write APIs */
84 static void nic_reg_write(struct nicpf *nic, u64 offset, u64 val)
85 {
86 writeq_relaxed(val, nic->reg_base + offset);
87 }
88
89 static u64 nic_reg_read(struct nicpf *nic, u64 offset)
90 {
91 return readq_relaxed(nic->reg_base + offset);
92 }
93
94 /* PF -> VF mailbox communication APIs */
95 static void nic_enable_mbx_intr(struct nicpf *nic)
96 {
97 /* Enable mailbox interrupt for all 128 VFs */
98 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0ull);
99 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64), ~0ull);
100 }
101
102 static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg)
103 {
104 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf));
105 }
106
107 static u64 nic_get_mbx_addr(int vf)
108 {
109 return NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT);
110 }
111
112 /* Send a mailbox message to VF
113 * @vf: vf to which this message to be sent
114 * @mbx: Message to be sent
115 */
116 static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx)
117 {
118 void __iomem *mbx_addr = nic->reg_base + nic_get_mbx_addr(vf);
119 u64 *msg = (u64 *)mbx;
120
121 /* In first revision HW, mbox interrupt is triggerred
122 * when PF writes to MBOX(1), in next revisions when
123 * PF writes to MBOX(0)
124 */
125 if (pass1_silicon(nic)) {
126 /* see the comment for nic_reg_write()/nic_reg_read()
127 * functions above
128 */
129 writeq_relaxed(msg[0], mbx_addr);
130 writeq_relaxed(msg[1], mbx_addr + 8);
131 } else {
132 writeq_relaxed(msg[1], mbx_addr + 8);
133 writeq_relaxed(msg[0], mbx_addr);
134 }
135 }
136
137 /* Responds to VF's READY message with VF's
138 * ID, node, MAC address e.t.c
139 * @vf: VF which sent READY message
140 */
141 static void nic_mbx_send_ready(struct nicpf *nic, int vf)
142 {
143 union nic_mbx mbx = {};
144 int bgx_idx, lmac;
145 const char *mac;
146
147 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY;
148 mbx.nic_cfg.vf_id = vf;
149
150 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE;
151
152 if (vf < MAX_LMAC) {
153 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
154 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
155
156 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac);
157 if (mac)
158 ether_addr_copy((u8 *)&mbx.nic_cfg.mac_addr, mac);
159 }
160 mbx.nic_cfg.sqs_mode = (vf >= nic->num_vf_en) ? true : false;
161 mbx.nic_cfg.node_id = nic->node;
162
163 mbx.nic_cfg.loopback_supported = vf < MAX_LMAC;
164
165 nic_send_msg_to_vf(nic, vf, &mbx);
166 }
167
168 /* ACKs VF's mailbox message
169 * @vf: VF to which ACK to be sent
170 */
171 static void nic_mbx_send_ack(struct nicpf *nic, int vf)
172 {
173 union nic_mbx mbx = {};
174
175 mbx.msg.msg = NIC_MBOX_MSG_ACK;
176 nic_send_msg_to_vf(nic, vf, &mbx);
177 }
178
179 /* NACKs VF's mailbox message that PF is not able to
180 * complete the action
181 * @vf: VF to which ACK to be sent
182 */
183 static void nic_mbx_send_nack(struct nicpf *nic, int vf)
184 {
185 union nic_mbx mbx = {};
186
187 mbx.msg.msg = NIC_MBOX_MSG_NACK;
188 nic_send_msg_to_vf(nic, vf, &mbx);
189 }
190
191 /* Flush all in flight receive packets to memory and
192 * bring down an active RQ
193 */
194 static int nic_rcv_queue_sw_sync(struct nicpf *nic)
195 {
196 u16 timeout = ~0x00;
197
198 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01);
199 /* Wait till sync cycle is finished */
200 while (timeout) {
201 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1)
202 break;
203 timeout--;
204 }
205 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00);
206 if (!timeout) {
207 dev_err(&nic->pdev->dev, "Receive queue software sync failed");
208 return 1;
209 }
210 return 0;
211 }
212
213 /* Get BGX Rx/Tx stats and respond to VF's request */
214 static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx)
215 {
216 int bgx_idx, lmac;
217 union nic_mbx mbx = {};
218
219 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
220 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
221
222 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
223 mbx.bgx_stats.vf_id = bgx->vf_id;
224 mbx.bgx_stats.rx = bgx->rx;
225 mbx.bgx_stats.idx = bgx->idx;
226 if (bgx->rx)
227 mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx,
228 lmac, bgx->idx);
229 else
230 mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx,
231 lmac, bgx->idx);
232 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx);
233 }
234
235 /* Update hardware min/max frame size */
236 static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf)
237 {
238 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) {
239 dev_err(&nic->pdev->dev,
240 "Invalid MTU setting from VF%d rejected, should be between %d and %d\n",
241 vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS);
242 return 1;
243 }
244 new_frs += ETH_HLEN;
245 if (new_frs <= nic->pkind.maxlen)
246 return 0;
247
248 nic->pkind.maxlen = new_frs;
249 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(u64 *)&nic->pkind);
250 return 0;
251 }
252
253 /* Set minimum transmit packet size */
254 static void nic_set_tx_pkt_pad(struct nicpf *nic, int size)
255 {
256 int lmac;
257 u64 lmac_cfg;
258
259 /* Max value that can be set is 60 */
260 if (size > 60)
261 size = 60;
262
263 for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) {
264 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3));
265 lmac_cfg &= ~(0xF << 2);
266 lmac_cfg |= ((size / 4) << 2);
267 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg);
268 }
269 }
270
271 /* Function to check number of LMACs present and set VF::LMAC mapping.
272 * Mapping will be used while initializing channels.
273 */
274 static void nic_set_lmac_vf_mapping(struct nicpf *nic)
275 {
276 unsigned bgx_map = bgx_get_map(nic->node);
277 int bgx, next_bgx_lmac = 0;
278 int lmac, lmac_cnt = 0;
279 u64 lmac_credit;
280
281 nic->num_vf_en = 0;
282
283 for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) {
284 if (!(bgx_map & (1 << bgx)))
285 continue;
286 lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
287 for (lmac = 0; lmac < lmac_cnt; lmac++)
288 nic->vf_lmac_map[next_bgx_lmac++] =
289 NIC_SET_VF_LMAC_MAP(bgx, lmac);
290 nic->num_vf_en += lmac_cnt;
291
292 /* Program LMAC credits */
293 lmac_credit = (1ull << 1); /* channel credit enable */
294 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */
295 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */
296 lmac_credit |= (((((48 * 1024) / lmac_cnt) -
297 NIC_HW_MAX_FRS) / 16) << 12);
298 lmac = bgx * MAX_LMAC_PER_BGX;
299 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++)
300 nic_reg_write(nic,
301 NIC_PF_LMAC_0_7_CREDIT + (lmac * 8),
302 lmac_credit);
303 }
304 }
305
306 #define BGX0_BLOCK 8
307 #define BGX1_BLOCK 9
308
309 static void nic_init_hw(struct nicpf *nic)
310 {
311 int i;
312
313 /* Enable NIC HW block */
314 nic_reg_write(nic, NIC_PF_CFG, 0x3);
315
316 /* Enable backpressure */
317 nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03);
318
319 /* Disable TNS mode on both interfaces */
320 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG,
321 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK);
322 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8),
323 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK);
324 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG,
325 (1ULL << 63) | BGX0_BLOCK);
326 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8),
327 (1ULL << 63) | BGX1_BLOCK);
328
329 /* PKIND configuration */
330 nic->pkind.minlen = 0;
331 nic->pkind.maxlen = NIC_HW_MAX_FRS + ETH_HLEN;
332 nic->pkind.lenerr_en = 1;
333 nic->pkind.rx_hdr = 0;
334 nic->pkind.hdr_sl = 0;
335
336 for (i = 0; i < NIC_MAX_PKIND; i++)
337 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3),
338 *(u64 *)&nic->pkind);
339
340 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS);
341
342 /* Timer config */
343 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK);
344
345 /* Enable VLAN ethertype matching and stripping */
346 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7,
347 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETH_P_8021Q);
348 }
349
350 /* Channel parse index configuration */
351 static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg)
352 {
353 u32 vnic, bgx, lmac, chan;
354 u32 padd, cpi_count = 0;
355 u64 cpi_base, cpi, rssi_base, rssi;
356 u8 qset, rq_idx = 0;
357
358 vnic = cfg->vf_id;
359 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
360 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
361
362 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
363 cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX);
364 rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX);
365
366 /* Rx channel configuration */
367 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3),
368 (1ull << 63) | (vnic << 0));
369 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3),
370 ((u64)cfg->cpi_alg << 62) | (cpi_base << 48));
371
372 if (cfg->cpi_alg == CPI_ALG_NONE)
373 cpi_count = 1;
374 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */
375 cpi_count = 8;
376 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */
377 cpi_count = 16;
378 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */
379 cpi_count = NIC_MAX_CPI_PER_LMAC;
380
381 /* RSS Qset, Qidx mapping */
382 qset = cfg->vf_id;
383 rssi = rssi_base;
384 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) {
385 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
386 (qset << 3) | rq_idx);
387 rq_idx++;
388 }
389
390 rssi = 0;
391 cpi = cpi_base;
392 for (; cpi < (cpi_base + cpi_count); cpi++) {
393 /* Determine port to channel adder */
394 if (cfg->cpi_alg != CPI_ALG_DIFF)
395 padd = cpi % cpi_count;
396 else
397 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */
398
399 /* Leave RSS_SIZE as '0' to disable RSS */
400 if (pass1_silicon(nic)) {
401 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
402 (vnic << 24) | (padd << 16) |
403 (rssi_base + rssi));
404 } else {
405 /* Set MPI_ALG to '0' to disable MCAM parsing */
406 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
407 (padd << 16));
408 /* MPI index is same as CPI if MPI_ALG is not enabled */
409 nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3),
410 (vnic << 24) | (rssi_base + rssi));
411 }
412
413 if ((rssi + 1) >= cfg->rq_cnt)
414 continue;
415
416 if (cfg->cpi_alg == CPI_ALG_VLAN)
417 rssi++;
418 else if (cfg->cpi_alg == CPI_ALG_VLAN16)
419 rssi = ((cpi - cpi_base) & 0xe) >> 1;
420 else if (cfg->cpi_alg == CPI_ALG_DIFF)
421 rssi = ((cpi - cpi_base) & 0x38) >> 3;
422 }
423 nic->cpi_base[cfg->vf_id] = cpi_base;
424 nic->rssi_base[cfg->vf_id] = rssi_base;
425 }
426
427 /* Responsds to VF with its RSS indirection table size */
428 static void nic_send_rss_size(struct nicpf *nic, int vf)
429 {
430 union nic_mbx mbx = {};
431 u64 *msg;
432
433 msg = (u64 *)&mbx;
434
435 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
436 mbx.rss_size.ind_tbl_size = nic->rss_ind_tbl_size;
437 nic_send_msg_to_vf(nic, vf, &mbx);
438 }
439
440 /* Receive side scaling configuration
441 * configure:
442 * - RSS index
443 * - indir table i.e hash::RQ mapping
444 * - no of hash bits to consider
445 */
446 static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
447 {
448 u8 qset, idx = 0;
449 u64 cpi_cfg, cpi_base, rssi_base, rssi;
450 u64 idx_addr;
451
452 rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset;
453
454 rssi = rssi_base;
455 qset = cfg->vf_id;
456
457 for (; rssi < (rssi_base + cfg->tbl_len); rssi++) {
458 u8 svf = cfg->ind_tbl[idx] >> 3;
459
460 if (svf)
461 qset = nic->vf_sqs[cfg->vf_id][svf - 1];
462 else
463 qset = cfg->vf_id;
464 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
465 (qset << 3) | (cfg->ind_tbl[idx] & 0x7));
466 idx++;
467 }
468
469 cpi_base = nic->cpi_base[cfg->vf_id];
470 if (pass1_silicon(nic))
471 idx_addr = NIC_PF_CPI_0_2047_CFG;
472 else
473 idx_addr = NIC_PF_MPI_0_2047_CFG;
474 cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3));
475 cpi_cfg &= ~(0xFULL << 20);
476 cpi_cfg |= (cfg->hash_bits << 20);
477 nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg);
478 }
479
480 /* 4 level transmit side scheduler configutation
481 * for TNS bypass mode
482 *
483 * Sample configuration for SQ0
484 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0
485 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0
486 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0
487 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0
488 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1
489 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1
490 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1
491 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1
492 */
493 static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic,
494 struct sq_cfg_msg *sq)
495 {
496 u32 bgx, lmac, chan;
497 u32 tl2, tl3, tl4;
498 u32 rr_quantum;
499 u8 sq_idx = sq->sq_num;
500 u8 pqs_vnic;
501
502 if (sq->sqs_mode)
503 pqs_vnic = nic->pqs_vf[vnic];
504 else
505 pqs_vnic = vnic;
506
507 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
508 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
509
510 /* 24 bytes for FCS, IPG and preamble */
511 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4);
512
513 tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX);
514 tl4 += sq_idx;
515 if (sq->sqs_mode)
516 tl4 += vnic * 8;
517
518 tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3);
519 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 |
520 ((u64)vnic << NIC_QS_ID_SHIFT) |
521 ((u32)sq_idx << NIC_Q_NUM_SHIFT), tl4);
522 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3),
523 ((u64)vnic << 27) | ((u32)sq_idx << 24) | rr_quantum);
524
525 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum);
526 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
527 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan);
528 /* Enable backpressure on the channel */
529 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1);
530
531 tl2 = tl3 >> 2;
532 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2);
533 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum);
534 /* No priorities as of now */
535 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00);
536 }
537
538 /* Send primary nicvf pointer to secondary QS's VF */
539 static void nic_send_pnicvf(struct nicpf *nic, int sqs)
540 {
541 union nic_mbx mbx = {};
542
543 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR;
544 mbx.nicvf.nicvf = nic->nicvf[nic->pqs_vf[sqs]];
545 nic_send_msg_to_vf(nic, sqs, &mbx);
546 }
547
548 /* Send SQS's nicvf pointer to primary QS's VF */
549 static void nic_send_snicvf(struct nicpf *nic, struct nicvf_ptr *nicvf)
550 {
551 union nic_mbx mbx = {};
552 int sqs_id = nic->vf_sqs[nicvf->vf_id][nicvf->sqs_id];
553
554 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR;
555 mbx.nicvf.sqs_id = nicvf->sqs_id;
556 mbx.nicvf.nicvf = nic->nicvf[sqs_id];
557 nic_send_msg_to_vf(nic, nicvf->vf_id, &mbx);
558 }
559
560 /* Find next available Qset that can be assigned as a
561 * secondary Qset to a VF.
562 */
563 static int nic_nxt_avail_sqs(struct nicpf *nic)
564 {
565 int sqs;
566
567 for (sqs = 0; sqs < nic->num_sqs_en; sqs++) {
568 if (!nic->sqs_used[sqs])
569 nic->sqs_used[sqs] = true;
570 else
571 continue;
572 return sqs + nic->num_vf_en;
573 }
574 return -1;
575 }
576
577 /* Allocate additional Qsets for requested VF */
578 static void nic_alloc_sqs(struct nicpf *nic, struct sqs_alloc *sqs)
579 {
580 union nic_mbx mbx = {};
581 int idx, alloc_qs = 0;
582 int sqs_id;
583
584 if (!nic->num_sqs_en)
585 goto send_mbox;
586
587 for (idx = 0; idx < sqs->qs_count; idx++) {
588 sqs_id = nic_nxt_avail_sqs(nic);
589 if (sqs_id < 0)
590 break;
591 nic->vf_sqs[sqs->vf_id][idx] = sqs_id;
592 nic->pqs_vf[sqs_id] = sqs->vf_id;
593 alloc_qs++;
594 }
595
596 send_mbox:
597 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS;
598 mbx.sqs_alloc.vf_id = sqs->vf_id;
599 mbx.sqs_alloc.qs_count = alloc_qs;
600 nic_send_msg_to_vf(nic, sqs->vf_id, &mbx);
601 }
602
603 static int nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk)
604 {
605 int bgx_idx, lmac_idx;
606
607 if (lbk->vf_id > MAX_LMAC)
608 return -1;
609
610 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
611 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
612
613 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable);
614
615 return 0;
616 }
617
618 /* Interrupt handler to handle mailbox messages from VFs */
619 static void nic_handle_mbx_intr(struct nicpf *nic, int vf)
620 {
621 union nic_mbx mbx = {};
622 u64 *mbx_data;
623 u64 mbx_addr;
624 u64 reg_addr;
625 u64 cfg;
626 int bgx, lmac;
627 int i;
628 int ret = 0;
629
630 nic->mbx_lock[vf] = true;
631
632 mbx_addr = nic_get_mbx_addr(vf);
633 mbx_data = (u64 *)&mbx;
634
635 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
636 *mbx_data = nic_reg_read(nic, mbx_addr);
637 mbx_data++;
638 mbx_addr += sizeof(u64);
639 }
640
641 dev_dbg(&nic->pdev->dev, "%s: Mailbox msg %d from VF%d\n",
642 __func__, mbx.msg.msg, vf);
643 switch (mbx.msg.msg) {
644 case NIC_MBOX_MSG_READY:
645 nic_mbx_send_ready(nic, vf);
646 if (vf < MAX_LMAC) {
647 nic->link[vf] = 0;
648 nic->duplex[vf] = 0;
649 nic->speed[vf] = 0;
650 }
651 ret = 1;
652 break;
653 case NIC_MBOX_MSG_QS_CFG:
654 reg_addr = NIC_PF_QSET_0_127_CFG |
655 (mbx.qs.num << NIC_QS_ID_SHIFT);
656 cfg = mbx.qs.cfg;
657 /* Check if its a secondary Qset */
658 if (vf >= nic->num_vf_en) {
659 cfg = cfg & (~0x7FULL);
660 /* Assign this Qset to primary Qset's VF */
661 cfg |= nic->pqs_vf[vf];
662 }
663 nic_reg_write(nic, reg_addr, cfg);
664 break;
665 case NIC_MBOX_MSG_RQ_CFG:
666 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG |
667 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
668 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
669 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
670 break;
671 case NIC_MBOX_MSG_RQ_BP_CFG:
672 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG |
673 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
674 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
675 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
676 break;
677 case NIC_MBOX_MSG_RQ_SW_SYNC:
678 ret = nic_rcv_queue_sw_sync(nic);
679 break;
680 case NIC_MBOX_MSG_RQ_DROP_CFG:
681 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG |
682 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
683 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
684 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
685 break;
686 case NIC_MBOX_MSG_SQ_CFG:
687 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG |
688 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) |
689 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT);
690 nic_reg_write(nic, reg_addr, mbx.sq.cfg);
691 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq);
692 break;
693 case NIC_MBOX_MSG_SET_MAC:
694 if (vf >= nic->num_vf_en)
695 break;
696 lmac = mbx.mac.vf_id;
697 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
698 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
699 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr);
700 break;
701 case NIC_MBOX_MSG_SET_MAX_FRS:
702 ret = nic_update_hw_frs(nic, mbx.frs.max_frs,
703 mbx.frs.vf_id);
704 break;
705 case NIC_MBOX_MSG_CPI_CFG:
706 nic_config_cpi(nic, &mbx.cpi_cfg);
707 break;
708 case NIC_MBOX_MSG_RSS_SIZE:
709 nic_send_rss_size(nic, vf);
710 goto unlock;
711 case NIC_MBOX_MSG_RSS_CFG:
712 case NIC_MBOX_MSG_RSS_CFG_CONT:
713 nic_config_rss(nic, &mbx.rss_cfg);
714 break;
715 case NIC_MBOX_MSG_CFG_DONE:
716 /* Last message of VF config msg sequence */
717 nic->vf_enabled[vf] = true;
718 goto unlock;
719 case NIC_MBOX_MSG_SHUTDOWN:
720 /* First msg in VF teardown sequence */
721 nic->vf_enabled[vf] = false;
722 if (vf >= nic->num_vf_en)
723 nic->sqs_used[vf - nic->num_vf_en] = false;
724 nic->pqs_vf[vf] = 0;
725 break;
726 case NIC_MBOX_MSG_ALLOC_SQS:
727 nic_alloc_sqs(nic, &mbx.sqs_alloc);
728 goto unlock;
729 case NIC_MBOX_MSG_NICVF_PTR:
730 nic->nicvf[vf] = mbx.nicvf.nicvf;
731 break;
732 case NIC_MBOX_MSG_PNICVF_PTR:
733 nic_send_pnicvf(nic, vf);
734 goto unlock;
735 case NIC_MBOX_MSG_SNICVF_PTR:
736 nic_send_snicvf(nic, &mbx.nicvf);
737 goto unlock;
738 case NIC_MBOX_MSG_BGX_STATS:
739 nic_get_bgx_stats(nic, &mbx.bgx_stats);
740 goto unlock;
741 case NIC_MBOX_MSG_LOOPBACK:
742 ret = nic_config_loopback(nic, &mbx.lbk);
743 break;
744 default:
745 dev_err(&nic->pdev->dev,
746 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg);
747 break;
748 }
749
750 if (!ret)
751 nic_mbx_send_ack(nic, vf);
752 else if (mbx.msg.msg != NIC_MBOX_MSG_READY)
753 nic_mbx_send_nack(nic, vf);
754 unlock:
755 nic->mbx_lock[vf] = false;
756 }
757
758 static void nic_mbx_intr_handler (struct nicpf *nic, int mbx)
759 {
760 u64 intr;
761 u8 vf, vf_per_mbx_reg = 64;
762
763 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3));
764 dev_dbg(&nic->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr);
765 for (vf = 0; vf < vf_per_mbx_reg; vf++) {
766 if (intr & (1ULL << vf)) {
767 dev_dbg(&nic->pdev->dev, "Intr from VF %d\n",
768 vf + (mbx * vf_per_mbx_reg));
769
770 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg));
771 nic_clear_mbx_intr(nic, vf, mbx);
772 }
773 }
774 }
775
776 static irqreturn_t nic_mbx0_intr_handler (int irq, void *nic_irq)
777 {
778 struct nicpf *nic = (struct nicpf *)nic_irq;
779
780 nic_mbx_intr_handler(nic, 0);
781
782 return IRQ_HANDLED;
783 }
784
785 static irqreturn_t nic_mbx1_intr_handler (int irq, void *nic_irq)
786 {
787 struct nicpf *nic = (struct nicpf *)nic_irq;
788
789 nic_mbx_intr_handler(nic, 1);
790
791 return IRQ_HANDLED;
792 }
793
794 static int nic_enable_msix(struct nicpf *nic)
795 {
796 int i, ret;
797
798 nic->num_vec = NIC_PF_MSIX_VECTORS;
799
800 for (i = 0; i < nic->num_vec; i++)
801 nic->msix_entries[i].entry = i;
802
803 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
804 if (ret) {
805 dev_err(&nic->pdev->dev,
806 "Request for #%d msix vectors failed\n",
807 nic->num_vec);
808 return ret;
809 }
810
811 nic->msix_enabled = 1;
812 return 0;
813 }
814
815 static void nic_disable_msix(struct nicpf *nic)
816 {
817 if (nic->msix_enabled) {
818 pci_disable_msix(nic->pdev);
819 nic->msix_enabled = 0;
820 nic->num_vec = 0;
821 }
822 }
823
824 static void nic_free_all_interrupts(struct nicpf *nic)
825 {
826 int irq;
827
828 for (irq = 0; irq < nic->num_vec; irq++) {
829 if (nic->irq_allocated[irq])
830 free_irq(nic->msix_entries[irq].vector, nic);
831 nic->irq_allocated[irq] = false;
832 }
833 }
834
835 static int nic_register_interrupts(struct nicpf *nic)
836 {
837 int ret;
838
839 /* Enable MSI-X */
840 ret = nic_enable_msix(nic);
841 if (ret)
842 return ret;
843
844 /* Register mailbox interrupt handlers */
845 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX0].vector,
846 nic_mbx0_intr_handler, 0, "NIC Mbox0", nic);
847 if (ret)
848 goto fail;
849
850 nic->irq_allocated[NIC_PF_INTR_ID_MBOX0] = true;
851
852 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX1].vector,
853 nic_mbx1_intr_handler, 0, "NIC Mbox1", nic);
854 if (ret)
855 goto fail;
856
857 nic->irq_allocated[NIC_PF_INTR_ID_MBOX1] = true;
858
859 /* Enable mailbox interrupt */
860 nic_enable_mbx_intr(nic);
861 return 0;
862
863 fail:
864 dev_err(&nic->pdev->dev, "Request irq failed\n");
865 nic_free_all_interrupts(nic);
866 return ret;
867 }
868
869 static void nic_unregister_interrupts(struct nicpf *nic)
870 {
871 nic_free_all_interrupts(nic);
872 nic_disable_msix(nic);
873 }
874
875 static int nic_num_sqs_en(struct nicpf *nic, int vf_en)
876 {
877 int pos, sqs_per_vf = MAX_SQS_PER_VF_SINGLE_NODE;
878 u16 total_vf;
879
880 /* Check if its a multi-node environment */
881 if (nr_node_ids > 1)
882 sqs_per_vf = MAX_SQS_PER_VF;
883
884 pos = pci_find_ext_capability(nic->pdev, PCI_EXT_CAP_ID_SRIOV);
885 pci_read_config_word(nic->pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf);
886 return min(total_vf - vf_en, vf_en * sqs_per_vf);
887 }
888
889 static int nic_sriov_init(struct pci_dev *pdev, struct nicpf *nic)
890 {
891 int pos = 0;
892 int vf_en;
893 int err;
894 u16 total_vf_cnt;
895
896 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
897 if (!pos) {
898 dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n");
899 return -ENODEV;
900 }
901
902 pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt);
903 if (total_vf_cnt < nic->num_vf_en)
904 nic->num_vf_en = total_vf_cnt;
905
906 if (!total_vf_cnt)
907 return 0;
908
909 vf_en = nic->num_vf_en;
910 nic->num_sqs_en = nic_num_sqs_en(nic, nic->num_vf_en);
911 vf_en += nic->num_sqs_en;
912
913 err = pci_enable_sriov(pdev, vf_en);
914 if (err) {
915 dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n",
916 vf_en);
917 nic->num_vf_en = 0;
918 return err;
919 }
920
921 dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n",
922 vf_en);
923
924 nic->flags |= NIC_SRIOV_ENABLED;
925 return 0;
926 }
927
928 /* Poll for BGX LMAC link status and update corresponding VF
929 * if there is a change, valid only if internal L2 switch
930 * is not present otherwise VF link is always treated as up
931 */
932 static void nic_poll_for_link(struct work_struct *work)
933 {
934 union nic_mbx mbx = {};
935 struct nicpf *nic;
936 struct bgx_link_status link;
937 u8 vf, bgx, lmac;
938
939 nic = container_of(work, struct nicpf, dwork.work);
940
941 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE;
942
943 for (vf = 0; vf < nic->num_vf_en; vf++) {
944 /* Poll only if VF is UP */
945 if (!nic->vf_enabled[vf])
946 continue;
947
948 /* Get BGX, LMAC indices for the VF */
949 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
950 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
951 /* Get interface link status */
952 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link);
953
954 /* Inform VF only if link status changed */
955 if (nic->link[vf] == link.link_up)
956 continue;
957
958 if (!nic->mbx_lock[vf]) {
959 nic->link[vf] = link.link_up;
960 nic->duplex[vf] = link.duplex;
961 nic->speed[vf] = link.speed;
962
963 /* Send a mbox message to VF with current link status */
964 mbx.link_status.link_up = link.link_up;
965 mbx.link_status.duplex = link.duplex;
966 mbx.link_status.speed = link.speed;
967 nic_send_msg_to_vf(nic, vf, &mbx);
968 }
969 }
970 queue_delayed_work(nic->check_link, &nic->dwork, HZ * 2);
971 }
972
973 static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
974 {
975 struct device *dev = &pdev->dev;
976 struct nicpf *nic;
977 int err;
978
979 BUILD_BUG_ON(sizeof(union nic_mbx) > 16);
980
981 nic = devm_kzalloc(dev, sizeof(*nic), GFP_KERNEL);
982 if (!nic)
983 return -ENOMEM;
984
985 pci_set_drvdata(pdev, nic);
986
987 nic->pdev = pdev;
988
989 err = pci_enable_device(pdev);
990 if (err) {
991 dev_err(dev, "Failed to enable PCI device\n");
992 pci_set_drvdata(pdev, NULL);
993 return err;
994 }
995
996 err = pci_request_regions(pdev, DRV_NAME);
997 if (err) {
998 dev_err(dev, "PCI request regions failed 0x%x\n", err);
999 goto err_disable_device;
1000 }
1001
1002 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
1003 if (err) {
1004 dev_err(dev, "Unable to get usable DMA configuration\n");
1005 goto err_release_regions;
1006 }
1007
1008 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
1009 if (err) {
1010 dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n");
1011 goto err_release_regions;
1012 }
1013
1014 /* MAP PF's configuration registers */
1015 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1016 if (!nic->reg_base) {
1017 dev_err(dev, "Cannot map config register space, aborting\n");
1018 err = -ENOMEM;
1019 goto err_release_regions;
1020 }
1021
1022 nic->node = nic_get_node_id(pdev);
1023
1024 nic_set_lmac_vf_mapping(nic);
1025
1026 /* Initialize hardware */
1027 nic_init_hw(nic);
1028
1029 /* Set RSS TBL size for each VF */
1030 nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
1031
1032 /* Register interrupts */
1033 err = nic_register_interrupts(nic);
1034 if (err)
1035 goto err_release_regions;
1036
1037 /* Configure SRIOV */
1038 err = nic_sriov_init(pdev, nic);
1039 if (err)
1040 goto err_unregister_interrupts;
1041
1042 /* Register a physical link status poll fn() */
1043 nic->check_link = alloc_workqueue("check_link_status",
1044 WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
1045 if (!nic->check_link) {
1046 err = -ENOMEM;
1047 goto err_disable_sriov;
1048 }
1049
1050 INIT_DELAYED_WORK(&nic->dwork, nic_poll_for_link);
1051 queue_delayed_work(nic->check_link, &nic->dwork, 0);
1052
1053 return 0;
1054
1055 err_disable_sriov:
1056 if (nic->flags & NIC_SRIOV_ENABLED)
1057 pci_disable_sriov(pdev);
1058 err_unregister_interrupts:
1059 nic_unregister_interrupts(nic);
1060 err_release_regions:
1061 pci_release_regions(pdev);
1062 err_disable_device:
1063 pci_disable_device(pdev);
1064 pci_set_drvdata(pdev, NULL);
1065 return err;
1066 }
1067
1068 static void nic_remove(struct pci_dev *pdev)
1069 {
1070 struct nicpf *nic = pci_get_drvdata(pdev);
1071
1072 if (nic->flags & NIC_SRIOV_ENABLED)
1073 pci_disable_sriov(pdev);
1074
1075 if (nic->check_link) {
1076 /* Destroy work Queue */
1077 cancel_delayed_work(&nic->dwork);
1078 flush_workqueue(nic->check_link);
1079 destroy_workqueue(nic->check_link);
1080 }
1081
1082 nic_unregister_interrupts(nic);
1083 pci_release_regions(pdev);
1084 pci_disable_device(pdev);
1085 pci_set_drvdata(pdev, NULL);
1086 }
1087
1088 static struct pci_driver nic_driver = {
1089 .name = DRV_NAME,
1090 .id_table = nic_id_table,
1091 .probe = nic_probe,
1092 .remove = nic_remove,
1093 };
1094
1095 static int __init nic_init_module(void)
1096 {
1097 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1098
1099 return pci_register_driver(&nic_driver);
1100 }
1101
1102 static void __exit nic_cleanup_module(void)
1103 {
1104 pci_unregister_driver(&nic_driver);
1105 }
1106
1107 module_init(nic_init_module);
1108 module_exit(nic_cleanup_module);
Michael's Linux tree.