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Merge tag 'dax-fixes-5.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm...
[thirdparty/linux.git] / drivers / net / ethernet / cavium / thunder / thunder_bgx.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Cavium, Inc.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/module.h>
8 #include <linux/interrupt.h>
9 #include <linux/pci.h>
10 #include <linux/netdevice.h>
11 #include <linux/etherdevice.h>
12 #include <linux/phy.h>
13 #include <linux/of.h>
14 #include <linux/of_mdio.h>
15 #include <linux/of_net.h>
16
17 #include "nic_reg.h"
18 #include "nic.h"
19 #include "thunder_bgx.h"
20
21 #define DRV_NAME "thunder_bgx"
22 #define DRV_VERSION "1.0"
23
24 /* RX_DMAC_CTL configuration */
25 enum MCAST_MODE {
26 MCAST_MODE_REJECT = 0x0,
27 MCAST_MODE_ACCEPT = 0x1,
28 MCAST_MODE_CAM_FILTER = 0x2,
29 RSVD = 0x3
30 };
31
32 #define BCAST_ACCEPT BIT(0)
33 #define CAM_ACCEPT BIT(3)
34 #define MCAST_MODE_MASK 0x3
35 #define BGX_MCAST_MODE(x) (x << 1)
36
37 struct dmac_map {
38 u64 vf_map;
39 u64 dmac;
40 };
41
42 struct lmac {
43 struct bgx *bgx;
44 /* actual number of DMACs configured */
45 u8 dmacs_cfg;
46 /* overal number of possible DMACs could be configured per LMAC */
47 u8 dmacs_count;
48 struct dmac_map *dmacs; /* DMAC:VFs tracking filter array */
49 u8 mac[ETH_ALEN];
50 u8 lmac_type;
51 u8 lane_to_sds;
52 bool use_training;
53 bool autoneg;
54 bool link_up;
55 int lmacid; /* ID within BGX */
56 int lmacid_bd; /* ID on board */
57 struct net_device netdev;
58 struct phy_device *phydev;
59 unsigned int last_duplex;
60 unsigned int last_link;
61 unsigned int last_speed;
62 bool is_sgmii;
63 struct delayed_work dwork;
64 struct workqueue_struct *check_link;
65 };
66
67 struct bgx {
68 u8 bgx_id;
69 struct lmac lmac[MAX_LMAC_PER_BGX];
70 u8 lmac_count;
71 u8 max_lmac;
72 u8 acpi_lmac_idx;
73 void __iomem *reg_base;
74 struct pci_dev *pdev;
75 bool is_dlm;
76 bool is_rgx;
77 };
78
79 static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
80 static int lmac_count; /* Total no of LMACs in system */
81
82 static int bgx_xaui_check_link(struct lmac *lmac);
83
84 /* Supported devices */
85 static const struct pci_device_id bgx_id_table[] = {
86 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
87 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) },
88 { 0, } /* end of table */
89 };
90
91 MODULE_AUTHOR("Cavium Inc");
92 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
93 MODULE_LICENSE("GPL v2");
94 MODULE_VERSION(DRV_VERSION);
95 MODULE_DEVICE_TABLE(pci, bgx_id_table);
96
97 /* The Cavium ThunderX network controller can *only* be found in SoCs
98 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
99 * registers on this platform are implicitly strongly ordered with respect
100 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
101 * with no memory barriers in this driver. The readq()/writeq() functions add
102 * explicit ordering operation which in this case are redundant, and only
103 * add overhead.
104 */
105
106 /* Register read/write APIs */
107 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
108 {
109 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
110
111 return readq_relaxed(addr);
112 }
113
114 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
115 {
116 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
117
118 writeq_relaxed(val, addr);
119 }
120
121 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
122 {
123 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
124
125 writeq_relaxed(val | readq_relaxed(addr), addr);
126 }
127
128 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
129 {
130 int timeout = 100;
131 u64 reg_val;
132
133 while (timeout) {
134 reg_val = bgx_reg_read(bgx, lmac, reg);
135 if (zero && !(reg_val & mask))
136 return 0;
137 if (!zero && (reg_val & mask))
138 return 0;
139 usleep_range(1000, 2000);
140 timeout--;
141 }
142 return 1;
143 }
144
145 static int max_bgx_per_node;
146 static void set_max_bgx_per_node(struct pci_dev *pdev)
147 {
148 u16 sdevid;
149
150 if (max_bgx_per_node)
151 return;
152
153 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
154 switch (sdevid) {
155 case PCI_SUBSYS_DEVID_81XX_BGX:
156 case PCI_SUBSYS_DEVID_81XX_RGX:
157 max_bgx_per_node = MAX_BGX_PER_CN81XX;
158 break;
159 case PCI_SUBSYS_DEVID_83XX_BGX:
160 max_bgx_per_node = MAX_BGX_PER_CN83XX;
161 break;
162 case PCI_SUBSYS_DEVID_88XX_BGX:
163 default:
164 max_bgx_per_node = MAX_BGX_PER_CN88XX;
165 break;
166 }
167 }
168
169 static struct bgx *get_bgx(int node, int bgx_idx)
170 {
171 int idx = (node * max_bgx_per_node) + bgx_idx;
172
173 return bgx_vnic[idx];
174 }
175
176 /* Return number of BGX present in HW */
177 unsigned bgx_get_map(int node)
178 {
179 int i;
180 unsigned map = 0;
181
182 for (i = 0; i < max_bgx_per_node; i++) {
183 if (bgx_vnic[(node * max_bgx_per_node) + i])
184 map |= (1 << i);
185 }
186
187 return map;
188 }
189 EXPORT_SYMBOL(bgx_get_map);
190
191 /* Return number of LMAC configured for this BGX */
192 int bgx_get_lmac_count(int node, int bgx_idx)
193 {
194 struct bgx *bgx;
195
196 bgx = get_bgx(node, bgx_idx);
197 if (bgx)
198 return bgx->lmac_count;
199
200 return 0;
201 }
202 EXPORT_SYMBOL(bgx_get_lmac_count);
203
204 /* Returns the current link status of LMAC */
205 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
206 {
207 struct bgx_link_status *link = (struct bgx_link_status *)status;
208 struct bgx *bgx;
209 struct lmac *lmac;
210
211 bgx = get_bgx(node, bgx_idx);
212 if (!bgx)
213 return;
214
215 lmac = &bgx->lmac[lmacid];
216 link->mac_type = lmac->lmac_type;
217 link->link_up = lmac->link_up;
218 link->duplex = lmac->last_duplex;
219 link->speed = lmac->last_speed;
220 }
221 EXPORT_SYMBOL(bgx_get_lmac_link_state);
222
223 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
224 {
225 struct bgx *bgx = get_bgx(node, bgx_idx);
226
227 if (bgx)
228 return bgx->lmac[lmacid].mac;
229
230 return NULL;
231 }
232 EXPORT_SYMBOL(bgx_get_lmac_mac);
233
234 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
235 {
236 struct bgx *bgx = get_bgx(node, bgx_idx);
237
238 if (!bgx)
239 return;
240
241 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
242 }
243 EXPORT_SYMBOL(bgx_set_lmac_mac);
244
245 static void bgx_flush_dmac_cam_filter(struct bgx *bgx, int lmacid)
246 {
247 struct lmac *lmac = NULL;
248 u8 idx = 0;
249
250 lmac = &bgx->lmac[lmacid];
251 /* reset CAM filters */
252 for (idx = 0; idx < lmac->dmacs_count; idx++)
253 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM +
254 ((lmacid * lmac->dmacs_count) + idx) *
255 sizeof(u64), 0);
256 }
257
258 static void bgx_lmac_remove_filters(struct lmac *lmac, u8 vf_id)
259 {
260 int i = 0;
261
262 if (!lmac)
263 return;
264
265 /* We've got reset filters request from some of attached VF, while the
266 * others might want to keep their configuration. So in this case lets
267 * iterate over all of configured filters and decrease number of
268 * referencies. if some addresses get zero refs remove them from list
269 */
270 for (i = lmac->dmacs_cfg - 1; i >= 0; i--) {
271 lmac->dmacs[i].vf_map &= ~BIT_ULL(vf_id);
272 if (!lmac->dmacs[i].vf_map) {
273 lmac->dmacs_cfg--;
274 lmac->dmacs[i].dmac = 0;
275 lmac->dmacs[i].vf_map = 0;
276 }
277 }
278 }
279
280 static int bgx_lmac_save_filter(struct lmac *lmac, u64 dmac, u8 vf_id)
281 {
282 u8 i = 0;
283
284 if (!lmac)
285 return -1;
286
287 /* At the same time we could have several VFs 'attached' to some
288 * particular LMAC, and each VF is represented as network interface
289 * for kernel. So from user perspective it should be possible to
290 * manipulate with its' (VF) receive modes. However from PF
291 * driver perspective we need to keep track of filter configurations
292 * for different VFs to prevent filter values dupes
293 */
294 for (i = 0; i < lmac->dmacs_cfg; i++) {
295 if (lmac->dmacs[i].dmac == dmac) {
296 lmac->dmacs[i].vf_map |= BIT_ULL(vf_id);
297 return -1;
298 }
299 }
300
301 if (!(lmac->dmacs_cfg < lmac->dmacs_count))
302 return -1;
303
304 /* keep it for further tracking */
305 lmac->dmacs[lmac->dmacs_cfg].dmac = dmac;
306 lmac->dmacs[lmac->dmacs_cfg].vf_map = BIT_ULL(vf_id);
307 lmac->dmacs_cfg++;
308 return 0;
309 }
310
311 static int bgx_set_dmac_cam_filter_mac(struct bgx *bgx, int lmacid,
312 u64 cam_dmac, u8 idx)
313 {
314 struct lmac *lmac = NULL;
315 u64 cfg = 0;
316
317 /* skip zero addresses as meaningless */
318 if (!cam_dmac || !bgx)
319 return -1;
320
321 lmac = &bgx->lmac[lmacid];
322
323 /* configure DCAM filtering for designated LMAC */
324 cfg = RX_DMACX_CAM_LMACID(lmacid & LMAC_ID_MASK) |
325 RX_DMACX_CAM_EN | cam_dmac;
326 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM +
327 ((lmacid * lmac->dmacs_count) + idx) * sizeof(u64), cfg);
328 return 0;
329 }
330
331 void bgx_set_dmac_cam_filter(int node, int bgx_idx, int lmacid,
332 u64 cam_dmac, u8 vf_id)
333 {
334 struct bgx *bgx = get_bgx(node, bgx_idx);
335 struct lmac *lmac = NULL;
336
337 if (!bgx)
338 return;
339
340 lmac = &bgx->lmac[lmacid];
341
342 if (!cam_dmac)
343 cam_dmac = ether_addr_to_u64(lmac->mac);
344
345 /* since we might have several VFs attached to particular LMAC
346 * and kernel could call mcast config for each of them with the
347 * same MAC, check if requested MAC is already in filtering list and
348 * updare/prepare list of MACs to be applied later to HW filters
349 */
350 bgx_lmac_save_filter(lmac, cam_dmac, vf_id);
351 }
352 EXPORT_SYMBOL(bgx_set_dmac_cam_filter);
353
354 void bgx_set_xcast_mode(int node, int bgx_idx, int lmacid, u8 mode)
355 {
356 struct bgx *bgx = get_bgx(node, bgx_idx);
357 struct lmac *lmac = NULL;
358 u64 cfg = 0;
359 u8 i = 0;
360
361 if (!bgx)
362 return;
363
364 lmac = &bgx->lmac[lmacid];
365
366 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL);
367 if (mode & BGX_XCAST_BCAST_ACCEPT)
368 cfg |= BCAST_ACCEPT;
369 else
370 cfg &= ~BCAST_ACCEPT;
371
372 /* disable all MCASTs and DMAC filtering */
373 cfg &= ~(CAM_ACCEPT | BGX_MCAST_MODE(MCAST_MODE_MASK));
374
375 /* check requested bits and set filtergin mode appropriately */
376 if (mode & (BGX_XCAST_MCAST_ACCEPT)) {
377 cfg |= (BGX_MCAST_MODE(MCAST_MODE_ACCEPT));
378 } else if (mode & BGX_XCAST_MCAST_FILTER) {
379 cfg |= (BGX_MCAST_MODE(MCAST_MODE_CAM_FILTER) | CAM_ACCEPT);
380 for (i = 0; i < lmac->dmacs_cfg; i++)
381 bgx_set_dmac_cam_filter_mac(bgx, lmacid,
382 lmac->dmacs[i].dmac, i);
383 }
384 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, cfg);
385 }
386 EXPORT_SYMBOL(bgx_set_xcast_mode);
387
388 void bgx_reset_xcast_mode(int node, int bgx_idx, int lmacid, u8 vf_id)
389 {
390 struct bgx *bgx = get_bgx(node, bgx_idx);
391
392 if (!bgx)
393 return;
394
395 bgx_lmac_remove_filters(&bgx->lmac[lmacid], vf_id);
396 bgx_flush_dmac_cam_filter(bgx, lmacid);
397 bgx_set_xcast_mode(node, bgx_idx, lmacid,
398 (BGX_XCAST_BCAST_ACCEPT | BGX_XCAST_MCAST_ACCEPT));
399 }
400 EXPORT_SYMBOL(bgx_reset_xcast_mode);
401
402 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
403 {
404 struct bgx *bgx = get_bgx(node, bgx_idx);
405 struct lmac *lmac;
406 u64 cfg;
407
408 if (!bgx)
409 return;
410 lmac = &bgx->lmac[lmacid];
411
412 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
413 if (enable)
414 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
415 else
416 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
417 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
418
419 if (bgx->is_rgx)
420 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed);
421 }
422 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
423
424 /* Enables or disables timestamp insertion by BGX for Rx packets */
425 void bgx_config_timestamping(int node, int bgx_idx, int lmacid, bool enable)
426 {
427 struct bgx *bgx = get_bgx(node, bgx_idx);
428 struct lmac *lmac;
429 u64 csr_offset, cfg;
430
431 if (!bgx)
432 return;
433
434 lmac = &bgx->lmac[lmacid];
435
436 if (lmac->lmac_type == BGX_MODE_SGMII ||
437 lmac->lmac_type == BGX_MODE_QSGMII ||
438 lmac->lmac_type == BGX_MODE_RGMII)
439 csr_offset = BGX_GMP_GMI_RXX_FRM_CTL;
440 else
441 csr_offset = BGX_SMUX_RX_FRM_CTL;
442
443 cfg = bgx_reg_read(bgx, lmacid, csr_offset);
444
445 if (enable)
446 cfg |= BGX_PKT_RX_PTP_EN;
447 else
448 cfg &= ~BGX_PKT_RX_PTP_EN;
449 bgx_reg_write(bgx, lmacid, csr_offset, cfg);
450 }
451 EXPORT_SYMBOL(bgx_config_timestamping);
452
453 void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause)
454 {
455 struct pfc *pfc = (struct pfc *)pause;
456 struct bgx *bgx = get_bgx(node, bgx_idx);
457 struct lmac *lmac;
458 u64 cfg;
459
460 if (!bgx)
461 return;
462 lmac = &bgx->lmac[lmacid];
463 if (lmac->is_sgmii)
464 return;
465
466 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
467 pfc->fc_rx = cfg & RX_EN;
468 pfc->fc_tx = cfg & TX_EN;
469 pfc->autoneg = 0;
470 }
471 EXPORT_SYMBOL(bgx_lmac_get_pfc);
472
473 void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause)
474 {
475 struct pfc *pfc = (struct pfc *)pause;
476 struct bgx *bgx = get_bgx(node, bgx_idx);
477 struct lmac *lmac;
478 u64 cfg;
479
480 if (!bgx)
481 return;
482 lmac = &bgx->lmac[lmacid];
483 if (lmac->is_sgmii)
484 return;
485
486 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
487 cfg &= ~(RX_EN | TX_EN);
488 cfg |= (pfc->fc_rx ? RX_EN : 0x00);
489 cfg |= (pfc->fc_tx ? TX_EN : 0x00);
490 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, cfg);
491 }
492 EXPORT_SYMBOL(bgx_lmac_set_pfc);
493
494 static void bgx_sgmii_change_link_state(struct lmac *lmac)
495 {
496 struct bgx *bgx = lmac->bgx;
497 u64 cmr_cfg;
498 u64 port_cfg = 0;
499 u64 misc_ctl = 0;
500 bool tx_en, rx_en;
501
502 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
503 tx_en = cmr_cfg & CMR_PKT_TX_EN;
504 rx_en = cmr_cfg & CMR_PKT_RX_EN;
505 cmr_cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
506 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
507
508 /* Wait for BGX RX to be idle */
509 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
510 GMI_PORT_CFG_RX_IDLE, false)) {
511 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI RX not idle\n",
512 bgx->bgx_id, lmac->lmacid);
513 return;
514 }
515
516 /* Wait for BGX TX to be idle */
517 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
518 GMI_PORT_CFG_TX_IDLE, false)) {
519 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI TX not idle\n",
520 bgx->bgx_id, lmac->lmacid);
521 return;
522 }
523
524 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
525 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
526
527 if (lmac->link_up) {
528 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
529 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
530 port_cfg |= (lmac->last_duplex << 2);
531 } else {
532 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
533 }
534
535 switch (lmac->last_speed) {
536 case 10:
537 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
538 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
539 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
540 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
541 misc_ctl |= 50; /* samp_pt */
542 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
543 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
544 break;
545 case 100:
546 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
547 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
548 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
549 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
550 misc_ctl |= 5; /* samp_pt */
551 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
552 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
553 break;
554 case 1000:
555 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
556 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
557 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
558 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
559 misc_ctl |= 1; /* samp_pt */
560 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
561 if (lmac->last_duplex)
562 bgx_reg_write(bgx, lmac->lmacid,
563 BGX_GMP_GMI_TXX_BURST, 0);
564 else
565 bgx_reg_write(bgx, lmac->lmacid,
566 BGX_GMP_GMI_TXX_BURST, 8192);
567 break;
568 default:
569 break;
570 }
571 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
572 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
573
574 /* Restore CMR config settings */
575 cmr_cfg |= (rx_en ? CMR_PKT_RX_EN : 0) | (tx_en ? CMR_PKT_TX_EN : 0);
576 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
577
578 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
579 xcv_setup_link(lmac->link_up, lmac->last_speed);
580 }
581
582 static void bgx_lmac_handler(struct net_device *netdev)
583 {
584 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
585 struct phy_device *phydev;
586 int link_changed = 0;
587
588 if (!lmac)
589 return;
590
591 phydev = lmac->phydev;
592
593 if (!phydev->link && lmac->last_link)
594 link_changed = -1;
595
596 if (phydev->link &&
597 (lmac->last_duplex != phydev->duplex ||
598 lmac->last_link != phydev->link ||
599 lmac->last_speed != phydev->speed)) {
600 link_changed = 1;
601 }
602
603 lmac->last_link = phydev->link;
604 lmac->last_speed = phydev->speed;
605 lmac->last_duplex = phydev->duplex;
606
607 if (!link_changed)
608 return;
609
610 if (link_changed > 0)
611 lmac->link_up = true;
612 else
613 lmac->link_up = false;
614
615 if (lmac->is_sgmii)
616 bgx_sgmii_change_link_state(lmac);
617 else
618 bgx_xaui_check_link(lmac);
619 }
620
621 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
622 {
623 struct bgx *bgx;
624
625 bgx = get_bgx(node, bgx_idx);
626 if (!bgx)
627 return 0;
628
629 if (idx > 8)
630 lmac = 0;
631 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
632 }
633 EXPORT_SYMBOL(bgx_get_rx_stats);
634
635 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
636 {
637 struct bgx *bgx;
638
639 bgx = get_bgx(node, bgx_idx);
640 if (!bgx)
641 return 0;
642
643 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
644 }
645 EXPORT_SYMBOL(bgx_get_tx_stats);
646
647 /* Configure BGX LMAC in internal loopback mode */
648 void bgx_lmac_internal_loopback(int node, int bgx_idx,
649 int lmac_idx, bool enable)
650 {
651 struct bgx *bgx;
652 struct lmac *lmac;
653 u64 cfg;
654
655 bgx = get_bgx(node, bgx_idx);
656 if (!bgx)
657 return;
658
659 lmac = &bgx->lmac[lmac_idx];
660 if (lmac->is_sgmii) {
661 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
662 if (enable)
663 cfg |= PCS_MRX_CTL_LOOPBACK1;
664 else
665 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
666 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
667 } else {
668 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
669 if (enable)
670 cfg |= SPU_CTL_LOOPBACK;
671 else
672 cfg &= ~SPU_CTL_LOOPBACK;
673 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
674 }
675 }
676 EXPORT_SYMBOL(bgx_lmac_internal_loopback);
677
678 static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
679 {
680 int lmacid = lmac->lmacid;
681 u64 cfg;
682
683 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
684 /* max packet size */
685 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
686
687 /* Disable frame alignment if using preamble */
688 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
689 if (cfg & 1)
690 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
691
692 /* Enable lmac */
693 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
694
695 /* PCS reset */
696 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
697 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
698 PCS_MRX_CTL_RESET, true)) {
699 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
700 return -1;
701 }
702
703 /* power down, reset autoneg, autoneg enable */
704 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
705 cfg &= ~PCS_MRX_CTL_PWR_DN;
706 cfg |= PCS_MRX_CTL_RST_AN;
707 if (lmac->phydev) {
708 cfg |= PCS_MRX_CTL_AN_EN;
709 } else {
710 /* In scenarios where PHY driver is not present or it's a
711 * non-standard PHY, FW sets AN_EN to inform Linux driver
712 * to do auto-neg and link polling or not.
713 */
714 if (cfg & PCS_MRX_CTL_AN_EN)
715 lmac->autoneg = true;
716 }
717 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
718
719 if (lmac->lmac_type == BGX_MODE_QSGMII) {
720 /* Disable disparity check for QSGMII */
721 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
722 cfg &= ~PCS_MISC_CTL_DISP_EN;
723 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
724 return 0;
725 }
726
727 if ((lmac->lmac_type == BGX_MODE_SGMII) && lmac->phydev) {
728 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
729 PCS_MRX_STATUS_AN_CPT, false)) {
730 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
731 return -1;
732 }
733 }
734
735 return 0;
736 }
737
738 static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
739 {
740 u64 cfg;
741 int lmacid = lmac->lmacid;
742
743 /* Reset SPU */
744 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
745 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
746 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
747 return -1;
748 }
749
750 /* Disable LMAC */
751 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
752 cfg &= ~CMR_EN;
753 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
754
755 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
756 /* Set interleaved running disparity for RXAUI */
757 if (lmac->lmac_type == BGX_MODE_RXAUI)
758 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
759 SPU_MISC_CTL_INTLV_RDISP);
760
761 /* Clear receive packet disable */
762 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
763 cfg &= ~SPU_MISC_CTL_RX_DIS;
764 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
765
766 /* clear all interrupts */
767 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
768 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
769 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
770 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
771 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
772 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
773
774 if (lmac->use_training) {
775 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
776 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
777 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
778 /* training enable */
779 bgx_reg_modify(bgx, lmacid,
780 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
781 }
782
783 /* Append FCS to each packet */
784 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
785
786 /* Disable forward error correction */
787 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
788 cfg &= ~SPU_FEC_CTL_FEC_EN;
789 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
790
791 /* Disable autoneg */
792 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
793 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
794 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
795
796 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
797 if (lmac->lmac_type == BGX_MODE_10G_KR)
798 cfg |= (1 << 23);
799 else if (lmac->lmac_type == BGX_MODE_40G_KR)
800 cfg |= (1 << 24);
801 else
802 cfg &= ~((1 << 23) | (1 << 24));
803 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
804 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
805
806 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
807 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
808 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
809
810 /* Enable lmac */
811 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
812
813 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
814 cfg &= ~SPU_CTL_LOW_POWER;
815 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
816
817 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
818 cfg &= ~SMU_TX_CTL_UNI_EN;
819 cfg |= SMU_TX_CTL_DIC_EN;
820 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
821
822 /* Enable receive and transmission of pause frames */
823 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, ((0xffffULL << 32) |
824 BCK_EN | DRP_EN | TX_EN | RX_EN));
825 /* Configure pause time and interval */
826 bgx_reg_write(bgx, lmacid,
827 BGX_SMUX_TX_PAUSE_PKT_TIME, DEFAULT_PAUSE_TIME);
828 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL);
829 cfg &= ~0xFFFFull;
830 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL,
831 cfg | (DEFAULT_PAUSE_TIME - 0x1000));
832 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_ZERO, 0x01);
833
834 /* take lmac_count into account */
835 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
836 /* max packet size */
837 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
838
839 return 0;
840 }
841
842 static int bgx_xaui_check_link(struct lmac *lmac)
843 {
844 struct bgx *bgx = lmac->bgx;
845 int lmacid = lmac->lmacid;
846 int lmac_type = lmac->lmac_type;
847 u64 cfg;
848
849 if (lmac->use_training) {
850 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
851 if (!(cfg & (1ull << 13))) {
852 cfg = (1ull << 13) | (1ull << 14);
853 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
854 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
855 cfg |= (1ull << 0);
856 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
857 return -1;
858 }
859 }
860
861 /* wait for PCS to come out of reset */
862 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
863 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
864 return -1;
865 }
866
867 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
868 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
869 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
870 SPU_BR_STATUS_BLK_LOCK, false)) {
871 dev_err(&bgx->pdev->dev,
872 "SPU_BR_STATUS_BLK_LOCK not completed\n");
873 return -1;
874 }
875 } else {
876 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
877 SPU_BX_STATUS_RX_ALIGN, false)) {
878 dev_err(&bgx->pdev->dev,
879 "SPU_BX_STATUS_RX_ALIGN not completed\n");
880 return -1;
881 }
882 }
883
884 /* Clear rcvflt bit (latching high) and read it back */
885 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
886 bgx_reg_modify(bgx, lmacid,
887 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
888 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
889 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
890 if (lmac->use_training) {
891 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
892 if (!(cfg & (1ull << 13))) {
893 cfg = (1ull << 13) | (1ull << 14);
894 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
895 cfg = bgx_reg_read(bgx, lmacid,
896 BGX_SPUX_BR_PMD_CRTL);
897 cfg |= (1ull << 0);
898 bgx_reg_write(bgx, lmacid,
899 BGX_SPUX_BR_PMD_CRTL, cfg);
900 return -1;
901 }
902 }
903 return -1;
904 }
905
906 /* Wait for BGX RX to be idle */
907 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
908 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
909 return -1;
910 }
911
912 /* Wait for BGX TX to be idle */
913 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
914 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
915 return -1;
916 }
917
918 /* Check for MAC RX faults */
919 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
920 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
921 cfg &= SMU_RX_CTL_STATUS;
922 if (!cfg)
923 return 0;
924
925 /* Rx local/remote fault seen.
926 * Do lmac reinit to see if condition recovers
927 */
928 bgx_lmac_xaui_init(bgx, lmac);
929
930 return -1;
931 }
932
933 static void bgx_poll_for_sgmii_link(struct lmac *lmac)
934 {
935 u64 pcs_link, an_result;
936 u8 speed;
937
938 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
939 BGX_GMP_PCS_MRX_STATUS);
940
941 /*Link state bit is sticky, read it again*/
942 if (!(pcs_link & PCS_MRX_STATUS_LINK))
943 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
944 BGX_GMP_PCS_MRX_STATUS);
945
946 if (bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_GMP_PCS_MRX_STATUS,
947 PCS_MRX_STATUS_AN_CPT, false)) {
948 lmac->link_up = false;
949 lmac->last_speed = SPEED_UNKNOWN;
950 lmac->last_duplex = DUPLEX_UNKNOWN;
951 goto next_poll;
952 }
953
954 lmac->link_up = ((pcs_link & PCS_MRX_STATUS_LINK) != 0) ? true : false;
955 an_result = bgx_reg_read(lmac->bgx, lmac->lmacid,
956 BGX_GMP_PCS_ANX_AN_RESULTS);
957
958 speed = (an_result >> 3) & 0x3;
959 lmac->last_duplex = (an_result >> 1) & 0x1;
960 switch (speed) {
961 case 0:
962 lmac->last_speed = SPEED_10;
963 break;
964 case 1:
965 lmac->last_speed = SPEED_100;
966 break;
967 case 2:
968 lmac->last_speed = SPEED_1000;
969 break;
970 default:
971 lmac->link_up = false;
972 lmac->last_speed = SPEED_UNKNOWN;
973 lmac->last_duplex = DUPLEX_UNKNOWN;
974 break;
975 }
976
977 next_poll:
978
979 if (lmac->last_link != lmac->link_up) {
980 if (lmac->link_up)
981 bgx_sgmii_change_link_state(lmac);
982 lmac->last_link = lmac->link_up;
983 }
984
985 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 3);
986 }
987
988 static void bgx_poll_for_link(struct work_struct *work)
989 {
990 struct lmac *lmac;
991 u64 spu_link, smu_link;
992
993 lmac = container_of(work, struct lmac, dwork.work);
994 if (lmac->is_sgmii) {
995 bgx_poll_for_sgmii_link(lmac);
996 return;
997 }
998
999 /* Receive link is latching low. Force it high and verify it */
1000 bgx_reg_modify(lmac->bgx, lmac->lmacid,
1001 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
1002 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
1003 SPU_STATUS1_RCV_LNK, false);
1004
1005 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
1006 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
1007
1008 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
1009 !(smu_link & SMU_RX_CTL_STATUS)) {
1010 lmac->link_up = 1;
1011 if (lmac->lmac_type == BGX_MODE_XLAUI)
1012 lmac->last_speed = SPEED_40000;
1013 else
1014 lmac->last_speed = SPEED_10000;
1015 lmac->last_duplex = DUPLEX_FULL;
1016 } else {
1017 lmac->link_up = 0;
1018 lmac->last_speed = SPEED_UNKNOWN;
1019 lmac->last_duplex = DUPLEX_UNKNOWN;
1020 }
1021
1022 if (lmac->last_link != lmac->link_up) {
1023 if (lmac->link_up) {
1024 if (bgx_xaui_check_link(lmac)) {
1025 /* Errors, clear link_up state */
1026 lmac->link_up = 0;
1027 lmac->last_speed = SPEED_UNKNOWN;
1028 lmac->last_duplex = DUPLEX_UNKNOWN;
1029 }
1030 }
1031 lmac->last_link = lmac->link_up;
1032 }
1033
1034 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
1035 }
1036
1037 static int phy_interface_mode(u8 lmac_type)
1038 {
1039 if (lmac_type == BGX_MODE_QSGMII)
1040 return PHY_INTERFACE_MODE_QSGMII;
1041 if (lmac_type == BGX_MODE_RGMII)
1042 return PHY_INTERFACE_MODE_RGMII;
1043
1044 return PHY_INTERFACE_MODE_SGMII;
1045 }
1046
1047 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
1048 {
1049 struct lmac *lmac;
1050 u64 cfg;
1051
1052 lmac = &bgx->lmac[lmacid];
1053 lmac->bgx = bgx;
1054
1055 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
1056 (lmac->lmac_type == BGX_MODE_QSGMII) ||
1057 (lmac->lmac_type == BGX_MODE_RGMII)) {
1058 lmac->is_sgmii = 1;
1059 if (bgx_lmac_sgmii_init(bgx, lmac))
1060 return -1;
1061 } else {
1062 lmac->is_sgmii = 0;
1063 if (bgx_lmac_xaui_init(bgx, lmac))
1064 return -1;
1065 }
1066
1067 if (lmac->is_sgmii) {
1068 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
1069 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
1070 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
1071 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
1072 } else {
1073 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
1074 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
1075 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
1076 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
1077 }
1078
1079 /* actual number of filters available to exact LMAC */
1080 lmac->dmacs_count = (RX_DMAC_COUNT / bgx->lmac_count);
1081 lmac->dmacs = kcalloc(lmac->dmacs_count, sizeof(*lmac->dmacs),
1082 GFP_KERNEL);
1083 if (!lmac->dmacs)
1084 return -ENOMEM;
1085
1086 /* Enable lmac */
1087 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
1088
1089 /* Restore default cfg, incase low level firmware changed it */
1090 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
1091
1092 if ((lmac->lmac_type != BGX_MODE_XFI) &&
1093 (lmac->lmac_type != BGX_MODE_XLAUI) &&
1094 (lmac->lmac_type != BGX_MODE_40G_KR) &&
1095 (lmac->lmac_type != BGX_MODE_10G_KR)) {
1096 if (!lmac->phydev) {
1097 if (lmac->autoneg) {
1098 bgx_reg_write(bgx, lmacid,
1099 BGX_GMP_PCS_LINKX_TIMER,
1100 PCS_LINKX_TIMER_COUNT);
1101 goto poll;
1102 } else {
1103 /* Default to below link speed and duplex */
1104 lmac->link_up = true;
1105 lmac->last_speed = SPEED_1000;
1106 lmac->last_duplex = DUPLEX_FULL;
1107 bgx_sgmii_change_link_state(lmac);
1108 return 0;
1109 }
1110 }
1111 lmac->phydev->dev_flags = 0;
1112
1113 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
1114 bgx_lmac_handler,
1115 phy_interface_mode(lmac->lmac_type)))
1116 return -ENODEV;
1117
1118 phy_start_aneg(lmac->phydev);
1119 return 0;
1120 }
1121
1122 poll:
1123 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
1124 WQ_MEM_RECLAIM, 1);
1125 if (!lmac->check_link)
1126 return -ENOMEM;
1127 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
1128 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
1129
1130 return 0;
1131 }
1132
1133 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
1134 {
1135 struct lmac *lmac;
1136 u64 cfg;
1137
1138 lmac = &bgx->lmac[lmacid];
1139 if (lmac->check_link) {
1140 /* Destroy work queue */
1141 cancel_delayed_work_sync(&lmac->dwork);
1142 destroy_workqueue(lmac->check_link);
1143 }
1144
1145 /* Disable packet reception */
1146 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1147 cfg &= ~CMR_PKT_RX_EN;
1148 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1149
1150 /* Give chance for Rx/Tx FIFO to get drained */
1151 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
1152 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
1153
1154 /* Disable packet transmission */
1155 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1156 cfg &= ~CMR_PKT_TX_EN;
1157 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1158
1159 /* Disable serdes lanes */
1160 if (!lmac->is_sgmii)
1161 bgx_reg_modify(bgx, lmacid,
1162 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
1163 else
1164 bgx_reg_modify(bgx, lmacid,
1165 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
1166
1167 /* Disable LMAC */
1168 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1169 cfg &= ~CMR_EN;
1170 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1171
1172 bgx_flush_dmac_cam_filter(bgx, lmacid);
1173 kfree(lmac->dmacs);
1174
1175 if ((lmac->lmac_type != BGX_MODE_XFI) &&
1176 (lmac->lmac_type != BGX_MODE_XLAUI) &&
1177 (lmac->lmac_type != BGX_MODE_40G_KR) &&
1178 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
1179 phy_disconnect(lmac->phydev);
1180
1181 lmac->phydev = NULL;
1182 }
1183
1184 static void bgx_init_hw(struct bgx *bgx)
1185 {
1186 int i;
1187 struct lmac *lmac;
1188
1189 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
1190 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
1191 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
1192
1193 /* Set lmac type and lane2serdes mapping */
1194 for (i = 0; i < bgx->lmac_count; i++) {
1195 lmac = &bgx->lmac[i];
1196 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
1197 (lmac->lmac_type << 8) | lmac->lane_to_sds);
1198 bgx->lmac[i].lmacid_bd = lmac_count;
1199 lmac_count++;
1200 }
1201
1202 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
1203 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
1204
1205 /* Set the backpressure AND mask */
1206 for (i = 0; i < bgx->lmac_count; i++)
1207 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
1208 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
1209 (i * MAX_BGX_CHANS_PER_LMAC));
1210
1211 /* Disable all MAC filtering */
1212 for (i = 0; i < RX_DMAC_COUNT; i++)
1213 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
1214
1215 /* Disable MAC steering (NCSI traffic) */
1216 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
1217 bgx_reg_write(bgx, 0, BGX_CMR_RX_STEERING + (i * 8), 0x00);
1218 }
1219
1220 static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
1221 {
1222 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
1223 }
1224
1225 static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
1226 {
1227 struct device *dev = &bgx->pdev->dev;
1228 struct lmac *lmac;
1229 char str[27];
1230
1231 if (!bgx->is_dlm && lmacid)
1232 return;
1233
1234 lmac = &bgx->lmac[lmacid];
1235 if (!bgx->is_dlm)
1236 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
1237 else
1238 sprintf(str, "BGX%d LMAC%d mode", bgx->bgx_id, lmacid);
1239
1240 switch (lmac->lmac_type) {
1241 case BGX_MODE_SGMII:
1242 dev_info(dev, "%s: SGMII\n", (char *)str);
1243 break;
1244 case BGX_MODE_XAUI:
1245 dev_info(dev, "%s: XAUI\n", (char *)str);
1246 break;
1247 case BGX_MODE_RXAUI:
1248 dev_info(dev, "%s: RXAUI\n", (char *)str);
1249 break;
1250 case BGX_MODE_XFI:
1251 if (!lmac->use_training)
1252 dev_info(dev, "%s: XFI\n", (char *)str);
1253 else
1254 dev_info(dev, "%s: 10G_KR\n", (char *)str);
1255 break;
1256 case BGX_MODE_XLAUI:
1257 if (!lmac->use_training)
1258 dev_info(dev, "%s: XLAUI\n", (char *)str);
1259 else
1260 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
1261 break;
1262 case BGX_MODE_QSGMII:
1263 dev_info(dev, "%s: QSGMII\n", (char *)str);
1264 break;
1265 case BGX_MODE_RGMII:
1266 dev_info(dev, "%s: RGMII\n", (char *)str);
1267 break;
1268 case BGX_MODE_INVALID:
1269 /* Nothing to do */
1270 break;
1271 }
1272 }
1273
1274 static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
1275 {
1276 switch (lmac->lmac_type) {
1277 case BGX_MODE_SGMII:
1278 case BGX_MODE_XFI:
1279 lmac->lane_to_sds = lmac->lmacid;
1280 break;
1281 case BGX_MODE_XAUI:
1282 case BGX_MODE_XLAUI:
1283 case BGX_MODE_RGMII:
1284 lmac->lane_to_sds = 0xE4;
1285 break;
1286 case BGX_MODE_RXAUI:
1287 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
1288 break;
1289 case BGX_MODE_QSGMII:
1290 /* There is no way to determine if DLM0/2 is QSGMII or
1291 * DLM1/3 is configured to QSGMII as bootloader will
1292 * configure all LMACs, so take whatever is configured
1293 * by low level firmware.
1294 */
1295 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
1296 break;
1297 default:
1298 lmac->lane_to_sds = 0;
1299 break;
1300 }
1301 }
1302
1303 static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid)
1304 {
1305 if ((lmac->lmac_type != BGX_MODE_10G_KR) &&
1306 (lmac->lmac_type != BGX_MODE_40G_KR)) {
1307 lmac->use_training = 0;
1308 return;
1309 }
1310
1311 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) &
1312 SPU_PMD_CRTL_TRAIN_EN;
1313 }
1314
1315 static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
1316 {
1317 struct lmac *lmac;
1318 u64 cmr_cfg;
1319 u8 lmac_type;
1320 u8 lane_to_sds;
1321
1322 lmac = &bgx->lmac[idx];
1323
1324 if (!bgx->is_dlm || bgx->is_rgx) {
1325 /* Read LMAC0 type to figure out QLM mode
1326 * This is configured by low level firmware
1327 */
1328 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
1329 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
1330 if (bgx->is_rgx)
1331 lmac->lmac_type = BGX_MODE_RGMII;
1332 lmac_set_training(bgx, lmac, 0);
1333 lmac_set_lane2sds(bgx, lmac);
1334 return;
1335 }
1336
1337 /* For DLMs or SLMs on 80/81/83xx so many lane configurations
1338 * are possible and vary across boards. Also Kernel doesn't have
1339 * any way to identify board type/info and since firmware does,
1340 * just take lmac type and serdes lane config as is.
1341 */
1342 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
1343 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
1344 lane_to_sds = (u8)(cmr_cfg & 0xFF);
1345 /* Check if config is reset value */
1346 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
1347 lmac->lmac_type = BGX_MODE_INVALID;
1348 else
1349 lmac->lmac_type = lmac_type;
1350 lmac->lane_to_sds = lane_to_sds;
1351 lmac_set_training(bgx, lmac, lmac->lmacid);
1352 }
1353
1354 static void bgx_get_qlm_mode(struct bgx *bgx)
1355 {
1356 struct lmac *lmac;
1357 u8 idx;
1358
1359 /* Init all LMAC's type to invalid */
1360 for (idx = 0; idx < bgx->max_lmac; idx++) {
1361 lmac = &bgx->lmac[idx];
1362 lmac->lmacid = idx;
1363 lmac->lmac_type = BGX_MODE_INVALID;
1364 lmac->use_training = false;
1365 }
1366
1367 /* It is assumed that low level firmware sets this value */
1368 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
1369 if (bgx->lmac_count > bgx->max_lmac)
1370 bgx->lmac_count = bgx->max_lmac;
1371
1372 for (idx = 0; idx < bgx->lmac_count; idx++) {
1373 bgx_set_lmac_config(bgx, idx);
1374 bgx_print_qlm_mode(bgx, idx);
1375 }
1376 }
1377
1378 #ifdef CONFIG_ACPI
1379
1380 static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1381 u8 *dst)
1382 {
1383 u8 mac[ETH_ALEN];
1384 u8 *addr;
1385
1386 addr = fwnode_get_mac_address(acpi_fwnode_handle(adev), mac, ETH_ALEN);
1387 if (!addr) {
1388 dev_err(dev, "MAC address invalid: %pM\n", mac);
1389 return -EINVAL;
1390 }
1391
1392 dev_info(dev, "MAC address set to: %pM\n", mac);
1393
1394 ether_addr_copy(dst, mac);
1395 return 0;
1396 }
1397
1398 /* Currently only sets the MAC address. */
1399 static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1400 u32 lvl, void *context, void **rv)
1401 {
1402 struct bgx *bgx = context;
1403 struct device *dev = &bgx->pdev->dev;
1404 struct acpi_device *adev;
1405
1406 if (acpi_bus_get_device(handle, &adev))
1407 goto out;
1408
1409 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->acpi_lmac_idx].mac);
1410
1411 SET_NETDEV_DEV(&bgx->lmac[bgx->acpi_lmac_idx].netdev, dev);
1412
1413 bgx->lmac[bgx->acpi_lmac_idx].lmacid = bgx->acpi_lmac_idx;
1414 bgx->acpi_lmac_idx++; /* move to next LMAC */
1415 out:
1416 return AE_OK;
1417 }
1418
1419 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1420 void *context, void **ret_val)
1421 {
1422 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1423 struct bgx *bgx = context;
1424 char bgx_sel[5];
1425
1426 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1427 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1428 pr_warn("Invalid link device\n");
1429 return AE_OK;
1430 }
1431
1432 if (strncmp(string.pointer, bgx_sel, 4))
1433 return AE_OK;
1434
1435 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1436 bgx_acpi_register_phy, NULL, bgx, NULL);
1437
1438 kfree(string.pointer);
1439 return AE_CTRL_TERMINATE;
1440 }
1441
1442 static int bgx_init_acpi_phy(struct bgx *bgx)
1443 {
1444 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1445 return 0;
1446 }
1447
1448 #else
1449
1450 static int bgx_init_acpi_phy(struct bgx *bgx)
1451 {
1452 return -ENODEV;
1453 }
1454
1455 #endif /* CONFIG_ACPI */
1456
1457 #if IS_ENABLED(CONFIG_OF_MDIO)
1458
1459 static int bgx_init_of_phy(struct bgx *bgx)
1460 {
1461 struct fwnode_handle *fwn;
1462 struct device_node *node = NULL;
1463 u8 lmac = 0;
1464
1465 device_for_each_child_node(&bgx->pdev->dev, fwn) {
1466 struct phy_device *pd;
1467 struct device_node *phy_np;
1468 const char *mac;
1469
1470 /* Should always be an OF node. But if it is not, we
1471 * cannot handle it, so exit the loop.
1472 */
1473 node = to_of_node(fwn);
1474 if (!node)
1475 break;
1476
1477 mac = of_get_mac_address(node);
1478 if (!IS_ERR(mac))
1479 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1480
1481 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1482 bgx->lmac[lmac].lmacid = lmac;
1483
1484 phy_np = of_parse_phandle(node, "phy-handle", 0);
1485 /* If there is no phy or defective firmware presents
1486 * this cortina phy, for which there is no driver
1487 * support, ignore it.
1488 */
1489 if (phy_np &&
1490 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1491 /* Wait until the phy drivers are available */
1492 pd = of_phy_find_device(phy_np);
1493 if (!pd)
1494 goto defer;
1495 bgx->lmac[lmac].phydev = pd;
1496 }
1497
1498 lmac++;
1499 if (lmac == bgx->max_lmac) {
1500 of_node_put(node);
1501 break;
1502 }
1503 }
1504 return 0;
1505
1506 defer:
1507 /* We are bailing out, try not to leak device reference counts
1508 * for phy devices we may have already found.
1509 */
1510 while (lmac) {
1511 if (bgx->lmac[lmac].phydev) {
1512 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1513 bgx->lmac[lmac].phydev = NULL;
1514 }
1515 lmac--;
1516 }
1517 of_node_put(node);
1518 return -EPROBE_DEFER;
1519 }
1520
1521 #else
1522
1523 static int bgx_init_of_phy(struct bgx *bgx)
1524 {
1525 return -ENODEV;
1526 }
1527
1528 #endif /* CONFIG_OF_MDIO */
1529
1530 static int bgx_init_phy(struct bgx *bgx)
1531 {
1532 if (!acpi_disabled)
1533 return bgx_init_acpi_phy(bgx);
1534
1535 return bgx_init_of_phy(bgx);
1536 }
1537
1538 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1539 {
1540 int err;
1541 struct device *dev = &pdev->dev;
1542 struct bgx *bgx = NULL;
1543 u8 lmac;
1544 u16 sdevid;
1545
1546 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1547 if (!bgx)
1548 return -ENOMEM;
1549 bgx->pdev = pdev;
1550
1551 pci_set_drvdata(pdev, bgx);
1552
1553 err = pci_enable_device(pdev);
1554 if (err) {
1555 dev_err(dev, "Failed to enable PCI device\n");
1556 pci_set_drvdata(pdev, NULL);
1557 return err;
1558 }
1559
1560 err = pci_request_regions(pdev, DRV_NAME);
1561 if (err) {
1562 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1563 goto err_disable_device;
1564 }
1565
1566 /* MAP configuration registers */
1567 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1568 if (!bgx->reg_base) {
1569 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1570 err = -ENOMEM;
1571 goto err_release_regions;
1572 }
1573
1574 set_max_bgx_per_node(pdev);
1575
1576 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1577 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
1578 bgx->bgx_id = (pci_resource_start(pdev,
1579 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
1580 bgx->bgx_id += nic_get_node_id(pdev) * max_bgx_per_node;
1581 bgx->max_lmac = MAX_LMAC_PER_BGX;
1582 bgx_vnic[bgx->bgx_id] = bgx;
1583 } else {
1584 bgx->is_rgx = true;
1585 bgx->max_lmac = 1;
1586 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1;
1587 bgx_vnic[bgx->bgx_id] = bgx;
1588 xcv_init_hw();
1589 }
1590
1591 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1592 * BGX i.e BGX2 can be split across 2 DLMs.
1593 */
1594 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1595 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) ||
1596 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2)))
1597 bgx->is_dlm = true;
1598
1599 bgx_get_qlm_mode(bgx);
1600
1601 err = bgx_init_phy(bgx);
1602 if (err)
1603 goto err_enable;
1604
1605 bgx_init_hw(bgx);
1606
1607 /* Enable all LMACs */
1608 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1609 err = bgx_lmac_enable(bgx, lmac);
1610 if (err) {
1611 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1612 bgx->bgx_id, lmac);
1613 while (lmac)
1614 bgx_lmac_disable(bgx, --lmac);
1615 goto err_enable;
1616 }
1617 }
1618
1619 return 0;
1620
1621 err_enable:
1622 bgx_vnic[bgx->bgx_id] = NULL;
1623 err_release_regions:
1624 pci_release_regions(pdev);
1625 err_disable_device:
1626 pci_disable_device(pdev);
1627 pci_set_drvdata(pdev, NULL);
1628 return err;
1629 }
1630
1631 static void bgx_remove(struct pci_dev *pdev)
1632 {
1633 struct bgx *bgx = pci_get_drvdata(pdev);
1634 u8 lmac;
1635
1636 /* Disable all LMACs */
1637 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1638 bgx_lmac_disable(bgx, lmac);
1639
1640 bgx_vnic[bgx->bgx_id] = NULL;
1641 pci_release_regions(pdev);
1642 pci_disable_device(pdev);
1643 pci_set_drvdata(pdev, NULL);
1644 }
1645
1646 static struct pci_driver bgx_driver = {
1647 .name = DRV_NAME,
1648 .id_table = bgx_id_table,
1649 .probe = bgx_probe,
1650 .remove = bgx_remove,
1651 };
1652
1653 static int __init bgx_init_module(void)
1654 {
1655 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1656
1657 return pci_register_driver(&bgx_driver);
1658 }
1659
1660 static void __exit bgx_cleanup_module(void)
1661 {
1662 pci_unregister_driver(&bgx_driver);
1663 }
1664
1665 module_init(bgx_init_module);
1666 module_exit(bgx_cleanup_module);
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