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gpu: host1x: Use SMMU on Tegra124 and Tegra210
[thirdparty/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cudbg_lib.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2017 Chelsio Communications. All rights reserved.
4 */
5
6 #include <linux/sort.h>
7 #include <linux/string.h>
8
9 #include "t4_regs.h"
10 #include "cxgb4.h"
11 #include "cxgb4_cudbg.h"
12 #include "cudbg_if.h"
13 #include "cudbg_lib_common.h"
14 #include "cudbg_entity.h"
15 #include "cudbg_lib.h"
16 #include "cudbg_zlib.h"
17
18 static int cudbg_do_compression(struct cudbg_init *pdbg_init,
19 struct cudbg_buffer *pin_buff,
20 struct cudbg_buffer *dbg_buff)
21 {
22 struct cudbg_buffer temp_in_buff = { 0 };
23 int bytes_left, bytes_read, bytes;
24 u32 offset = dbg_buff->offset;
25 int rc;
26
27 temp_in_buff.offset = pin_buff->offset;
28 temp_in_buff.data = pin_buff->data;
29 temp_in_buff.size = pin_buff->size;
30
31 bytes_left = pin_buff->size;
32 bytes_read = 0;
33 while (bytes_left > 0) {
34 /* Do compression in smaller chunks */
35 bytes = min_t(unsigned long, bytes_left,
36 (unsigned long)CUDBG_CHUNK_SIZE);
37 temp_in_buff.data = (char *)pin_buff->data + bytes_read;
38 temp_in_buff.size = bytes;
39 rc = cudbg_compress_buff(pdbg_init, &temp_in_buff, dbg_buff);
40 if (rc)
41 return rc;
42 bytes_left -= bytes;
43 bytes_read += bytes;
44 }
45
46 pin_buff->size = dbg_buff->offset - offset;
47 return 0;
48 }
49
50 static int cudbg_write_and_release_buff(struct cudbg_init *pdbg_init,
51 struct cudbg_buffer *pin_buff,
52 struct cudbg_buffer *dbg_buff)
53 {
54 int rc = 0;
55
56 if (pdbg_init->compress_type == CUDBG_COMPRESSION_NONE) {
57 cudbg_update_buff(pin_buff, dbg_buff);
58 } else {
59 rc = cudbg_do_compression(pdbg_init, pin_buff, dbg_buff);
60 if (rc)
61 goto out;
62 }
63
64 out:
65 cudbg_put_buff(pdbg_init, pin_buff);
66 return rc;
67 }
68
69 static int is_fw_attached(struct cudbg_init *pdbg_init)
70 {
71 struct adapter *padap = pdbg_init->adap;
72
73 if (!(padap->flags & CXGB4_FW_OK) || padap->use_bd)
74 return 0;
75
76 return 1;
77 }
78
79 /* This function will add additional padding bytes into debug_buffer to make it
80 * 4 byte aligned.
81 */
82 void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff,
83 struct cudbg_entity_hdr *entity_hdr)
84 {
85 u8 zero_buf[4] = {0};
86 u8 padding, remain;
87
88 remain = (dbg_buff->offset - entity_hdr->start_offset) % 4;
89 padding = 4 - remain;
90 if (remain) {
91 memcpy(((u8 *)dbg_buff->data) + dbg_buff->offset, &zero_buf,
92 padding);
93 dbg_buff->offset += padding;
94 entity_hdr->num_pad = padding;
95 }
96 entity_hdr->size = dbg_buff->offset - entity_hdr->start_offset;
97 }
98
99 struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i)
100 {
101 struct cudbg_hdr *cudbg_hdr = (struct cudbg_hdr *)outbuf;
102
103 return (struct cudbg_entity_hdr *)
104 ((char *)outbuf + cudbg_hdr->hdr_len +
105 (sizeof(struct cudbg_entity_hdr) * (i - 1)));
106 }
107
108 static int cudbg_read_vpd_reg(struct adapter *padap, u32 addr, u32 len,
109 void *dest)
110 {
111 int vaddr, rc;
112
113 vaddr = t4_eeprom_ptov(addr, padap->pf, EEPROMPFSIZE);
114 if (vaddr < 0)
115 return vaddr;
116
117 rc = pci_read_vpd(padap->pdev, vaddr, len, dest);
118 if (rc < 0)
119 return rc;
120
121 return 0;
122 }
123
124 static int cudbg_mem_desc_cmp(const void *a, const void *b)
125 {
126 return ((const struct cudbg_mem_desc *)a)->base -
127 ((const struct cudbg_mem_desc *)b)->base;
128 }
129
130 int cudbg_fill_meminfo(struct adapter *padap,
131 struct cudbg_meminfo *meminfo_buff)
132 {
133 struct cudbg_mem_desc *md;
134 u32 lo, hi, used, alloc;
135 int n, i;
136
137 memset(meminfo_buff->avail, 0,
138 ARRAY_SIZE(meminfo_buff->avail) *
139 sizeof(struct cudbg_mem_desc));
140 memset(meminfo_buff->mem, 0,
141 (ARRAY_SIZE(cudbg_region) + 3) * sizeof(struct cudbg_mem_desc));
142 md = meminfo_buff->mem;
143
144 for (i = 0; i < ARRAY_SIZE(meminfo_buff->mem); i++) {
145 meminfo_buff->mem[i].limit = 0;
146 meminfo_buff->mem[i].idx = i;
147 }
148
149 /* Find and sort the populated memory ranges */
150 i = 0;
151 lo = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A);
152 if (lo & EDRAM0_ENABLE_F) {
153 hi = t4_read_reg(padap, MA_EDRAM0_BAR_A);
154 meminfo_buff->avail[i].base =
155 cudbg_mbytes_to_bytes(EDRAM0_BASE_G(hi));
156 meminfo_buff->avail[i].limit =
157 meminfo_buff->avail[i].base +
158 cudbg_mbytes_to_bytes(EDRAM0_SIZE_G(hi));
159 meminfo_buff->avail[i].idx = 0;
160 i++;
161 }
162
163 if (lo & EDRAM1_ENABLE_F) {
164 hi = t4_read_reg(padap, MA_EDRAM1_BAR_A);
165 meminfo_buff->avail[i].base =
166 cudbg_mbytes_to_bytes(EDRAM1_BASE_G(hi));
167 meminfo_buff->avail[i].limit =
168 meminfo_buff->avail[i].base +
169 cudbg_mbytes_to_bytes(EDRAM1_SIZE_G(hi));
170 meminfo_buff->avail[i].idx = 1;
171 i++;
172 }
173
174 if (is_t5(padap->params.chip)) {
175 if (lo & EXT_MEM0_ENABLE_F) {
176 hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A);
177 meminfo_buff->avail[i].base =
178 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
179 meminfo_buff->avail[i].limit =
180 meminfo_buff->avail[i].base +
181 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
182 meminfo_buff->avail[i].idx = 3;
183 i++;
184 }
185
186 if (lo & EXT_MEM1_ENABLE_F) {
187 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
188 meminfo_buff->avail[i].base =
189 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
190 meminfo_buff->avail[i].limit =
191 meminfo_buff->avail[i].base +
192 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
193 meminfo_buff->avail[i].idx = 4;
194 i++;
195 }
196 } else {
197 if (lo & EXT_MEM_ENABLE_F) {
198 hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A);
199 meminfo_buff->avail[i].base =
200 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
201 meminfo_buff->avail[i].limit =
202 meminfo_buff->avail[i].base +
203 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
204 meminfo_buff->avail[i].idx = 2;
205 i++;
206 }
207
208 if (lo & HMA_MUX_F) {
209 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
210 meminfo_buff->avail[i].base =
211 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
212 meminfo_buff->avail[i].limit =
213 meminfo_buff->avail[i].base +
214 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
215 meminfo_buff->avail[i].idx = 5;
216 i++;
217 }
218 }
219
220 if (!i) /* no memory available */
221 return CUDBG_STATUS_ENTITY_NOT_FOUND;
222
223 meminfo_buff->avail_c = i;
224 sort(meminfo_buff->avail, i, sizeof(struct cudbg_mem_desc),
225 cudbg_mem_desc_cmp, NULL);
226 (md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A);
227 (md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A);
228 (md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A);
229 (md++)->base = t4_read_reg(padap, TP_CMM_TCB_BASE_A);
230 (md++)->base = t4_read_reg(padap, TP_CMM_MM_BASE_A);
231 (md++)->base = t4_read_reg(padap, TP_CMM_TIMER_BASE_A);
232 (md++)->base = t4_read_reg(padap, TP_CMM_MM_RX_FLST_BASE_A);
233 (md++)->base = t4_read_reg(padap, TP_CMM_MM_TX_FLST_BASE_A);
234 (md++)->base = t4_read_reg(padap, TP_CMM_MM_PS_FLST_BASE_A);
235
236 /* the next few have explicit upper bounds */
237 md->base = t4_read_reg(padap, TP_PMM_TX_BASE_A);
238 md->limit = md->base - 1 +
239 t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A) *
240 PMTXMAXPAGE_G(t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A));
241 md++;
242
243 md->base = t4_read_reg(padap, TP_PMM_RX_BASE_A);
244 md->limit = md->base - 1 +
245 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) *
246 PMRXMAXPAGE_G(t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A));
247 md++;
248
249 if (t4_read_reg(padap, LE_DB_CONFIG_A) & HASHEN_F) {
250 if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) {
251 hi = t4_read_reg(padap, LE_DB_TID_HASHBASE_A) / 4;
252 md->base = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
253 } else {
254 hi = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
255 md->base = t4_read_reg(padap,
256 LE_DB_HASH_TBL_BASE_ADDR_A);
257 }
258 md->limit = 0;
259 } else {
260 md->base = 0;
261 md->idx = ARRAY_SIZE(cudbg_region); /* hide it */
262 }
263 md++;
264
265 #define ulp_region(reg) do { \
266 md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\
267 (md++)->limit = t4_read_reg(padap, ULP_ ## reg ## _ULIMIT_A);\
268 } while (0)
269
270 ulp_region(RX_ISCSI);
271 ulp_region(RX_TDDP);
272 ulp_region(TX_TPT);
273 ulp_region(RX_STAG);
274 ulp_region(RX_RQ);
275 ulp_region(RX_RQUDP);
276 ulp_region(RX_PBL);
277 ulp_region(TX_PBL);
278 #undef ulp_region
279 md->base = 0;
280 md->idx = ARRAY_SIZE(cudbg_region);
281 if (!is_t4(padap->params.chip)) {
282 u32 fifo_size = t4_read_reg(padap, SGE_DBVFIFO_SIZE_A);
283 u32 sge_ctrl = t4_read_reg(padap, SGE_CONTROL2_A);
284 u32 size = 0;
285
286 if (is_t5(padap->params.chip)) {
287 if (sge_ctrl & VFIFO_ENABLE_F)
288 size = DBVFIFO_SIZE_G(fifo_size);
289 } else {
290 size = T6_DBVFIFO_SIZE_G(fifo_size);
291 }
292
293 if (size) {
294 md->base = BASEADDR_G(t4_read_reg(padap,
295 SGE_DBVFIFO_BADDR_A));
296 md->limit = md->base + (size << 2) - 1;
297 }
298 }
299
300 md++;
301
302 md->base = t4_read_reg(padap, ULP_RX_CTX_BASE_A);
303 md->limit = 0;
304 md++;
305 md->base = t4_read_reg(padap, ULP_TX_ERR_TABLE_BASE_A);
306 md->limit = 0;
307 md++;
308
309 md->base = padap->vres.ocq.start;
310 if (padap->vres.ocq.size)
311 md->limit = md->base + padap->vres.ocq.size - 1;
312 else
313 md->idx = ARRAY_SIZE(cudbg_region); /* hide it */
314 md++;
315
316 /* add any address-space holes, there can be up to 3 */
317 for (n = 0; n < i - 1; n++)
318 if (meminfo_buff->avail[n].limit <
319 meminfo_buff->avail[n + 1].base)
320 (md++)->base = meminfo_buff->avail[n].limit;
321
322 if (meminfo_buff->avail[n].limit)
323 (md++)->base = meminfo_buff->avail[n].limit;
324
325 n = md - meminfo_buff->mem;
326 meminfo_buff->mem_c = n;
327
328 sort(meminfo_buff->mem, n, sizeof(struct cudbg_mem_desc),
329 cudbg_mem_desc_cmp, NULL);
330
331 lo = t4_read_reg(padap, CIM_SDRAM_BASE_ADDR_A);
332 hi = t4_read_reg(padap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1;
333 meminfo_buff->up_ram_lo = lo;
334 meminfo_buff->up_ram_hi = hi;
335
336 lo = t4_read_reg(padap, CIM_EXTMEM2_BASE_ADDR_A);
337 hi = t4_read_reg(padap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1;
338 meminfo_buff->up_extmem2_lo = lo;
339 meminfo_buff->up_extmem2_hi = hi;
340
341 lo = t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A);
342 for (i = 0, meminfo_buff->free_rx_cnt = 0; i < 2; i++)
343 meminfo_buff->free_rx_cnt +=
344 FREERXPAGECOUNT_G(t4_read_reg(padap,
345 TP_FLM_FREE_RX_CNT_A));
346
347 meminfo_buff->rx_pages_data[0] = PMRXMAXPAGE_G(lo);
348 meminfo_buff->rx_pages_data[1] =
349 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) >> 10;
350 meminfo_buff->rx_pages_data[2] = (lo & PMRXNUMCHN_F) ? 2 : 1;
351
352 lo = t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A);
353 hi = t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A);
354 for (i = 0, meminfo_buff->free_tx_cnt = 0; i < 4; i++)
355 meminfo_buff->free_tx_cnt +=
356 FREETXPAGECOUNT_G(t4_read_reg(padap,
357 TP_FLM_FREE_TX_CNT_A));
358
359 meminfo_buff->tx_pages_data[0] = PMTXMAXPAGE_G(lo);
360 meminfo_buff->tx_pages_data[1] =
361 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10);
362 meminfo_buff->tx_pages_data[2] =
363 hi >= (1 << 20) ? 'M' : 'K';
364 meminfo_buff->tx_pages_data[3] = 1 << PMTXNUMCHN_G(lo);
365
366 meminfo_buff->p_structs = t4_read_reg(padap, TP_CMM_MM_MAX_PSTRUCT_A);
367 meminfo_buff->p_structs_free_cnt =
368 FREEPSTRUCTCOUNT_G(t4_read_reg(padap, TP_FLM_FREE_PS_CNT_A));
369
370 for (i = 0; i < 4; i++) {
371 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
372 lo = t4_read_reg(padap,
373 MPS_RX_MAC_BG_PG_CNT0_A + i * 4);
374 else
375 lo = t4_read_reg(padap, MPS_RX_PG_RSV0_A + i * 4);
376 if (is_t5(padap->params.chip)) {
377 used = T5_USED_G(lo);
378 alloc = T5_ALLOC_G(lo);
379 } else {
380 used = USED_G(lo);
381 alloc = ALLOC_G(lo);
382 }
383 meminfo_buff->port_used[i] = used;
384 meminfo_buff->port_alloc[i] = alloc;
385 }
386
387 for (i = 0; i < padap->params.arch.nchan; i++) {
388 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
389 lo = t4_read_reg(padap,
390 MPS_RX_LPBK_BG_PG_CNT0_A + i * 4);
391 else
392 lo = t4_read_reg(padap, MPS_RX_PG_RSV4_A + i * 4);
393 if (is_t5(padap->params.chip)) {
394 used = T5_USED_G(lo);
395 alloc = T5_ALLOC_G(lo);
396 } else {
397 used = USED_G(lo);
398 alloc = ALLOC_G(lo);
399 }
400 meminfo_buff->loopback_used[i] = used;
401 meminfo_buff->loopback_alloc[i] = alloc;
402 }
403
404 return 0;
405 }
406
407 int cudbg_collect_reg_dump(struct cudbg_init *pdbg_init,
408 struct cudbg_buffer *dbg_buff,
409 struct cudbg_error *cudbg_err)
410 {
411 struct adapter *padap = pdbg_init->adap;
412 struct cudbg_buffer temp_buff = { 0 };
413 u32 buf_size = 0;
414 int rc = 0;
415
416 if (is_t4(padap->params.chip))
417 buf_size = T4_REGMAP_SIZE;
418 else if (is_t5(padap->params.chip) || is_t6(padap->params.chip))
419 buf_size = T5_REGMAP_SIZE;
420
421 rc = cudbg_get_buff(pdbg_init, dbg_buff, buf_size, &temp_buff);
422 if (rc)
423 return rc;
424 t4_get_regs(padap, (void *)temp_buff.data, temp_buff.size);
425 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
426 }
427
428 int cudbg_collect_fw_devlog(struct cudbg_init *pdbg_init,
429 struct cudbg_buffer *dbg_buff,
430 struct cudbg_error *cudbg_err)
431 {
432 struct adapter *padap = pdbg_init->adap;
433 struct cudbg_buffer temp_buff = { 0 };
434 struct devlog_params *dparams;
435 int rc = 0;
436
437 rc = t4_init_devlog_params(padap);
438 if (rc < 0) {
439 cudbg_err->sys_err = rc;
440 return rc;
441 }
442
443 dparams = &padap->params.devlog;
444 rc = cudbg_get_buff(pdbg_init, dbg_buff, dparams->size, &temp_buff);
445 if (rc)
446 return rc;
447
448 /* Collect FW devlog */
449 if (dparams->start != 0) {
450 spin_lock(&padap->win0_lock);
451 rc = t4_memory_rw(padap, padap->params.drv_memwin,
452 dparams->memtype, dparams->start,
453 dparams->size,
454 (__be32 *)(char *)temp_buff.data,
455 1);
456 spin_unlock(&padap->win0_lock);
457 if (rc) {
458 cudbg_err->sys_err = rc;
459 cudbg_put_buff(pdbg_init, &temp_buff);
460 return rc;
461 }
462 }
463 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
464 }
465
466 int cudbg_collect_cim_la(struct cudbg_init *pdbg_init,
467 struct cudbg_buffer *dbg_buff,
468 struct cudbg_error *cudbg_err)
469 {
470 struct adapter *padap = pdbg_init->adap;
471 struct cudbg_buffer temp_buff = { 0 };
472 int size, rc;
473 u32 cfg = 0;
474
475 if (is_t6(padap->params.chip)) {
476 size = padap->params.cim_la_size / 10 + 1;
477 size *= 10 * sizeof(u32);
478 } else {
479 size = padap->params.cim_la_size / 8;
480 size *= 8 * sizeof(u32);
481 }
482
483 size += sizeof(cfg);
484 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
485 if (rc)
486 return rc;
487
488 rc = t4_cim_read(padap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
489 if (rc) {
490 cudbg_err->sys_err = rc;
491 cudbg_put_buff(pdbg_init, &temp_buff);
492 return rc;
493 }
494
495 memcpy((char *)temp_buff.data, &cfg, sizeof(cfg));
496 rc = t4_cim_read_la(padap,
497 (u32 *)((char *)temp_buff.data + sizeof(cfg)),
498 NULL);
499 if (rc < 0) {
500 cudbg_err->sys_err = rc;
501 cudbg_put_buff(pdbg_init, &temp_buff);
502 return rc;
503 }
504 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
505 }
506
507 int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init,
508 struct cudbg_buffer *dbg_buff,
509 struct cudbg_error *cudbg_err)
510 {
511 struct adapter *padap = pdbg_init->adap;
512 struct cudbg_buffer temp_buff = { 0 };
513 int size, rc;
514
515 size = 2 * CIM_MALA_SIZE * 5 * sizeof(u32);
516 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
517 if (rc)
518 return rc;
519
520 t4_cim_read_ma_la(padap,
521 (u32 *)temp_buff.data,
522 (u32 *)((char *)temp_buff.data +
523 5 * CIM_MALA_SIZE));
524 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
525 }
526
527 int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init,
528 struct cudbg_buffer *dbg_buff,
529 struct cudbg_error *cudbg_err)
530 {
531 struct adapter *padap = pdbg_init->adap;
532 struct cudbg_buffer temp_buff = { 0 };
533 struct cudbg_cim_qcfg *cim_qcfg_data;
534 int rc;
535
536 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_cim_qcfg),
537 &temp_buff);
538 if (rc)
539 return rc;
540
541 cim_qcfg_data = (struct cudbg_cim_qcfg *)temp_buff.data;
542 cim_qcfg_data->chip = padap->params.chip;
543 rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A,
544 ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat);
545 if (rc) {
546 cudbg_err->sys_err = rc;
547 cudbg_put_buff(pdbg_init, &temp_buff);
548 return rc;
549 }
550
551 rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A,
552 ARRAY_SIZE(cim_qcfg_data->obq_wr),
553 cim_qcfg_data->obq_wr);
554 if (rc) {
555 cudbg_err->sys_err = rc;
556 cudbg_put_buff(pdbg_init, &temp_buff);
557 return rc;
558 }
559
560 t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size,
561 cim_qcfg_data->thres);
562 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
563 }
564
565 static int cudbg_read_cim_ibq(struct cudbg_init *pdbg_init,
566 struct cudbg_buffer *dbg_buff,
567 struct cudbg_error *cudbg_err, int qid)
568 {
569 struct adapter *padap = pdbg_init->adap;
570 struct cudbg_buffer temp_buff = { 0 };
571 int no_of_read_words, rc = 0;
572 u32 qsize;
573
574 /* collect CIM IBQ */
575 qsize = CIM_IBQ_SIZE * 4 * sizeof(u32);
576 rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
577 if (rc)
578 return rc;
579
580 /* t4_read_cim_ibq will return no. of read words or error */
581 no_of_read_words = t4_read_cim_ibq(padap, qid,
582 (u32 *)temp_buff.data, qsize);
583 /* no_of_read_words is less than or equal to 0 means error */
584 if (no_of_read_words <= 0) {
585 if (!no_of_read_words)
586 rc = CUDBG_SYSTEM_ERROR;
587 else
588 rc = no_of_read_words;
589 cudbg_err->sys_err = rc;
590 cudbg_put_buff(pdbg_init, &temp_buff);
591 return rc;
592 }
593 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
594 }
595
596 int cudbg_collect_cim_ibq_tp0(struct cudbg_init *pdbg_init,
597 struct cudbg_buffer *dbg_buff,
598 struct cudbg_error *cudbg_err)
599 {
600 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 0);
601 }
602
603 int cudbg_collect_cim_ibq_tp1(struct cudbg_init *pdbg_init,
604 struct cudbg_buffer *dbg_buff,
605 struct cudbg_error *cudbg_err)
606 {
607 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 1);
608 }
609
610 int cudbg_collect_cim_ibq_ulp(struct cudbg_init *pdbg_init,
611 struct cudbg_buffer *dbg_buff,
612 struct cudbg_error *cudbg_err)
613 {
614 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 2);
615 }
616
617 int cudbg_collect_cim_ibq_sge0(struct cudbg_init *pdbg_init,
618 struct cudbg_buffer *dbg_buff,
619 struct cudbg_error *cudbg_err)
620 {
621 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 3);
622 }
623
624 int cudbg_collect_cim_ibq_sge1(struct cudbg_init *pdbg_init,
625 struct cudbg_buffer *dbg_buff,
626 struct cudbg_error *cudbg_err)
627 {
628 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 4);
629 }
630
631 int cudbg_collect_cim_ibq_ncsi(struct cudbg_init *pdbg_init,
632 struct cudbg_buffer *dbg_buff,
633 struct cudbg_error *cudbg_err)
634 {
635 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 5);
636 }
637
638 u32 cudbg_cim_obq_size(struct adapter *padap, int qid)
639 {
640 u32 value;
641
642 t4_write_reg(padap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
643 QUENUMSELECT_V(qid));
644 value = t4_read_reg(padap, CIM_QUEUE_CONFIG_CTRL_A);
645 value = CIMQSIZE_G(value) * 64; /* size in number of words */
646 return value * sizeof(u32);
647 }
648
649 static int cudbg_read_cim_obq(struct cudbg_init *pdbg_init,
650 struct cudbg_buffer *dbg_buff,
651 struct cudbg_error *cudbg_err, int qid)
652 {
653 struct adapter *padap = pdbg_init->adap;
654 struct cudbg_buffer temp_buff = { 0 };
655 int no_of_read_words, rc = 0;
656 u32 qsize;
657
658 /* collect CIM OBQ */
659 qsize = cudbg_cim_obq_size(padap, qid);
660 rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
661 if (rc)
662 return rc;
663
664 /* t4_read_cim_obq will return no. of read words or error */
665 no_of_read_words = t4_read_cim_obq(padap, qid,
666 (u32 *)temp_buff.data, qsize);
667 /* no_of_read_words is less than or equal to 0 means error */
668 if (no_of_read_words <= 0) {
669 if (!no_of_read_words)
670 rc = CUDBG_SYSTEM_ERROR;
671 else
672 rc = no_of_read_words;
673 cudbg_err->sys_err = rc;
674 cudbg_put_buff(pdbg_init, &temp_buff);
675 return rc;
676 }
677 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
678 }
679
680 int cudbg_collect_cim_obq_ulp0(struct cudbg_init *pdbg_init,
681 struct cudbg_buffer *dbg_buff,
682 struct cudbg_error *cudbg_err)
683 {
684 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 0);
685 }
686
687 int cudbg_collect_cim_obq_ulp1(struct cudbg_init *pdbg_init,
688 struct cudbg_buffer *dbg_buff,
689 struct cudbg_error *cudbg_err)
690 {
691 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 1);
692 }
693
694 int cudbg_collect_cim_obq_ulp2(struct cudbg_init *pdbg_init,
695 struct cudbg_buffer *dbg_buff,
696 struct cudbg_error *cudbg_err)
697 {
698 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 2);
699 }
700
701 int cudbg_collect_cim_obq_ulp3(struct cudbg_init *pdbg_init,
702 struct cudbg_buffer *dbg_buff,
703 struct cudbg_error *cudbg_err)
704 {
705 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 3);
706 }
707
708 int cudbg_collect_cim_obq_sge(struct cudbg_init *pdbg_init,
709 struct cudbg_buffer *dbg_buff,
710 struct cudbg_error *cudbg_err)
711 {
712 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 4);
713 }
714
715 int cudbg_collect_cim_obq_ncsi(struct cudbg_init *pdbg_init,
716 struct cudbg_buffer *dbg_buff,
717 struct cudbg_error *cudbg_err)
718 {
719 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 5);
720 }
721
722 int cudbg_collect_obq_sge_rx_q0(struct cudbg_init *pdbg_init,
723 struct cudbg_buffer *dbg_buff,
724 struct cudbg_error *cudbg_err)
725 {
726 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 6);
727 }
728
729 int cudbg_collect_obq_sge_rx_q1(struct cudbg_init *pdbg_init,
730 struct cudbg_buffer *dbg_buff,
731 struct cudbg_error *cudbg_err)
732 {
733 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 7);
734 }
735
736 static int cudbg_meminfo_get_mem_index(struct adapter *padap,
737 struct cudbg_meminfo *mem_info,
738 u8 mem_type, u8 *idx)
739 {
740 u8 i, flag;
741
742 switch (mem_type) {
743 case MEM_EDC0:
744 flag = EDC0_FLAG;
745 break;
746 case MEM_EDC1:
747 flag = EDC1_FLAG;
748 break;
749 case MEM_MC0:
750 /* Some T5 cards have both MC0 and MC1. */
751 flag = is_t5(padap->params.chip) ? MC0_FLAG : MC_FLAG;
752 break;
753 case MEM_MC1:
754 flag = MC1_FLAG;
755 break;
756 case MEM_HMA:
757 flag = HMA_FLAG;
758 break;
759 default:
760 return CUDBG_STATUS_ENTITY_NOT_FOUND;
761 }
762
763 for (i = 0; i < mem_info->avail_c; i++) {
764 if (mem_info->avail[i].idx == flag) {
765 *idx = i;
766 return 0;
767 }
768 }
769
770 return CUDBG_STATUS_ENTITY_NOT_FOUND;
771 }
772
773 /* Fetch the @region_name's start and end from @meminfo. */
774 static int cudbg_get_mem_region(struct adapter *padap,
775 struct cudbg_meminfo *meminfo,
776 u8 mem_type, const char *region_name,
777 struct cudbg_mem_desc *mem_desc)
778 {
779 u8 mc, found = 0;
780 u32 idx = 0;
781 int rc, i;
782
783 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc);
784 if (rc)
785 return rc;
786
787 i = match_string(cudbg_region, ARRAY_SIZE(cudbg_region), region_name);
788 if (i < 0)
789 return -EINVAL;
790
791 idx = i;
792 for (i = 0; i < meminfo->mem_c; i++) {
793 if (meminfo->mem[i].idx >= ARRAY_SIZE(cudbg_region))
794 continue; /* Skip holes */
795
796 if (!(meminfo->mem[i].limit))
797 meminfo->mem[i].limit =
798 i < meminfo->mem_c - 1 ?
799 meminfo->mem[i + 1].base - 1 : ~0;
800
801 if (meminfo->mem[i].idx == idx) {
802 /* Check if the region exists in @mem_type memory */
803 if (meminfo->mem[i].base < meminfo->avail[mc].base &&
804 meminfo->mem[i].limit < meminfo->avail[mc].base)
805 return -EINVAL;
806
807 if (meminfo->mem[i].base > meminfo->avail[mc].limit)
808 return -EINVAL;
809
810 memcpy(mem_desc, &meminfo->mem[i],
811 sizeof(struct cudbg_mem_desc));
812 found = 1;
813 break;
814 }
815 }
816 if (!found)
817 return -EINVAL;
818
819 return 0;
820 }
821
822 /* Fetch and update the start and end of the requested memory region w.r.t 0
823 * in the corresponding EDC/MC/HMA.
824 */
825 static int cudbg_get_mem_relative(struct adapter *padap,
826 struct cudbg_meminfo *meminfo,
827 u8 mem_type, u32 *out_base, u32 *out_end)
828 {
829 u8 mc_idx;
830 int rc;
831
832 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc_idx);
833 if (rc)
834 return rc;
835
836 if (*out_base < meminfo->avail[mc_idx].base)
837 *out_base = 0;
838 else
839 *out_base -= meminfo->avail[mc_idx].base;
840
841 if (*out_end > meminfo->avail[mc_idx].limit)
842 *out_end = meminfo->avail[mc_idx].limit;
843 else
844 *out_end -= meminfo->avail[mc_idx].base;
845
846 return 0;
847 }
848
849 /* Get TX and RX Payload region */
850 static int cudbg_get_payload_range(struct adapter *padap, u8 mem_type,
851 const char *region_name,
852 struct cudbg_region_info *payload)
853 {
854 struct cudbg_mem_desc mem_desc = { 0 };
855 struct cudbg_meminfo meminfo;
856 int rc;
857
858 rc = cudbg_fill_meminfo(padap, &meminfo);
859 if (rc)
860 return rc;
861
862 rc = cudbg_get_mem_region(padap, &meminfo, mem_type, region_name,
863 &mem_desc);
864 if (rc) {
865 payload->exist = false;
866 return 0;
867 }
868
869 payload->exist = true;
870 payload->start = mem_desc.base;
871 payload->end = mem_desc.limit;
872
873 return cudbg_get_mem_relative(padap, &meminfo, mem_type,
874 &payload->start, &payload->end);
875 }
876
877 static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
878 int mtype, u32 addr, u32 len, void *hbuf)
879 {
880 u32 win_pf, memoffset, mem_aperture, mem_base;
881 struct adapter *adap = pdbg_init->adap;
882 u32 pos, offset, resid;
883 u32 *res_buf;
884 u64 *buf;
885 int ret;
886
887 /* Argument sanity checks ...
888 */
889 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
890 return -EINVAL;
891
892 buf = (u64 *)hbuf;
893
894 /* Try to do 64-bit reads. Residual will be handled later. */
895 resid = len & 0x7;
896 len -= resid;
897
898 ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
899 &mem_aperture);
900 if (ret)
901 return ret;
902
903 addr = addr + memoffset;
904 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
905
906 pos = addr & ~(mem_aperture - 1);
907 offset = addr - pos;
908
909 /* Set up initial PCI-E Memory Window to cover the start of our
910 * transfer.
911 */
912 t4_memory_update_win(adap, win, pos | win_pf);
913
914 /* Transfer data from the adapter */
915 while (len > 0) {
916 *buf++ = le64_to_cpu((__force __le64)
917 t4_read_reg64(adap, mem_base + offset));
918 offset += sizeof(u64);
919 len -= sizeof(u64);
920
921 /* If we've reached the end of our current window aperture,
922 * move the PCI-E Memory Window on to the next.
923 */
924 if (offset == mem_aperture) {
925 pos += mem_aperture;
926 offset = 0;
927 t4_memory_update_win(adap, win, pos | win_pf);
928 }
929 }
930
931 res_buf = (u32 *)buf;
932 /* Read residual in 32-bit multiples */
933 while (resid > sizeof(u32)) {
934 *res_buf++ = le32_to_cpu((__force __le32)
935 t4_read_reg(adap, mem_base + offset));
936 offset += sizeof(u32);
937 resid -= sizeof(u32);
938
939 /* If we've reached the end of our current window aperture,
940 * move the PCI-E Memory Window on to the next.
941 */
942 if (offset == mem_aperture) {
943 pos += mem_aperture;
944 offset = 0;
945 t4_memory_update_win(adap, win, pos | win_pf);
946 }
947 }
948
949 /* Transfer residual < 32-bits */
950 if (resid)
951 t4_memory_rw_residual(adap, resid, mem_base + offset,
952 (u8 *)res_buf, T4_MEMORY_READ);
953
954 return 0;
955 }
956
957 #define CUDBG_YIELD_ITERATION 256
958
959 static int cudbg_read_fw_mem(struct cudbg_init *pdbg_init,
960 struct cudbg_buffer *dbg_buff, u8 mem_type,
961 unsigned long tot_len,
962 struct cudbg_error *cudbg_err)
963 {
964 static const char * const region_name[] = { "Tx payload:",
965 "Rx payload:" };
966 unsigned long bytes, bytes_left, bytes_read = 0;
967 struct adapter *padap = pdbg_init->adap;
968 struct cudbg_buffer temp_buff = { 0 };
969 struct cudbg_region_info payload[2];
970 u32 yield_count = 0;
971 int rc = 0;
972 u8 i;
973
974 /* Get TX/RX Payload region range if they exist */
975 memset(payload, 0, sizeof(payload));
976 for (i = 0; i < ARRAY_SIZE(region_name); i++) {
977 rc = cudbg_get_payload_range(padap, mem_type, region_name[i],
978 &payload[i]);
979 if (rc)
980 return rc;
981
982 if (payload[i].exist) {
983 /* Align start and end to avoid wrap around */
984 payload[i].start = roundup(payload[i].start,
985 CUDBG_CHUNK_SIZE);
986 payload[i].end = rounddown(payload[i].end,
987 CUDBG_CHUNK_SIZE);
988 }
989 }
990
991 bytes_left = tot_len;
992 while (bytes_left > 0) {
993 /* As MC size is huge and read through PIO access, this
994 * loop will hold cpu for a longer time. OS may think that
995 * the process is hanged and will generate CPU stall traces.
996 * So yield the cpu regularly.
997 */
998 yield_count++;
999 if (!(yield_count % CUDBG_YIELD_ITERATION))
1000 schedule();
1001
1002 bytes = min_t(unsigned long, bytes_left,
1003 (unsigned long)CUDBG_CHUNK_SIZE);
1004 rc = cudbg_get_buff(pdbg_init, dbg_buff, bytes, &temp_buff);
1005 if (rc)
1006 return rc;
1007
1008 for (i = 0; i < ARRAY_SIZE(payload); i++)
1009 if (payload[i].exist &&
1010 bytes_read >= payload[i].start &&
1011 bytes_read + bytes <= payload[i].end)
1012 /* TX and RX Payload regions can't overlap */
1013 goto skip_read;
1014
1015 spin_lock(&padap->win0_lock);
1016 rc = cudbg_memory_read(pdbg_init, MEMWIN_NIC, mem_type,
1017 bytes_read, bytes, temp_buff.data);
1018 spin_unlock(&padap->win0_lock);
1019 if (rc) {
1020 cudbg_err->sys_err = rc;
1021 cudbg_put_buff(pdbg_init, &temp_buff);
1022 return rc;
1023 }
1024
1025 skip_read:
1026 bytes_left -= bytes;
1027 bytes_read += bytes;
1028 rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff,
1029 dbg_buff);
1030 if (rc) {
1031 cudbg_put_buff(pdbg_init, &temp_buff);
1032 return rc;
1033 }
1034 }
1035 return rc;
1036 }
1037
1038 static void cudbg_t4_fwcache(struct cudbg_init *pdbg_init,
1039 struct cudbg_error *cudbg_err)
1040 {
1041 struct adapter *padap = pdbg_init->adap;
1042 int rc;
1043
1044 if (is_fw_attached(pdbg_init)) {
1045 /* Flush uP dcache before reading edcX/mcX */
1046 rc = t4_fwcache(padap, FW_PARAM_DEV_FWCACHE_FLUSH);
1047 if (rc)
1048 cudbg_err->sys_warn = rc;
1049 }
1050 }
1051
1052 static unsigned long cudbg_mem_region_size(struct cudbg_init *pdbg_init,
1053 struct cudbg_error *cudbg_err,
1054 u8 mem_type)
1055 {
1056 struct adapter *padap = pdbg_init->adap;
1057 struct cudbg_meminfo mem_info;
1058 u8 mc_idx;
1059 int rc;
1060
1061 memset(&mem_info, 0, sizeof(struct cudbg_meminfo));
1062 rc = cudbg_fill_meminfo(padap, &mem_info);
1063 if (rc)
1064 return rc;
1065
1066 cudbg_t4_fwcache(pdbg_init, cudbg_err);
1067 rc = cudbg_meminfo_get_mem_index(padap, &mem_info, mem_type, &mc_idx);
1068 if (rc)
1069 return rc;
1070
1071 return mem_info.avail[mc_idx].limit - mem_info.avail[mc_idx].base;
1072 }
1073
1074 static int cudbg_collect_mem_region(struct cudbg_init *pdbg_init,
1075 struct cudbg_buffer *dbg_buff,
1076 struct cudbg_error *cudbg_err,
1077 u8 mem_type)
1078 {
1079 unsigned long size = cudbg_mem_region_size(pdbg_init, cudbg_err, mem_type);
1080
1081 return cudbg_read_fw_mem(pdbg_init, dbg_buff, mem_type, size,
1082 cudbg_err);
1083 }
1084
1085 int cudbg_collect_edc0_meminfo(struct cudbg_init *pdbg_init,
1086 struct cudbg_buffer *dbg_buff,
1087 struct cudbg_error *cudbg_err)
1088 {
1089 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1090 MEM_EDC0);
1091 }
1092
1093 int cudbg_collect_edc1_meminfo(struct cudbg_init *pdbg_init,
1094 struct cudbg_buffer *dbg_buff,
1095 struct cudbg_error *cudbg_err)
1096 {
1097 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1098 MEM_EDC1);
1099 }
1100
1101 int cudbg_collect_mc0_meminfo(struct cudbg_init *pdbg_init,
1102 struct cudbg_buffer *dbg_buff,
1103 struct cudbg_error *cudbg_err)
1104 {
1105 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1106 MEM_MC0);
1107 }
1108
1109 int cudbg_collect_mc1_meminfo(struct cudbg_init *pdbg_init,
1110 struct cudbg_buffer *dbg_buff,
1111 struct cudbg_error *cudbg_err)
1112 {
1113 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1114 MEM_MC1);
1115 }
1116
1117 int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init,
1118 struct cudbg_buffer *dbg_buff,
1119 struct cudbg_error *cudbg_err)
1120 {
1121 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1122 MEM_HMA);
1123 }
1124
1125 int cudbg_collect_rss(struct cudbg_init *pdbg_init,
1126 struct cudbg_buffer *dbg_buff,
1127 struct cudbg_error *cudbg_err)
1128 {
1129 struct adapter *padap = pdbg_init->adap;
1130 struct cudbg_buffer temp_buff = { 0 };
1131 int rc, nentries;
1132
1133 nentries = t4_chip_rss_size(padap);
1134 rc = cudbg_get_buff(pdbg_init, dbg_buff, nentries * sizeof(u16),
1135 &temp_buff);
1136 if (rc)
1137 return rc;
1138
1139 rc = t4_read_rss(padap, (u16 *)temp_buff.data);
1140 if (rc) {
1141 cudbg_err->sys_err = rc;
1142 cudbg_put_buff(pdbg_init, &temp_buff);
1143 return rc;
1144 }
1145 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1146 }
1147
1148 int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init,
1149 struct cudbg_buffer *dbg_buff,
1150 struct cudbg_error *cudbg_err)
1151 {
1152 struct adapter *padap = pdbg_init->adap;
1153 struct cudbg_buffer temp_buff = { 0 };
1154 struct cudbg_rss_vf_conf *vfconf;
1155 int vf, rc, vf_count;
1156
1157 vf_count = padap->params.arch.vfcount;
1158 rc = cudbg_get_buff(pdbg_init, dbg_buff,
1159 vf_count * sizeof(struct cudbg_rss_vf_conf),
1160 &temp_buff);
1161 if (rc)
1162 return rc;
1163
1164 vfconf = (struct cudbg_rss_vf_conf *)temp_buff.data;
1165 for (vf = 0; vf < vf_count; vf++)
1166 t4_read_rss_vf_config(padap, vf, &vfconf[vf].rss_vf_vfl,
1167 &vfconf[vf].rss_vf_vfh, true);
1168 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1169 }
1170
1171 int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init,
1172 struct cudbg_buffer *dbg_buff,
1173 struct cudbg_error *cudbg_err)
1174 {
1175 struct adapter *padap = pdbg_init->adap;
1176 struct cudbg_buffer temp_buff = { 0 };
1177 int rc;
1178
1179 rc = cudbg_get_buff(pdbg_init, dbg_buff, NMTUS * sizeof(u16),
1180 &temp_buff);
1181 if (rc)
1182 return rc;
1183
1184 t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL);
1185 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1186 }
1187
1188 int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init,
1189 struct cudbg_buffer *dbg_buff,
1190 struct cudbg_error *cudbg_err)
1191 {
1192 struct adapter *padap = pdbg_init->adap;
1193 struct cudbg_buffer temp_buff = { 0 };
1194 struct cudbg_pm_stats *pm_stats_buff;
1195 int rc;
1196
1197 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_pm_stats),
1198 &temp_buff);
1199 if (rc)
1200 return rc;
1201
1202 pm_stats_buff = (struct cudbg_pm_stats *)temp_buff.data;
1203 t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc);
1204 t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc);
1205 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1206 }
1207
1208 int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,
1209 struct cudbg_buffer *dbg_buff,
1210 struct cudbg_error *cudbg_err)
1211 {
1212 struct adapter *padap = pdbg_init->adap;
1213 struct cudbg_buffer temp_buff = { 0 };
1214 struct cudbg_hw_sched *hw_sched_buff;
1215 int i, rc = 0;
1216
1217 if (!padap->params.vpd.cclk)
1218 return CUDBG_STATUS_CCLK_NOT_DEFINED;
1219
1220 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_hw_sched),
1221 &temp_buff);
1222
1223 if (rc)
1224 return rc;
1225
1226 hw_sched_buff = (struct cudbg_hw_sched *)temp_buff.data;
1227 hw_sched_buff->map = t4_read_reg(padap, TP_TX_MOD_QUEUE_REQ_MAP_A);
1228 hw_sched_buff->mode = TIMERMODE_G(t4_read_reg(padap, TP_MOD_CONFIG_A));
1229 t4_read_pace_tbl(padap, hw_sched_buff->pace_tab);
1230 for (i = 0; i < NTX_SCHED; ++i)
1231 t4_get_tx_sched(padap, i, &hw_sched_buff->kbps[i],
1232 &hw_sched_buff->ipg[i], true);
1233 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1234 }
1235
1236 int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
1237 struct cudbg_buffer *dbg_buff,
1238 struct cudbg_error *cudbg_err)
1239 {
1240 struct adapter *padap = pdbg_init->adap;
1241 struct cudbg_buffer temp_buff = { 0 };
1242 struct ireg_buf *ch_tp_pio;
1243 int i, rc, n = 0;
1244 u32 size;
1245
1246 if (is_t5(padap->params.chip))
1247 n = sizeof(t5_tp_pio_array) +
1248 sizeof(t5_tp_tm_pio_array) +
1249 sizeof(t5_tp_mib_index_array);
1250 else
1251 n = sizeof(t6_tp_pio_array) +
1252 sizeof(t6_tp_tm_pio_array) +
1253 sizeof(t6_tp_mib_index_array);
1254
1255 n = n / (IREG_NUM_ELEM * sizeof(u32));
1256 size = sizeof(struct ireg_buf) * n;
1257 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1258 if (rc)
1259 return rc;
1260
1261 ch_tp_pio = (struct ireg_buf *)temp_buff.data;
1262
1263 /* TP_PIO */
1264 if (is_t5(padap->params.chip))
1265 n = sizeof(t5_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1266 else if (is_t6(padap->params.chip))
1267 n = sizeof(t6_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1268
1269 for (i = 0; i < n; i++) {
1270 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1271 u32 *buff = ch_tp_pio->outbuf;
1272
1273 if (is_t5(padap->params.chip)) {
1274 tp_pio->ireg_addr = t5_tp_pio_array[i][0];
1275 tp_pio->ireg_data = t5_tp_pio_array[i][1];
1276 tp_pio->ireg_local_offset = t5_tp_pio_array[i][2];
1277 tp_pio->ireg_offset_range = t5_tp_pio_array[i][3];
1278 } else if (is_t6(padap->params.chip)) {
1279 tp_pio->ireg_addr = t6_tp_pio_array[i][0];
1280 tp_pio->ireg_data = t6_tp_pio_array[i][1];
1281 tp_pio->ireg_local_offset = t6_tp_pio_array[i][2];
1282 tp_pio->ireg_offset_range = t6_tp_pio_array[i][3];
1283 }
1284 t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range,
1285 tp_pio->ireg_local_offset, true);
1286 ch_tp_pio++;
1287 }
1288
1289 /* TP_TM_PIO */
1290 if (is_t5(padap->params.chip))
1291 n = sizeof(t5_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1292 else if (is_t6(padap->params.chip))
1293 n = sizeof(t6_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1294
1295 for (i = 0; i < n; i++) {
1296 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1297 u32 *buff = ch_tp_pio->outbuf;
1298
1299 if (is_t5(padap->params.chip)) {
1300 tp_pio->ireg_addr = t5_tp_tm_pio_array[i][0];
1301 tp_pio->ireg_data = t5_tp_tm_pio_array[i][1];
1302 tp_pio->ireg_local_offset = t5_tp_tm_pio_array[i][2];
1303 tp_pio->ireg_offset_range = t5_tp_tm_pio_array[i][3];
1304 } else if (is_t6(padap->params.chip)) {
1305 tp_pio->ireg_addr = t6_tp_tm_pio_array[i][0];
1306 tp_pio->ireg_data = t6_tp_tm_pio_array[i][1];
1307 tp_pio->ireg_local_offset = t6_tp_tm_pio_array[i][2];
1308 tp_pio->ireg_offset_range = t6_tp_tm_pio_array[i][3];
1309 }
1310 t4_tp_tm_pio_read(padap, buff, tp_pio->ireg_offset_range,
1311 tp_pio->ireg_local_offset, true);
1312 ch_tp_pio++;
1313 }
1314
1315 /* TP_MIB_INDEX */
1316 if (is_t5(padap->params.chip))
1317 n = sizeof(t5_tp_mib_index_array) /
1318 (IREG_NUM_ELEM * sizeof(u32));
1319 else if (is_t6(padap->params.chip))
1320 n = sizeof(t6_tp_mib_index_array) /
1321 (IREG_NUM_ELEM * sizeof(u32));
1322
1323 for (i = 0; i < n ; i++) {
1324 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1325 u32 *buff = ch_tp_pio->outbuf;
1326
1327 if (is_t5(padap->params.chip)) {
1328 tp_pio->ireg_addr = t5_tp_mib_index_array[i][0];
1329 tp_pio->ireg_data = t5_tp_mib_index_array[i][1];
1330 tp_pio->ireg_local_offset =
1331 t5_tp_mib_index_array[i][2];
1332 tp_pio->ireg_offset_range =
1333 t5_tp_mib_index_array[i][3];
1334 } else if (is_t6(padap->params.chip)) {
1335 tp_pio->ireg_addr = t6_tp_mib_index_array[i][0];
1336 tp_pio->ireg_data = t6_tp_mib_index_array[i][1];
1337 tp_pio->ireg_local_offset =
1338 t6_tp_mib_index_array[i][2];
1339 tp_pio->ireg_offset_range =
1340 t6_tp_mib_index_array[i][3];
1341 }
1342 t4_tp_mib_read(padap, buff, tp_pio->ireg_offset_range,
1343 tp_pio->ireg_local_offset, true);
1344 ch_tp_pio++;
1345 }
1346 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1347 }
1348
1349 static void cudbg_read_sge_qbase_indirect_reg(struct adapter *padap,
1350 struct sge_qbase_reg_field *qbase,
1351 u32 func, bool is_pf)
1352 {
1353 u32 *buff, i;
1354
1355 if (is_pf) {
1356 buff = qbase->pf_data_value[func];
1357 } else {
1358 buff = qbase->vf_data_value[func];
1359 /* In SGE_QBASE_INDEX,
1360 * Entries 0->7 are PF0->7, Entries 8->263 are VFID0->256.
1361 */
1362 func += 8;
1363 }
1364
1365 t4_write_reg(padap, qbase->reg_addr, func);
1366 for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++, buff++)
1367 *buff = t4_read_reg(padap, qbase->reg_data[i]);
1368 }
1369
1370 int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init,
1371 struct cudbg_buffer *dbg_buff,
1372 struct cudbg_error *cudbg_err)
1373 {
1374 struct adapter *padap = pdbg_init->adap;
1375 struct cudbg_buffer temp_buff = { 0 };
1376 struct sge_qbase_reg_field *sge_qbase;
1377 struct ireg_buf *ch_sge_dbg;
1378 int i, rc;
1379
1380 rc = cudbg_get_buff(pdbg_init, dbg_buff,
1381 sizeof(*ch_sge_dbg) * 2 + sizeof(*sge_qbase),
1382 &temp_buff);
1383 if (rc)
1384 return rc;
1385
1386 ch_sge_dbg = (struct ireg_buf *)temp_buff.data;
1387 for (i = 0; i < 2; i++) {
1388 struct ireg_field *sge_pio = &ch_sge_dbg->tp_pio;
1389 u32 *buff = ch_sge_dbg->outbuf;
1390
1391 sge_pio->ireg_addr = t5_sge_dbg_index_array[i][0];
1392 sge_pio->ireg_data = t5_sge_dbg_index_array[i][1];
1393 sge_pio->ireg_local_offset = t5_sge_dbg_index_array[i][2];
1394 sge_pio->ireg_offset_range = t5_sge_dbg_index_array[i][3];
1395 t4_read_indirect(padap,
1396 sge_pio->ireg_addr,
1397 sge_pio->ireg_data,
1398 buff,
1399 sge_pio->ireg_offset_range,
1400 sge_pio->ireg_local_offset);
1401 ch_sge_dbg++;
1402 }
1403
1404 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
1405 sge_qbase = (struct sge_qbase_reg_field *)ch_sge_dbg;
1406 /* 1 addr reg SGE_QBASE_INDEX and 4 data reg
1407 * SGE_QBASE_MAP[0-3]
1408 */
1409 sge_qbase->reg_addr = t6_sge_qbase_index_array[0];
1410 for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++)
1411 sge_qbase->reg_data[i] =
1412 t6_sge_qbase_index_array[i + 1];
1413
1414 for (i = 0; i <= PCIE_FW_MASTER_M; i++)
1415 cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
1416 i, true);
1417
1418 for (i = 0; i < padap->params.arch.vfcount; i++)
1419 cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
1420 i, false);
1421
1422 sge_qbase->vfcount = padap->params.arch.vfcount;
1423 }
1424
1425 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1426 }
1427
1428 int cudbg_collect_ulprx_la(struct cudbg_init *pdbg_init,
1429 struct cudbg_buffer *dbg_buff,
1430 struct cudbg_error *cudbg_err)
1431 {
1432 struct adapter *padap = pdbg_init->adap;
1433 struct cudbg_buffer temp_buff = { 0 };
1434 struct cudbg_ulprx_la *ulprx_la_buff;
1435 int rc;
1436
1437 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_ulprx_la),
1438 &temp_buff);
1439 if (rc)
1440 return rc;
1441
1442 ulprx_la_buff = (struct cudbg_ulprx_la *)temp_buff.data;
1443 t4_ulprx_read_la(padap, (u32 *)ulprx_la_buff->data);
1444 ulprx_la_buff->size = ULPRX_LA_SIZE;
1445 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1446 }
1447
1448 int cudbg_collect_tp_la(struct cudbg_init *pdbg_init,
1449 struct cudbg_buffer *dbg_buff,
1450 struct cudbg_error *cudbg_err)
1451 {
1452 struct adapter *padap = pdbg_init->adap;
1453 struct cudbg_buffer temp_buff = { 0 };
1454 struct cudbg_tp_la *tp_la_buff;
1455 int size, rc;
1456
1457 size = sizeof(struct cudbg_tp_la) + TPLA_SIZE * sizeof(u64);
1458 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1459 if (rc)
1460 return rc;
1461
1462 tp_la_buff = (struct cudbg_tp_la *)temp_buff.data;
1463 tp_la_buff->mode = DBGLAMODE_G(t4_read_reg(padap, TP_DBG_LA_CONFIG_A));
1464 t4_tp_read_la(padap, (u64 *)tp_la_buff->data, NULL);
1465 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1466 }
1467
1468 int cudbg_collect_meminfo(struct cudbg_init *pdbg_init,
1469 struct cudbg_buffer *dbg_buff,
1470 struct cudbg_error *cudbg_err)
1471 {
1472 struct adapter *padap = pdbg_init->adap;
1473 struct cudbg_buffer temp_buff = { 0 };
1474 struct cudbg_meminfo *meminfo_buff;
1475 struct cudbg_ver_hdr *ver_hdr;
1476 int rc;
1477
1478 rc = cudbg_get_buff(pdbg_init, dbg_buff,
1479 sizeof(struct cudbg_ver_hdr) +
1480 sizeof(struct cudbg_meminfo),
1481 &temp_buff);
1482 if (rc)
1483 return rc;
1484
1485 ver_hdr = (struct cudbg_ver_hdr *)temp_buff.data;
1486 ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
1487 ver_hdr->revision = CUDBG_MEMINFO_REV;
1488 ver_hdr->size = sizeof(struct cudbg_meminfo);
1489
1490 meminfo_buff = (struct cudbg_meminfo *)(temp_buff.data +
1491 sizeof(*ver_hdr));
1492 rc = cudbg_fill_meminfo(padap, meminfo_buff);
1493 if (rc) {
1494 cudbg_err->sys_err = rc;
1495 cudbg_put_buff(pdbg_init, &temp_buff);
1496 return rc;
1497 }
1498
1499 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1500 }
1501
1502 int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init,
1503 struct cudbg_buffer *dbg_buff,
1504 struct cudbg_error *cudbg_err)
1505 {
1506 struct cudbg_cim_pif_la *cim_pif_la_buff;
1507 struct adapter *padap = pdbg_init->adap;
1508 struct cudbg_buffer temp_buff = { 0 };
1509 int size, rc;
1510
1511 size = sizeof(struct cudbg_cim_pif_la) +
1512 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32);
1513 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1514 if (rc)
1515 return rc;
1516
1517 cim_pif_la_buff = (struct cudbg_cim_pif_la *)temp_buff.data;
1518 cim_pif_la_buff->size = CIM_PIFLA_SIZE;
1519 t4_cim_read_pif_la(padap, (u32 *)cim_pif_la_buff->data,
1520 (u32 *)cim_pif_la_buff->data + 6 * CIM_PIFLA_SIZE,
1521 NULL, NULL);
1522 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1523 }
1524
1525 int cudbg_collect_clk_info(struct cudbg_init *pdbg_init,
1526 struct cudbg_buffer *dbg_buff,
1527 struct cudbg_error *cudbg_err)
1528 {
1529 struct adapter *padap = pdbg_init->adap;
1530 struct cudbg_buffer temp_buff = { 0 };
1531 struct cudbg_clk_info *clk_info_buff;
1532 u64 tp_tick_us;
1533 int rc;
1534
1535 if (!padap->params.vpd.cclk)
1536 return CUDBG_STATUS_CCLK_NOT_DEFINED;
1537
1538 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_clk_info),
1539 &temp_buff);
1540 if (rc)
1541 return rc;
1542
1543 clk_info_buff = (struct cudbg_clk_info *)temp_buff.data;
1544 clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* psec */
1545 clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A);
1546 clk_info_buff->tre = TIMERRESOLUTION_G(clk_info_buff->res);
1547 clk_info_buff->dack_re = DELAYEDACKRESOLUTION_G(clk_info_buff->res);
1548 tp_tick_us = (clk_info_buff->cclk_ps << clk_info_buff->tre) / 1000000;
1549
1550 clk_info_buff->dack_timer =
1551 (clk_info_buff->cclk_ps << clk_info_buff->dack_re) / 1000000 *
1552 t4_read_reg(padap, TP_DACK_TIMER_A);
1553 clk_info_buff->retransmit_min =
1554 tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A);
1555 clk_info_buff->retransmit_max =
1556 tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A);
1557 clk_info_buff->persist_timer_min =
1558 tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A);
1559 clk_info_buff->persist_timer_max =
1560 tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A);
1561 clk_info_buff->keepalive_idle_timer =
1562 tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A);
1563 clk_info_buff->keepalive_interval =
1564 tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A);
1565 clk_info_buff->initial_srtt =
1566 tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A));
1567 clk_info_buff->finwait2_timer =
1568 tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A);
1569
1570 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1571 }
1572
1573 int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init,
1574 struct cudbg_buffer *dbg_buff,
1575 struct cudbg_error *cudbg_err)
1576 {
1577 struct adapter *padap = pdbg_init->adap;
1578 struct cudbg_buffer temp_buff = { 0 };
1579 struct ireg_buf *ch_pcie;
1580 int i, rc, n;
1581 u32 size;
1582
1583 n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
1584 size = sizeof(struct ireg_buf) * n * 2;
1585 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1586 if (rc)
1587 return rc;
1588
1589 ch_pcie = (struct ireg_buf *)temp_buff.data;
1590 /* PCIE_PDBG */
1591 for (i = 0; i < n; i++) {
1592 struct ireg_field *pcie_pio = &ch_pcie->tp_pio;
1593 u32 *buff = ch_pcie->outbuf;
1594
1595 pcie_pio->ireg_addr = t5_pcie_pdbg_array[i][0];
1596 pcie_pio->ireg_data = t5_pcie_pdbg_array[i][1];
1597 pcie_pio->ireg_local_offset = t5_pcie_pdbg_array[i][2];
1598 pcie_pio->ireg_offset_range = t5_pcie_pdbg_array[i][3];
1599 t4_read_indirect(padap,
1600 pcie_pio->ireg_addr,
1601 pcie_pio->ireg_data,
1602 buff,
1603 pcie_pio->ireg_offset_range,
1604 pcie_pio->ireg_local_offset);
1605 ch_pcie++;
1606 }
1607
1608 /* PCIE_CDBG */
1609 n = sizeof(t5_pcie_cdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
1610 for (i = 0; i < n; i++) {
1611 struct ireg_field *pcie_pio = &ch_pcie->tp_pio;
1612 u32 *buff = ch_pcie->outbuf;
1613
1614 pcie_pio->ireg_addr = t5_pcie_cdbg_array[i][0];
1615 pcie_pio->ireg_data = t5_pcie_cdbg_array[i][1];
1616 pcie_pio->ireg_local_offset = t5_pcie_cdbg_array[i][2];
1617 pcie_pio->ireg_offset_range = t5_pcie_cdbg_array[i][3];
1618 t4_read_indirect(padap,
1619 pcie_pio->ireg_addr,
1620 pcie_pio->ireg_data,
1621 buff,
1622 pcie_pio->ireg_offset_range,
1623 pcie_pio->ireg_local_offset);
1624 ch_pcie++;
1625 }
1626 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1627 }
1628
1629 int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init,
1630 struct cudbg_buffer *dbg_buff,
1631 struct cudbg_error *cudbg_err)
1632 {
1633 struct adapter *padap = pdbg_init->adap;
1634 struct cudbg_buffer temp_buff = { 0 };
1635 struct ireg_buf *ch_pm;
1636 int i, rc, n;
1637 u32 size;
1638
1639 n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32));
1640 size = sizeof(struct ireg_buf) * n * 2;
1641 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1642 if (rc)
1643 return rc;
1644
1645 ch_pm = (struct ireg_buf *)temp_buff.data;
1646 /* PM_RX */
1647 for (i = 0; i < n; i++) {
1648 struct ireg_field *pm_pio = &ch_pm->tp_pio;
1649 u32 *buff = ch_pm->outbuf;
1650
1651 pm_pio->ireg_addr = t5_pm_rx_array[i][0];
1652 pm_pio->ireg_data = t5_pm_rx_array[i][1];
1653 pm_pio->ireg_local_offset = t5_pm_rx_array[i][2];
1654 pm_pio->ireg_offset_range = t5_pm_rx_array[i][3];
1655 t4_read_indirect(padap,
1656 pm_pio->ireg_addr,
1657 pm_pio->ireg_data,
1658 buff,
1659 pm_pio->ireg_offset_range,
1660 pm_pio->ireg_local_offset);
1661 ch_pm++;
1662 }
1663
1664 /* PM_TX */
1665 n = sizeof(t5_pm_tx_array) / (IREG_NUM_ELEM * sizeof(u32));
1666 for (i = 0; i < n; i++) {
1667 struct ireg_field *pm_pio = &ch_pm->tp_pio;
1668 u32 *buff = ch_pm->outbuf;
1669
1670 pm_pio->ireg_addr = t5_pm_tx_array[i][0];
1671 pm_pio->ireg_data = t5_pm_tx_array[i][1];
1672 pm_pio->ireg_local_offset = t5_pm_tx_array[i][2];
1673 pm_pio->ireg_offset_range = t5_pm_tx_array[i][3];
1674 t4_read_indirect(padap,
1675 pm_pio->ireg_addr,
1676 pm_pio->ireg_data,
1677 buff,
1678 pm_pio->ireg_offset_range,
1679 pm_pio->ireg_local_offset);
1680 ch_pm++;
1681 }
1682 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1683 }
1684
1685 int cudbg_collect_tid(struct cudbg_init *pdbg_init,
1686 struct cudbg_buffer *dbg_buff,
1687 struct cudbg_error *cudbg_err)
1688 {
1689 struct adapter *padap = pdbg_init->adap;
1690 struct cudbg_tid_info_region_rev1 *tid1;
1691 struct cudbg_buffer temp_buff = { 0 };
1692 struct cudbg_tid_info_region *tid;
1693 u32 para[2], val[2];
1694 int rc;
1695
1696 rc = cudbg_get_buff(pdbg_init, dbg_buff,
1697 sizeof(struct cudbg_tid_info_region_rev1),
1698 &temp_buff);
1699 if (rc)
1700 return rc;
1701
1702 tid1 = (struct cudbg_tid_info_region_rev1 *)temp_buff.data;
1703 tid = &tid1->tid;
1704 tid1->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
1705 tid1->ver_hdr.revision = CUDBG_TID_INFO_REV;
1706 tid1->ver_hdr.size = sizeof(struct cudbg_tid_info_region_rev1) -
1707 sizeof(struct cudbg_ver_hdr);
1708
1709 /* If firmware is not attached/alive, use backdoor register
1710 * access to collect dump.
1711 */
1712 if (!is_fw_attached(pdbg_init))
1713 goto fill_tid;
1714
1715 #define FW_PARAM_PFVF_A(param) \
1716 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
1717 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \
1718 FW_PARAMS_PARAM_Y_V(0) | \
1719 FW_PARAMS_PARAM_Z_V(0))
1720
1721 para[0] = FW_PARAM_PFVF_A(ETHOFLD_START);
1722 para[1] = FW_PARAM_PFVF_A(ETHOFLD_END);
1723 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val);
1724 if (rc < 0) {
1725 cudbg_err->sys_err = rc;
1726 cudbg_put_buff(pdbg_init, &temp_buff);
1727 return rc;
1728 }
1729 tid->uotid_base = val[0];
1730 tid->nuotids = val[1] - val[0] + 1;
1731
1732 if (is_t5(padap->params.chip)) {
1733 tid->sb = t4_read_reg(padap, LE_DB_SERVER_INDEX_A) / 4;
1734 } else if (is_t6(padap->params.chip)) {
1735 tid1->tid_start =
1736 t4_read_reg(padap, LE_DB_ACTIVE_TABLE_START_INDEX_A);
1737 tid->sb = t4_read_reg(padap, LE_DB_SRVR_START_INDEX_A);
1738
1739 para[0] = FW_PARAM_PFVF_A(HPFILTER_START);
1740 para[1] = FW_PARAM_PFVF_A(HPFILTER_END);
1741 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2,
1742 para, val);
1743 if (rc < 0) {
1744 cudbg_err->sys_err = rc;
1745 cudbg_put_buff(pdbg_init, &temp_buff);
1746 return rc;
1747 }
1748 tid->hpftid_base = val[0];
1749 tid->nhpftids = val[1] - val[0] + 1;
1750 }
1751
1752 #undef FW_PARAM_PFVF_A
1753
1754 fill_tid:
1755 tid->ntids = padap->tids.ntids;
1756 tid->nstids = padap->tids.nstids;
1757 tid->stid_base = padap->tids.stid_base;
1758 tid->hash_base = padap->tids.hash_base;
1759
1760 tid->natids = padap->tids.natids;
1761 tid->nftids = padap->tids.nftids;
1762 tid->ftid_base = padap->tids.ftid_base;
1763 tid->aftid_base = padap->tids.aftid_base;
1764 tid->aftid_end = padap->tids.aftid_end;
1765
1766 tid->sftid_base = padap->tids.sftid_base;
1767 tid->nsftids = padap->tids.nsftids;
1768
1769 tid->flags = padap->flags;
1770 tid->le_db_conf = t4_read_reg(padap, LE_DB_CONFIG_A);
1771 tid->ip_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV4_A);
1772 tid->ipv6_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV6_A);
1773
1774 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1775 }
1776
1777 int cudbg_collect_pcie_config(struct cudbg_init *pdbg_init,
1778 struct cudbg_buffer *dbg_buff,
1779 struct cudbg_error *cudbg_err)
1780 {
1781 struct adapter *padap = pdbg_init->adap;
1782 struct cudbg_buffer temp_buff = { 0 };
1783 u32 size, *value, j;
1784 int i, rc, n;
1785
1786 size = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS;
1787 n = sizeof(t5_pcie_config_array) / (2 * sizeof(u32));
1788 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1789 if (rc)
1790 return rc;
1791
1792 value = (u32 *)temp_buff.data;
1793 for (i = 0; i < n; i++) {
1794 for (j = t5_pcie_config_array[i][0];
1795 j <= t5_pcie_config_array[i][1]; j += 4) {
1796 t4_hw_pci_read_cfg4(padap, j, value);
1797 value++;
1798 }
1799 }
1800 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1801 }
1802
1803 static int cudbg_sge_ctxt_check_valid(u32 *buf, int type)
1804 {
1805 int index, bit, bit_pos = 0;
1806
1807 switch (type) {
1808 case CTXT_EGRESS:
1809 bit_pos = 176;
1810 break;
1811 case CTXT_INGRESS:
1812 bit_pos = 141;
1813 break;
1814 case CTXT_FLM:
1815 bit_pos = 89;
1816 break;
1817 }
1818 index = bit_pos / 32;
1819 bit = bit_pos % 32;
1820 return buf[index] & (1U << bit);
1821 }
1822
1823 static int cudbg_get_ctxt_region_info(struct adapter *padap,
1824 struct cudbg_region_info *ctx_info,
1825 u8 *mem_type)
1826 {
1827 struct cudbg_mem_desc mem_desc;
1828 struct cudbg_meminfo meminfo;
1829 u32 i, j, value, found;
1830 u8 flq;
1831 int rc;
1832
1833 rc = cudbg_fill_meminfo(padap, &meminfo);
1834 if (rc)
1835 return rc;
1836
1837 /* Get EGRESS and INGRESS context region size */
1838 for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) {
1839 found = 0;
1840 memset(&mem_desc, 0, sizeof(struct cudbg_mem_desc));
1841 for (j = 0; j < ARRAY_SIZE(meminfo.avail); j++) {
1842 rc = cudbg_get_mem_region(padap, &meminfo, j,
1843 cudbg_region[i],
1844 &mem_desc);
1845 if (!rc) {
1846 found = 1;
1847 rc = cudbg_get_mem_relative(padap, &meminfo, j,
1848 &mem_desc.base,
1849 &mem_desc.limit);
1850 if (rc) {
1851 ctx_info[i].exist = false;
1852 break;
1853 }
1854 ctx_info[i].exist = true;
1855 ctx_info[i].start = mem_desc.base;
1856 ctx_info[i].end = mem_desc.limit;
1857 mem_type[i] = j;
1858 break;
1859 }
1860 }
1861 if (!found)
1862 ctx_info[i].exist = false;
1863 }
1864
1865 /* Get FLM and CNM max qid. */
1866 value = t4_read_reg(padap, SGE_FLM_CFG_A);
1867
1868 /* Get number of data freelist queues */
1869 flq = HDRSTARTFLQ_G(value);
1870 ctx_info[CTXT_FLM].exist = true;
1871 ctx_info[CTXT_FLM].end = (CUDBG_MAX_FL_QIDS >> flq) * SGE_CTXT_SIZE;
1872
1873 /* The number of CONM contexts are same as number of freelist
1874 * queues.
1875 */
1876 ctx_info[CTXT_CNM].exist = true;
1877 ctx_info[CTXT_CNM].end = ctx_info[CTXT_FLM].end;
1878
1879 return 0;
1880 }
1881
1882 int cudbg_dump_context_size(struct adapter *padap)
1883 {
1884 struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
1885 u8 mem_type[CTXT_INGRESS + 1] = { 0 };
1886 u32 i, size = 0;
1887 int rc;
1888
1889 /* Get max valid qid for each type of queue */
1890 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
1891 if (rc)
1892 return rc;
1893
1894 for (i = 0; i < CTXT_CNM; i++) {
1895 if (!region_info[i].exist) {
1896 if (i == CTXT_EGRESS || i == CTXT_INGRESS)
1897 size += CUDBG_LOWMEM_MAX_CTXT_QIDS *
1898 SGE_CTXT_SIZE;
1899 continue;
1900 }
1901
1902 size += (region_info[i].end - region_info[i].start + 1) /
1903 SGE_CTXT_SIZE;
1904 }
1905 return size * sizeof(struct cudbg_ch_cntxt);
1906 }
1907
1908 static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid,
1909 enum ctxt_type ctype, u32 *data)
1910 {
1911 struct adapter *padap = pdbg_init->adap;
1912 int rc = -1;
1913
1914 /* Under heavy traffic, the SGE Queue contexts registers will be
1915 * frequently accessed by firmware.
1916 *
1917 * To avoid conflicts with firmware, always ask firmware to fetch
1918 * the SGE Queue contexts via mailbox. On failure, fallback to
1919 * accessing hardware registers directly.
1920 */
1921 if (is_fw_attached(pdbg_init))
1922 rc = t4_sge_ctxt_rd(padap, padap->mbox, cid, ctype, data);
1923 if (rc)
1924 t4_sge_ctxt_rd_bd(padap, cid, ctype, data);
1925 }
1926
1927 static void cudbg_get_sge_ctxt_fw(struct cudbg_init *pdbg_init, u32 max_qid,
1928 u8 ctxt_type,
1929 struct cudbg_ch_cntxt **out_buff)
1930 {
1931 struct cudbg_ch_cntxt *buff = *out_buff;
1932 int rc;
1933 u32 j;
1934
1935 for (j = 0; j < max_qid; j++) {
1936 cudbg_read_sge_ctxt(pdbg_init, j, ctxt_type, buff->data);
1937 rc = cudbg_sge_ctxt_check_valid(buff->data, ctxt_type);
1938 if (!rc)
1939 continue;
1940
1941 buff->cntxt_type = ctxt_type;
1942 buff->cntxt_id = j;
1943 buff++;
1944 if (ctxt_type == CTXT_FLM) {
1945 cudbg_read_sge_ctxt(pdbg_init, j, CTXT_CNM, buff->data);
1946 buff->cntxt_type = CTXT_CNM;
1947 buff->cntxt_id = j;
1948 buff++;
1949 }
1950 }
1951
1952 *out_buff = buff;
1953 }
1954
1955 int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
1956 struct cudbg_buffer *dbg_buff,
1957 struct cudbg_error *cudbg_err)
1958 {
1959 struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
1960 struct adapter *padap = pdbg_init->adap;
1961 u32 j, size, max_ctx_size, max_ctx_qid;
1962 u8 mem_type[CTXT_INGRESS + 1] = { 0 };
1963 struct cudbg_buffer temp_buff = { 0 };
1964 struct cudbg_ch_cntxt *buff;
1965 u64 *dst_off, *src_off;
1966 u8 *ctx_buf;
1967 u8 i, k;
1968 int rc;
1969
1970 /* Get max valid qid for each type of queue */
1971 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
1972 if (rc)
1973 return rc;
1974
1975 rc = cudbg_dump_context_size(padap);
1976 if (rc <= 0)
1977 return CUDBG_STATUS_ENTITY_NOT_FOUND;
1978
1979 size = rc;
1980 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1981 if (rc)
1982 return rc;
1983
1984 /* Get buffer with enough space to read the biggest context
1985 * region in memory.
1986 */
1987 max_ctx_size = max(region_info[CTXT_EGRESS].end -
1988 region_info[CTXT_EGRESS].start + 1,
1989 region_info[CTXT_INGRESS].end -
1990 region_info[CTXT_INGRESS].start + 1);
1991
1992 ctx_buf = kvzalloc(max_ctx_size, GFP_KERNEL);
1993 if (!ctx_buf) {
1994 cudbg_put_buff(pdbg_init, &temp_buff);
1995 return -ENOMEM;
1996 }
1997
1998 buff = (struct cudbg_ch_cntxt *)temp_buff.data;
1999
2000 /* Collect EGRESS and INGRESS context data.
2001 * In case of failures, fallback to collecting via FW or
2002 * backdoor access.
2003 */
2004 for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) {
2005 if (!region_info[i].exist) {
2006 max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
2007 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
2008 &buff);
2009 continue;
2010 }
2011
2012 max_ctx_size = region_info[i].end - region_info[i].start + 1;
2013 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
2014
2015 /* If firmware is not attached/alive, use backdoor register
2016 * access to collect dump.
2017 */
2018 if (is_fw_attached(pdbg_init)) {
2019 t4_sge_ctxt_flush(padap, padap->mbox, i);
2020
2021 rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type[i],
2022 region_info[i].start, max_ctx_size,
2023 (__be32 *)ctx_buf, 1);
2024 }
2025
2026 if (rc || !is_fw_attached(pdbg_init)) {
2027 max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
2028 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
2029 &buff);
2030 continue;
2031 }
2032
2033 for (j = 0; j < max_ctx_qid; j++) {
2034 src_off = (u64 *)(ctx_buf + j * SGE_CTXT_SIZE);
2035 dst_off = (u64 *)buff->data;
2036
2037 /* The data is stored in 64-bit cpu order. Convert it
2038 * to big endian before parsing.
2039 */
2040 for (k = 0; k < SGE_CTXT_SIZE / sizeof(u64); k++)
2041 dst_off[k] = cpu_to_be64(src_off[k]);
2042
2043 rc = cudbg_sge_ctxt_check_valid(buff->data, i);
2044 if (!rc)
2045 continue;
2046
2047 buff->cntxt_type = i;
2048 buff->cntxt_id = j;
2049 buff++;
2050 }
2051 }
2052
2053 kvfree(ctx_buf);
2054
2055 /* Collect FREELIST and CONGESTION MANAGER contexts */
2056 max_ctx_size = region_info[CTXT_FLM].end -
2057 region_info[CTXT_FLM].start + 1;
2058 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
2059 /* Since FLM and CONM are 1-to-1 mapped, the below function
2060 * will fetch both FLM and CONM contexts.
2061 */
2062 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, CTXT_FLM, &buff);
2063
2064 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2065 }
2066
2067 static inline void cudbg_tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)
2068 {
2069 *mask = x | y;
2070 y = (__force u64)cpu_to_be64(y);
2071 memcpy(addr, (char *)&y + 2, ETH_ALEN);
2072 }
2073
2074 static void cudbg_mps_rpl_backdoor(struct adapter *padap,
2075 struct fw_ldst_mps_rplc *mps_rplc)
2076 {
2077 if (is_t5(padap->params.chip)) {
2078 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
2079 MPS_VF_RPLCT_MAP3_A));
2080 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
2081 MPS_VF_RPLCT_MAP2_A));
2082 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
2083 MPS_VF_RPLCT_MAP1_A));
2084 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
2085 MPS_VF_RPLCT_MAP0_A));
2086 } else {
2087 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
2088 MPS_VF_RPLCT_MAP7_A));
2089 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
2090 MPS_VF_RPLCT_MAP6_A));
2091 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
2092 MPS_VF_RPLCT_MAP5_A));
2093 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
2094 MPS_VF_RPLCT_MAP4_A));
2095 }
2096 mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP3_A));
2097 mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP2_A));
2098 mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP1_A));
2099 mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP0_A));
2100 }
2101
2102 static int cudbg_collect_tcam_index(struct cudbg_init *pdbg_init,
2103 struct cudbg_mps_tcam *tcam, u32 idx)
2104 {
2105 struct adapter *padap = pdbg_init->adap;
2106 u64 tcamy, tcamx, val;
2107 u32 ctl, data2;
2108 int rc = 0;
2109
2110 if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) {
2111 /* CtlReqID - 1: use Host Driver Requester ID
2112 * CtlCmdType - 0: Read, 1: Write
2113 * CtlTcamSel - 0: TCAM0, 1: TCAM1
2114 * CtlXYBitSel- 0: Y bit, 1: X bit
2115 */
2116
2117 /* Read tcamy */
2118 ctl = CTLREQID_V(1) | CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0);
2119 if (idx < 256)
2120 ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0);
2121 else
2122 ctl |= CTLTCAMINDEX_V(idx - 256) | CTLTCAMSEL_V(1);
2123
2124 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
2125 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
2126 tcamy = DMACH_G(val) << 32;
2127 tcamy |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
2128 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
2129 tcam->lookup_type = DATALKPTYPE_G(data2);
2130
2131 /* 0 - Outer header, 1 - Inner header
2132 * [71:48] bit locations are overloaded for
2133 * outer vs. inner lookup types.
2134 */
2135 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) {
2136 /* Inner header VNI */
2137 tcam->vniy = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2);
2138 tcam->vniy = (tcam->vniy << 16) | VIDL_G(val);
2139 tcam->dip_hit = data2 & DATADIPHIT_F;
2140 } else {
2141 tcam->vlan_vld = data2 & DATAVIDH2_F;
2142 tcam->ivlan = VIDL_G(val);
2143 }
2144
2145 tcam->port_num = DATAPORTNUM_G(data2);
2146
2147 /* Read tcamx. Change the control param */
2148 ctl |= CTLXYBITSEL_V(1);
2149 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
2150 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
2151 tcamx = DMACH_G(val) << 32;
2152 tcamx |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
2153 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
2154 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) {
2155 /* Inner header VNI mask */
2156 tcam->vnix = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2);
2157 tcam->vnix = (tcam->vnix << 16) | VIDL_G(val);
2158 }
2159 } else {
2160 tcamy = t4_read_reg64(padap, MPS_CLS_TCAM_Y_L(idx));
2161 tcamx = t4_read_reg64(padap, MPS_CLS_TCAM_X_L(idx));
2162 }
2163
2164 /* If no entry, return */
2165 if (tcamx & tcamy)
2166 return rc;
2167
2168 tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx));
2169 tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx));
2170
2171 if (is_t5(padap->params.chip))
2172 tcam->repli = (tcam->cls_lo & REPLICATE_F);
2173 else if (is_t6(padap->params.chip))
2174 tcam->repli = (tcam->cls_lo & T6_REPLICATE_F);
2175
2176 if (tcam->repli) {
2177 struct fw_ldst_cmd ldst_cmd;
2178 struct fw_ldst_mps_rplc mps_rplc;
2179
2180 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
2181 ldst_cmd.op_to_addrspace =
2182 htonl(FW_CMD_OP_V(FW_LDST_CMD) |
2183 FW_CMD_REQUEST_F | FW_CMD_READ_F |
2184 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS));
2185 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
2186 ldst_cmd.u.mps.rplc.fid_idx =
2187 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) |
2188 FW_LDST_CMD_IDX_V(idx));
2189
2190 /* If firmware is not attached/alive, use backdoor register
2191 * access to collect dump.
2192 */
2193 if (is_fw_attached(pdbg_init))
2194 rc = t4_wr_mbox(padap, padap->mbox, &ldst_cmd,
2195 sizeof(ldst_cmd), &ldst_cmd);
2196
2197 if (rc || !is_fw_attached(pdbg_init)) {
2198 cudbg_mps_rpl_backdoor(padap, &mps_rplc);
2199 /* Ignore error since we collected directly from
2200 * reading registers.
2201 */
2202 rc = 0;
2203 } else {
2204 mps_rplc = ldst_cmd.u.mps.rplc;
2205 }
2206
2207 tcam->rplc[0] = ntohl(mps_rplc.rplc31_0);
2208 tcam->rplc[1] = ntohl(mps_rplc.rplc63_32);
2209 tcam->rplc[2] = ntohl(mps_rplc.rplc95_64);
2210 tcam->rplc[3] = ntohl(mps_rplc.rplc127_96);
2211 if (padap->params.arch.mps_rplc_size > CUDBG_MAX_RPLC_SIZE) {
2212 tcam->rplc[4] = ntohl(mps_rplc.rplc159_128);
2213 tcam->rplc[5] = ntohl(mps_rplc.rplc191_160);
2214 tcam->rplc[6] = ntohl(mps_rplc.rplc223_192);
2215 tcam->rplc[7] = ntohl(mps_rplc.rplc255_224);
2216 }
2217 }
2218 cudbg_tcamxy2valmask(tcamx, tcamy, tcam->addr, &tcam->mask);
2219 tcam->idx = idx;
2220 tcam->rplc_size = padap->params.arch.mps_rplc_size;
2221 return rc;
2222 }
2223
2224 int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init,
2225 struct cudbg_buffer *dbg_buff,
2226 struct cudbg_error *cudbg_err)
2227 {
2228 struct adapter *padap = pdbg_init->adap;
2229 struct cudbg_buffer temp_buff = { 0 };
2230 u32 size = 0, i, n, total_size = 0;
2231 struct cudbg_mps_tcam *tcam;
2232 int rc;
2233
2234 n = padap->params.arch.mps_tcam_size;
2235 size = sizeof(struct cudbg_mps_tcam) * n;
2236 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2237 if (rc)
2238 return rc;
2239
2240 tcam = (struct cudbg_mps_tcam *)temp_buff.data;
2241 for (i = 0; i < n; i++) {
2242 rc = cudbg_collect_tcam_index(pdbg_init, tcam, i);
2243 if (rc) {
2244 cudbg_err->sys_err = rc;
2245 cudbg_put_buff(pdbg_init, &temp_buff);
2246 return rc;
2247 }
2248 total_size += sizeof(struct cudbg_mps_tcam);
2249 tcam++;
2250 }
2251
2252 if (!total_size) {
2253 rc = CUDBG_SYSTEM_ERROR;
2254 cudbg_err->sys_err = rc;
2255 cudbg_put_buff(pdbg_init, &temp_buff);
2256 return rc;
2257 }
2258 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2259 }
2260
2261 int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init,
2262 struct cudbg_buffer *dbg_buff,
2263 struct cudbg_error *cudbg_err)
2264 {
2265 struct adapter *padap = pdbg_init->adap;
2266 struct cudbg_buffer temp_buff = { 0 };
2267 char vpd_str[CUDBG_VPD_VER_LEN + 1];
2268 u32 scfg_vers, vpd_vers, fw_vers;
2269 struct cudbg_vpd_data *vpd_data;
2270 struct vpd_params vpd = { 0 };
2271 int rc, ret;
2272
2273 rc = t4_get_raw_vpd_params(padap, &vpd);
2274 if (rc)
2275 return rc;
2276
2277 rc = t4_get_fw_version(padap, &fw_vers);
2278 if (rc)
2279 return rc;
2280
2281 /* Serial Configuration Version is located beyond the PF's vpd size.
2282 * Temporarily give access to entire EEPROM to get it.
2283 */
2284 rc = pci_set_vpd_size(padap->pdev, EEPROMVSIZE);
2285 if (rc < 0)
2286 return rc;
2287
2288 ret = cudbg_read_vpd_reg(padap, CUDBG_SCFG_VER_ADDR, CUDBG_SCFG_VER_LEN,
2289 &scfg_vers);
2290
2291 /* Restore back to original PF's vpd size */
2292 rc = pci_set_vpd_size(padap->pdev, CUDBG_VPD_PF_SIZE);
2293 if (rc < 0)
2294 return rc;
2295
2296 if (ret)
2297 return ret;
2298
2299 rc = cudbg_read_vpd_reg(padap, CUDBG_VPD_VER_ADDR, CUDBG_VPD_VER_LEN,
2300 vpd_str);
2301 if (rc)
2302 return rc;
2303
2304 vpd_str[CUDBG_VPD_VER_LEN] = '\0';
2305 rc = kstrtouint(vpd_str, 0, &vpd_vers);
2306 if (rc)
2307 return rc;
2308
2309 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_vpd_data),
2310 &temp_buff);
2311 if (rc)
2312 return rc;
2313
2314 vpd_data = (struct cudbg_vpd_data *)temp_buff.data;
2315 memcpy(vpd_data->sn, vpd.sn, SERNUM_LEN + 1);
2316 memcpy(vpd_data->bn, vpd.pn, PN_LEN + 1);
2317 memcpy(vpd_data->na, vpd.na, MACADDR_LEN + 1);
2318 memcpy(vpd_data->mn, vpd.id, ID_LEN + 1);
2319 vpd_data->scfg_vers = scfg_vers;
2320 vpd_data->vpd_vers = vpd_vers;
2321 vpd_data->fw_major = FW_HDR_FW_VER_MAJOR_G(fw_vers);
2322 vpd_data->fw_minor = FW_HDR_FW_VER_MINOR_G(fw_vers);
2323 vpd_data->fw_micro = FW_HDR_FW_VER_MICRO_G(fw_vers);
2324 vpd_data->fw_build = FW_HDR_FW_VER_BUILD_G(fw_vers);
2325 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2326 }
2327
2328 static int cudbg_read_tid(struct cudbg_init *pdbg_init, u32 tid,
2329 struct cudbg_tid_data *tid_data)
2330 {
2331 struct adapter *padap = pdbg_init->adap;
2332 int i, cmd_retry = 8;
2333 u32 val;
2334
2335 /* Fill REQ_DATA regs with 0's */
2336 for (i = 0; i < NUM_LE_DB_DBGI_REQ_DATA_INSTANCES; i++)
2337 t4_write_reg(padap, LE_DB_DBGI_REQ_DATA_A + (i << 2), 0);
2338
2339 /* Write DBIG command */
2340 val = DBGICMD_V(4) | DBGITID_V(tid);
2341 t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val);
2342 tid_data->dbig_cmd = val;
2343
2344 val = DBGICMDSTRT_F | DBGICMDMODE_V(1); /* LE mode */
2345 t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val);
2346 tid_data->dbig_conf = val;
2347
2348 /* Poll the DBGICMDBUSY bit */
2349 val = 1;
2350 while (val) {
2351 val = t4_read_reg(padap, LE_DB_DBGI_CONFIG_A);
2352 val = val & DBGICMDBUSY_F;
2353 cmd_retry--;
2354 if (!cmd_retry)
2355 return CUDBG_SYSTEM_ERROR;
2356 }
2357
2358 /* Check RESP status */
2359 val = t4_read_reg(padap, LE_DB_DBGI_RSP_STATUS_A);
2360 tid_data->dbig_rsp_stat = val;
2361 if (!(val & 1))
2362 return CUDBG_SYSTEM_ERROR;
2363
2364 /* Read RESP data */
2365 for (i = 0; i < NUM_LE_DB_DBGI_RSP_DATA_INSTANCES; i++)
2366 tid_data->data[i] = t4_read_reg(padap,
2367 LE_DB_DBGI_RSP_DATA_A +
2368 (i << 2));
2369 tid_data->tid = tid;
2370 return 0;
2371 }
2372
2373 static int cudbg_get_le_type(u32 tid, struct cudbg_tcam tcam_region)
2374 {
2375 int type = LE_ET_UNKNOWN;
2376
2377 if (tid < tcam_region.server_start)
2378 type = LE_ET_TCAM_CON;
2379 else if (tid < tcam_region.filter_start)
2380 type = LE_ET_TCAM_SERVER;
2381 else if (tid < tcam_region.clip_start)
2382 type = LE_ET_TCAM_FILTER;
2383 else if (tid < tcam_region.routing_start)
2384 type = LE_ET_TCAM_CLIP;
2385 else if (tid < tcam_region.tid_hash_base)
2386 type = LE_ET_TCAM_ROUTING;
2387 else if (tid < tcam_region.max_tid)
2388 type = LE_ET_HASH_CON;
2389 else
2390 type = LE_ET_INVALID_TID;
2391
2392 return type;
2393 }
2394
2395 static int cudbg_is_ipv6_entry(struct cudbg_tid_data *tid_data,
2396 struct cudbg_tcam tcam_region)
2397 {
2398 int ipv6 = 0;
2399 int le_type;
2400
2401 le_type = cudbg_get_le_type(tid_data->tid, tcam_region);
2402 if (tid_data->tid & 1)
2403 return 0;
2404
2405 if (le_type == LE_ET_HASH_CON) {
2406 ipv6 = tid_data->data[16] & 0x8000;
2407 } else if (le_type == LE_ET_TCAM_CON) {
2408 ipv6 = tid_data->data[16] & 0x8000;
2409 if (ipv6)
2410 ipv6 = tid_data->data[9] == 0x00C00000;
2411 } else {
2412 ipv6 = 0;
2413 }
2414 return ipv6;
2415 }
2416
2417 void cudbg_fill_le_tcam_info(struct adapter *padap,
2418 struct cudbg_tcam *tcam_region)
2419 {
2420 u32 value;
2421
2422 /* Get the LE regions */
2423 value = t4_read_reg(padap, LE_DB_TID_HASHBASE_A); /* hash base index */
2424 tcam_region->tid_hash_base = value;
2425
2426 /* Get routing table index */
2427 value = t4_read_reg(padap, LE_DB_ROUTING_TABLE_INDEX_A);
2428 tcam_region->routing_start = value;
2429
2430 /* Get clip table index. For T6 there is separate CLIP TCAM */
2431 if (is_t6(padap->params.chip))
2432 value = t4_read_reg(padap, LE_DB_CLCAM_TID_BASE_A);
2433 else
2434 value = t4_read_reg(padap, LE_DB_CLIP_TABLE_INDEX_A);
2435 tcam_region->clip_start = value;
2436
2437 /* Get filter table index */
2438 value = t4_read_reg(padap, LE_DB_FILTER_TABLE_INDEX_A);
2439 tcam_region->filter_start = value;
2440
2441 /* Get server table index */
2442 value = t4_read_reg(padap, LE_DB_SERVER_INDEX_A);
2443 tcam_region->server_start = value;
2444
2445 /* Check whether hash is enabled and calculate the max tids */
2446 value = t4_read_reg(padap, LE_DB_CONFIG_A);
2447 if ((value >> HASHEN_S) & 1) {
2448 value = t4_read_reg(padap, LE_DB_HASH_CONFIG_A);
2449 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
2450 tcam_region->max_tid = (value & 0xFFFFF) +
2451 tcam_region->tid_hash_base;
2452 } else {
2453 value = HASHTIDSIZE_G(value);
2454 value = 1 << value;
2455 tcam_region->max_tid = value +
2456 tcam_region->tid_hash_base;
2457 }
2458 } else { /* hash not enabled */
2459 if (is_t6(padap->params.chip))
2460 tcam_region->max_tid = (value & ASLIPCOMPEN_F) ?
2461 CUDBG_MAX_TID_COMP_EN :
2462 CUDBG_MAX_TID_COMP_DIS;
2463 else
2464 tcam_region->max_tid = CUDBG_MAX_TCAM_TID;
2465 }
2466
2467 if (is_t6(padap->params.chip))
2468 tcam_region->max_tid += CUDBG_T6_CLIP;
2469 }
2470
2471 int cudbg_collect_le_tcam(struct cudbg_init *pdbg_init,
2472 struct cudbg_buffer *dbg_buff,
2473 struct cudbg_error *cudbg_err)
2474 {
2475 struct adapter *padap = pdbg_init->adap;
2476 struct cudbg_buffer temp_buff = { 0 };
2477 struct cudbg_tcam tcam_region = { 0 };
2478 struct cudbg_tid_data *tid_data;
2479 u32 bytes = 0;
2480 int rc, size;
2481 u32 i;
2482
2483 cudbg_fill_le_tcam_info(padap, &tcam_region);
2484
2485 size = sizeof(struct cudbg_tid_data) * tcam_region.max_tid;
2486 size += sizeof(struct cudbg_tcam);
2487 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2488 if (rc)
2489 return rc;
2490
2491 memcpy(temp_buff.data, &tcam_region, sizeof(struct cudbg_tcam));
2492 bytes = sizeof(struct cudbg_tcam);
2493 tid_data = (struct cudbg_tid_data *)(temp_buff.data + bytes);
2494 /* read all tid */
2495 for (i = 0; i < tcam_region.max_tid; ) {
2496 rc = cudbg_read_tid(pdbg_init, i, tid_data);
2497 if (rc) {
2498 cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
2499 /* Update tcam header and exit */
2500 tcam_region.max_tid = i;
2501 memcpy(temp_buff.data, &tcam_region,
2502 sizeof(struct cudbg_tcam));
2503 goto out;
2504 }
2505
2506 if (cudbg_is_ipv6_entry(tid_data, tcam_region)) {
2507 /* T6 CLIP TCAM: ipv6 takes 4 entries */
2508 if (is_t6(padap->params.chip) &&
2509 i >= tcam_region.clip_start &&
2510 i < tcam_region.clip_start + CUDBG_T6_CLIP)
2511 i += 4;
2512 else /* Main TCAM: ipv6 takes two tids */
2513 i += 2;
2514 } else {
2515 i++;
2516 }
2517
2518 tid_data++;
2519 bytes += sizeof(struct cudbg_tid_data);
2520 }
2521
2522 out:
2523 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2524 }
2525
2526 int cudbg_collect_cctrl(struct cudbg_init *pdbg_init,
2527 struct cudbg_buffer *dbg_buff,
2528 struct cudbg_error *cudbg_err)
2529 {
2530 struct adapter *padap = pdbg_init->adap;
2531 struct cudbg_buffer temp_buff = { 0 };
2532 u32 size;
2533 int rc;
2534
2535 size = sizeof(u16) * NMTUS * NCCTRL_WIN;
2536 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2537 if (rc)
2538 return rc;
2539
2540 t4_read_cong_tbl(padap, (void *)temp_buff.data);
2541 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2542 }
2543
2544 int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
2545 struct cudbg_buffer *dbg_buff,
2546 struct cudbg_error *cudbg_err)
2547 {
2548 struct adapter *padap = pdbg_init->adap;
2549 struct cudbg_buffer temp_buff = { 0 };
2550 struct ireg_buf *ma_indr;
2551 int i, rc, n;
2552 u32 size, j;
2553
2554 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
2555 return CUDBG_STATUS_ENTITY_NOT_FOUND;
2556
2557 n = sizeof(t6_ma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
2558 size = sizeof(struct ireg_buf) * n * 2;
2559 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2560 if (rc)
2561 return rc;
2562
2563 ma_indr = (struct ireg_buf *)temp_buff.data;
2564 for (i = 0; i < n; i++) {
2565 struct ireg_field *ma_fli = &ma_indr->tp_pio;
2566 u32 *buff = ma_indr->outbuf;
2567
2568 ma_fli->ireg_addr = t6_ma_ireg_array[i][0];
2569 ma_fli->ireg_data = t6_ma_ireg_array[i][1];
2570 ma_fli->ireg_local_offset = t6_ma_ireg_array[i][2];
2571 ma_fli->ireg_offset_range = t6_ma_ireg_array[i][3];
2572 t4_read_indirect(padap, ma_fli->ireg_addr, ma_fli->ireg_data,
2573 buff, ma_fli->ireg_offset_range,
2574 ma_fli->ireg_local_offset);
2575 ma_indr++;
2576 }
2577
2578 n = sizeof(t6_ma_ireg_array2) / (IREG_NUM_ELEM * sizeof(u32));
2579 for (i = 0; i < n; i++) {
2580 struct ireg_field *ma_fli = &ma_indr->tp_pio;
2581 u32 *buff = ma_indr->outbuf;
2582
2583 ma_fli->ireg_addr = t6_ma_ireg_array2[i][0];
2584 ma_fli->ireg_data = t6_ma_ireg_array2[i][1];
2585 ma_fli->ireg_local_offset = t6_ma_ireg_array2[i][2];
2586 for (j = 0; j < t6_ma_ireg_array2[i][3]; j++) {
2587 t4_read_indirect(padap, ma_fli->ireg_addr,
2588 ma_fli->ireg_data, buff, 1,
2589 ma_fli->ireg_local_offset);
2590 buff++;
2591 ma_fli->ireg_local_offset += 0x20;
2592 }
2593 ma_indr++;
2594 }
2595 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2596 }
2597
2598 int cudbg_collect_ulptx_la(struct cudbg_init *pdbg_init,
2599 struct cudbg_buffer *dbg_buff,
2600 struct cudbg_error *cudbg_err)
2601 {
2602 struct adapter *padap = pdbg_init->adap;
2603 struct cudbg_buffer temp_buff = { 0 };
2604 struct cudbg_ulptx_la *ulptx_la_buff;
2605 struct cudbg_ver_hdr *ver_hdr;
2606 u32 i, j;
2607 int rc;
2608
2609 rc = cudbg_get_buff(pdbg_init, dbg_buff,
2610 sizeof(struct cudbg_ver_hdr) +
2611 sizeof(struct cudbg_ulptx_la),
2612 &temp_buff);
2613 if (rc)
2614 return rc;
2615
2616 ver_hdr = (struct cudbg_ver_hdr *)temp_buff.data;
2617 ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
2618 ver_hdr->revision = CUDBG_ULPTX_LA_REV;
2619 ver_hdr->size = sizeof(struct cudbg_ulptx_la);
2620
2621 ulptx_la_buff = (struct cudbg_ulptx_la *)(temp_buff.data +
2622 sizeof(*ver_hdr));
2623 for (i = 0; i < CUDBG_NUM_ULPTX; i++) {
2624 ulptx_la_buff->rdptr[i] = t4_read_reg(padap,
2625 ULP_TX_LA_RDPTR_0_A +
2626 0x10 * i);
2627 ulptx_la_buff->wrptr[i] = t4_read_reg(padap,
2628 ULP_TX_LA_WRPTR_0_A +
2629 0x10 * i);
2630 ulptx_la_buff->rddata[i] = t4_read_reg(padap,
2631 ULP_TX_LA_RDDATA_0_A +
2632 0x10 * i);
2633 for (j = 0; j < CUDBG_NUM_ULPTX_READ; j++)
2634 ulptx_la_buff->rd_data[i][j] =
2635 t4_read_reg(padap,
2636 ULP_TX_LA_RDDATA_0_A + 0x10 * i);
2637 }
2638
2639 for (i = 0; i < CUDBG_NUM_ULPTX_ASIC_READ; i++) {
2640 t4_write_reg(padap, ULP_TX_ASIC_DEBUG_CTRL_A, 0x1);
2641 ulptx_la_buff->rdptr_asic[i] =
2642 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_CTRL_A);
2643 ulptx_la_buff->rddata_asic[i][0] =
2644 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_0_A);
2645 ulptx_la_buff->rddata_asic[i][1] =
2646 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_1_A);
2647 ulptx_la_buff->rddata_asic[i][2] =
2648 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_2_A);
2649 ulptx_la_buff->rddata_asic[i][3] =
2650 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_3_A);
2651 ulptx_la_buff->rddata_asic[i][4] =
2652 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_4_A);
2653 ulptx_la_buff->rddata_asic[i][5] =
2654 t4_read_reg(padap, PM_RX_BASE_ADDR);
2655 }
2656
2657 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2658 }
2659
2660 int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init,
2661 struct cudbg_buffer *dbg_buff,
2662 struct cudbg_error *cudbg_err)
2663 {
2664 struct adapter *padap = pdbg_init->adap;
2665 struct cudbg_buffer temp_buff = { 0 };
2666 u32 local_offset, local_range;
2667 struct ireg_buf *up_cim;
2668 u32 size, j, iter;
2669 u32 instance = 0;
2670 int i, rc, n;
2671
2672 if (is_t5(padap->params.chip))
2673 n = sizeof(t5_up_cim_reg_array) /
2674 ((IREG_NUM_ELEM + 1) * sizeof(u32));
2675 else if (is_t6(padap->params.chip))
2676 n = sizeof(t6_up_cim_reg_array) /
2677 ((IREG_NUM_ELEM + 1) * sizeof(u32));
2678 else
2679 return CUDBG_STATUS_NOT_IMPLEMENTED;
2680
2681 size = sizeof(struct ireg_buf) * n;
2682 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2683 if (rc)
2684 return rc;
2685
2686 up_cim = (struct ireg_buf *)temp_buff.data;
2687 for (i = 0; i < n; i++) {
2688 struct ireg_field *up_cim_reg = &up_cim->tp_pio;
2689 u32 *buff = up_cim->outbuf;
2690
2691 if (is_t5(padap->params.chip)) {
2692 up_cim_reg->ireg_addr = t5_up_cim_reg_array[i][0];
2693 up_cim_reg->ireg_data = t5_up_cim_reg_array[i][1];
2694 up_cim_reg->ireg_local_offset =
2695 t5_up_cim_reg_array[i][2];
2696 up_cim_reg->ireg_offset_range =
2697 t5_up_cim_reg_array[i][3];
2698 instance = t5_up_cim_reg_array[i][4];
2699 } else if (is_t6(padap->params.chip)) {
2700 up_cim_reg->ireg_addr = t6_up_cim_reg_array[i][0];
2701 up_cim_reg->ireg_data = t6_up_cim_reg_array[i][1];
2702 up_cim_reg->ireg_local_offset =
2703 t6_up_cim_reg_array[i][2];
2704 up_cim_reg->ireg_offset_range =
2705 t6_up_cim_reg_array[i][3];
2706 instance = t6_up_cim_reg_array[i][4];
2707 }
2708
2709 switch (instance) {
2710 case NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES:
2711 iter = up_cim_reg->ireg_offset_range;
2712 local_offset = 0x120;
2713 local_range = 1;
2714 break;
2715 case NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES:
2716 iter = up_cim_reg->ireg_offset_range;
2717 local_offset = 0x10;
2718 local_range = 1;
2719 break;
2720 default:
2721 iter = 1;
2722 local_offset = 0;
2723 local_range = up_cim_reg->ireg_offset_range;
2724 break;
2725 }
2726
2727 for (j = 0; j < iter; j++, buff++) {
2728 rc = t4_cim_read(padap,
2729 up_cim_reg->ireg_local_offset +
2730 (j * local_offset), local_range, buff);
2731 if (rc) {
2732 cudbg_put_buff(pdbg_init, &temp_buff);
2733 return rc;
2734 }
2735 }
2736 up_cim++;
2737 }
2738 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2739 }
2740
2741 int cudbg_collect_pbt_tables(struct cudbg_init *pdbg_init,
2742 struct cudbg_buffer *dbg_buff,
2743 struct cudbg_error *cudbg_err)
2744 {
2745 struct adapter *padap = pdbg_init->adap;
2746 struct cudbg_buffer temp_buff = { 0 };
2747 struct cudbg_pbt_tables *pbt;
2748 int i, rc;
2749 u32 addr;
2750
2751 rc = cudbg_get_buff(pdbg_init, dbg_buff,
2752 sizeof(struct cudbg_pbt_tables),
2753 &temp_buff);
2754 if (rc)
2755 return rc;
2756
2757 pbt = (struct cudbg_pbt_tables *)temp_buff.data;
2758 /* PBT dynamic entries */
2759 addr = CUDBG_CHAC_PBT_ADDR;
2760 for (i = 0; i < CUDBG_PBT_DYNAMIC_ENTRIES; i++) {
2761 rc = t4_cim_read(padap, addr + (i * 4), 1,
2762 &pbt->pbt_dynamic[i]);
2763 if (rc) {
2764 cudbg_err->sys_err = rc;
2765 cudbg_put_buff(pdbg_init, &temp_buff);
2766 return rc;
2767 }
2768 }
2769
2770 /* PBT static entries */
2771 /* static entries start when bit 6 is set */
2772 addr = CUDBG_CHAC_PBT_ADDR + (1 << 6);
2773 for (i = 0; i < CUDBG_PBT_STATIC_ENTRIES; i++) {
2774 rc = t4_cim_read(padap, addr + (i * 4), 1,
2775 &pbt->pbt_static[i]);
2776 if (rc) {
2777 cudbg_err->sys_err = rc;
2778 cudbg_put_buff(pdbg_init, &temp_buff);
2779 return rc;
2780 }
2781 }
2782
2783 /* LRF entries */
2784 addr = CUDBG_CHAC_PBT_LRF;
2785 for (i = 0; i < CUDBG_LRF_ENTRIES; i++) {
2786 rc = t4_cim_read(padap, addr + (i * 4), 1,
2787 &pbt->lrf_table[i]);
2788 if (rc) {
2789 cudbg_err->sys_err = rc;
2790 cudbg_put_buff(pdbg_init, &temp_buff);
2791 return rc;
2792 }
2793 }
2794
2795 /* PBT data entries */
2796 addr = CUDBG_CHAC_PBT_DATA;
2797 for (i = 0; i < CUDBG_PBT_DATA_ENTRIES; i++) {
2798 rc = t4_cim_read(padap, addr + (i * 4), 1,
2799 &pbt->pbt_data[i]);
2800 if (rc) {
2801 cudbg_err->sys_err = rc;
2802 cudbg_put_buff(pdbg_init, &temp_buff);
2803 return rc;
2804 }
2805 }
2806 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2807 }
2808
2809 int cudbg_collect_mbox_log(struct cudbg_init *pdbg_init,
2810 struct cudbg_buffer *dbg_buff,
2811 struct cudbg_error *cudbg_err)
2812 {
2813 struct adapter *padap = pdbg_init->adap;
2814 struct cudbg_mbox_log *mboxlog = NULL;
2815 struct cudbg_buffer temp_buff = { 0 };
2816 struct mbox_cmd_log *log = NULL;
2817 struct mbox_cmd *entry;
2818 unsigned int entry_idx;
2819 u16 mbox_cmds;
2820 int i, k, rc;
2821 u64 flit;
2822 u32 size;
2823
2824 log = padap->mbox_log;
2825 mbox_cmds = padap->mbox_log->size;
2826 size = sizeof(struct cudbg_mbox_log) * mbox_cmds;
2827 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2828 if (rc)
2829 return rc;
2830
2831 mboxlog = (struct cudbg_mbox_log *)temp_buff.data;
2832 for (k = 0; k < mbox_cmds; k++) {
2833 entry_idx = log->cursor + k;
2834 if (entry_idx >= log->size)
2835 entry_idx -= log->size;
2836
2837 entry = mbox_cmd_log_entry(log, entry_idx);
2838 /* skip over unused entries */
2839 if (entry->timestamp == 0)
2840 continue;
2841
2842 memcpy(&mboxlog->entry, entry, sizeof(struct mbox_cmd));
2843 for (i = 0; i < MBOX_LEN / 8; i++) {
2844 flit = entry->cmd[i];
2845 mboxlog->hi[i] = (u32)(flit >> 32);
2846 mboxlog->lo[i] = (u32)flit;
2847 }
2848 mboxlog++;
2849 }
2850 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2851 }
2852
2853 int cudbg_collect_hma_indirect(struct cudbg_init *pdbg_init,
2854 struct cudbg_buffer *dbg_buff,
2855 struct cudbg_error *cudbg_err)
2856 {
2857 struct adapter *padap = pdbg_init->adap;
2858 struct cudbg_buffer temp_buff = { 0 };
2859 struct ireg_buf *hma_indr;
2860 int i, rc, n;
2861 u32 size;
2862
2863 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
2864 return CUDBG_STATUS_ENTITY_NOT_FOUND;
2865
2866 n = sizeof(t6_hma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
2867 size = sizeof(struct ireg_buf) * n;
2868 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2869 if (rc)
2870 return rc;
2871
2872 hma_indr = (struct ireg_buf *)temp_buff.data;
2873 for (i = 0; i < n; i++) {
2874 struct ireg_field *hma_fli = &hma_indr->tp_pio;
2875 u32 *buff = hma_indr->outbuf;
2876
2877 hma_fli->ireg_addr = t6_hma_ireg_array[i][0];
2878 hma_fli->ireg_data = t6_hma_ireg_array[i][1];
2879 hma_fli->ireg_local_offset = t6_hma_ireg_array[i][2];
2880 hma_fli->ireg_offset_range = t6_hma_ireg_array[i][3];
2881 t4_read_indirect(padap, hma_fli->ireg_addr, hma_fli->ireg_data,
2882 buff, hma_fli->ireg_offset_range,
2883 hma_fli->ireg_local_offset);
2884 hma_indr++;
2885 }
2886 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2887 }
2888
2889 void cudbg_fill_qdesc_num_and_size(const struct adapter *padap,
2890 u32 *num, u32 *size)
2891 {
2892 u32 tot_entries = 0, tot_size = 0;
2893
2894 /* NIC TXQ, RXQ, FLQ, and CTRLQ */
2895 tot_entries += MAX_ETH_QSETS * 3;
2896 tot_entries += MAX_CTRL_QUEUES;
2897
2898 tot_size += MAX_ETH_QSETS * MAX_TXQ_ENTRIES * MAX_TXQ_DESC_SIZE;
2899 tot_size += MAX_ETH_QSETS * MAX_RSPQ_ENTRIES * MAX_RXQ_DESC_SIZE;
2900 tot_size += MAX_ETH_QSETS * MAX_RX_BUFFERS * MAX_FL_DESC_SIZE;
2901 tot_size += MAX_CTRL_QUEUES * MAX_CTRL_TXQ_ENTRIES *
2902 MAX_CTRL_TXQ_DESC_SIZE;
2903
2904 /* FW_EVTQ and INTRQ */
2905 tot_entries += INGQ_EXTRAS;
2906 tot_size += INGQ_EXTRAS * MAX_RSPQ_ENTRIES * MAX_RXQ_DESC_SIZE;
2907
2908 /* PTP_TXQ */
2909 tot_entries += 1;
2910 tot_size += MAX_TXQ_ENTRIES * MAX_TXQ_DESC_SIZE;
2911
2912 /* ULD TXQ, RXQ, and FLQ */
2913 tot_entries += CXGB4_TX_MAX * MAX_OFLD_QSETS;
2914 tot_entries += CXGB4_ULD_MAX * MAX_ULD_QSETS * 2;
2915
2916 tot_size += CXGB4_TX_MAX * MAX_OFLD_QSETS * MAX_TXQ_ENTRIES *
2917 MAX_TXQ_DESC_SIZE;
2918 tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * MAX_RSPQ_ENTRIES *
2919 MAX_RXQ_DESC_SIZE;
2920 tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * MAX_RX_BUFFERS *
2921 MAX_FL_DESC_SIZE;
2922
2923 /* ULD CIQ */
2924 tot_entries += CXGB4_ULD_MAX * MAX_ULD_QSETS;
2925 tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * SGE_MAX_IQ_SIZE *
2926 MAX_RXQ_DESC_SIZE;
2927
2928 /* ETHOFLD TXQ, RXQ, and FLQ */
2929 tot_entries += MAX_OFLD_QSETS * 3;
2930 tot_size += MAX_OFLD_QSETS * MAX_TXQ_ENTRIES * MAX_TXQ_DESC_SIZE;
2931
2932 tot_size += sizeof(struct cudbg_ver_hdr) +
2933 sizeof(struct cudbg_qdesc_info) +
2934 sizeof(struct cudbg_qdesc_entry) * tot_entries;
2935
2936 if (num)
2937 *num = tot_entries;
2938
2939 if (size)
2940 *size = tot_size;
2941 }
2942
2943 int cudbg_collect_qdesc(struct cudbg_init *pdbg_init,
2944 struct cudbg_buffer *dbg_buff,
2945 struct cudbg_error *cudbg_err)
2946 {
2947 u32 num_queues = 0, tot_entries = 0, size = 0;
2948 struct adapter *padap = pdbg_init->adap;
2949 struct cudbg_buffer temp_buff = { 0 };
2950 struct cudbg_qdesc_entry *qdesc_entry;
2951 struct cudbg_qdesc_info *qdesc_info;
2952 struct cudbg_ver_hdr *ver_hdr;
2953 struct sge *s = &padap->sge;
2954 u32 i, j, cur_off, tot_len;
2955 u8 *data;
2956 int rc;
2957
2958 cudbg_fill_qdesc_num_and_size(padap, &tot_entries, &size);
2959 size = min_t(u32, size, CUDBG_DUMP_BUFF_SIZE);
2960 tot_len = size;
2961 data = kvzalloc(size, GFP_KERNEL);
2962 if (!data)
2963 return -ENOMEM;
2964
2965 ver_hdr = (struct cudbg_ver_hdr *)data;
2966 ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
2967 ver_hdr->revision = CUDBG_QDESC_REV;
2968 ver_hdr->size = sizeof(struct cudbg_qdesc_info);
2969 size -= sizeof(*ver_hdr);
2970
2971 qdesc_info = (struct cudbg_qdesc_info *)(data +
2972 sizeof(*ver_hdr));
2973 size -= sizeof(*qdesc_info);
2974 qdesc_entry = (struct cudbg_qdesc_entry *)qdesc_info->data;
2975
2976 #define QDESC_GET(q, desc, type, label) do { \
2977 if (size <= 0) { \
2978 goto label; \
2979 } \
2980 if (desc) { \
2981 cudbg_fill_qdesc_##q(q, type, qdesc_entry); \
2982 size -= sizeof(*qdesc_entry) + qdesc_entry->data_size; \
2983 num_queues++; \
2984 qdesc_entry = cudbg_next_qdesc(qdesc_entry); \
2985 } \
2986 } while (0)
2987
2988 #define QDESC_GET_TXQ(q, type, label) do { \
2989 struct sge_txq *txq = (struct sge_txq *)q; \
2990 QDESC_GET(txq, txq->desc, type, label); \
2991 } while (0)
2992
2993 #define QDESC_GET_RXQ(q, type, label) do { \
2994 struct sge_rspq *rxq = (struct sge_rspq *)q; \
2995 QDESC_GET(rxq, rxq->desc, type, label); \
2996 } while (0)
2997
2998 #define QDESC_GET_FLQ(q, type, label) do { \
2999 struct sge_fl *flq = (struct sge_fl *)q; \
3000 QDESC_GET(flq, flq->desc, type, label); \
3001 } while (0)
3002
3003 /* NIC TXQ */
3004 for (i = 0; i < s->ethqsets; i++)
3005 QDESC_GET_TXQ(&s->ethtxq[i].q, CUDBG_QTYPE_NIC_TXQ, out);
3006
3007 /* NIC RXQ */
3008 for (i = 0; i < s->ethqsets; i++)
3009 QDESC_GET_RXQ(&s->ethrxq[i].rspq, CUDBG_QTYPE_NIC_RXQ, out);
3010
3011 /* NIC FLQ */
3012 for (i = 0; i < s->ethqsets; i++)
3013 QDESC_GET_FLQ(&s->ethrxq[i].fl, CUDBG_QTYPE_NIC_FLQ, out);
3014
3015 /* NIC CTRLQ */
3016 for (i = 0; i < padap->params.nports; i++)
3017 QDESC_GET_TXQ(&s->ctrlq[i].q, CUDBG_QTYPE_CTRLQ, out);
3018
3019 /* FW_EVTQ */
3020 QDESC_GET_RXQ(&s->fw_evtq, CUDBG_QTYPE_FWEVTQ, out);
3021
3022 /* INTRQ */
3023 QDESC_GET_RXQ(&s->intrq, CUDBG_QTYPE_INTRQ, out);
3024
3025 /* PTP_TXQ */
3026 QDESC_GET_TXQ(&s->ptptxq.q, CUDBG_QTYPE_PTP_TXQ, out);
3027
3028 /* ULD Queues */
3029 mutex_lock(&uld_mutex);
3030
3031 if (s->uld_txq_info) {
3032 struct sge_uld_txq_info *utxq;
3033
3034 /* ULD TXQ */
3035 for (j = 0; j < CXGB4_TX_MAX; j++) {
3036 if (!s->uld_txq_info[j])
3037 continue;
3038
3039 utxq = s->uld_txq_info[j];
3040 for (i = 0; i < utxq->ntxq; i++)
3041 QDESC_GET_TXQ(&utxq->uldtxq[i].q,
3042 cudbg_uld_txq_to_qtype(j),
3043 out_unlock);
3044 }
3045 }
3046
3047 if (s->uld_rxq_info) {
3048 struct sge_uld_rxq_info *urxq;
3049 u32 base;
3050
3051 /* ULD RXQ */
3052 for (j = 0; j < CXGB4_ULD_MAX; j++) {
3053 if (!s->uld_rxq_info[j])
3054 continue;
3055
3056 urxq = s->uld_rxq_info[j];
3057 for (i = 0; i < urxq->nrxq; i++)
3058 QDESC_GET_RXQ(&urxq->uldrxq[i].rspq,
3059 cudbg_uld_rxq_to_qtype(j),
3060 out_unlock);
3061 }
3062
3063 /* ULD FLQ */
3064 for (j = 0; j < CXGB4_ULD_MAX; j++) {
3065 if (!s->uld_rxq_info[j])
3066 continue;
3067
3068 urxq = s->uld_rxq_info[j];
3069 for (i = 0; i < urxq->nrxq; i++)
3070 QDESC_GET_FLQ(&urxq->uldrxq[i].fl,
3071 cudbg_uld_flq_to_qtype(j),
3072 out_unlock);
3073 }
3074
3075 /* ULD CIQ */
3076 for (j = 0; j < CXGB4_ULD_MAX; j++) {
3077 if (!s->uld_rxq_info[j])
3078 continue;
3079
3080 urxq = s->uld_rxq_info[j];
3081 base = urxq->nrxq;
3082 for (i = 0; i < urxq->nciq; i++)
3083 QDESC_GET_RXQ(&urxq->uldrxq[base + i].rspq,
3084 cudbg_uld_ciq_to_qtype(j),
3085 out_unlock);
3086 }
3087 }
3088
3089 /* ETHOFLD TXQ */
3090 if (s->eohw_txq)
3091 for (i = 0; i < s->eoqsets; i++)
3092 QDESC_GET_TXQ(&s->eohw_txq[i].q,
3093 CUDBG_QTYPE_ETHOFLD_TXQ, out);
3094
3095 /* ETHOFLD RXQ and FLQ */
3096 if (s->eohw_rxq) {
3097 for (i = 0; i < s->eoqsets; i++)
3098 QDESC_GET_RXQ(&s->eohw_rxq[i].rspq,
3099 CUDBG_QTYPE_ETHOFLD_RXQ, out);
3100
3101 for (i = 0; i < s->eoqsets; i++)
3102 QDESC_GET_FLQ(&s->eohw_rxq[i].fl,
3103 CUDBG_QTYPE_ETHOFLD_FLQ, out);
3104 }
3105
3106 out_unlock:
3107 mutex_unlock(&uld_mutex);
3108
3109 out:
3110 qdesc_info->qdesc_entry_size = sizeof(*qdesc_entry);
3111 qdesc_info->num_queues = num_queues;
3112 cur_off = 0;
3113 while (tot_len) {
3114 u32 chunk_size = min_t(u32, tot_len, CUDBG_CHUNK_SIZE);
3115
3116 rc = cudbg_get_buff(pdbg_init, dbg_buff, chunk_size,
3117 &temp_buff);
3118 if (rc) {
3119 cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3120 goto out_free;
3121 }
3122
3123 memcpy(temp_buff.data, data + cur_off, chunk_size);
3124 tot_len -= chunk_size;
3125 cur_off += chunk_size;
3126 rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff,
3127 dbg_buff);
3128 if (rc) {
3129 cudbg_put_buff(pdbg_init, &temp_buff);
3130 cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3131 goto out_free;
3132 }
3133 }
3134
3135 out_free:
3136 if (data)
3137 kvfree(data);
3138
3139 #undef QDESC_GET_FLQ
3140 #undef QDESC_GET_RXQ
3141 #undef QDESC_GET_TXQ
3142 #undef QDESC_GET
3143
3144 return rc;
3145 }
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