2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/seq_file.h>
36 #include <linux/debugfs.h>
37 #include <linux/string_helpers.h>
38 #include <linux/sort.h>
39 #include <linux/ctype.h>
43 #include "t4_values.h"
45 #include "cxgb4_debugfs.h"
49 /* generic seq_file support for showing a table of size rows x width. */
50 static void *seq_tab_get_idx(struct seq_tab
*tb
, loff_t pos
)
52 pos
-= tb
->skip_first
;
53 return pos
>= tb
->rows
? NULL
: &tb
->data
[pos
* tb
->width
];
56 static void *seq_tab_start(struct seq_file
*seq
, loff_t
*pos
)
58 struct seq_tab
*tb
= seq
->private;
60 if (tb
->skip_first
&& *pos
== 0)
61 return SEQ_START_TOKEN
;
63 return seq_tab_get_idx(tb
, *pos
);
66 static void *seq_tab_next(struct seq_file
*seq
, void *v
, loff_t
*pos
)
68 v
= seq_tab_get_idx(seq
->private, *pos
+ 1);
74 static void seq_tab_stop(struct seq_file
*seq
, void *v
)
78 static int seq_tab_show(struct seq_file
*seq
, void *v
)
80 const struct seq_tab
*tb
= seq
->private;
82 return tb
->show(seq
, v
, ((char *)v
- tb
->data
) / tb
->width
);
85 static const struct seq_operations seq_tab_ops
= {
86 .start
= seq_tab_start
,
92 struct seq_tab
*seq_open_tab(struct file
*f
, unsigned int rows
,
93 unsigned int width
, unsigned int have_header
,
94 int (*show
)(struct seq_file
*seq
, void *v
, int i
))
98 p
= __seq_open_private(f
, &seq_tab_ops
, sizeof(*p
) + rows
* width
);
103 p
->skip_first
= have_header
!= 0;
108 /* Trim the size of a seq_tab to the supplied number of rows. The operation is
111 static int seq_tab_trim(struct seq_tab
*p
, unsigned int new_rows
)
113 if (new_rows
> p
->rows
)
119 static int cim_la_show(struct seq_file
*seq
, void *v
, int idx
)
121 if (v
== SEQ_START_TOKEN
)
122 seq_puts(seq
, "Status Data PC LS0Stat LS0Addr "
128 " %02x %x%07x %x%07x %08x %08x %08x%08x%08x%08x\n",
129 (p
[0] >> 4) & 0xff, p
[0] & 0xf, p
[1] >> 4,
130 p
[1] & 0xf, p
[2] >> 4, p
[2] & 0xf, p
[3], p
[4], p
[5],
136 static int cim_la_show_3in1(struct seq_file
*seq
, void *v
, int idx
)
138 if (v
== SEQ_START_TOKEN
) {
139 seq_puts(seq
, "Status Data PC\n");
143 seq_printf(seq
, " %02x %08x %08x\n", p
[5] & 0xff, p
[6],
145 seq_printf(seq
, " %02x %02x%06x %02x%06x\n",
146 (p
[3] >> 8) & 0xff, p
[3] & 0xff, p
[4] >> 8,
147 p
[4] & 0xff, p
[5] >> 8);
148 seq_printf(seq
, " %02x %x%07x %x%07x\n", (p
[0] >> 4) & 0xff,
149 p
[0] & 0xf, p
[1] >> 4, p
[1] & 0xf, p
[2] >> 4);
154 static int cim_la_show_t6(struct seq_file
*seq
, void *v
, int idx
)
156 if (v
== SEQ_START_TOKEN
) {
157 seq_puts(seq
, "Status Inst Data PC LS0Stat "
158 "LS0Addr LS0Data LS1Stat LS1Addr LS1Data\n");
162 seq_printf(seq
, " %02x %04x%04x %04x%04x %04x%04x %08x %08x %08x %08x %08x %08x\n",
163 (p
[9] >> 16) & 0xff, /* Status */
164 p
[9] & 0xffff, p
[8] >> 16, /* Inst */
165 p
[8] & 0xffff, p
[7] >> 16, /* Data */
166 p
[7] & 0xffff, p
[6] >> 16, /* PC */
167 p
[2], p
[1], p
[0], /* LS0 Stat, Addr and Data */
168 p
[5], p
[4], p
[3]); /* LS1 Stat, Addr and Data */
173 static int cim_la_show_pc_t6(struct seq_file
*seq
, void *v
, int idx
)
175 if (v
== SEQ_START_TOKEN
) {
176 seq_puts(seq
, "Status Inst Data PC\n");
180 seq_printf(seq
, " %02x %08x %08x %08x\n",
181 p
[3] & 0xff, p
[2], p
[1], p
[0]);
182 seq_printf(seq
, " %02x %02x%06x %02x%06x %02x%06x\n",
183 (p
[6] >> 8) & 0xff, p
[6] & 0xff, p
[5] >> 8,
184 p
[5] & 0xff, p
[4] >> 8, p
[4] & 0xff, p
[3] >> 8);
185 seq_printf(seq
, " %02x %04x%04x %04x%04x %04x%04x\n",
186 (p
[9] >> 16) & 0xff, p
[9] & 0xffff, p
[8] >> 16,
187 p
[8] & 0xffff, p
[7] >> 16, p
[7] & 0xffff,
193 static int cim_la_open(struct inode
*inode
, struct file
*file
)
198 struct adapter
*adap
= inode
->i_private
;
200 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &cfg
);
204 if (is_t6(adap
->params
.chip
)) {
205 /* +1 to account for integer division of CIMLA_SIZE/10 */
206 p
= seq_open_tab(file
, (adap
->params
.cim_la_size
/ 10) + 1,
208 cfg
& UPDBGLACAPTPCONLY_F
?
209 cim_la_show_pc_t6
: cim_la_show_t6
);
211 p
= seq_open_tab(file
, adap
->params
.cim_la_size
/ 8,
213 cfg
& UPDBGLACAPTPCONLY_F
? cim_la_show_3in1
:
219 ret
= t4_cim_read_la(adap
, (u32
*)p
->data
, NULL
);
221 seq_release_private(inode
, file
);
225 static const struct file_operations cim_la_fops
= {
226 .owner
= THIS_MODULE
,
230 .release
= seq_release_private
233 static int cim_pif_la_show(struct seq_file
*seq
, void *v
, int idx
)
237 if (v
== SEQ_START_TOKEN
) {
238 seq_puts(seq
, "Cntl ID DataBE Addr Data\n");
239 } else if (idx
< CIM_PIFLA_SIZE
) {
240 seq_printf(seq
, " %02x %02x %04x %08x %08x%08x%08x%08x\n",
241 (p
[5] >> 22) & 0xff, (p
[5] >> 16) & 0x3f,
242 p
[5] & 0xffff, p
[4], p
[3], p
[2], p
[1], p
[0]);
244 if (idx
== CIM_PIFLA_SIZE
)
245 seq_puts(seq
, "\nCntl ID Data\n");
246 seq_printf(seq
, " %02x %02x %08x%08x%08x%08x\n",
247 (p
[4] >> 6) & 0xff, p
[4] & 0x3f,
248 p
[3], p
[2], p
[1], p
[0]);
253 static int cim_pif_la_open(struct inode
*inode
, struct file
*file
)
256 struct adapter
*adap
= inode
->i_private
;
258 p
= seq_open_tab(file
, 2 * CIM_PIFLA_SIZE
, 6 * sizeof(u32
), 1,
263 t4_cim_read_pif_la(adap
, (u32
*)p
->data
,
264 (u32
*)p
->data
+ 6 * CIM_PIFLA_SIZE
, NULL
, NULL
);
268 static const struct file_operations cim_pif_la_fops
= {
269 .owner
= THIS_MODULE
,
270 .open
= cim_pif_la_open
,
273 .release
= seq_release_private
276 static int cim_ma_la_show(struct seq_file
*seq
, void *v
, int idx
)
280 if (v
== SEQ_START_TOKEN
) {
282 } else if (idx
< CIM_MALA_SIZE
) {
283 seq_printf(seq
, "%02x%08x%08x%08x%08x\n",
284 p
[4], p
[3], p
[2], p
[1], p
[0]);
286 if (idx
== CIM_MALA_SIZE
)
288 "\nCnt ID Tag UE Data RDY VLD\n");
289 seq_printf(seq
, "%3u %2u %x %u %08x%08x %u %u\n",
290 (p
[2] >> 10) & 0xff, (p
[2] >> 7) & 7,
291 (p
[2] >> 3) & 0xf, (p
[2] >> 2) & 1,
292 (p
[1] >> 2) | ((p
[2] & 3) << 30),
293 (p
[0] >> 2) | ((p
[1] & 3) << 30), (p
[0] >> 1) & 1,
299 static int cim_ma_la_open(struct inode
*inode
, struct file
*file
)
302 struct adapter
*adap
= inode
->i_private
;
304 p
= seq_open_tab(file
, 2 * CIM_MALA_SIZE
, 5 * sizeof(u32
), 1,
309 t4_cim_read_ma_la(adap
, (u32
*)p
->data
,
310 (u32
*)p
->data
+ 5 * CIM_MALA_SIZE
);
314 static const struct file_operations cim_ma_la_fops
= {
315 .owner
= THIS_MODULE
,
316 .open
= cim_ma_la_open
,
319 .release
= seq_release_private
322 static int cim_qcfg_show(struct seq_file
*seq
, void *v
)
324 static const char * const qname
[] = {
325 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",
326 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI",
331 struct adapter
*adap
= seq
->private;
332 u16 base
[CIM_NUM_IBQ
+ CIM_NUM_OBQ_T5
];
333 u16 size
[CIM_NUM_IBQ
+ CIM_NUM_OBQ_T5
];
334 u32 stat
[(4 * (CIM_NUM_IBQ
+ CIM_NUM_OBQ_T5
))];
335 u16 thres
[CIM_NUM_IBQ
];
336 u32 obq_wr_t4
[2 * CIM_NUM_OBQ
], *wr
;
337 u32 obq_wr_t5
[2 * CIM_NUM_OBQ_T5
];
339 int cim_num_obq
= is_t4(adap
->params
.chip
) ?
340 CIM_NUM_OBQ
: CIM_NUM_OBQ_T5
;
342 i
= t4_cim_read(adap
, is_t4(adap
->params
.chip
) ? UP_IBQ_0_RDADDR_A
:
343 UP_IBQ_0_SHADOW_RDADDR_A
,
344 ARRAY_SIZE(stat
), stat
);
346 if (is_t4(adap
->params
.chip
)) {
347 i
= t4_cim_read(adap
, UP_OBQ_0_REALADDR_A
,
348 ARRAY_SIZE(obq_wr_t4
), obq_wr_t4
);
351 i
= t4_cim_read(adap
, UP_OBQ_0_SHADOW_REALADDR_A
,
352 ARRAY_SIZE(obq_wr_t5
), obq_wr_t5
);
359 t4_read_cimq_cfg(adap
, base
, size
, thres
);
362 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail\n");
363 for (i
= 0; i
< CIM_NUM_IBQ
; i
++, p
+= 4)
364 seq_printf(seq
, "%7s %5x %5u %5u %6x %4x %4u %4u %5u\n",
365 qname
[i
], base
[i
], size
[i
], thres
[i
],
366 IBQRDADDR_G(p
[0]), IBQWRADDR_G(p
[1]),
367 QUESOPCNT_G(p
[3]), QUEEOPCNT_G(p
[3]),
368 QUEREMFLITS_G(p
[2]) * 16);
369 for ( ; i
< CIM_NUM_IBQ
+ cim_num_obq
; i
++, p
+= 4, wr
+= 2)
370 seq_printf(seq
, "%7s %5x %5u %12x %4x %4u %4u %5u\n",
371 qname
[i
], base
[i
], size
[i
],
372 QUERDADDR_G(p
[0]) & 0x3fff, wr
[0] - base
[i
],
373 QUESOPCNT_G(p
[3]), QUEEOPCNT_G(p
[3]),
374 QUEREMFLITS_G(p
[2]) * 16);
378 static int cim_qcfg_open(struct inode
*inode
, struct file
*file
)
380 return single_open(file
, cim_qcfg_show
, inode
->i_private
);
383 static const struct file_operations cim_qcfg_fops
= {
384 .owner
= THIS_MODULE
,
385 .open
= cim_qcfg_open
,
388 .release
= single_release
,
391 static int cimq_show(struct seq_file
*seq
, void *v
, int idx
)
395 seq_printf(seq
, "%#06x: %08x %08x %08x %08x\n", idx
* 16, p
[0], p
[1],
400 static int cim_ibq_open(struct inode
*inode
, struct file
*file
)
404 unsigned int qid
= (uintptr_t)inode
->i_private
& 7;
405 struct adapter
*adap
= inode
->i_private
- qid
;
407 p
= seq_open_tab(file
, CIM_IBQ_SIZE
, 4 * sizeof(u32
), 0, cimq_show
);
411 ret
= t4_read_cim_ibq(adap
, qid
, (u32
*)p
->data
, CIM_IBQ_SIZE
* 4);
413 seq_release_private(inode
, file
);
419 static const struct file_operations cim_ibq_fops
= {
420 .owner
= THIS_MODULE
,
421 .open
= cim_ibq_open
,
424 .release
= seq_release_private
427 static int cim_obq_open(struct inode
*inode
, struct file
*file
)
431 unsigned int qid
= (uintptr_t)inode
->i_private
& 7;
432 struct adapter
*adap
= inode
->i_private
- qid
;
434 p
= seq_open_tab(file
, 6 * CIM_OBQ_SIZE
, 4 * sizeof(u32
), 0, cimq_show
);
438 ret
= t4_read_cim_obq(adap
, qid
, (u32
*)p
->data
, 6 * CIM_OBQ_SIZE
* 4);
440 seq_release_private(inode
, file
);
442 seq_tab_trim(p
, ret
/ 4);
448 static const struct file_operations cim_obq_fops
= {
449 .owner
= THIS_MODULE
,
450 .open
= cim_obq_open
,
453 .release
= seq_release_private
462 static void field_desc_show(struct seq_file
*seq
, u64 v
,
463 const struct field_desc
*p
)
469 u64 mask
= (1ULL << p
->width
) - 1;
470 int len
= scnprintf(buf
, sizeof(buf
), "%s: %llu", p
->name
,
471 ((unsigned long long)v
>> p
->start
) & mask
);
473 if (line_size
+ len
>= 79) {
475 seq_puts(seq
, "\n ");
477 seq_printf(seq
, "%s ", buf
);
478 line_size
+= len
+ 1;
484 static struct field_desc tp_la0
[] = {
485 { "RcfOpCodeOut", 60, 4 },
487 { "WcfState", 52, 4 },
488 { "RcfOpcSrcOut", 50, 2 },
489 { "CRxError", 49, 1 },
490 { "ERxError", 48, 1 },
491 { "SanityFailed", 47, 1 },
492 { "SpuriousMsg", 46, 1 },
493 { "FlushInputMsg", 45, 1 },
494 { "FlushInputCpl", 44, 1 },
495 { "RssUpBit", 43, 1 },
496 { "RssFilterHit", 42, 1 },
498 { "InitTcb", 31, 1 },
499 { "LineNumber", 24, 7 },
501 { "EdataOut", 22, 1 },
503 { "CdataOut", 20, 1 },
504 { "EreadPdu", 19, 1 },
505 { "CreadPdu", 18, 1 },
506 { "TunnelPkt", 17, 1 },
507 { "RcfPeerFin", 16, 1 },
508 { "RcfReasonOut", 12, 4 },
509 { "TxCchannel", 10, 2 },
510 { "RcfTxChannel", 8, 2 },
511 { "RxEchannel", 6, 2 },
512 { "RcfRxChannel", 5, 1 },
513 { "RcfDataOutSrdy", 4, 1 },
515 { "RxOoDvld", 2, 1 },
516 { "RxCongestion", 1, 1 },
517 { "TxCongestion", 0, 1 },
521 static int tp_la_show(struct seq_file
*seq
, void *v
, int idx
)
525 field_desc_show(seq
, *p
, tp_la0
);
529 static int tp_la_show2(struct seq_file
*seq
, void *v
, int idx
)
535 field_desc_show(seq
, p
[0], tp_la0
);
536 if (idx
< (TPLA_SIZE
/ 2 - 1) || p
[1] != ~0ULL)
537 field_desc_show(seq
, p
[1], tp_la0
);
541 static int tp_la_show3(struct seq_file
*seq
, void *v
, int idx
)
543 static struct field_desc tp_la1
[] = {
544 { "CplCmdIn", 56, 8 },
545 { "CplCmdOut", 48, 8 },
546 { "ESynOut", 47, 1 },
547 { "EAckOut", 46, 1 },
548 { "EFinOut", 45, 1 },
549 { "ERstOut", 44, 1 },
555 { "DataInVld", 38, 1 },
557 { "RxBufEmpty", 36, 1 },
559 { "RxFbCongestion", 34, 1 },
560 { "TxFbCongestion", 33, 1 },
561 { "TxPktSumSrdy", 32, 1 },
562 { "RcfUlpType", 28, 4 },
564 { "Ebypass", 26, 1 },
566 { "Static0", 24, 1 },
568 { "Cbypass", 22, 1 },
570 { "CPktOut", 20, 1 },
571 { "RxPagePoolFull", 18, 2 },
572 { "RxLpbkPkt", 17, 1 },
573 { "TxLpbkPkt", 16, 1 },
574 { "RxVfValid", 15, 1 },
575 { "SynLearned", 14, 1 },
576 { "SetDelEntry", 13, 1 },
577 { "SetInvEntry", 12, 1 },
578 { "CpcmdDvld", 11, 1 },
579 { "CpcmdSave", 10, 1 },
580 { "RxPstructsFull", 8, 2 },
581 { "EpcmdDvld", 7, 1 },
582 { "EpcmdFlush", 6, 1 },
583 { "EpcmdTrimPrefix", 5, 1 },
584 { "EpcmdTrimPostfix", 4, 1 },
585 { "ERssIp4Pkt", 3, 1 },
586 { "ERssIp6Pkt", 2, 1 },
587 { "ERssTcpUdpPkt", 1, 1 },
588 { "ERssFceFipPkt", 0, 1 },
591 static struct field_desc tp_la2
[] = {
592 { "CplCmdIn", 56, 8 },
593 { "MpsVfVld", 55, 1 },
601 { "DataInVld", 38, 1 },
603 { "RxBufEmpty", 36, 1 },
605 { "RxFbCongestion", 34, 1 },
606 { "TxFbCongestion", 33, 1 },
607 { "TxPktSumSrdy", 32, 1 },
608 { "RcfUlpType", 28, 4 },
610 { "Ebypass", 26, 1 },
612 { "Static0", 24, 1 },
614 { "Cbypass", 22, 1 },
616 { "CPktOut", 20, 1 },
617 { "RxPagePoolFull", 18, 2 },
618 { "RxLpbkPkt", 17, 1 },
619 { "TxLpbkPkt", 16, 1 },
620 { "RxVfValid", 15, 1 },
621 { "SynLearned", 14, 1 },
622 { "SetDelEntry", 13, 1 },
623 { "SetInvEntry", 12, 1 },
624 { "CpcmdDvld", 11, 1 },
625 { "CpcmdSave", 10, 1 },
626 { "RxPstructsFull", 8, 2 },
627 { "EpcmdDvld", 7, 1 },
628 { "EpcmdFlush", 6, 1 },
629 { "EpcmdTrimPrefix", 5, 1 },
630 { "EpcmdTrimPostfix", 4, 1 },
631 { "ERssIp4Pkt", 3, 1 },
632 { "ERssIp6Pkt", 2, 1 },
633 { "ERssTcpUdpPkt", 1, 1 },
634 { "ERssFceFipPkt", 0, 1 },
641 field_desc_show(seq
, p
[0], tp_la0
);
642 if (idx
< (TPLA_SIZE
/ 2 - 1) || p
[1] != ~0ULL)
643 field_desc_show(seq
, p
[1], (p
[0] & BIT(17)) ? tp_la2
: tp_la1
);
647 static int tp_la_open(struct inode
*inode
, struct file
*file
)
650 struct adapter
*adap
= inode
->i_private
;
652 switch (DBGLAMODE_G(t4_read_reg(adap
, TP_DBG_LA_CONFIG_A
))) {
654 p
= seq_open_tab(file
, TPLA_SIZE
/ 2, 2 * sizeof(u64
), 0,
658 p
= seq_open_tab(file
, TPLA_SIZE
/ 2, 2 * sizeof(u64
), 0,
662 p
= seq_open_tab(file
, TPLA_SIZE
, sizeof(u64
), 0, tp_la_show
);
667 t4_tp_read_la(adap
, (u64
*)p
->data
, NULL
);
671 static ssize_t
tp_la_write(struct file
*file
, const char __user
*buf
,
672 size_t count
, loff_t
*pos
)
677 size_t size
= min(sizeof(s
) - 1, count
);
678 struct adapter
*adap
= file_inode(file
)->i_private
;
680 if (copy_from_user(s
, buf
, size
))
683 err
= kstrtoul(s
, 0, &val
);
688 adap
->params
.tp
.la_mask
= val
<< 16;
689 t4_set_reg_field(adap
, TP_DBG_LA_CONFIG_A
, 0xffff0000U
,
690 adap
->params
.tp
.la_mask
);
694 static const struct file_operations tp_la_fops
= {
695 .owner
= THIS_MODULE
,
699 .release
= seq_release_private
,
703 static int ulprx_la_show(struct seq_file
*seq
, void *v
, int idx
)
707 if (v
== SEQ_START_TOKEN
)
708 seq_puts(seq
, " Pcmd Type Message"
711 seq_printf(seq
, "%08x%08x %4x %08x %08x%08x%08x%08x\n",
712 p
[1], p
[0], p
[2], p
[3], p
[7], p
[6], p
[5], p
[4]);
716 static int ulprx_la_open(struct inode
*inode
, struct file
*file
)
719 struct adapter
*adap
= inode
->i_private
;
721 p
= seq_open_tab(file
, ULPRX_LA_SIZE
, 8 * sizeof(u32
), 1,
726 t4_ulprx_read_la(adap
, (u32
*)p
->data
);
730 static const struct file_operations ulprx_la_fops
= {
731 .owner
= THIS_MODULE
,
732 .open
= ulprx_la_open
,
735 .release
= seq_release_private
738 /* Show the PM memory stats. These stats include:
741 * Read: memory read operation
742 * Write Bypass: cut-through
743 * Bypass + mem: cut-through and save copy
747 * Write Bypass: cut-through
748 * Flush: payload trim or drop
750 static int pm_stats_show(struct seq_file
*seq
, void *v
)
752 static const char * const tx_pm_stats
[] = {
753 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:"
755 static const char * const rx_pm_stats
[] = {
756 "Read:", "Write bypass:", "Write mem:", "Flush:"
760 u32 tx_cnt
[T6_PM_NSTATS
], rx_cnt
[T6_PM_NSTATS
];
761 u64 tx_cyc
[T6_PM_NSTATS
], rx_cyc
[T6_PM_NSTATS
];
762 struct adapter
*adap
= seq
->private;
764 t4_pmtx_get_stats(adap
, tx_cnt
, tx_cyc
);
765 t4_pmrx_get_stats(adap
, rx_cnt
, rx_cyc
);
767 seq_printf(seq
, "%13s %10s %20s\n", " ", "Tx pcmds", "Tx bytes");
768 for (i
= 0; i
< PM_NSTATS
- 1; i
++)
769 seq_printf(seq
, "%-13s %10u %20llu\n",
770 tx_pm_stats
[i
], tx_cnt
[i
], tx_cyc
[i
]);
772 seq_printf(seq
, "%13s %10s %20s\n", " ", "Rx pcmds", "Rx bytes");
773 for (i
= 0; i
< PM_NSTATS
- 1; i
++)
774 seq_printf(seq
, "%-13s %10u %20llu\n",
775 rx_pm_stats
[i
], rx_cnt
[i
], rx_cyc
[i
]);
777 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) > CHELSIO_T5
) {
778 /* In T5 the granularity of the total wait is too fine.
779 * It is not useful as it reaches the max value too fast.
780 * Hence display this Input FIFO wait for T6 onwards.
782 seq_printf(seq
, "%13s %10s %20s\n",
783 " ", "Total wait", "Total Occupancy");
784 seq_printf(seq
, "Tx FIFO wait %10u %20llu\n",
785 tx_cnt
[i
], tx_cyc
[i
]);
786 seq_printf(seq
, "Rx FIFO wait %10u %20llu\n",
787 rx_cnt
[i
], rx_cyc
[i
]);
789 /* Skip index 6 as there is nothing useful ihere */
792 /* At index 7, a new stat for read latency (count, total wait)
795 seq_printf(seq
, "%13s %10s %20s\n",
796 " ", "Reads", "Total wait");
797 seq_printf(seq
, "Tx latency %10u %20llu\n",
798 tx_cnt
[i
], tx_cyc
[i
]);
799 seq_printf(seq
, "Rx latency %10u %20llu\n",
800 rx_cnt
[i
], rx_cyc
[i
]);
805 static int pm_stats_open(struct inode
*inode
, struct file
*file
)
807 return single_open(file
, pm_stats_show
, inode
->i_private
);
810 static ssize_t
pm_stats_clear(struct file
*file
, const char __user
*buf
,
811 size_t count
, loff_t
*pos
)
813 struct adapter
*adap
= file_inode(file
)->i_private
;
815 t4_write_reg(adap
, PM_RX_STAT_CONFIG_A
, 0);
816 t4_write_reg(adap
, PM_TX_STAT_CONFIG_A
, 0);
820 static const struct file_operations pm_stats_debugfs_fops
= {
821 .owner
= THIS_MODULE
,
822 .open
= pm_stats_open
,
825 .release
= single_release
,
826 .write
= pm_stats_clear
829 static int tx_rate_show(struct seq_file
*seq
, void *v
)
831 u64 nrate
[NCHAN
], orate
[NCHAN
];
832 struct adapter
*adap
= seq
->private;
834 t4_get_chan_txrate(adap
, nrate
, orate
);
835 if (adap
->params
.arch
.nchan
== NCHAN
) {
836 seq_puts(seq
, " channel 0 channel 1 "
837 "channel 2 channel 3\n");
838 seq_printf(seq
, "NIC B/s: %10llu %10llu %10llu %10llu\n",
839 (unsigned long long)nrate
[0],
840 (unsigned long long)nrate
[1],
841 (unsigned long long)nrate
[2],
842 (unsigned long long)nrate
[3]);
843 seq_printf(seq
, "Offload B/s: %10llu %10llu %10llu %10llu\n",
844 (unsigned long long)orate
[0],
845 (unsigned long long)orate
[1],
846 (unsigned long long)orate
[2],
847 (unsigned long long)orate
[3]);
849 seq_puts(seq
, " channel 0 channel 1\n");
850 seq_printf(seq
, "NIC B/s: %10llu %10llu\n",
851 (unsigned long long)nrate
[0],
852 (unsigned long long)nrate
[1]);
853 seq_printf(seq
, "Offload B/s: %10llu %10llu\n",
854 (unsigned long long)orate
[0],
855 (unsigned long long)orate
[1]);
860 DEFINE_SIMPLE_DEBUGFS_FILE(tx_rate
);
862 static int cctrl_tbl_show(struct seq_file
*seq
, void *v
)
864 static const char * const dec_fac
[] = {
865 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
869 u16 (*incr
)[NCCTRL_WIN
];
870 struct adapter
*adap
= seq
->private;
872 incr
= kmalloc(sizeof(*incr
) * NMTUS
, GFP_KERNEL
);
876 t4_read_cong_tbl(adap
, incr
);
878 for (i
= 0; i
< NCCTRL_WIN
; ++i
) {
879 seq_printf(seq
, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i
,
880 incr
[0][i
], incr
[1][i
], incr
[2][i
], incr
[3][i
],
881 incr
[4][i
], incr
[5][i
], incr
[6][i
], incr
[7][i
]);
882 seq_printf(seq
, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
883 incr
[8][i
], incr
[9][i
], incr
[10][i
], incr
[11][i
],
884 incr
[12][i
], incr
[13][i
], incr
[14][i
], incr
[15][i
],
885 adap
->params
.a_wnd
[i
],
886 dec_fac
[adap
->params
.b_wnd
[i
]]);
893 DEFINE_SIMPLE_DEBUGFS_FILE(cctrl_tbl
);
895 /* Format a value in a unit that differs from the value's native unit by the
898 static char *unit_conv(char *buf
, size_t len
, unsigned int val
,
901 unsigned int rem
= val
% factor
;
904 snprintf(buf
, len
, "%u", val
/ factor
);
906 while (rem
% 10 == 0)
908 snprintf(buf
, len
, "%u.%u", val
/ factor
, rem
);
913 static int clk_show(struct seq_file
*seq
, void *v
)
916 struct adapter
*adap
= seq
->private;
917 unsigned int cclk_ps
= 1000000000 / adap
->params
.vpd
.cclk
; /* in ps */
918 u32 res
= t4_read_reg(adap
, TP_TIMER_RESOLUTION_A
);
919 unsigned int tre
= TIMERRESOLUTION_G(res
);
920 unsigned int dack_re
= DELAYEDACKRESOLUTION_G(res
);
921 unsigned long long tp_tick_us
= (cclk_ps
<< tre
) / 1000000; /* in us */
923 seq_printf(seq
, "Core clock period: %s ns\n",
924 unit_conv(buf
, sizeof(buf
), cclk_ps
, 1000));
925 seq_printf(seq
, "TP timer tick: %s us\n",
926 unit_conv(buf
, sizeof(buf
), (cclk_ps
<< tre
), 1000000));
927 seq_printf(seq
, "TCP timestamp tick: %s us\n",
928 unit_conv(buf
, sizeof(buf
),
929 (cclk_ps
<< TIMESTAMPRESOLUTION_G(res
)), 1000000));
930 seq_printf(seq
, "DACK tick: %s us\n",
931 unit_conv(buf
, sizeof(buf
), (cclk_ps
<< dack_re
), 1000000));
932 seq_printf(seq
, "DACK timer: %u us\n",
933 ((cclk_ps
<< dack_re
) / 1000000) *
934 t4_read_reg(adap
, TP_DACK_TIMER_A
));
935 seq_printf(seq
, "Retransmit min: %llu us\n",
936 tp_tick_us
* t4_read_reg(adap
, TP_RXT_MIN_A
));
937 seq_printf(seq
, "Retransmit max: %llu us\n",
938 tp_tick_us
* t4_read_reg(adap
, TP_RXT_MAX_A
));
939 seq_printf(seq
, "Persist timer min: %llu us\n",
940 tp_tick_us
* t4_read_reg(adap
, TP_PERS_MIN_A
));
941 seq_printf(seq
, "Persist timer max: %llu us\n",
942 tp_tick_us
* t4_read_reg(adap
, TP_PERS_MAX_A
));
943 seq_printf(seq
, "Keepalive idle timer: %llu us\n",
944 tp_tick_us
* t4_read_reg(adap
, TP_KEEP_IDLE_A
));
945 seq_printf(seq
, "Keepalive interval: %llu us\n",
946 tp_tick_us
* t4_read_reg(adap
, TP_KEEP_INTVL_A
));
947 seq_printf(seq
, "Initial SRTT: %llu us\n",
948 tp_tick_us
* INITSRTT_G(t4_read_reg(adap
, TP_INIT_SRTT_A
)));
949 seq_printf(seq
, "FINWAIT2 timer: %llu us\n",
950 tp_tick_us
* t4_read_reg(adap
, TP_FINWAIT2_TIMER_A
));
955 DEFINE_SIMPLE_DEBUGFS_FILE(clk
);
957 /* Firmware Device Log dump. */
958 static const char * const devlog_level_strings
[] = {
959 [FW_DEVLOG_LEVEL_EMERG
] = "EMERG",
960 [FW_DEVLOG_LEVEL_CRIT
] = "CRIT",
961 [FW_DEVLOG_LEVEL_ERR
] = "ERR",
962 [FW_DEVLOG_LEVEL_NOTICE
] = "NOTICE",
963 [FW_DEVLOG_LEVEL_INFO
] = "INFO",
964 [FW_DEVLOG_LEVEL_DEBUG
] = "DEBUG"
967 static const char * const devlog_facility_strings
[] = {
968 [FW_DEVLOG_FACILITY_CORE
] = "CORE",
969 [FW_DEVLOG_FACILITY_CF
] = "CF",
970 [FW_DEVLOG_FACILITY_SCHED
] = "SCHED",
971 [FW_DEVLOG_FACILITY_TIMER
] = "TIMER",
972 [FW_DEVLOG_FACILITY_RES
] = "RES",
973 [FW_DEVLOG_FACILITY_HW
] = "HW",
974 [FW_DEVLOG_FACILITY_FLR
] = "FLR",
975 [FW_DEVLOG_FACILITY_DMAQ
] = "DMAQ",
976 [FW_DEVLOG_FACILITY_PHY
] = "PHY",
977 [FW_DEVLOG_FACILITY_MAC
] = "MAC",
978 [FW_DEVLOG_FACILITY_PORT
] = "PORT",
979 [FW_DEVLOG_FACILITY_VI
] = "VI",
980 [FW_DEVLOG_FACILITY_FILTER
] = "FILTER",
981 [FW_DEVLOG_FACILITY_ACL
] = "ACL",
982 [FW_DEVLOG_FACILITY_TM
] = "TM",
983 [FW_DEVLOG_FACILITY_QFC
] = "QFC",
984 [FW_DEVLOG_FACILITY_DCB
] = "DCB",
985 [FW_DEVLOG_FACILITY_ETH
] = "ETH",
986 [FW_DEVLOG_FACILITY_OFLD
] = "OFLD",
987 [FW_DEVLOG_FACILITY_RI
] = "RI",
988 [FW_DEVLOG_FACILITY_ISCSI
] = "ISCSI",
989 [FW_DEVLOG_FACILITY_FCOE
] = "FCOE",
990 [FW_DEVLOG_FACILITY_FOISCSI
] = "FOISCSI",
991 [FW_DEVLOG_FACILITY_FOFCOE
] = "FOFCOE"
994 /* Information gathered by Device Log Open routine for the display routine.
997 unsigned int nentries
; /* number of entries in log[] */
998 unsigned int first
; /* first [temporal] entry in log[] */
999 struct fw_devlog_e log
[0]; /* Firmware Device Log */
1002 /* Dump a Firmaware Device Log entry.
1004 static int devlog_show(struct seq_file
*seq
, void *v
)
1006 if (v
== SEQ_START_TOKEN
)
1007 seq_printf(seq
, "%10s %15s %8s %8s %s\n",
1008 "Seq#", "Tstamp", "Level", "Facility", "Message");
1010 struct devlog_info
*dinfo
= seq
->private;
1011 int fidx
= (uintptr_t)v
- 2;
1012 unsigned long index
;
1013 struct fw_devlog_e
*e
;
1015 /* Get a pointer to the log entry to display. Skip unused log
1018 index
= dinfo
->first
+ fidx
;
1019 if (index
>= dinfo
->nentries
)
1020 index
-= dinfo
->nentries
;
1021 e
= &dinfo
->log
[index
];
1022 if (e
->timestamp
== 0)
1025 /* Print the message. This depends on the firmware using
1026 * exactly the same formating strings as the kernel so we may
1027 * eventually have to put a format interpreter in here ...
1029 seq_printf(seq
, "%10d %15llu %8s %8s ",
1030 be32_to_cpu(e
->seqno
),
1031 be64_to_cpu(e
->timestamp
),
1032 (e
->level
< ARRAY_SIZE(devlog_level_strings
)
1033 ? devlog_level_strings
[e
->level
]
1035 (e
->facility
< ARRAY_SIZE(devlog_facility_strings
)
1036 ? devlog_facility_strings
[e
->facility
]
1038 seq_printf(seq
, e
->fmt
,
1039 be32_to_cpu(e
->params
[0]),
1040 be32_to_cpu(e
->params
[1]),
1041 be32_to_cpu(e
->params
[2]),
1042 be32_to_cpu(e
->params
[3]),
1043 be32_to_cpu(e
->params
[4]),
1044 be32_to_cpu(e
->params
[5]),
1045 be32_to_cpu(e
->params
[6]),
1046 be32_to_cpu(e
->params
[7]));
1051 /* Sequential File Operations for Device Log.
1053 static inline void *devlog_get_idx(struct devlog_info
*dinfo
, loff_t pos
)
1055 if (pos
> dinfo
->nentries
)
1058 return (void *)(uintptr_t)(pos
+ 1);
1061 static void *devlog_start(struct seq_file
*seq
, loff_t
*pos
)
1063 struct devlog_info
*dinfo
= seq
->private;
1066 ? devlog_get_idx(dinfo
, *pos
)
1070 static void *devlog_next(struct seq_file
*seq
, void *v
, loff_t
*pos
)
1072 struct devlog_info
*dinfo
= seq
->private;
1075 return devlog_get_idx(dinfo
, *pos
);
1078 static void devlog_stop(struct seq_file
*seq
, void *v
)
1082 static const struct seq_operations devlog_seq_ops
= {
1083 .start
= devlog_start
,
1084 .next
= devlog_next
,
1085 .stop
= devlog_stop
,
1089 /* Set up for reading the firmware's device log. We read the entire log here
1090 * and then display it incrementally in devlog_show().
1092 static int devlog_open(struct inode
*inode
, struct file
*file
)
1094 struct adapter
*adap
= inode
->i_private
;
1095 struct devlog_params
*dparams
= &adap
->params
.devlog
;
1096 struct devlog_info
*dinfo
;
1101 /* If we don't know where the log is we can't do anything.
1103 if (dparams
->start
== 0)
1106 /* Allocate the space to read in the firmware's device log and set up
1107 * for the iterated call to our display function.
1109 dinfo
= __seq_open_private(file
, &devlog_seq_ops
,
1110 sizeof(*dinfo
) + dparams
->size
);
1114 /* Record the basic log buffer information and read in the raw log.
1116 dinfo
->nentries
= (dparams
->size
/ sizeof(struct fw_devlog_e
));
1118 spin_lock(&adap
->win0_lock
);
1119 ret
= t4_memory_rw(adap
, adap
->params
.drv_memwin
, dparams
->memtype
,
1120 dparams
->start
, dparams
->size
, (__be32
*)dinfo
->log
,
1122 spin_unlock(&adap
->win0_lock
);
1124 seq_release_private(inode
, file
);
1128 /* Find the earliest (lowest Sequence Number) log entry in the
1129 * circular Device Log.
1131 for (fseqno
= ~((u32
)0), index
= 0; index
< dinfo
->nentries
; index
++) {
1132 struct fw_devlog_e
*e
= &dinfo
->log
[index
];
1135 if (e
->timestamp
== 0)
1138 seqno
= be32_to_cpu(e
->seqno
);
1139 if (seqno
< fseqno
) {
1141 dinfo
->first
= index
;
1147 static const struct file_operations devlog_fops
= {
1148 .owner
= THIS_MODULE
,
1149 .open
= devlog_open
,
1151 .llseek
= seq_lseek
,
1152 .release
= seq_release_private
1155 static int mbox_show(struct seq_file
*seq
, void *v
)
1157 static const char * const owner
[] = { "none", "FW", "driver",
1158 "unknown", "<unread>" };
1161 unsigned int mbox
= (uintptr_t)seq
->private & 7;
1162 struct adapter
*adap
= seq
->private - mbox
;
1163 void __iomem
*addr
= adap
->regs
+ PF_REG(mbox
, CIM_PF_MAILBOX_DATA_A
);
1165 /* For T4 we don't have a shadow copy of the Mailbox Control register.
1166 * And since reading that real register causes a side effect of
1167 * granting ownership, we're best of simply not reading it at all.
1169 if (is_t4(adap
->params
.chip
)) {
1170 i
= 4; /* index of "<unread>" */
1172 unsigned int ctrl_reg
= CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A
;
1173 void __iomem
*ctrl
= adap
->regs
+ PF_REG(mbox
, ctrl_reg
);
1175 i
= MBOWNER_G(readl(ctrl
));
1178 seq_printf(seq
, "mailbox owned by %s\n\n", owner
[i
]);
1180 for (i
= 0; i
< MBOX_LEN
; i
+= 8)
1181 seq_printf(seq
, "%016llx\n",
1182 (unsigned long long)readq(addr
+ i
));
1186 static int mbox_open(struct inode
*inode
, struct file
*file
)
1188 return single_open(file
, mbox_show
, inode
->i_private
);
1191 static ssize_t
mbox_write(struct file
*file
, const char __user
*buf
,
1192 size_t count
, loff_t
*pos
)
1195 char c
= '\n', s
[256];
1196 unsigned long long data
[8];
1197 const struct inode
*ino
;
1199 struct adapter
*adap
;
1203 if (count
> sizeof(s
) - 1 || !count
)
1205 if (copy_from_user(s
, buf
, count
))
1209 if (sscanf(s
, "%llx %llx %llx %llx %llx %llx %llx %llx%c", &data
[0],
1210 &data
[1], &data
[2], &data
[3], &data
[4], &data
[5], &data
[6],
1211 &data
[7], &c
) < 8 || c
!= '\n')
1214 ino
= file_inode(file
);
1215 mbox
= (uintptr_t)ino
->i_private
& 7;
1216 adap
= ino
->i_private
- mbox
;
1217 addr
= adap
->regs
+ PF_REG(mbox
, CIM_PF_MAILBOX_DATA_A
);
1218 ctrl
= addr
+ MBOX_LEN
;
1220 if (MBOWNER_G(readl(ctrl
)) != X_MBOWNER_PL
)
1223 for (i
= 0; i
< 8; i
++)
1224 writeq(data
[i
], addr
+ 8 * i
);
1226 writel(MBMSGVALID_F
| MBOWNER_V(X_MBOWNER_FW
), ctrl
);
1230 static const struct file_operations mbox_debugfs_fops
= {
1231 .owner
= THIS_MODULE
,
1234 .llseek
= seq_lseek
,
1235 .release
= single_release
,
1239 static int mps_trc_show(struct seq_file
*seq
, void *v
)
1242 struct trace_params tp
;
1243 unsigned int trcidx
= (uintptr_t)seq
->private & 3;
1244 struct adapter
*adap
= seq
->private - trcidx
;
1246 t4_get_trace_filter(adap
, &tp
, trcidx
, &enabled
);
1248 seq_puts(seq
, "tracer is disabled\n");
1252 if (tp
.skip_ofst
* 8 >= TRACE_LEN
) {
1253 dev_err(adap
->pdev_dev
, "illegal trace pattern skip offset\n");
1257 i
= adap
->chan_map
[tp
.port
& 3];
1258 if (i
>= MAX_NPORTS
) {
1259 dev_err(adap
->pdev_dev
, "tracer %u is assigned "
1260 "to non-existing port\n", trcidx
);
1263 seq_printf(seq
, "tracer is capturing %s %s, ",
1264 adap
->port
[i
]->name
, tp
.port
< 4 ? "Rx" : "Tx");
1266 seq_printf(seq
, "tracer is capturing loopback %d, ",
1268 seq_printf(seq
, "snap length: %u, min length: %u\n", tp
.snap_len
,
1270 seq_printf(seq
, "packets captured %smatch filter\n",
1271 tp
.invert
? "do not " : "");
1274 seq_puts(seq
, "filter pattern: ");
1275 for (i
= 0; i
< tp
.skip_ofst
* 2; i
+= 2)
1276 seq_printf(seq
, "%08x%08x", tp
.data
[i
], tp
.data
[i
+ 1]);
1278 for (i
= 0; i
< tp
.skip_ofst
* 2; i
+= 2)
1279 seq_printf(seq
, "%08x%08x", tp
.mask
[i
], tp
.mask
[i
+ 1]);
1280 seq_puts(seq
, "@0\n");
1283 seq_puts(seq
, "filter pattern: ");
1284 for (i
= tp
.skip_ofst
* 2; i
< TRACE_LEN
/ 4; i
+= 2)
1285 seq_printf(seq
, "%08x%08x", tp
.data
[i
], tp
.data
[i
+ 1]);
1287 for (i
= tp
.skip_ofst
* 2; i
< TRACE_LEN
/ 4; i
+= 2)
1288 seq_printf(seq
, "%08x%08x", tp
.mask
[i
], tp
.mask
[i
+ 1]);
1289 seq_printf(seq
, "@%u\n", (tp
.skip_ofst
+ tp
.skip_len
) * 8);
1293 static int mps_trc_open(struct inode
*inode
, struct file
*file
)
1295 return single_open(file
, mps_trc_show
, inode
->i_private
);
1298 static unsigned int xdigit2int(unsigned char c
)
1300 return isdigit(c
) ? c
- '0' : tolower(c
) - 'a' + 10;
1303 #define TRC_PORT_NONE 0xff
1304 #define TRC_RSS_ENABLE 0x33
1305 #define TRC_RSS_DISABLE 0x13
1307 /* Set an MPS trace filter. Syntax is:
1311 * to disable tracing, or
1313 * interface qid=<qid no> [snaplen=<val>] [minlen=<val>] [not] [<pattern>]...
1315 * where interface is one of rxN, txN, or loopbackN, N = 0..3, qid can be one
1316 * of the NIC's response qid obtained from sge_qinfo and pattern has the form
1318 * <pattern data>[/<pattern mask>][@<anchor>]
1320 * Up to 2 filter patterns can be specified. If 2 are supplied the first one
1321 * must be anchored at 0. An omited mask is taken as a mask of 1s, an omitted
1322 * anchor is taken as 0.
1324 static ssize_t
mps_trc_write(struct file
*file
, const char __user
*buf
,
1325 size_t count
, loff_t
*pos
)
1329 struct trace_params tp
;
1330 const struct inode
*ino
;
1331 unsigned int trcidx
;
1332 char *s
, *p
, *word
, *end
;
1333 struct adapter
*adap
;
1336 ino
= file_inode(file
);
1337 trcidx
= (uintptr_t)ino
->i_private
& 3;
1338 adap
= ino
->i_private
- trcidx
;
1340 /* Don't accept input more than 1K, can't be anything valid except lots
1341 * of whitespace. Well, use less.
1345 p
= s
= kzalloc(count
+ 1, GFP_USER
);
1348 if (copy_from_user(s
, buf
, count
)) {
1353 if (s
[count
- 1] == '\n')
1354 s
[count
- 1] = '\0';
1356 enable
= strcmp("disable", s
) != 0;
1360 /* enable or disable trace multi rss filter */
1361 if (adap
->trace_rss
)
1362 t4_write_reg(adap
, MPS_TRC_CFG_A
, TRC_RSS_ENABLE
);
1364 t4_write_reg(adap
, MPS_TRC_CFG_A
, TRC_RSS_DISABLE
);
1366 memset(&tp
, 0, sizeof(tp
));
1367 tp
.port
= TRC_PORT_NONE
;
1368 i
= 0; /* counts pattern nibbles */
1373 word
= strsep(&p
, " ");
1377 if (!strncmp(word
, "qid=", 4)) {
1378 end
= (char *)word
+ 4;
1379 ret
= kstrtouint(end
, 10, &j
);
1382 if (!adap
->trace_rss
) {
1383 t4_write_reg(adap
, MPS_T5_TRC_RSS_CONTROL_A
, j
);
1389 t4_write_reg(adap
, MPS_TRC_RSS_CONTROL_A
, j
);
1393 MPS_TRC_FILTER1_RSS_CONTROL_A
, j
);
1397 MPS_TRC_FILTER2_RSS_CONTROL_A
, j
);
1401 MPS_TRC_FILTER3_RSS_CONTROL_A
, j
);
1406 if (!strncmp(word
, "snaplen=", 8)) {
1407 end
= (char *)word
+ 8;
1408 ret
= kstrtouint(end
, 10, &j
);
1409 if (ret
|| j
> 9600) {
1410 inval
: count
= -EINVAL
;
1416 if (!strncmp(word
, "minlen=", 7)) {
1417 end
= (char *)word
+ 7;
1418 ret
= kstrtouint(end
, 10, &j
);
1419 if (ret
|| j
> TFMINPKTSIZE_M
)
1424 if (!strcmp(word
, "not")) {
1425 tp
.invert
= !tp
.invert
;
1428 if (!strncmp(word
, "loopback", 8) && tp
.port
== TRC_PORT_NONE
) {
1429 if (word
[8] < '0' || word
[8] > '3' || word
[9])
1431 tp
.port
= word
[8] - '0' + 8;
1434 if (!strncmp(word
, "tx", 2) && tp
.port
== TRC_PORT_NONE
) {
1435 if (word
[2] < '0' || word
[2] > '3' || word
[3])
1437 tp
.port
= word
[2] - '0' + 4;
1438 if (adap
->chan_map
[tp
.port
& 3] >= MAX_NPORTS
)
1442 if (!strncmp(word
, "rx", 2) && tp
.port
== TRC_PORT_NONE
) {
1443 if (word
[2] < '0' || word
[2] > '3' || word
[3])
1445 tp
.port
= word
[2] - '0';
1446 if (adap
->chan_map
[tp
.port
] >= MAX_NPORTS
)
1450 if (!isxdigit(*word
))
1453 /* we have found a trace pattern */
1454 if (i
) { /* split pattern */
1455 if (tp
.skip_len
) /* too many splits */
1457 tp
.skip_ofst
= i
/ 16;
1460 data
= &tp
.data
[i
/ 8];
1461 mask
= &tp
.mask
[i
/ 8];
1464 while (isxdigit(*word
)) {
1465 if (i
>= TRACE_LEN
* 2) {
1469 *data
= (*data
<< 4) + xdigit2int(*word
++);
1475 while (isxdigit(*word
)) {
1476 if (j
>= i
) /* mask longer than data */
1478 *mask
= (*mask
<< 4) + xdigit2int(*word
++);
1482 if (i
!= j
) /* mask shorter than data */
1484 } else { /* no mask, use all 1s */
1485 for ( ; i
- j
>= 8; j
+= 8)
1486 *mask
++ = 0xffffffff;
1488 *mask
= (1 << (i
% 8) * 4) - 1;
1491 end
= (char *)word
+ 1;
1492 ret
= kstrtouint(end
, 10, &j
);
1493 if (*end
&& *end
!= '\n')
1495 if (j
& 7) /* doesn't start at multiple of 8 */
1498 if (j
< tp
.skip_ofst
) /* overlaps earlier pattern */
1500 if (j
- tp
.skip_ofst
> 31) /* skip too big */
1502 tp
.skip_len
= j
- tp
.skip_ofst
;
1505 *data
<<= (8 - i
% 8) * 4;
1506 *mask
<<= (8 - i
% 8) * 4;
1507 i
= (i
+ 15) & ~15; /* 8-byte align */
1511 if (tp
.port
== TRC_PORT_NONE
)
1515 i
= t4_set_trace_filter(adap
, &tp
, trcidx
, enable
);
1523 static const struct file_operations mps_trc_debugfs_fops
= {
1524 .owner
= THIS_MODULE
,
1525 .open
= mps_trc_open
,
1527 .llseek
= seq_lseek
,
1528 .release
= single_release
,
1529 .write
= mps_trc_write
1532 static ssize_t
flash_read(struct file
*file
, char __user
*buf
, size_t count
,
1536 loff_t avail
= file_inode(file
)->i_size
;
1537 struct adapter
*adap
= file
->private_data
;
1543 if (count
> avail
- pos
)
1544 count
= avail
- pos
;
1552 len
= min(count
+ ofst
, sizeof(data
));
1553 ret
= t4_read_flash(adap
, pos
- ofst
, (len
+ 3) / 4,
1559 if (copy_to_user(buf
, data
+ ofst
, len
))
1566 count
= pos
- *ppos
;
1571 static const struct file_operations flash_debugfs_fops
= {
1572 .owner
= THIS_MODULE
,
1577 static inline void tcamxy2valmask(u64 x
, u64 y
, u8
*addr
, u64
*mask
)
1580 y
= (__force u64
)cpu_to_be64(y
);
1581 memcpy(addr
, (char *)&y
+ 2, ETH_ALEN
);
1584 static int mps_tcam_show(struct seq_file
*seq
, void *v
)
1586 struct adapter
*adap
= seq
->private;
1587 unsigned int chip_ver
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
1588 if (v
== SEQ_START_TOKEN
) {
1589 if (chip_ver
> CHELSIO_T5
) {
1590 seq_puts(seq
, "Idx Ethernet address Mask "
1591 " VNI Mask IVLAN Vld "
1592 "DIP_Hit Lookup Port "
1595 " P0 P1 P2 P3 ML\n");
1597 if (adap
->params
.arch
.mps_rplc_size
> 128)
1598 seq_puts(seq
, "Idx Ethernet address Mask "
1601 " P0 P1 P2 P3 ML\n");
1603 seq_puts(seq
, "Idx Ethernet address Mask "
1604 "Vld Ports PF VF Replication"
1605 " P0 P1 P2 P3 ML\n");
1610 bool replicate
, dip_hit
= false, vlan_vld
= false;
1611 unsigned int idx
= (uintptr_t)v
- 2;
1612 u64 tcamy
, tcamx
, val
;
1613 u32 cls_lo
, cls_hi
, ctl
, data2
, vnix
= 0, vniy
= 0;
1615 u8 lookup_type
= 0, port_num
= 0;
1618 if (chip_ver
> CHELSIO_T5
) {
1619 /* CtlCmdType - 0: Read, 1: Write
1620 * CtlTcamSel - 0: TCAM0, 1: TCAM1
1621 * CtlXYBitSel- 0: Y bit, 1: X bit
1625 ctl
= CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0);
1627 ctl
|= CTLTCAMINDEX_V(idx
) | CTLTCAMSEL_V(0);
1629 ctl
|= CTLTCAMINDEX_V(idx
- 256) |
1631 t4_write_reg(adap
, MPS_CLS_TCAM_DATA2_CTL_A
, ctl
);
1632 val
= t4_read_reg(adap
, MPS_CLS_TCAM_DATA1_A
);
1633 tcamy
= DMACH_G(val
) << 32;
1634 tcamy
|= t4_read_reg(adap
, MPS_CLS_TCAM_DATA0_A
);
1635 data2
= t4_read_reg(adap
, MPS_CLS_TCAM_DATA2_CTL_A
);
1636 lookup_type
= DATALKPTYPE_G(data2
);
1637 /* 0 - Outer header, 1 - Inner header
1638 * [71:48] bit locations are overloaded for
1639 * outer vs. inner lookup types.
1641 if (lookup_type
&& (lookup_type
!= DATALKPTYPE_M
)) {
1642 /* Inner header VNI */
1643 vniy
= ((data2
& DATAVIDH2_F
) << 23) |
1644 (DATAVIDH1_G(data2
) << 16) | VIDL_G(val
);
1645 dip_hit
= data2
& DATADIPHIT_F
;
1647 vlan_vld
= data2
& DATAVIDH2_F
;
1648 ivlan
= VIDL_G(val
);
1650 port_num
= DATAPORTNUM_G(data2
);
1652 /* Read tcamx. Change the control param */
1653 ctl
|= CTLXYBITSEL_V(1);
1654 t4_write_reg(adap
, MPS_CLS_TCAM_DATA2_CTL_A
, ctl
);
1655 val
= t4_read_reg(adap
, MPS_CLS_TCAM_DATA1_A
);
1656 tcamx
= DMACH_G(val
) << 32;
1657 tcamx
|= t4_read_reg(adap
, MPS_CLS_TCAM_DATA0_A
);
1658 data2
= t4_read_reg(adap
, MPS_CLS_TCAM_DATA2_CTL_A
);
1659 if (lookup_type
&& (lookup_type
!= DATALKPTYPE_M
)) {
1660 /* Inner header VNI mask */
1661 vnix
= ((data2
& DATAVIDH2_F
) << 23) |
1662 (DATAVIDH1_G(data2
) << 16) | VIDL_G(val
);
1665 tcamy
= t4_read_reg64(adap
, MPS_CLS_TCAM_Y_L(idx
));
1666 tcamx
= t4_read_reg64(adap
, MPS_CLS_TCAM_X_L(idx
));
1669 cls_lo
= t4_read_reg(adap
, MPS_CLS_SRAM_L(idx
));
1670 cls_hi
= t4_read_reg(adap
, MPS_CLS_SRAM_H(idx
));
1672 if (tcamx
& tcamy
) {
1673 seq_printf(seq
, "%3u -\n", idx
);
1677 rplc
[0] = rplc
[1] = rplc
[2] = rplc
[3] = 0;
1678 if (chip_ver
> CHELSIO_T5
)
1679 replicate
= (cls_lo
& T6_REPLICATE_F
);
1681 replicate
= (cls_lo
& REPLICATE_F
);
1684 struct fw_ldst_cmd ldst_cmd
;
1686 struct fw_ldst_mps_rplc mps_rplc
;
1689 memset(&ldst_cmd
, 0, sizeof(ldst_cmd
));
1691 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS
);
1692 ldst_cmd
.op_to_addrspace
=
1693 htonl(FW_CMD_OP_V(FW_LDST_CMD
) |
1697 ldst_cmd
.cycles_to_len16
= htonl(FW_LEN16(ldst_cmd
));
1698 ldst_cmd
.u
.mps
.rplc
.fid_idx
=
1699 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC
) |
1700 FW_LDST_CMD_IDX_V(idx
));
1701 ret
= t4_wr_mbox(adap
, adap
->mbox
, &ldst_cmd
,
1702 sizeof(ldst_cmd
), &ldst_cmd
);
1704 dev_warn(adap
->pdev_dev
, "Can't read MPS "
1705 "replication map for idx %d: %d\n",
1708 mps_rplc
= ldst_cmd
.u
.mps
.rplc
;
1709 rplc
[0] = ntohl(mps_rplc
.rplc31_0
);
1710 rplc
[1] = ntohl(mps_rplc
.rplc63_32
);
1711 rplc
[2] = ntohl(mps_rplc
.rplc95_64
);
1712 rplc
[3] = ntohl(mps_rplc
.rplc127_96
);
1713 if (adap
->params
.arch
.mps_rplc_size
> 128) {
1714 rplc
[4] = ntohl(mps_rplc
.rplc159_128
);
1715 rplc
[5] = ntohl(mps_rplc
.rplc191_160
);
1716 rplc
[6] = ntohl(mps_rplc
.rplc223_192
);
1717 rplc
[7] = ntohl(mps_rplc
.rplc255_224
);
1722 tcamxy2valmask(tcamx
, tcamy
, addr
, &mask
);
1723 if (chip_ver
> CHELSIO_T5
) {
1724 /* Inner header lookup */
1725 if (lookup_type
&& (lookup_type
!= DATALKPTYPE_M
)) {
1727 "%3u %02x:%02x:%02x:%02x:%02x:%02x "
1728 "%012llx %06x %06x - - %3c"
1730 "%3c %#x%4u%4d", idx
, addr
[0],
1731 addr
[1], addr
[2], addr
[3],
1733 (unsigned long long)mask
,
1734 vniy
, vnix
, dip_hit
? 'Y' : 'N',
1735 lookup_type
? 'I' : 'O', port_num
,
1736 (cls_lo
& T6_SRAM_VLD_F
) ? 'Y' : 'N',
1739 (cls_lo
& T6_VF_VALID_F
) ?
1740 T6_VF_G(cls_lo
) : -1);
1743 "%3u %02x:%02x:%02x:%02x:%02x:%02x "
1745 idx
, addr
[0], addr
[1], addr
[2],
1746 addr
[3], addr
[4], addr
[5],
1747 (unsigned long long)mask
);
1750 seq_printf(seq
, "%4u Y ", ivlan
);
1752 seq_puts(seq
, " - N ");
1755 "- %3c %4x %3c %#x%4u%4d",
1756 lookup_type
? 'I' : 'O', port_num
,
1757 (cls_lo
& T6_SRAM_VLD_F
) ? 'Y' : 'N',
1760 (cls_lo
& T6_VF_VALID_F
) ?
1761 T6_VF_G(cls_lo
) : -1);
1764 seq_printf(seq
, "%3u %02x:%02x:%02x:%02x:%02x:%02x "
1765 "%012llx%3c %#x%4u%4d",
1766 idx
, addr
[0], addr
[1], addr
[2], addr
[3],
1767 addr
[4], addr
[5], (unsigned long long)mask
,
1768 (cls_lo
& SRAM_VLD_F
) ? 'Y' : 'N',
1771 (cls_lo
& VF_VALID_F
) ? VF_G(cls_lo
) : -1);
1774 if (adap
->params
.arch
.mps_rplc_size
> 128)
1775 seq_printf(seq
, " %08x %08x %08x %08x "
1776 "%08x %08x %08x %08x",
1777 rplc
[7], rplc
[6], rplc
[5], rplc
[4],
1778 rplc
[3], rplc
[2], rplc
[1], rplc
[0]);
1780 seq_printf(seq
, " %08x %08x %08x %08x",
1781 rplc
[3], rplc
[2], rplc
[1], rplc
[0]);
1783 if (adap
->params
.arch
.mps_rplc_size
> 128)
1784 seq_printf(seq
, "%72c", ' ');
1786 seq_printf(seq
, "%36c", ' ');
1789 if (chip_ver
> CHELSIO_T5
)
1790 seq_printf(seq
, "%4u%3u%3u%3u %#x\n",
1791 T6_SRAM_PRIO0_G(cls_lo
),
1792 T6_SRAM_PRIO1_G(cls_lo
),
1793 T6_SRAM_PRIO2_G(cls_lo
),
1794 T6_SRAM_PRIO3_G(cls_lo
),
1795 (cls_lo
>> T6_MULTILISTEN0_S
) & 0xf);
1797 seq_printf(seq
, "%4u%3u%3u%3u %#x\n",
1798 SRAM_PRIO0_G(cls_lo
), SRAM_PRIO1_G(cls_lo
),
1799 SRAM_PRIO2_G(cls_lo
), SRAM_PRIO3_G(cls_lo
),
1800 (cls_lo
>> MULTILISTEN0_S
) & 0xf);
1805 static inline void *mps_tcam_get_idx(struct seq_file
*seq
, loff_t pos
)
1807 struct adapter
*adap
= seq
->private;
1808 int max_mac_addr
= is_t4(adap
->params
.chip
) ?
1809 NUM_MPS_CLS_SRAM_L_INSTANCES
:
1810 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
1811 return ((pos
<= max_mac_addr
) ? (void *)(uintptr_t)(pos
+ 1) : NULL
);
1814 static void *mps_tcam_start(struct seq_file
*seq
, loff_t
*pos
)
1816 return *pos
? mps_tcam_get_idx(seq
, *pos
) : SEQ_START_TOKEN
;
1819 static void *mps_tcam_next(struct seq_file
*seq
, void *v
, loff_t
*pos
)
1822 return mps_tcam_get_idx(seq
, *pos
);
1825 static void mps_tcam_stop(struct seq_file
*seq
, void *v
)
1829 static const struct seq_operations mps_tcam_seq_ops
= {
1830 .start
= mps_tcam_start
,
1831 .next
= mps_tcam_next
,
1832 .stop
= mps_tcam_stop
,
1833 .show
= mps_tcam_show
1836 static int mps_tcam_open(struct inode
*inode
, struct file
*file
)
1838 int res
= seq_open(file
, &mps_tcam_seq_ops
);
1841 struct seq_file
*seq
= file
->private_data
;
1843 seq
->private = inode
->i_private
;
1848 static const struct file_operations mps_tcam_debugfs_fops
= {
1849 .owner
= THIS_MODULE
,
1850 .open
= mps_tcam_open
,
1852 .llseek
= seq_lseek
,
1853 .release
= seq_release
,
1856 /* Display various sensor information.
1858 static int sensors_show(struct seq_file
*seq
, void *v
)
1860 struct adapter
*adap
= seq
->private;
1861 u32 param
[7], val
[7];
1864 /* Note that if the sensors haven't been initialized and turned on
1865 * we'll get values of 0, so treat those as "<unknown>" ...
1867 param
[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
1868 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DIAG
) |
1869 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_DIAG_TMP
));
1870 param
[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
1871 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DIAG
) |
1872 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_DIAG_VDD
));
1873 ret
= t4_query_params(adap
, adap
->mbox
, adap
->pf
, 0, 2,
1876 if (ret
< 0 || val
[0] == 0)
1877 seq_puts(seq
, "Temperature: <unknown>\n");
1879 seq_printf(seq
, "Temperature: %dC\n", val
[0]);
1881 if (ret
< 0 || val
[1] == 0)
1882 seq_puts(seq
, "Core VDD: <unknown>\n");
1884 seq_printf(seq
, "Core VDD: %dmV\n", val
[1]);
1889 DEFINE_SIMPLE_DEBUGFS_FILE(sensors
);
1891 #if IS_ENABLED(CONFIG_IPV6)
1892 static int clip_tbl_open(struct inode
*inode
, struct file
*file
)
1894 return single_open(file
, clip_tbl_show
, inode
->i_private
);
1897 static const struct file_operations clip_tbl_debugfs_fops
= {
1898 .owner
= THIS_MODULE
,
1899 .open
= clip_tbl_open
,
1901 .llseek
= seq_lseek
,
1902 .release
= single_release
1909 static int rss_show(struct seq_file
*seq
, void *v
, int idx
)
1913 seq_printf(seq
, "%4d: %4u %4u %4u %4u %4u %4u %4u %4u\n",
1914 idx
* 8, entry
[0], entry
[1], entry
[2], entry
[3], entry
[4],
1915 entry
[5], entry
[6], entry
[7]);
1919 static int rss_open(struct inode
*inode
, struct file
*file
)
1923 struct adapter
*adap
= inode
->i_private
;
1925 p
= seq_open_tab(file
, RSS_NENTRIES
/ 8, 8 * sizeof(u16
), 0, rss_show
);
1929 ret
= t4_read_rss(adap
, (u16
*)p
->data
);
1931 seq_release_private(inode
, file
);
1936 static const struct file_operations rss_debugfs_fops
= {
1937 .owner
= THIS_MODULE
,
1940 .llseek
= seq_lseek
,
1941 .release
= seq_release_private
1944 /* RSS Configuration.
1947 /* Small utility function to return the strings "yes" or "no" if the supplied
1948 * argument is non-zero.
1950 static const char *yesno(int x
)
1952 static const char *yes
= "yes";
1953 static const char *no
= "no";
1955 return x
? yes
: no
;
1958 static int rss_config_show(struct seq_file
*seq
, void *v
)
1960 struct adapter
*adapter
= seq
->private;
1961 static const char * const keymode
[] = {
1963 "global and per-VF scramble",
1964 "per-PF and per-VF scramble",
1965 "per-VF and per-VF scramble",
1969 rssconf
= t4_read_reg(adapter
, TP_RSS_CONFIG_A
);
1970 seq_printf(seq
, "TP_RSS_CONFIG: %#x\n", rssconf
);
1971 seq_printf(seq
, " Tnl4TupEnIpv6: %3s\n", yesno(rssconf
&
1973 seq_printf(seq
, " Tnl2TupEnIpv6: %3s\n", yesno(rssconf
&
1975 seq_printf(seq
, " Tnl4TupEnIpv4: %3s\n", yesno(rssconf
&
1977 seq_printf(seq
, " Tnl2TupEnIpv4: %3s\n", yesno(rssconf
&
1979 seq_printf(seq
, " TnlTcpSel: %3s\n", yesno(rssconf
& TNLTCPSEL_F
));
1980 seq_printf(seq
, " TnlIp6Sel: %3s\n", yesno(rssconf
& TNLIP6SEL_F
));
1981 seq_printf(seq
, " TnlVrtSel: %3s\n", yesno(rssconf
& TNLVRTSEL_F
));
1982 seq_printf(seq
, " TnlMapEn: %3s\n", yesno(rssconf
& TNLMAPEN_F
));
1983 seq_printf(seq
, " OfdHashSave: %3s\n", yesno(rssconf
&
1985 seq_printf(seq
, " OfdVrtSel: %3s\n", yesno(rssconf
& OFDVRTSEL_F
));
1986 seq_printf(seq
, " OfdMapEn: %3s\n", yesno(rssconf
& OFDMAPEN_F
));
1987 seq_printf(seq
, " OfdLkpEn: %3s\n", yesno(rssconf
& OFDLKPEN_F
));
1988 seq_printf(seq
, " Syn4TupEnIpv6: %3s\n", yesno(rssconf
&
1990 seq_printf(seq
, " Syn2TupEnIpv6: %3s\n", yesno(rssconf
&
1992 seq_printf(seq
, " Syn4TupEnIpv4: %3s\n", yesno(rssconf
&
1994 seq_printf(seq
, " Syn2TupEnIpv4: %3s\n", yesno(rssconf
&
1996 seq_printf(seq
, " Syn4TupEnIpv6: %3s\n", yesno(rssconf
&
1998 seq_printf(seq
, " SynIp6Sel: %3s\n", yesno(rssconf
& SYNIP6SEL_F
));
1999 seq_printf(seq
, " SynVrt6Sel: %3s\n", yesno(rssconf
& SYNVRTSEL_F
));
2000 seq_printf(seq
, " SynMapEn: %3s\n", yesno(rssconf
& SYNMAPEN_F
));
2001 seq_printf(seq
, " SynLkpEn: %3s\n", yesno(rssconf
& SYNLKPEN_F
));
2002 seq_printf(seq
, " ChnEn: %3s\n", yesno(rssconf
&
2004 seq_printf(seq
, " PrtEn: %3s\n", yesno(rssconf
&
2006 seq_printf(seq
, " TnlAllLkp: %3s\n", yesno(rssconf
&
2008 seq_printf(seq
, " VrtEn: %3s\n", yesno(rssconf
&
2010 seq_printf(seq
, " CngEn: %3s\n", yesno(rssconf
&
2011 CONGESTIONENABLE_F
));
2012 seq_printf(seq
, " HashToeplitz: %3s\n", yesno(rssconf
&
2014 seq_printf(seq
, " Udp4En: %3s\n", yesno(rssconf
& UDPENABLE_F
));
2015 seq_printf(seq
, " Disable: %3s\n", yesno(rssconf
& DISABLE_F
));
2017 seq_puts(seq
, "\n");
2019 rssconf
= t4_read_reg(adapter
, TP_RSS_CONFIG_TNL_A
);
2020 seq_printf(seq
, "TP_RSS_CONFIG_TNL: %#x\n", rssconf
);
2021 seq_printf(seq
, " MaskSize: %3d\n", MASKSIZE_G(rssconf
));
2022 seq_printf(seq
, " MaskFilter: %3d\n", MASKFILTER_G(rssconf
));
2023 if (CHELSIO_CHIP_VERSION(adapter
->params
.chip
) > CHELSIO_T5
) {
2024 seq_printf(seq
, " HashAll: %3s\n",
2025 yesno(rssconf
& HASHALL_F
));
2026 seq_printf(seq
, " HashEth: %3s\n",
2027 yesno(rssconf
& HASHETH_F
));
2029 seq_printf(seq
, " UseWireCh: %3s\n", yesno(rssconf
& USEWIRECH_F
));
2031 seq_puts(seq
, "\n");
2033 rssconf
= t4_read_reg(adapter
, TP_RSS_CONFIG_OFD_A
);
2034 seq_printf(seq
, "TP_RSS_CONFIG_OFD: %#x\n", rssconf
);
2035 seq_printf(seq
, " MaskSize: %3d\n", MASKSIZE_G(rssconf
));
2036 seq_printf(seq
, " RRCplMapEn: %3s\n", yesno(rssconf
&
2038 seq_printf(seq
, " RRCplQueWidth: %3d\n", RRCPLQUEWIDTH_G(rssconf
));
2040 seq_puts(seq
, "\n");
2042 rssconf
= t4_read_reg(adapter
, TP_RSS_CONFIG_SYN_A
);
2043 seq_printf(seq
, "TP_RSS_CONFIG_SYN: %#x\n", rssconf
);
2044 seq_printf(seq
, " MaskSize: %3d\n", MASKSIZE_G(rssconf
));
2045 seq_printf(seq
, " UseWireCh: %3s\n", yesno(rssconf
& USEWIRECH_F
));
2047 seq_puts(seq
, "\n");
2049 rssconf
= t4_read_reg(adapter
, TP_RSS_CONFIG_VRT_A
);
2050 seq_printf(seq
, "TP_RSS_CONFIG_VRT: %#x\n", rssconf
);
2051 if (CHELSIO_CHIP_VERSION(adapter
->params
.chip
) > CHELSIO_T5
) {
2052 seq_printf(seq
, " KeyWrAddrX: %3d\n",
2053 KEYWRADDRX_G(rssconf
));
2054 seq_printf(seq
, " KeyExtend: %3s\n",
2055 yesno(rssconf
& KEYEXTEND_F
));
2057 seq_printf(seq
, " VfRdRg: %3s\n", yesno(rssconf
& VFRDRG_F
));
2058 seq_printf(seq
, " VfRdEn: %3s\n", yesno(rssconf
& VFRDEN_F
));
2059 seq_printf(seq
, " VfPerrEn: %3s\n", yesno(rssconf
& VFPERREN_F
));
2060 seq_printf(seq
, " KeyPerrEn: %3s\n", yesno(rssconf
& KEYPERREN_F
));
2061 seq_printf(seq
, " DisVfVlan: %3s\n", yesno(rssconf
&
2063 seq_printf(seq
, " EnUpSwt: %3s\n", yesno(rssconf
& ENABLEUP0_F
));
2064 seq_printf(seq
, " HashDelay: %3d\n", HASHDELAY_G(rssconf
));
2065 if (CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
)
2066 seq_printf(seq
, " VfWrAddr: %3d\n", VFWRADDR_G(rssconf
));
2068 seq_printf(seq
, " VfWrAddr: %3d\n",
2069 T6_VFWRADDR_G(rssconf
));
2070 seq_printf(seq
, " KeyMode: %s\n", keymode
[KEYMODE_G(rssconf
)]);
2071 seq_printf(seq
, " VfWrEn: %3s\n", yesno(rssconf
& VFWREN_F
));
2072 seq_printf(seq
, " KeyWrEn: %3s\n", yesno(rssconf
& KEYWREN_F
));
2073 seq_printf(seq
, " KeyWrAddr: %3d\n", KEYWRADDR_G(rssconf
));
2075 seq_puts(seq
, "\n");
2077 rssconf
= t4_read_reg(adapter
, TP_RSS_CONFIG_CNG_A
);
2078 seq_printf(seq
, "TP_RSS_CONFIG_CNG: %#x\n", rssconf
);
2079 seq_printf(seq
, " ChnCount3: %3s\n", yesno(rssconf
& CHNCOUNT3_F
));
2080 seq_printf(seq
, " ChnCount2: %3s\n", yesno(rssconf
& CHNCOUNT2_F
));
2081 seq_printf(seq
, " ChnCount1: %3s\n", yesno(rssconf
& CHNCOUNT1_F
));
2082 seq_printf(seq
, " ChnCount0: %3s\n", yesno(rssconf
& CHNCOUNT0_F
));
2083 seq_printf(seq
, " ChnUndFlow3: %3s\n", yesno(rssconf
&
2085 seq_printf(seq
, " ChnUndFlow2: %3s\n", yesno(rssconf
&
2087 seq_printf(seq
, " ChnUndFlow1: %3s\n", yesno(rssconf
&
2089 seq_printf(seq
, " ChnUndFlow0: %3s\n", yesno(rssconf
&
2091 seq_printf(seq
, " RstChn3: %3s\n", yesno(rssconf
& RSTCHN3_F
));
2092 seq_printf(seq
, " RstChn2: %3s\n", yesno(rssconf
& RSTCHN2_F
));
2093 seq_printf(seq
, " RstChn1: %3s\n", yesno(rssconf
& RSTCHN1_F
));
2094 seq_printf(seq
, " RstChn0: %3s\n", yesno(rssconf
& RSTCHN0_F
));
2095 seq_printf(seq
, " UpdVld: %3s\n", yesno(rssconf
& UPDVLD_F
));
2096 seq_printf(seq
, " Xoff: %3s\n", yesno(rssconf
& XOFF_F
));
2097 seq_printf(seq
, " UpdChn3: %3s\n", yesno(rssconf
& UPDCHN3_F
));
2098 seq_printf(seq
, " UpdChn2: %3s\n", yesno(rssconf
& UPDCHN2_F
));
2099 seq_printf(seq
, " UpdChn1: %3s\n", yesno(rssconf
& UPDCHN1_F
));
2100 seq_printf(seq
, " UpdChn0: %3s\n", yesno(rssconf
& UPDCHN0_F
));
2101 seq_printf(seq
, " Queue: %3d\n", QUEUE_G(rssconf
));
2106 DEFINE_SIMPLE_DEBUGFS_FILE(rss_config
);
2111 static int rss_key_show(struct seq_file
*seq
, void *v
)
2115 t4_read_rss_key(seq
->private, key
);
2116 seq_printf(seq
, "%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x\n",
2117 key
[9], key
[8], key
[7], key
[6], key
[5], key
[4], key
[3],
2118 key
[2], key
[1], key
[0]);
2122 static int rss_key_open(struct inode
*inode
, struct file
*file
)
2124 return single_open(file
, rss_key_show
, inode
->i_private
);
2127 static ssize_t
rss_key_write(struct file
*file
, const char __user
*buf
,
2128 size_t count
, loff_t
*pos
)
2133 struct adapter
*adap
= file_inode(file
)->i_private
;
2135 if (count
> sizeof(s
) - 1)
2137 if (copy_from_user(s
, buf
, count
))
2139 for (i
= count
; i
> 0 && isspace(s
[i
- 1]); i
--)
2143 for (p
= s
, i
= 9; i
>= 0; i
--) {
2145 for (j
= 0; j
< 8; j
++, p
++) {
2148 key
[i
] = (key
[i
] << 4) | hex2val(*p
);
2152 t4_write_rss_key(adap
, key
, -1);
2156 static const struct file_operations rss_key_debugfs_fops
= {
2157 .owner
= THIS_MODULE
,
2158 .open
= rss_key_open
,
2160 .llseek
= seq_lseek
,
2161 .release
= single_release
,
2162 .write
= rss_key_write
2165 /* PF RSS Configuration.
2168 struct rss_pf_conf
{
2174 static int rss_pf_config_show(struct seq_file
*seq
, void *v
, int idx
)
2176 struct rss_pf_conf
*pfconf
;
2178 if (v
== SEQ_START_TOKEN
) {
2179 /* use the 0th entry to dump the PF Map Index Size */
2180 pfconf
= seq
->private + offsetof(struct seq_tab
, data
);
2181 seq_printf(seq
, "PF Map Index Size = %d\n\n",
2182 LKPIDXSIZE_G(pfconf
->rss_pf_map
));
2184 seq_puts(seq
, " RSS PF VF Hash Tuple Enable Default\n");
2185 seq_puts(seq
, " Enable IPF Mask Mask IPv6 IPv4 UDP Queue\n");
2186 seq_puts(seq
, " PF Map Chn Prt Map Size Size Four Two Four Two Four Ch1 Ch0\n");
2188 #define G_PFnLKPIDX(map, n) \
2189 (((map) >> PF1LKPIDX_S*(n)) & PF0LKPIDX_M)
2190 #define G_PFnMSKSIZE(mask, n) \
2191 (((mask) >> PF1MSKSIZE_S*(n)) & PF1MSKSIZE_M)
2194 seq_printf(seq
, "%3d %3s %3s %3s %3d %3d %3d %3s %3s %3s %3s %3s %3d %3d\n",
2196 yesno(pfconf
->rss_pf_config
& MAPENABLE_F
),
2197 yesno(pfconf
->rss_pf_config
& CHNENABLE_F
),
2198 yesno(pfconf
->rss_pf_config
& PRTENABLE_F
),
2199 G_PFnLKPIDX(pfconf
->rss_pf_map
, idx
),
2200 G_PFnMSKSIZE(pfconf
->rss_pf_mask
, idx
),
2201 IVFWIDTH_G(pfconf
->rss_pf_config
),
2202 yesno(pfconf
->rss_pf_config
& IP6FOURTUPEN_F
),
2203 yesno(pfconf
->rss_pf_config
& IP6TWOTUPEN_F
),
2204 yesno(pfconf
->rss_pf_config
& IP4FOURTUPEN_F
),
2205 yesno(pfconf
->rss_pf_config
& IP4TWOTUPEN_F
),
2206 yesno(pfconf
->rss_pf_config
& UDPFOURTUPEN_F
),
2207 CH1DEFAULTQUEUE_G(pfconf
->rss_pf_config
),
2208 CH0DEFAULTQUEUE_G(pfconf
->rss_pf_config
));
2216 static int rss_pf_config_open(struct inode
*inode
, struct file
*file
)
2218 struct adapter
*adapter
= inode
->i_private
;
2220 u32 rss_pf_map
, rss_pf_mask
;
2221 struct rss_pf_conf
*pfconf
;
2224 p
= seq_open_tab(file
, 8, sizeof(*pfconf
), 1, rss_pf_config_show
);
2228 pfconf
= (struct rss_pf_conf
*)p
->data
;
2229 rss_pf_map
= t4_read_rss_pf_map(adapter
);
2230 rss_pf_mask
= t4_read_rss_pf_mask(adapter
);
2231 for (pf
= 0; pf
< 8; pf
++) {
2232 pfconf
[pf
].rss_pf_map
= rss_pf_map
;
2233 pfconf
[pf
].rss_pf_mask
= rss_pf_mask
;
2234 t4_read_rss_pf_config(adapter
, pf
, &pfconf
[pf
].rss_pf_config
);
2239 static const struct file_operations rss_pf_config_debugfs_fops
= {
2240 .owner
= THIS_MODULE
,
2241 .open
= rss_pf_config_open
,
2243 .llseek
= seq_lseek
,
2244 .release
= seq_release_private
2247 /* VF RSS Configuration.
2250 struct rss_vf_conf
{
2255 static int rss_vf_config_show(struct seq_file
*seq
, void *v
, int idx
)
2257 if (v
== SEQ_START_TOKEN
) {
2258 seq_puts(seq
, " RSS Hash Tuple Enable\n");
2259 seq_puts(seq
, " Enable IVF Dis Enb IPv6 IPv4 UDP Def Secret Key\n");
2260 seq_puts(seq
, " VF Chn Prt Map VLAN uP Four Two Four Two Four Que Idx Hash\n");
2262 struct rss_vf_conf
*vfconf
= v
;
2264 seq_printf(seq
, "%3d %3s %3s %3d %3s %3s %3s %3s %3s %3s %3s %4d %3d %#10x\n",
2266 yesno(vfconf
->rss_vf_vfh
& VFCHNEN_F
),
2267 yesno(vfconf
->rss_vf_vfh
& VFPRTEN_F
),
2268 VFLKPIDX_G(vfconf
->rss_vf_vfh
),
2269 yesno(vfconf
->rss_vf_vfh
& VFVLNEX_F
),
2270 yesno(vfconf
->rss_vf_vfh
& VFUPEN_F
),
2271 yesno(vfconf
->rss_vf_vfh
& VFIP4FOURTUPEN_F
),
2272 yesno(vfconf
->rss_vf_vfh
& VFIP6TWOTUPEN_F
),
2273 yesno(vfconf
->rss_vf_vfh
& VFIP4FOURTUPEN_F
),
2274 yesno(vfconf
->rss_vf_vfh
& VFIP4TWOTUPEN_F
),
2275 yesno(vfconf
->rss_vf_vfh
& ENABLEUDPHASH_F
),
2276 DEFAULTQUEUE_G(vfconf
->rss_vf_vfh
),
2277 KEYINDEX_G(vfconf
->rss_vf_vfh
),
2278 vfconf
->rss_vf_vfl
);
2283 static int rss_vf_config_open(struct inode
*inode
, struct file
*file
)
2285 struct adapter
*adapter
= inode
->i_private
;
2287 struct rss_vf_conf
*vfconf
;
2288 int vf
, vfcount
= adapter
->params
.arch
.vfcount
;
2290 p
= seq_open_tab(file
, vfcount
, sizeof(*vfconf
), 1, rss_vf_config_show
);
2294 vfconf
= (struct rss_vf_conf
*)p
->data
;
2295 for (vf
= 0; vf
< vfcount
; vf
++) {
2296 t4_read_rss_vf_config(adapter
, vf
, &vfconf
[vf
].rss_vf_vfl
,
2297 &vfconf
[vf
].rss_vf_vfh
);
2302 static const struct file_operations rss_vf_config_debugfs_fops
= {
2303 .owner
= THIS_MODULE
,
2304 .open
= rss_vf_config_open
,
2306 .llseek
= seq_lseek
,
2307 .release
= seq_release_private
2311 * ethqset2pinfo - return port_info of an Ethernet Queue Set
2312 * @adap: the adapter
2313 * @qset: Ethernet Queue Set
2315 static inline struct port_info
*ethqset2pinfo(struct adapter
*adap
, int qset
)
2319 for_each_port(adap
, pidx
) {
2320 struct port_info
*pi
= adap2pinfo(adap
, pidx
);
2322 if (qset
>= pi
->first_qset
&&
2323 qset
< pi
->first_qset
+ pi
->nqsets
)
2327 /* should never happen! */
2332 static int sge_qinfo_show(struct seq_file
*seq
, void *v
)
2334 struct adapter
*adap
= seq
->private;
2335 int eth_entries
= DIV_ROUND_UP(adap
->sge
.ethqsets
, 4);
2336 int iscsi_entries
= DIV_ROUND_UP(adap
->sge
.iscsiqsets
, 4);
2337 int rdma_entries
= DIV_ROUND_UP(adap
->sge
.rdmaqs
, 4);
2338 int ciq_entries
= DIV_ROUND_UP(adap
->sge
.rdmaciqs
, 4);
2339 int ctrl_entries
= DIV_ROUND_UP(MAX_CTRL_QUEUES
, 4);
2340 int i
, r
= (uintptr_t)v
- 1;
2341 int iscsi_idx
= r
- eth_entries
;
2342 int rdma_idx
= iscsi_idx
- iscsi_entries
;
2343 int ciq_idx
= rdma_idx
- rdma_entries
;
2344 int ctrl_idx
= ciq_idx
- ciq_entries
;
2345 int fq_idx
= ctrl_idx
- ctrl_entries
;
2348 seq_putc(seq
, '\n');
2350 #define S3(fmt_spec, s, v) \
2352 seq_printf(seq, "%-12s", s); \
2353 for (i = 0; i < n; ++i) \
2354 seq_printf(seq, " %16" fmt_spec, v); \
2355 seq_putc(seq, '\n'); \
2357 #define S(s, v) S3("s", s, v)
2358 #define T3(fmt_spec, s, v) S3(fmt_spec, s, tx[i].v)
2359 #define T(s, v) S3("u", s, tx[i].v)
2360 #define TL(s, v) T3("lu", s, v)
2361 #define R3(fmt_spec, s, v) S3(fmt_spec, s, rx[i].v)
2362 #define R(s, v) S3("u", s, rx[i].v)
2363 #define RL(s, v) R3("lu", s, v)
2365 if (r
< eth_entries
) {
2366 int base_qset
= r
* 4;
2367 const struct sge_eth_rxq
*rx
= &adap
->sge
.ethrxq
[base_qset
];
2368 const struct sge_eth_txq
*tx
= &adap
->sge
.ethtxq
[base_qset
];
2369 int n
= min(4, adap
->sge
.ethqsets
- 4 * r
);
2371 S("QType:", "Ethernet");
2373 rx
[i
].rspq
.netdev
? rx
[i
].rspq
.netdev
->name
: "N/A");
2374 T("TxQ ID:", q
.cntxt_id
);
2375 T("TxQ size:", q
.size
);
2376 T("TxQ inuse:", q
.in_use
);
2377 T("TxQ CIDX:", q
.cidx
);
2378 T("TxQ PIDX:", q
.pidx
);
2379 #ifdef CONFIG_CHELSIO_T4_DCB
2380 T("DCB Prio:", dcb_prio
);
2381 S3("u", "DCB PGID:",
2382 (ethqset2pinfo(adap
, base_qset
+ i
)->dcb
.pgid
>>
2383 4*(7-tx
[i
].dcb_prio
)) & 0xf);
2385 (ethqset2pinfo(adap
, base_qset
+ i
)->dcb
.pfcen
>>
2386 1*(7-tx
[i
].dcb_prio
)) & 0x1);
2388 R("RspQ ID:", rspq
.abs_id
);
2389 R("RspQ size:", rspq
.size
);
2390 R("RspQE size:", rspq
.iqe_len
);
2391 R("RspQ CIDX:", rspq
.cidx
);
2392 R("RspQ Gen:", rspq
.gen
);
2393 S3("u", "Intr delay:", qtimer_val(adap
, &rx
[i
].rspq
));
2394 S3("u", "Intr pktcnt:",
2395 adap
->sge
.counter_val
[rx
[i
].rspq
.pktcnt_idx
]);
2396 R("FL ID:", fl
.cntxt_id
);
2397 R("FL size:", fl
.size
- 8);
2398 R("FL pend:", fl
.pend_cred
);
2399 R("FL avail:", fl
.avail
);
2400 R("FL PIDX:", fl
.pidx
);
2401 R("FL CIDX:", fl
.cidx
);
2402 RL("RxPackets:", stats
.pkts
);
2403 RL("RxCSO:", stats
.rx_cso
);
2404 RL("VLANxtract:", stats
.vlan_ex
);
2405 RL("LROmerged:", stats
.lro_merged
);
2406 RL("LROpackets:", stats
.lro_pkts
);
2407 RL("RxDrops:", stats
.rx_drops
);
2409 TL("TxCSO:", tx_cso
);
2410 TL("VLANins:", vlan_ins
);
2411 TL("TxQFull:", q
.stops
);
2412 TL("TxQRestarts:", q
.restarts
);
2413 TL("TxMapErr:", mapping_err
);
2414 RL("FLAllocErr:", fl
.alloc_failed
);
2415 RL("FLLrgAlcErr:", fl
.large_alloc_failed
);
2416 RL("FLMapErr:", fl
.mapping_err
);
2417 RL("FLLow:", fl
.low
);
2418 RL("FLStarving:", fl
.starving
);
2420 } else if (iscsi_idx
< iscsi_entries
) {
2421 const struct sge_ofld_rxq
*rx
=
2422 &adap
->sge
.iscsirxq
[iscsi_idx
* 4];
2423 const struct sge_ofld_txq
*tx
=
2424 &adap
->sge
.ofldtxq
[iscsi_idx
* 4];
2425 int n
= min(4, adap
->sge
.iscsiqsets
- 4 * iscsi_idx
);
2427 S("QType:", "iSCSI");
2428 T("TxQ ID:", q
.cntxt_id
);
2429 T("TxQ size:", q
.size
);
2430 T("TxQ inuse:", q
.in_use
);
2431 T("TxQ CIDX:", q
.cidx
);
2432 T("TxQ PIDX:", q
.pidx
);
2433 R("RspQ ID:", rspq
.abs_id
);
2434 R("RspQ size:", rspq
.size
);
2435 R("RspQE size:", rspq
.iqe_len
);
2436 R("RspQ CIDX:", rspq
.cidx
);
2437 R("RspQ Gen:", rspq
.gen
);
2438 S3("u", "Intr delay:", qtimer_val(adap
, &rx
[i
].rspq
));
2439 S3("u", "Intr pktcnt:",
2440 adap
->sge
.counter_val
[rx
[i
].rspq
.pktcnt_idx
]);
2441 R("FL ID:", fl
.cntxt_id
);
2442 R("FL size:", fl
.size
- 8);
2443 R("FL pend:", fl
.pend_cred
);
2444 R("FL avail:", fl
.avail
);
2445 R("FL PIDX:", fl
.pidx
);
2446 R("FL CIDX:", fl
.cidx
);
2447 RL("RxPackets:", stats
.pkts
);
2448 RL("RxImmPkts:", stats
.imm
);
2449 RL("RxNoMem:", stats
.nomem
);
2450 RL("FLAllocErr:", fl
.alloc_failed
);
2451 RL("FLLrgAlcErr:", fl
.large_alloc_failed
);
2452 RL("FLMapErr:", fl
.mapping_err
);
2453 RL("FLLow:", fl
.low
);
2454 RL("FLStarving:", fl
.starving
);
2456 } else if (rdma_idx
< rdma_entries
) {
2457 const struct sge_ofld_rxq
*rx
=
2458 &adap
->sge
.rdmarxq
[rdma_idx
* 4];
2459 int n
= min(4, adap
->sge
.rdmaqs
- 4 * rdma_idx
);
2461 S("QType:", "RDMA-CPL");
2463 rx
[i
].rspq
.netdev
? rx
[i
].rspq
.netdev
->name
: "N/A");
2464 R("RspQ ID:", rspq
.abs_id
);
2465 R("RspQ size:", rspq
.size
);
2466 R("RspQE size:", rspq
.iqe_len
);
2467 R("RspQ CIDX:", rspq
.cidx
);
2468 R("RspQ Gen:", rspq
.gen
);
2469 S3("u", "Intr delay:", qtimer_val(adap
, &rx
[i
].rspq
));
2470 S3("u", "Intr pktcnt:",
2471 adap
->sge
.counter_val
[rx
[i
].rspq
.pktcnt_idx
]);
2472 R("FL ID:", fl
.cntxt_id
);
2473 R("FL size:", fl
.size
- 8);
2474 R("FL pend:", fl
.pend_cred
);
2475 R("FL avail:", fl
.avail
);
2476 R("FL PIDX:", fl
.pidx
);
2477 R("FL CIDX:", fl
.cidx
);
2478 RL("RxPackets:", stats
.pkts
);
2479 RL("RxImmPkts:", stats
.imm
);
2480 RL("RxNoMem:", stats
.nomem
);
2481 RL("FLAllocErr:", fl
.alloc_failed
);
2482 RL("FLLrgAlcErr:", fl
.large_alloc_failed
);
2483 RL("FLMapErr:", fl
.mapping_err
);
2484 RL("FLLow:", fl
.low
);
2485 RL("FLStarving:", fl
.starving
);
2487 } else if (ciq_idx
< ciq_entries
) {
2488 const struct sge_ofld_rxq
*rx
= &adap
->sge
.rdmaciq
[ciq_idx
* 4];
2489 int n
= min(4, adap
->sge
.rdmaciqs
- 4 * ciq_idx
);
2491 S("QType:", "RDMA-CIQ");
2493 rx
[i
].rspq
.netdev
? rx
[i
].rspq
.netdev
->name
: "N/A");
2494 R("RspQ ID:", rspq
.abs_id
);
2495 R("RspQ size:", rspq
.size
);
2496 R("RspQE size:", rspq
.iqe_len
);
2497 R("RspQ CIDX:", rspq
.cidx
);
2498 R("RspQ Gen:", rspq
.gen
);
2499 S3("u", "Intr delay:", qtimer_val(adap
, &rx
[i
].rspq
));
2500 S3("u", "Intr pktcnt:",
2501 adap
->sge
.counter_val
[rx
[i
].rspq
.pktcnt_idx
]);
2502 RL("RxAN:", stats
.an
);
2503 RL("RxNoMem:", stats
.nomem
);
2505 } else if (ctrl_idx
< ctrl_entries
) {
2506 const struct sge_ctrl_txq
*tx
= &adap
->sge
.ctrlq
[ctrl_idx
* 4];
2507 int n
= min(4, adap
->params
.nports
- 4 * ctrl_idx
);
2509 S("QType:", "Control");
2510 T("TxQ ID:", q
.cntxt_id
);
2511 T("TxQ size:", q
.size
);
2512 T("TxQ inuse:", q
.in_use
);
2513 T("TxQ CIDX:", q
.cidx
);
2514 T("TxQ PIDX:", q
.pidx
);
2515 TL("TxQFull:", q
.stops
);
2516 TL("TxQRestarts:", q
.restarts
);
2517 } else if (fq_idx
== 0) {
2518 const struct sge_rspq
*evtq
= &adap
->sge
.fw_evtq
;
2520 seq_printf(seq
, "%-12s %16s\n", "QType:", "FW event queue");
2521 seq_printf(seq
, "%-12s %16u\n", "RspQ ID:", evtq
->abs_id
);
2522 seq_printf(seq
, "%-12s %16u\n", "RspQ size:", evtq
->size
);
2523 seq_printf(seq
, "%-12s %16u\n", "RspQE size:", evtq
->iqe_len
);
2524 seq_printf(seq
, "%-12s %16u\n", "RspQ CIDX:", evtq
->cidx
);
2525 seq_printf(seq
, "%-12s %16u\n", "RspQ Gen:", evtq
->gen
);
2526 seq_printf(seq
, "%-12s %16u\n", "Intr delay:",
2527 qtimer_val(adap
, evtq
));
2528 seq_printf(seq
, "%-12s %16u\n", "Intr pktcnt:",
2529 adap
->sge
.counter_val
[evtq
->pktcnt_idx
]);
2542 static int sge_queue_entries(const struct adapter
*adap
)
2544 return DIV_ROUND_UP(adap
->sge
.ethqsets
, 4) +
2545 DIV_ROUND_UP(adap
->sge
.iscsiqsets
, 4) +
2546 DIV_ROUND_UP(adap
->sge
.rdmaqs
, 4) +
2547 DIV_ROUND_UP(adap
->sge
.rdmaciqs
, 4) +
2548 DIV_ROUND_UP(MAX_CTRL_QUEUES
, 4) + 1;
2551 static void *sge_queue_start(struct seq_file
*seq
, loff_t
*pos
)
2553 int entries
= sge_queue_entries(seq
->private);
2555 return *pos
< entries
? (void *)((uintptr_t)*pos
+ 1) : NULL
;
2558 static void sge_queue_stop(struct seq_file
*seq
, void *v
)
2562 static void *sge_queue_next(struct seq_file
*seq
, void *v
, loff_t
*pos
)
2564 int entries
= sge_queue_entries(seq
->private);
2567 return *pos
< entries
? (void *)((uintptr_t)*pos
+ 1) : NULL
;
2570 static const struct seq_operations sge_qinfo_seq_ops
= {
2571 .start
= sge_queue_start
,
2572 .next
= sge_queue_next
,
2573 .stop
= sge_queue_stop
,
2574 .show
= sge_qinfo_show
2577 static int sge_qinfo_open(struct inode
*inode
, struct file
*file
)
2579 int res
= seq_open(file
, &sge_qinfo_seq_ops
);
2582 struct seq_file
*seq
= file
->private_data
;
2584 seq
->private = inode
->i_private
;
2589 static const struct file_operations sge_qinfo_debugfs_fops
= {
2590 .owner
= THIS_MODULE
,
2591 .open
= sge_qinfo_open
,
2593 .llseek
= seq_lseek
,
2594 .release
= seq_release
,
2597 int mem_open(struct inode
*inode
, struct file
*file
)
2600 struct adapter
*adap
;
2602 file
->private_data
= inode
->i_private
;
2604 mem
= (uintptr_t)file
->private_data
& 0x3;
2605 adap
= file
->private_data
- mem
;
2607 (void)t4_fwcache(adap
, FW_PARAM_DEV_FWCACHE_FLUSH
);
2612 static ssize_t
mem_read(struct file
*file
, char __user
*buf
, size_t count
,
2616 loff_t avail
= file_inode(file
)->i_size
;
2617 unsigned int mem
= (uintptr_t)file
->private_data
& 3;
2618 struct adapter
*adap
= file
->private_data
- mem
;
2626 if (count
> avail
- pos
)
2627 count
= avail
- pos
;
2629 data
= t4_alloc_mem(count
);
2633 spin_lock(&adap
->win0_lock
);
2634 ret
= t4_memory_rw(adap
, 0, mem
, pos
, count
, data
, T4_MEMORY_READ
);
2635 spin_unlock(&adap
->win0_lock
);
2640 ret
= copy_to_user(buf
, data
, count
);
2646 *ppos
= pos
+ count
;
2649 static const struct file_operations mem_debugfs_fops
= {
2650 .owner
= THIS_MODULE
,
2651 .open
= simple_open
,
2653 .llseek
= default_llseek
,
2656 static int tid_info_show(struct seq_file
*seq
, void *v
)
2658 struct adapter
*adap
= seq
->private;
2659 const struct tid_info
*t
= &adap
->tids
;
2660 enum chip_type chip
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
2662 if (t4_read_reg(adap
, LE_DB_CONFIG_A
) & HASHEN_F
) {
2665 if (chip
<= CHELSIO_T5
)
2666 sb
= t4_read_reg(adap
, LE_DB_SERVER_INDEX_A
) / 4;
2668 sb
= t4_read_reg(adap
, LE_DB_SRVR_START_INDEX_A
);
2671 seq_printf(seq
, "TID range: 0..%u/%u..%u", sb
- 1,
2672 adap
->tids
.hash_base
,
2674 seq_printf(seq
, ", in use: %u/%u\n",
2675 atomic_read(&t
->tids_in_use
),
2676 atomic_read(&t
->hash_tids_in_use
));
2677 } else if (adap
->flags
& FW_OFLD_CONN
) {
2678 seq_printf(seq
, "TID range: %u..%u/%u..%u",
2681 adap
->tids
.hash_base
,
2683 seq_printf(seq
, ", in use: %u/%u\n",
2684 atomic_read(&t
->tids_in_use
),
2685 atomic_read(&t
->hash_tids_in_use
));
2687 seq_printf(seq
, "TID range: %u..%u",
2688 adap
->tids
.hash_base
,
2690 seq_printf(seq
, ", in use: %u\n",
2691 atomic_read(&t
->hash_tids_in_use
));
2693 } else if (t
->ntids
) {
2694 seq_printf(seq
, "TID range: 0..%u", t
->ntids
- 1);
2695 seq_printf(seq
, ", in use: %u\n",
2696 atomic_read(&t
->tids_in_use
));
2700 seq_printf(seq
, "STID range: %u..%u, in use: %u\n",
2702 (chip
<= CHELSIO_T5
)) ?
2703 t
->stid_base
+ 1 : t
->stid_base
,
2704 t
->stid_base
+ t
->nstids
- 1, t
->stids_in_use
);
2706 seq_printf(seq
, "ATID range: 0..%u, in use: %u\n",
2707 t
->natids
- 1, t
->atids_in_use
);
2708 seq_printf(seq
, "FTID range: %u..%u\n", t
->ftid_base
,
2709 t
->ftid_base
+ t
->nftids
- 1);
2711 seq_printf(seq
, "SFTID range: %u..%u in use: %u\n",
2712 t
->sftid_base
, t
->sftid_base
+ t
->nsftids
- 2,
2715 seq_printf(seq
, "HW TID usage: %u IP users, %u IPv6 users\n",
2716 t4_read_reg(adap
, LE_DB_ACT_CNT_IPV4_A
),
2717 t4_read_reg(adap
, LE_DB_ACT_CNT_IPV6_A
));
2721 DEFINE_SIMPLE_DEBUGFS_FILE(tid_info
);
2723 static void add_debugfs_mem(struct adapter
*adap
, const char *name
,
2724 unsigned int idx
, unsigned int size_mb
)
2726 debugfs_create_file_size(name
, S_IRUSR
, adap
->debugfs_root
,
2727 (void *)adap
+ idx
, &mem_debugfs_fops
,
2731 static int blocked_fl_open(struct inode
*inode
, struct file
*file
)
2733 file
->private_data
= inode
->i_private
;
2737 static ssize_t
blocked_fl_read(struct file
*filp
, char __user
*ubuf
,
2738 size_t count
, loff_t
*ppos
)
2741 const struct adapter
*adap
= filp
->private_data
;
2743 ssize_t size
= (adap
->sge
.egr_sz
+ 3) / 4 +
2744 adap
->sge
.egr_sz
/ 32 + 2; /* includes ,/\n/\0 */
2746 buf
= kzalloc(size
, GFP_KERNEL
);
2750 len
= snprintf(buf
, size
- 1, "%*pb\n",
2751 adap
->sge
.egr_sz
, adap
->sge
.blocked_fl
);
2752 len
+= sprintf(buf
+ len
, "\n");
2753 size
= simple_read_from_buffer(ubuf
, count
, ppos
, buf
, len
);
2758 static ssize_t
blocked_fl_write(struct file
*filp
, const char __user
*ubuf
,
2759 size_t count
, loff_t
*ppos
)
2763 struct adapter
*adap
= filp
->private_data
;
2765 t
= kcalloc(BITS_TO_LONGS(adap
->sge
.egr_sz
), sizeof(long), GFP_KERNEL
);
2769 err
= bitmap_parse_user(ubuf
, count
, t
, adap
->sge
.egr_sz
);
2773 bitmap_copy(adap
->sge
.blocked_fl
, t
, adap
->sge
.egr_sz
);
2778 static const struct file_operations blocked_fl_fops
= {
2779 .owner
= THIS_MODULE
,
2780 .open
= blocked_fl_open
,
2781 .read
= blocked_fl_read
,
2782 .write
= blocked_fl_write
,
2783 .llseek
= generic_file_llseek
,
2792 static int mem_desc_cmp(const void *a
, const void *b
)
2794 return ((const struct mem_desc
*)a
)->base
-
2795 ((const struct mem_desc
*)b
)->base
;
2798 static void mem_region_show(struct seq_file
*seq
, const char *name
,
2799 unsigned int from
, unsigned int to
)
2803 string_get_size((u64
)to
- from
+ 1, 1, STRING_UNITS_2
, buf
,
2805 seq_printf(seq
, "%-15s %#x-%#x [%s]\n", name
, from
, to
, buf
);
2808 static int meminfo_show(struct seq_file
*seq
, void *v
)
2810 static const char * const memory
[] = { "EDC0:", "EDC1:", "MC:",
2812 static const char * const region
[] = {
2813 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
2814 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
2815 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
2816 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
2817 "RQUDP region:", "PBL region:", "TXPBL region:",
2818 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
2823 u32 lo
, hi
, used
, alloc
;
2824 struct mem_desc avail
[4];
2825 struct mem_desc mem
[ARRAY_SIZE(region
) + 3]; /* up to 3 holes */
2826 struct mem_desc
*md
= mem
;
2827 struct adapter
*adap
= seq
->private;
2829 for (i
= 0; i
< ARRAY_SIZE(mem
); i
++) {
2834 /* Find and sort the populated memory ranges */
2836 lo
= t4_read_reg(adap
, MA_TARGET_MEM_ENABLE_A
);
2837 if (lo
& EDRAM0_ENABLE_F
) {
2838 hi
= t4_read_reg(adap
, MA_EDRAM0_BAR_A
);
2839 avail
[i
].base
= EDRAM0_BASE_G(hi
) << 20;
2840 avail
[i
].limit
= avail
[i
].base
+ (EDRAM0_SIZE_G(hi
) << 20);
2844 if (lo
& EDRAM1_ENABLE_F
) {
2845 hi
= t4_read_reg(adap
, MA_EDRAM1_BAR_A
);
2846 avail
[i
].base
= EDRAM1_BASE_G(hi
) << 20;
2847 avail
[i
].limit
= avail
[i
].base
+ (EDRAM1_SIZE_G(hi
) << 20);
2852 if (is_t5(adap
->params
.chip
)) {
2853 if (lo
& EXT_MEM0_ENABLE_F
) {
2854 hi
= t4_read_reg(adap
, MA_EXT_MEMORY0_BAR_A
);
2855 avail
[i
].base
= EXT_MEM0_BASE_G(hi
) << 20;
2857 avail
[i
].base
+ (EXT_MEM0_SIZE_G(hi
) << 20);
2861 if (lo
& EXT_MEM1_ENABLE_F
) {
2862 hi
= t4_read_reg(adap
, MA_EXT_MEMORY1_BAR_A
);
2863 avail
[i
].base
= EXT_MEM1_BASE_G(hi
) << 20;
2865 avail
[i
].base
+ (EXT_MEM1_SIZE_G(hi
) << 20);
2870 if (lo
& EXT_MEM_ENABLE_F
) {
2871 hi
= t4_read_reg(adap
, MA_EXT_MEMORY_BAR_A
);
2872 avail
[i
].base
= EXT_MEM_BASE_G(hi
) << 20;
2874 avail
[i
].base
+ (EXT_MEM_SIZE_G(hi
) << 20);
2879 if (!i
) /* no memory available */
2881 sort(avail
, i
, sizeof(struct mem_desc
), mem_desc_cmp
, NULL
);
2883 (md
++)->base
= t4_read_reg(adap
, SGE_DBQ_CTXT_BADDR_A
);
2884 (md
++)->base
= t4_read_reg(adap
, SGE_IMSG_CTXT_BADDR_A
);
2885 (md
++)->base
= t4_read_reg(adap
, SGE_FLM_CACHE_BADDR_A
);
2886 (md
++)->base
= t4_read_reg(adap
, TP_CMM_TCB_BASE_A
);
2887 (md
++)->base
= t4_read_reg(adap
, TP_CMM_MM_BASE_A
);
2888 (md
++)->base
= t4_read_reg(adap
, TP_CMM_TIMER_BASE_A
);
2889 (md
++)->base
= t4_read_reg(adap
, TP_CMM_MM_RX_FLST_BASE_A
);
2890 (md
++)->base
= t4_read_reg(adap
, TP_CMM_MM_TX_FLST_BASE_A
);
2891 (md
++)->base
= t4_read_reg(adap
, TP_CMM_MM_PS_FLST_BASE_A
);
2893 /* the next few have explicit upper bounds */
2894 md
->base
= t4_read_reg(adap
, TP_PMM_TX_BASE_A
);
2895 md
->limit
= md
->base
- 1 +
2896 t4_read_reg(adap
, TP_PMM_TX_PAGE_SIZE_A
) *
2897 PMTXMAXPAGE_G(t4_read_reg(adap
, TP_PMM_TX_MAX_PAGE_A
));
2900 md
->base
= t4_read_reg(adap
, TP_PMM_RX_BASE_A
);
2901 md
->limit
= md
->base
- 1 +
2902 t4_read_reg(adap
, TP_PMM_RX_PAGE_SIZE_A
) *
2903 PMRXMAXPAGE_G(t4_read_reg(adap
, TP_PMM_RX_MAX_PAGE_A
));
2906 if (t4_read_reg(adap
, LE_DB_CONFIG_A
) & HASHEN_F
) {
2907 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) <= CHELSIO_T5
) {
2908 hi
= t4_read_reg(adap
, LE_DB_TID_HASHBASE_A
) / 4;
2909 md
->base
= t4_read_reg(adap
, LE_DB_HASH_TID_BASE_A
);
2911 hi
= t4_read_reg(adap
, LE_DB_HASH_TID_BASE_A
);
2912 md
->base
= t4_read_reg(adap
,
2913 LE_DB_HASH_TBL_BASE_ADDR_A
);
2918 md
->idx
= ARRAY_SIZE(region
); /* hide it */
2922 #define ulp_region(reg) do { \
2923 md->base = t4_read_reg(adap, ULP_ ## reg ## _LLIMIT_A);\
2924 (md++)->limit = t4_read_reg(adap, ULP_ ## reg ## _ULIMIT_A); \
2927 ulp_region(RX_ISCSI
);
2928 ulp_region(RX_TDDP
);
2930 ulp_region(RX_STAG
);
2932 ulp_region(RX_RQUDP
);
2937 md
->idx
= ARRAY_SIZE(region
);
2938 if (!is_t4(adap
->params
.chip
)) {
2940 u32 sge_ctrl
= t4_read_reg(adap
, SGE_CONTROL2_A
);
2941 u32 fifo_size
= t4_read_reg(adap
, SGE_DBVFIFO_SIZE_A
);
2943 if (is_t5(adap
->params
.chip
)) {
2944 if (sge_ctrl
& VFIFO_ENABLE_F
)
2945 size
= DBVFIFO_SIZE_G(fifo_size
);
2947 size
= T6_DBVFIFO_SIZE_G(fifo_size
);
2951 md
->base
= BASEADDR_G(t4_read_reg(adap
,
2952 SGE_DBVFIFO_BADDR_A
));
2953 md
->limit
= md
->base
+ (size
<< 2) - 1;
2959 md
->base
= t4_read_reg(adap
, ULP_RX_CTX_BASE_A
);
2962 md
->base
= t4_read_reg(adap
, ULP_TX_ERR_TABLE_BASE_A
);
2966 md
->base
= adap
->vres
.ocq
.start
;
2967 if (adap
->vres
.ocq
.size
)
2968 md
->limit
= md
->base
+ adap
->vres
.ocq
.size
- 1;
2970 md
->idx
= ARRAY_SIZE(region
); /* hide it */
2973 /* add any address-space holes, there can be up to 3 */
2974 for (n
= 0; n
< i
- 1; n
++)
2975 if (avail
[n
].limit
< avail
[n
+ 1].base
)
2976 (md
++)->base
= avail
[n
].limit
;
2978 (md
++)->base
= avail
[n
].limit
;
2981 sort(mem
, n
, sizeof(struct mem_desc
), mem_desc_cmp
, NULL
);
2983 for (lo
= 0; lo
< i
; lo
++)
2984 mem_region_show(seq
, memory
[avail
[lo
].idx
], avail
[lo
].base
,
2985 avail
[lo
].limit
- 1);
2987 seq_putc(seq
, '\n');
2988 for (i
= 0; i
< n
; i
++) {
2989 if (mem
[i
].idx
>= ARRAY_SIZE(region
))
2990 continue; /* skip holes */
2992 mem
[i
].limit
= i
< n
- 1 ? mem
[i
+ 1].base
- 1 : ~0;
2993 mem_region_show(seq
, region
[mem
[i
].idx
], mem
[i
].base
,
2997 seq_putc(seq
, '\n');
2998 lo
= t4_read_reg(adap
, CIM_SDRAM_BASE_ADDR_A
);
2999 hi
= t4_read_reg(adap
, CIM_SDRAM_ADDR_SIZE_A
) + lo
- 1;
3000 mem_region_show(seq
, "uP RAM:", lo
, hi
);
3002 lo
= t4_read_reg(adap
, CIM_EXTMEM2_BASE_ADDR_A
);
3003 hi
= t4_read_reg(adap
, CIM_EXTMEM2_ADDR_SIZE_A
) + lo
- 1;
3004 mem_region_show(seq
, "uP Extmem2:", lo
, hi
);
3006 lo
= t4_read_reg(adap
, TP_PMM_RX_MAX_PAGE_A
);
3007 seq_printf(seq
, "\n%u Rx pages of size %uKiB for %u channels\n",
3009 t4_read_reg(adap
, TP_PMM_RX_PAGE_SIZE_A
) >> 10,
3010 (lo
& PMRXNUMCHN_F
) ? 2 : 1);
3012 lo
= t4_read_reg(adap
, TP_PMM_TX_MAX_PAGE_A
);
3013 hi
= t4_read_reg(adap
, TP_PMM_TX_PAGE_SIZE_A
);
3014 seq_printf(seq
, "%u Tx pages of size %u%ciB for %u channels\n",
3016 hi
>= (1 << 20) ? (hi
>> 20) : (hi
>> 10),
3017 hi
>= (1 << 20) ? 'M' : 'K', 1 << PMTXNUMCHN_G(lo
));
3018 seq_printf(seq
, "%u p-structs\n\n",
3019 t4_read_reg(adap
, TP_CMM_MM_MAX_PSTRUCT_A
));
3021 for (i
= 0; i
< 4; i
++) {
3022 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) > CHELSIO_T5
)
3023 lo
= t4_read_reg(adap
, MPS_RX_MAC_BG_PG_CNT0_A
+ i
* 4);
3025 lo
= t4_read_reg(adap
, MPS_RX_PG_RSV0_A
+ i
* 4);
3026 if (is_t5(adap
->params
.chip
)) {
3027 used
= T5_USED_G(lo
);
3028 alloc
= T5_ALLOC_G(lo
);
3031 alloc
= ALLOC_G(lo
);
3033 /* For T6 these are MAC buffer groups */
3034 seq_printf(seq
, "Port %d using %u pages out of %u allocated\n",
3037 for (i
= 0; i
< adap
->params
.arch
.nchan
; i
++) {
3038 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) > CHELSIO_T5
)
3039 lo
= t4_read_reg(adap
,
3040 MPS_RX_LPBK_BG_PG_CNT0_A
+ i
* 4);
3042 lo
= t4_read_reg(adap
, MPS_RX_PG_RSV4_A
+ i
* 4);
3043 if (is_t5(adap
->params
.chip
)) {
3044 used
= T5_USED_G(lo
);
3045 alloc
= T5_ALLOC_G(lo
);
3048 alloc
= ALLOC_G(lo
);
3050 /* For T6 these are MAC buffer groups */
3052 "Loopback %d using %u pages out of %u allocated\n",
3058 static int meminfo_open(struct inode
*inode
, struct file
*file
)
3060 return single_open(file
, meminfo_show
, inode
->i_private
);
3063 static const struct file_operations meminfo_fops
= {
3064 .owner
= THIS_MODULE
,
3065 .open
= meminfo_open
,
3067 .llseek
= seq_lseek
,
3068 .release
= single_release
,
3070 /* Add an array of Debug FS files.
3072 void add_debugfs_files(struct adapter
*adap
,
3073 struct t4_debugfs_entry
*files
,
3074 unsigned int nfiles
)
3078 /* debugfs support is best effort */
3079 for (i
= 0; i
< nfiles
; i
++)
3080 debugfs_create_file(files
[i
].name
, files
[i
].mode
,
3082 (void *)adap
+ files
[i
].data
,
3086 int t4_setup_debugfs(struct adapter
*adap
)
3092 static struct t4_debugfs_entry t4_debugfs_files
[] = {
3093 { "cim_la", &cim_la_fops
, S_IRUSR
, 0 },
3094 { "cim_pif_la", &cim_pif_la_fops
, S_IRUSR
, 0 },
3095 { "cim_ma_la", &cim_ma_la_fops
, S_IRUSR
, 0 },
3096 { "cim_qcfg", &cim_qcfg_fops
, S_IRUSR
, 0 },
3097 { "clk", &clk_debugfs_fops
, S_IRUSR
, 0 },
3098 { "devlog", &devlog_fops
, S_IRUSR
, 0 },
3099 { "mbox0", &mbox_debugfs_fops
, S_IRUSR
| S_IWUSR
, 0 },
3100 { "mbox1", &mbox_debugfs_fops
, S_IRUSR
| S_IWUSR
, 1 },
3101 { "mbox2", &mbox_debugfs_fops
, S_IRUSR
| S_IWUSR
, 2 },
3102 { "mbox3", &mbox_debugfs_fops
, S_IRUSR
| S_IWUSR
, 3 },
3103 { "mbox4", &mbox_debugfs_fops
, S_IRUSR
| S_IWUSR
, 4 },
3104 { "mbox5", &mbox_debugfs_fops
, S_IRUSR
| S_IWUSR
, 5 },
3105 { "mbox6", &mbox_debugfs_fops
, S_IRUSR
| S_IWUSR
, 6 },
3106 { "mbox7", &mbox_debugfs_fops
, S_IRUSR
| S_IWUSR
, 7 },
3107 { "trace0", &mps_trc_debugfs_fops
, S_IRUSR
| S_IWUSR
, 0 },
3108 { "trace1", &mps_trc_debugfs_fops
, S_IRUSR
| S_IWUSR
, 1 },
3109 { "trace2", &mps_trc_debugfs_fops
, S_IRUSR
| S_IWUSR
, 2 },
3110 { "trace3", &mps_trc_debugfs_fops
, S_IRUSR
| S_IWUSR
, 3 },
3111 { "l2t", &t4_l2t_fops
, S_IRUSR
, 0},
3112 { "mps_tcam", &mps_tcam_debugfs_fops
, S_IRUSR
, 0 },
3113 { "rss", &rss_debugfs_fops
, S_IRUSR
, 0 },
3114 { "rss_config", &rss_config_debugfs_fops
, S_IRUSR
, 0 },
3115 { "rss_key", &rss_key_debugfs_fops
, S_IRUSR
, 0 },
3116 { "rss_pf_config", &rss_pf_config_debugfs_fops
, S_IRUSR
, 0 },
3117 { "rss_vf_config", &rss_vf_config_debugfs_fops
, S_IRUSR
, 0 },
3118 { "sge_qinfo", &sge_qinfo_debugfs_fops
, S_IRUSR
, 0 },
3119 { "ibq_tp0", &cim_ibq_fops
, S_IRUSR
, 0 },
3120 { "ibq_tp1", &cim_ibq_fops
, S_IRUSR
, 1 },
3121 { "ibq_ulp", &cim_ibq_fops
, S_IRUSR
, 2 },
3122 { "ibq_sge0", &cim_ibq_fops
, S_IRUSR
, 3 },
3123 { "ibq_sge1", &cim_ibq_fops
, S_IRUSR
, 4 },
3124 { "ibq_ncsi", &cim_ibq_fops
, S_IRUSR
, 5 },
3125 { "obq_ulp0", &cim_obq_fops
, S_IRUSR
, 0 },
3126 { "obq_ulp1", &cim_obq_fops
, S_IRUSR
, 1 },
3127 { "obq_ulp2", &cim_obq_fops
, S_IRUSR
, 2 },
3128 { "obq_ulp3", &cim_obq_fops
, S_IRUSR
, 3 },
3129 { "obq_sge", &cim_obq_fops
, S_IRUSR
, 4 },
3130 { "obq_ncsi", &cim_obq_fops
, S_IRUSR
, 5 },
3131 { "tp_la", &tp_la_fops
, S_IRUSR
, 0 },
3132 { "ulprx_la", &ulprx_la_fops
, S_IRUSR
, 0 },
3133 { "sensors", &sensors_debugfs_fops
, S_IRUSR
, 0 },
3134 { "pm_stats", &pm_stats_debugfs_fops
, S_IRUSR
, 0 },
3135 { "tx_rate", &tx_rate_debugfs_fops
, S_IRUSR
, 0 },
3136 { "cctrl", &cctrl_tbl_debugfs_fops
, S_IRUSR
, 0 },
3137 #if IS_ENABLED(CONFIG_IPV6)
3138 { "clip_tbl", &clip_tbl_debugfs_fops
, S_IRUSR
, 0 },
3140 { "tids", &tid_info_debugfs_fops
, S_IRUSR
, 0},
3141 { "blocked_fl", &blocked_fl_fops
, S_IRUSR
| S_IWUSR
, 0 },
3142 { "meminfo", &meminfo_fops
, S_IRUSR
, 0 },
3145 /* Debug FS nodes common to all T5 and later adapters.
3147 static struct t4_debugfs_entry t5_debugfs_files
[] = {
3148 { "obq_sge_rx_q0", &cim_obq_fops
, S_IRUSR
, 6 },
3149 { "obq_sge_rx_q1", &cim_obq_fops
, S_IRUSR
, 7 },
3152 add_debugfs_files(adap
,
3154 ARRAY_SIZE(t4_debugfs_files
));
3155 if (!is_t4(adap
->params
.chip
))
3156 add_debugfs_files(adap
,
3158 ARRAY_SIZE(t5_debugfs_files
));
3160 i
= t4_read_reg(adap
, MA_TARGET_MEM_ENABLE_A
);
3161 if (i
& EDRAM0_ENABLE_F
) {
3162 size
= t4_read_reg(adap
, MA_EDRAM0_BAR_A
);
3163 add_debugfs_mem(adap
, "edc0", MEM_EDC0
, EDRAM0_SIZE_G(size
));
3165 if (i
& EDRAM1_ENABLE_F
) {
3166 size
= t4_read_reg(adap
, MA_EDRAM1_BAR_A
);
3167 add_debugfs_mem(adap
, "edc1", MEM_EDC1
, EDRAM1_SIZE_G(size
));
3169 if (is_t5(adap
->params
.chip
)) {
3170 if (i
& EXT_MEM0_ENABLE_F
) {
3171 size
= t4_read_reg(adap
, MA_EXT_MEMORY0_BAR_A
);
3172 add_debugfs_mem(adap
, "mc0", MEM_MC0
,
3173 EXT_MEM0_SIZE_G(size
));
3175 if (i
& EXT_MEM1_ENABLE_F
) {
3176 size
= t4_read_reg(adap
, MA_EXT_MEMORY1_BAR_A
);
3177 add_debugfs_mem(adap
, "mc1", MEM_MC1
,
3178 EXT_MEM1_SIZE_G(size
));
3181 if (i
& EXT_MEM_ENABLE_F
) {
3182 size
= t4_read_reg(adap
, MA_EXT_MEMORY_BAR_A
);
3183 add_debugfs_mem(adap
, "mc", MEM_MC
,
3184 EXT_MEM_SIZE_G(size
));
3188 de
= debugfs_create_file_size("flash", S_IRUSR
, adap
->debugfs_root
, adap
,
3189 &flash_debugfs_fops
, adap
->params
.sf_size
);
3190 debugfs_create_bool("use_backdoor", S_IWUSR
| S_IRUSR
,
3191 adap
->debugfs_root
, &adap
->use_bd
);
3192 debugfs_create_bool("trace_rss", S_IWUSR
| S_IRUSR
,
3193 adap
->debugfs_root
, &adap
->trace_rss
);