1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 #define DRV_NAME "uli526x"
10 #define DRV_VERSION "0.9.3"
11 #define DRV_RELDATE "2005-7-29"
13 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/string.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/skbuff.h>
27 #include <linux/delay.h>
28 #include <linux/spinlock.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/bitops.h>
32 #include <asm/processor.h>
35 #include <linux/uaccess.h>
37 #define uw32(reg, val) iowrite32(val, ioaddr + (reg))
38 #define ur32(reg) ioread32(ioaddr + (reg))
40 /* Board/System/Debug information/definition ---------------- */
41 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
42 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
44 #define ULI526X_IO_SIZE 0x100
45 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
46 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
47 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
48 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
49 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
50 #define TX_BUF_ALLOC 0x600
51 #define RX_ALLOC_SIZE 0x620
52 #define ULI526X_RESET 1
54 #define CR6_DEFAULT 0x22200000
55 #define CR7_DEFAULT 0x180c1
56 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
57 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
58 #define MAX_PACKET_SIZE 1514
59 #define ULI5261_MAX_MULTICAST 14
60 #define RX_COPY_SIZE 100
61 #define MAX_CHECK_PACKET 0x8000
63 #define ULI526X_10MHF 0
64 #define ULI526X_100MHF 1
65 #define ULI526X_10MFD 4
66 #define ULI526X_100MFD 5
67 #define ULI526X_AUTO 8
69 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
70 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
71 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
72 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
73 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
74 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
76 #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
77 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
78 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
80 #define ULI526X_DBUG(dbug_now, msg, value) \
82 if (uli526x_debug || (dbug_now)) \
83 pr_err("%s %lx\n", (msg), (long) (value)); \
86 #define SHOW_MEDIA_TYPE(mode) \
87 pr_err("Change Speed to %sMhz %s duplex\n", \
88 mode & 1 ? "100" : "10", \
89 mode & 4 ? "full" : "half");
92 /* CR9 definition: SROM/MII */
93 #define CR9_SROM_READ 0x4800
96 #define CR9_CRDOUT 0x8
97 #define SROM_DATA_0 0x0
98 #define SROM_DATA_1 0x4
99 #define PHY_DATA_1 0x20000
100 #define PHY_DATA_0 0x00000
101 #define MDCLKH 0x10000
103 #define PHY_POWER_DOWN 0x800
105 #define SROM_V41_CODE 0x14
107 /* Structure/enum declaration ------------------------------- */
109 __le32 tdes0
, tdes1
, tdes2
, tdes3
; /* Data for the card */
110 char *tx_buf_ptr
; /* Data for us */
111 struct tx_desc
*next_tx_desc
;
112 } __attribute__(( aligned(32) ));
115 __le32 rdes0
, rdes1
, rdes2
, rdes3
; /* Data for the card */
116 struct sk_buff
*rx_skb_ptr
; /* Data for us */
117 struct rx_desc
*next_rx_desc
;
118 } __attribute__(( aligned(32) ));
120 struct uli526x_board_info
{
122 void (*write
)(struct uli526x_board_info
*, u8
, u8
, u16
);
123 u16 (*read
)(struct uli526x_board_info
*, u8
, u8
);
125 struct net_device
*next_dev
; /* next device */
126 struct pci_dev
*pdev
; /* PCI device */
129 void __iomem
*ioaddr
; /* I/O base address */
136 /* pointer for memory physical address */
137 dma_addr_t buf_pool_dma_ptr
; /* Tx buffer pool memory */
138 dma_addr_t buf_pool_dma_start
; /* Tx buffer pool align dword */
139 dma_addr_t desc_pool_dma_ptr
; /* descriptor pool memory */
140 dma_addr_t first_tx_desc_dma
;
141 dma_addr_t first_rx_desc_dma
;
143 /* descriptor pointer */
144 unsigned char *buf_pool_ptr
; /* Tx buffer pool memory */
145 unsigned char *buf_pool_start
; /* Tx buffer pool align dword */
146 unsigned char *desc_pool_ptr
; /* descriptor pool memory */
147 struct tx_desc
*first_tx_desc
;
148 struct tx_desc
*tx_insert_ptr
;
149 struct tx_desc
*tx_remove_ptr
;
150 struct rx_desc
*first_rx_desc
;
151 struct rx_desc
*rx_insert_ptr
;
152 struct rx_desc
*rx_ready_ptr
; /* packet come pointer */
153 unsigned long tx_packet_cnt
; /* transmitted packet count */
154 unsigned long rx_avail_cnt
; /* available rx descriptor count */
155 unsigned long interval_rx_cnt
; /* rx packet count a callback time */
158 u16 NIC_capability
; /* NIC media capability */
159 u16 PHY_reg4
; /* Saved Phyxcer register 4 value */
161 u8 media_mode
; /* user specify media mode */
162 u8 op_mode
; /* real work media mode */
164 u8 link_failed
; /* Ever link failed */
165 u8 wait_reset
; /* Hardware failed, need to reset */
166 struct timer_list timer
;
168 /* Driver defined statistic counter */
169 unsigned long tx_fifo_underrun
;
170 unsigned long tx_loss_carrier
;
171 unsigned long tx_no_carrier
;
172 unsigned long tx_late_collision
;
173 unsigned long tx_excessive_collision
;
174 unsigned long tx_jabber_timeout
;
175 unsigned long reset_count
;
176 unsigned long reset_cr8
;
177 unsigned long reset_fatal
;
178 unsigned long reset_TXtimeout
;
181 unsigned char srom
[128];
185 enum uli526x_offsets
{
186 DCR0
= 0x00, DCR1
= 0x08, DCR2
= 0x10, DCR3
= 0x18, DCR4
= 0x20,
187 DCR5
= 0x28, DCR6
= 0x30, DCR7
= 0x38, DCR8
= 0x40, DCR9
= 0x48,
188 DCR10
= 0x50, DCR11
= 0x58, DCR12
= 0x60, DCR13
= 0x68, DCR14
= 0x70,
192 enum uli526x_CR6_bits
{
193 CR6_RXSC
= 0x2, CR6_PBF
= 0x8, CR6_PM
= 0x40, CR6_PAM
= 0x80,
194 CR6_FDM
= 0x200, CR6_TXSC
= 0x2000, CR6_STI
= 0x100000,
195 CR6_SFT
= 0x200000, CR6_RXA
= 0x40000000, CR6_NO_PURGE
= 0x20000000
198 /* Global variable declaration ----------------------------- */
199 static int printed_version
;
200 static const char version
[] =
201 "ULi M5261/M5263 net driver, version " DRV_VERSION
" (" DRV_RELDATE
")";
203 static int uli526x_debug
;
204 static unsigned char uli526x_media_mode
= ULI526X_AUTO
;
205 static u32 uli526x_cr6_user_set
;
207 /* For module input parameter */
212 /* function declaration ------------------------------------- */
213 static int uli526x_open(struct net_device
*);
214 static netdev_tx_t
uli526x_start_xmit(struct sk_buff
*,
215 struct net_device
*);
216 static int uli526x_stop(struct net_device
*);
217 static void uli526x_set_filter_mode(struct net_device
*);
218 static const struct ethtool_ops netdev_ethtool_ops
;
219 static u16
read_srom_word(struct uli526x_board_info
*, int);
220 static irqreturn_t
uli526x_interrupt(int, void *);
221 #ifdef CONFIG_NET_POLL_CONTROLLER
222 static void uli526x_poll(struct net_device
*dev
);
224 static void uli526x_descriptor_init(struct net_device
*, void __iomem
*);
225 static void allocate_rx_buffer(struct net_device
*);
226 static void update_cr6(u32
, void __iomem
*);
227 static void send_filter_frame(struct net_device
*, int);
228 static u16
phy_readby_cr9(struct uli526x_board_info
*, u8
, u8
);
229 static u16
phy_readby_cr10(struct uli526x_board_info
*, u8
, u8
);
230 static void phy_writeby_cr9(struct uli526x_board_info
*, u8
, u8
, u16
);
231 static void phy_writeby_cr10(struct uli526x_board_info
*, u8
, u8
, u16
);
232 static void phy_write_1bit(struct uli526x_board_info
*db
, u32
);
233 static u16
phy_read_1bit(struct uli526x_board_info
*db
);
234 static u8
uli526x_sense_speed(struct uli526x_board_info
*);
235 static void uli526x_process_mode(struct uli526x_board_info
*);
236 static void uli526x_timer(struct timer_list
*t
);
237 static void uli526x_rx_packet(struct net_device
*, struct uli526x_board_info
*);
238 static void uli526x_free_tx_pkt(struct net_device
*, struct uli526x_board_info
*);
239 static void uli526x_reuse_skb(struct uli526x_board_info
*, struct sk_buff
*);
240 static void uli526x_dynamic_reset(struct net_device
*);
241 static void uli526x_free_rxbuffer(struct uli526x_board_info
*);
242 static void uli526x_init(struct net_device
*);
243 static void uli526x_set_phyxcer(struct uli526x_board_info
*);
245 static void srom_clk_write(struct uli526x_board_info
*db
, u32 data
)
247 void __iomem
*ioaddr
= db
->ioaddr
;
249 uw32(DCR9
, data
| CR9_SROM_READ
| CR9_SRCS
);
251 uw32(DCR9
, data
| CR9_SROM_READ
| CR9_SRCS
| CR9_SRCLK
);
253 uw32(DCR9
, data
| CR9_SROM_READ
| CR9_SRCS
);
257 /* ULI526X network board routine ---------------------------- */
259 static const struct net_device_ops netdev_ops
= {
260 .ndo_open
= uli526x_open
,
261 .ndo_stop
= uli526x_stop
,
262 .ndo_start_xmit
= uli526x_start_xmit
,
263 .ndo_set_rx_mode
= uli526x_set_filter_mode
,
264 .ndo_set_mac_address
= eth_mac_addr
,
265 .ndo_validate_addr
= eth_validate_addr
,
266 #ifdef CONFIG_NET_POLL_CONTROLLER
267 .ndo_poll_controller
= uli526x_poll
,
272 * Search ULI526X board, allocate space and register it
275 static int uli526x_init_one(struct pci_dev
*pdev
,
276 const struct pci_device_id
*ent
)
278 struct uli526x_board_info
*db
; /* board information structure */
279 struct net_device
*dev
;
280 void __iomem
*ioaddr
;
283 ULI526X_DBUG(0, "uli526x_init_one()", 0);
285 if (!printed_version
++)
286 pr_info("%s\n", version
);
288 /* Init network device */
289 dev
= alloc_etherdev(sizeof(*db
));
292 SET_NETDEV_DEV(dev
, &pdev
->dev
);
294 if (pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))) {
295 pr_warn("32-bit PCI DMA not available\n");
300 /* Enable Master/IO access, Disable memory access */
301 err
= pci_enable_device(pdev
);
305 if (!pci_resource_start(pdev
, 0)) {
306 pr_err("I/O base is zero\n");
308 goto err_out_disable
;
311 if (pci_resource_len(pdev
, 0) < (ULI526X_IO_SIZE
) ) {
312 pr_err("Allocated I/O size too small\n");
314 goto err_out_disable
;
317 err
= pci_request_regions(pdev
, DRV_NAME
);
319 pr_err("Failed to request PCI regions\n");
320 goto err_out_disable
;
323 /* Init system & device */
324 db
= netdev_priv(dev
);
326 /* Allocate Tx/Rx descriptor memory */
329 db
->desc_pool_ptr
= pci_alloc_consistent(pdev
, sizeof(struct tx_desc
) * DESC_ALL_CNT
+ 0x20, &db
->desc_pool_dma_ptr
);
330 if (!db
->desc_pool_ptr
)
331 goto err_out_release
;
333 db
->buf_pool_ptr
= pci_alloc_consistent(pdev
, TX_BUF_ALLOC
* TX_DESC_CNT
+ 4, &db
->buf_pool_dma_ptr
);
334 if (!db
->buf_pool_ptr
)
335 goto err_out_free_tx_desc
;
337 db
->first_tx_desc
= (struct tx_desc
*) db
->desc_pool_ptr
;
338 db
->first_tx_desc_dma
= db
->desc_pool_dma_ptr
;
339 db
->buf_pool_start
= db
->buf_pool_ptr
;
340 db
->buf_pool_dma_start
= db
->buf_pool_dma_ptr
;
342 switch (ent
->driver_data
) {
344 db
->phy
.write
= phy_writeby_cr10
;
345 db
->phy
.read
= phy_readby_cr10
;
348 db
->phy
.write
= phy_writeby_cr9
;
349 db
->phy
.read
= phy_readby_cr9
;
354 ioaddr
= pci_iomap(pdev
, 0, 0);
356 goto err_out_free_tx_buf
;
362 pci_set_drvdata(pdev
, dev
);
364 /* Register some necessary functions */
365 dev
->netdev_ops
= &netdev_ops
;
366 dev
->ethtool_ops
= &netdev_ethtool_ops
;
368 spin_lock_init(&db
->lock
);
371 /* read 64 word srom data */
372 for (i
= 0; i
< 64; i
++)
373 ((__le16
*) db
->srom
)[i
] = cpu_to_le16(read_srom_word(db
, i
));
375 /* Set Node address */
376 if(((u16
*) db
->srom
)[0] == 0xffff || ((u16
*) db
->srom
)[0] == 0) /* SROM absent, so read MAC address from ID Table */
378 uw32(DCR0
, 0x10000); //Diagnosis mode
379 uw32(DCR13
, 0x1c0); //Reset dianostic pointer port
380 uw32(DCR14
, 0); //Clear reset port
381 uw32(DCR14
, 0x10); //Reset ID Table pointer
382 uw32(DCR14
, 0); //Clear reset port
383 uw32(DCR13
, 0); //Clear CR13
384 uw32(DCR13
, 0x1b0); //Select ID Table access port
385 //Read MAC address from CR14
386 for (i
= 0; i
< 6; i
++)
387 dev
->dev_addr
[i
] = ur32(DCR14
);
389 uw32(DCR13
, 0); //Clear CR13
390 uw32(DCR0
, 0); //Clear CR0
395 for (i
= 0; i
< 6; i
++)
396 dev
->dev_addr
[i
] = db
->srom
[20 + i
];
398 err
= register_netdev (dev
);
402 netdev_info(dev
, "ULi M%04lx at pci%s, %pM, irq %d\n",
403 ent
->driver_data
>> 16, pci_name(pdev
),
404 dev
->dev_addr
, pdev
->irq
);
406 pci_set_master(pdev
);
411 pci_iounmap(pdev
, db
->ioaddr
);
413 pci_free_consistent(pdev
, TX_BUF_ALLOC
* TX_DESC_CNT
+ 4,
414 db
->buf_pool_ptr
, db
->buf_pool_dma_ptr
);
415 err_out_free_tx_desc
:
416 pci_free_consistent(pdev
, sizeof(struct tx_desc
) * DESC_ALL_CNT
+ 0x20,
417 db
->desc_pool_ptr
, db
->desc_pool_dma_ptr
);
419 pci_release_regions(pdev
);
421 pci_disable_device(pdev
);
429 static void uli526x_remove_one(struct pci_dev
*pdev
)
431 struct net_device
*dev
= pci_get_drvdata(pdev
);
432 struct uli526x_board_info
*db
= netdev_priv(dev
);
434 unregister_netdev(dev
);
435 pci_iounmap(pdev
, db
->ioaddr
);
436 pci_free_consistent(db
->pdev
, sizeof(struct tx_desc
) *
437 DESC_ALL_CNT
+ 0x20, db
->desc_pool_ptr
,
438 db
->desc_pool_dma_ptr
);
439 pci_free_consistent(db
->pdev
, TX_BUF_ALLOC
* TX_DESC_CNT
+ 4,
440 db
->buf_pool_ptr
, db
->buf_pool_dma_ptr
);
441 pci_release_regions(pdev
);
442 pci_disable_device(pdev
);
448 * Open the interface.
449 * The interface is opened whenever "ifconfig" activates it.
452 static int uli526x_open(struct net_device
*dev
)
455 struct uli526x_board_info
*db
= netdev_priv(dev
);
457 ULI526X_DBUG(0, "uli526x_open", 0);
459 /* system variable init */
460 db
->cr6_data
= CR6_DEFAULT
| uli526x_cr6_user_set
;
461 db
->tx_packet_cnt
= 0;
462 db
->rx_avail_cnt
= 0;
464 netif_carrier_off(dev
);
467 db
->NIC_capability
= 0xf; /* All capability*/
468 db
->PHY_reg4
= 0x1e0;
470 /* CR6 operation mode decision */
471 db
->cr6_data
|= ULI526X_TXTH_256
;
472 db
->cr0_data
= CR0_DEFAULT
;
474 /* Initialize ULI526X board */
477 ret
= request_irq(db
->pdev
->irq
, uli526x_interrupt
, IRQF_SHARED
,
482 /* Active System Interface */
483 netif_wake_queue(dev
);
485 /* set and active a timer process */
486 timer_setup(&db
->timer
, uli526x_timer
, 0);
487 db
->timer
.expires
= ULI526X_TIMER_WUT
+ HZ
* 2;
488 add_timer(&db
->timer
);
494 /* Initialize ULI526X board
495 * Reset ULI526X board
496 * Initialize TX/Rx descriptor chain structure
497 * Send the set-up frame
498 * Enable Tx/Rx machine
501 static void uli526x_init(struct net_device
*dev
)
503 struct uli526x_board_info
*db
= netdev_priv(dev
);
504 struct uli_phy_ops
*phy
= &db
->phy
;
505 void __iomem
*ioaddr
= db
->ioaddr
;
511 ULI526X_DBUG(0, "uli526x_init()", 0);
513 /* Reset M526x MAC controller */
514 uw32(DCR0
, ULI526X_RESET
); /* RESET MAC */
516 uw32(DCR0
, db
->cr0_data
);
519 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
521 for (phy_tmp
= 0; phy_tmp
< 32; phy_tmp
++) {
524 phy_value
= phy
->read(db
, phy_tmp
, 3); //peer add
525 if (phy_value
!= 0xffff && phy_value
!= 0) {
526 db
->phy_addr
= phy_tmp
;
532 pr_warn("Can not find the phy address!!!\n");
533 /* Parser SROM and media mode */
534 db
->media_mode
= uli526x_media_mode
;
536 /* phyxcer capability setting */
537 phy_reg_reset
= phy
->read(db
, db
->phy_addr
, 0);
538 phy_reg_reset
= (phy_reg_reset
| 0x8000);
539 phy
->write(db
, db
->phy_addr
, 0, phy_reg_reset
);
541 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
542 * functions") or phy data sheet for details on phy reset
546 while (timeout
-- && phy
->read(db
, db
->phy_addr
, 0) & 0x8000)
549 /* Process Phyxcer Media Mode */
550 uli526x_set_phyxcer(db
);
552 /* Media Mode Process */
553 if ( !(db
->media_mode
& ULI526X_AUTO
) )
554 db
->op_mode
= db
->media_mode
; /* Force Mode */
556 /* Initialize Transmit/Receive descriptor and CR3/4 */
557 uli526x_descriptor_init(dev
, ioaddr
);
559 /* Init CR6 to program M526X operation */
560 update_cr6(db
->cr6_data
, ioaddr
);
562 /* Send setup frame */
563 send_filter_frame(dev
, netdev_mc_count(dev
)); /* M5261/M5263 */
565 /* Init CR7, interrupt active bit */
566 db
->cr7_data
= CR7_DEFAULT
;
567 uw32(DCR7
, db
->cr7_data
);
569 /* Init CR15, Tx jabber and Rx watchdog timer */
570 uw32(DCR15
, db
->cr15_data
);
572 /* Enable ULI526X Tx/Rx function */
573 db
->cr6_data
|= CR6_RXSC
| CR6_TXSC
;
574 update_cr6(db
->cr6_data
, ioaddr
);
579 * Hardware start transmission.
580 * Send a packet to media from the upper layer.
583 static netdev_tx_t
uli526x_start_xmit(struct sk_buff
*skb
,
584 struct net_device
*dev
)
586 struct uli526x_board_info
*db
= netdev_priv(dev
);
587 void __iomem
*ioaddr
= db
->ioaddr
;
588 struct tx_desc
*txptr
;
591 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
593 /* Resource flag check */
594 netif_stop_queue(dev
);
596 /* Too large packet check */
597 if (skb
->len
> MAX_PACKET_SIZE
) {
598 netdev_err(dev
, "big packet = %d\n", (u16
)skb
->len
);
599 dev_kfree_skb_any(skb
);
603 spin_lock_irqsave(&db
->lock
, flags
);
605 /* No Tx resource check, it never happen nromally */
606 if (db
->tx_packet_cnt
>= TX_FREE_DESC_CNT
) {
607 spin_unlock_irqrestore(&db
->lock
, flags
);
608 netdev_err(dev
, "No Tx resource %ld\n", db
->tx_packet_cnt
);
609 return NETDEV_TX_BUSY
;
612 /* Disable NIC interrupt */
615 /* transmit this packet */
616 txptr
= db
->tx_insert_ptr
;
617 skb_copy_from_linear_data(skb
, txptr
->tx_buf_ptr
, skb
->len
);
618 txptr
->tdes1
= cpu_to_le32(0xe1000000 | skb
->len
);
620 /* Point to next transmit free descriptor */
621 db
->tx_insert_ptr
= txptr
->next_tx_desc
;
623 /* Transmit Packet Process */
624 if (db
->tx_packet_cnt
< TX_DESC_CNT
) {
625 txptr
->tdes0
= cpu_to_le32(0x80000000); /* Set owner bit */
626 db
->tx_packet_cnt
++; /* Ready to send */
627 uw32(DCR1
, 0x1); /* Issue Tx polling */
628 netif_trans_update(dev
); /* saved time stamp */
631 /* Tx resource check */
632 if ( db
->tx_packet_cnt
< TX_FREE_DESC_CNT
)
633 netif_wake_queue(dev
);
635 /* Restore CR7 to enable interrupt */
636 spin_unlock_irqrestore(&db
->lock
, flags
);
637 uw32(DCR7
, db
->cr7_data
);
640 dev_consume_skb_any(skb
);
647 * Stop the interface.
648 * The interface is stopped when it is brought.
651 static int uli526x_stop(struct net_device
*dev
)
653 struct uli526x_board_info
*db
= netdev_priv(dev
);
654 void __iomem
*ioaddr
= db
->ioaddr
;
657 netif_stop_queue(dev
);
660 del_timer_sync(&db
->timer
);
662 /* Reset & stop ULI526X board */
663 uw32(DCR0
, ULI526X_RESET
);
665 db
->phy
.write(db
, db
->phy_addr
, 0, 0x8000);
668 free_irq(db
->pdev
->irq
, dev
);
670 /* free allocated rx buffer */
671 uli526x_free_rxbuffer(db
);
678 * M5261/M5263 insterrupt handler
679 * receive the packet to upper layer, free the transmitted packet
682 static irqreturn_t
uli526x_interrupt(int irq
, void *dev_id
)
684 struct net_device
*dev
= dev_id
;
685 struct uli526x_board_info
*db
= netdev_priv(dev
);
686 void __iomem
*ioaddr
= db
->ioaddr
;
689 spin_lock_irqsave(&db
->lock
, flags
);
692 /* Got ULI526X status */
693 db
->cr5_data
= ur32(DCR5
);
694 uw32(DCR5
, db
->cr5_data
);
695 if ( !(db
->cr5_data
& 0x180c1) ) {
696 /* Restore CR7 to enable interrupt mask */
697 uw32(DCR7
, db
->cr7_data
);
698 spin_unlock_irqrestore(&db
->lock
, flags
);
702 /* Check system status */
703 if (db
->cr5_data
& 0x2000) {
704 /* system bus error happen */
705 ULI526X_DBUG(1, "System bus error happen. CR5=", db
->cr5_data
);
707 db
->wait_reset
= 1; /* Need to RESET */
708 spin_unlock_irqrestore(&db
->lock
, flags
);
712 /* Received the coming packet */
713 if ( (db
->cr5_data
& 0x40) && db
->rx_avail_cnt
)
714 uli526x_rx_packet(dev
, db
);
716 /* reallocate rx descriptor buffer */
717 if (db
->rx_avail_cnt
<RX_DESC_CNT
)
718 allocate_rx_buffer(dev
);
720 /* Free the transmitted descriptor */
721 if ( db
->cr5_data
& 0x01)
722 uli526x_free_tx_pkt(dev
, db
);
724 /* Restore CR7 to enable interrupt mask */
725 uw32(DCR7
, db
->cr7_data
);
727 spin_unlock_irqrestore(&db
->lock
, flags
);
731 #ifdef CONFIG_NET_POLL_CONTROLLER
732 static void uli526x_poll(struct net_device
*dev
)
734 struct uli526x_board_info
*db
= netdev_priv(dev
);
736 /* ISR grabs the irqsave lock, so this should be safe */
737 uli526x_interrupt(db
->pdev
->irq
, dev
);
742 * Free TX resource after TX complete
745 static void uli526x_free_tx_pkt(struct net_device
*dev
,
746 struct uli526x_board_info
* db
)
748 struct tx_desc
*txptr
;
751 txptr
= db
->tx_remove_ptr
;
752 while(db
->tx_packet_cnt
) {
753 tdes0
= le32_to_cpu(txptr
->tdes0
);
754 if (tdes0
& 0x80000000)
757 /* A packet sent completed */
759 dev
->stats
.tx_packets
++;
761 /* Transmit statistic counter */
762 if ( tdes0
!= 0x7fffffff ) {
763 dev
->stats
.collisions
+= (tdes0
>> 3) & 0xf;
764 dev
->stats
.tx_bytes
+= le32_to_cpu(txptr
->tdes1
) & 0x7ff;
765 if (tdes0
& TDES0_ERR_MASK
) {
766 dev
->stats
.tx_errors
++;
767 if (tdes0
& 0x0002) { /* UnderRun */
768 db
->tx_fifo_underrun
++;
769 if ( !(db
->cr6_data
& CR6_SFT
) ) {
770 db
->cr6_data
= db
->cr6_data
| CR6_SFT
;
771 update_cr6(db
->cr6_data
, db
->ioaddr
);
775 db
->tx_excessive_collision
++;
777 db
->tx_late_collision
++;
781 db
->tx_loss_carrier
++;
783 db
->tx_jabber_timeout
++;
787 txptr
= txptr
->next_tx_desc
;
790 /* Update TX remove pointer to next */
791 db
->tx_remove_ptr
= txptr
;
793 /* Resource available check */
794 if ( db
->tx_packet_cnt
< TX_WAKE_DESC_CNT
)
795 netif_wake_queue(dev
); /* Active upper layer, send again */
800 * Receive the come packet and pass to upper layer
803 static void uli526x_rx_packet(struct net_device
*dev
, struct uli526x_board_info
* db
)
805 struct rx_desc
*rxptr
;
810 rxptr
= db
->rx_ready_ptr
;
812 while(db
->rx_avail_cnt
) {
813 rdes0
= le32_to_cpu(rxptr
->rdes0
);
814 if (rdes0
& 0x80000000) /* packet owner check */
820 db
->interval_rx_cnt
++;
822 pci_unmap_single(db
->pdev
, le32_to_cpu(rxptr
->rdes2
), RX_ALLOC_SIZE
, PCI_DMA_FROMDEVICE
);
823 if ( (rdes0
& 0x300) != 0x300) {
824 /* A packet without First/Last flag */
826 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0
);
827 uli526x_reuse_skb(db
, rxptr
->rx_skb_ptr
);
829 /* A packet with First/Last flag */
830 rxlen
= ( (rdes0
>> 16) & 0x3fff) - 4;
832 /* error summary bit check */
833 if (rdes0
& 0x8000) {
834 /* This is a error packet */
835 dev
->stats
.rx_errors
++;
837 dev
->stats
.rx_fifo_errors
++;
839 dev
->stats
.rx_crc_errors
++;
841 dev
->stats
.rx_length_errors
++;
844 if ( !(rdes0
& 0x8000) ||
845 ((db
->cr6_data
& CR6_PM
) && (rxlen
>6)) ) {
846 struct sk_buff
*new_skb
= NULL
;
848 skb
= rxptr
->rx_skb_ptr
;
850 /* Good packet, send to upper layer */
851 /* Shorst packet used new SKB */
852 if ((rxlen
< RX_COPY_SIZE
) &&
853 (((new_skb
= netdev_alloc_skb(dev
, rxlen
+ 2)) != NULL
))) {
855 /* size less than COPY_SIZE, allocate a rxlen SKB */
856 skb_reserve(skb
, 2); /* 16byte align */
858 skb_tail_pointer(rxptr
->rx_skb_ptr
),
860 uli526x_reuse_skb(db
, rxptr
->rx_skb_ptr
);
864 skb
->protocol
= eth_type_trans(skb
, dev
);
866 dev
->stats
.rx_packets
++;
867 dev
->stats
.rx_bytes
+= rxlen
;
870 /* Reuse SKB buffer when the packet is error */
871 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0
);
872 uli526x_reuse_skb(db
, rxptr
->rx_skb_ptr
);
876 rxptr
= rxptr
->next_rx_desc
;
879 db
->rx_ready_ptr
= rxptr
;
884 * Set ULI526X multicast address
887 static void uli526x_set_filter_mode(struct net_device
* dev
)
889 struct uli526x_board_info
*db
= netdev_priv(dev
);
892 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
893 spin_lock_irqsave(&db
->lock
, flags
);
895 if (dev
->flags
& IFF_PROMISC
) {
896 ULI526X_DBUG(0, "Enable PROM Mode", 0);
897 db
->cr6_data
|= CR6_PM
| CR6_PBF
;
898 update_cr6(db
->cr6_data
, db
->ioaddr
);
899 spin_unlock_irqrestore(&db
->lock
, flags
);
903 if (dev
->flags
& IFF_ALLMULTI
||
904 netdev_mc_count(dev
) > ULI5261_MAX_MULTICAST
) {
905 ULI526X_DBUG(0, "Pass all multicast address",
906 netdev_mc_count(dev
));
907 db
->cr6_data
&= ~(CR6_PM
| CR6_PBF
);
908 db
->cr6_data
|= CR6_PAM
;
909 spin_unlock_irqrestore(&db
->lock
, flags
);
913 ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev
));
914 send_filter_frame(dev
, netdev_mc_count(dev
)); /* M5261/M5263 */
915 spin_unlock_irqrestore(&db
->lock
, flags
);
919 ULi_ethtool_get_link_ksettings(struct uli526x_board_info
*db
,
920 struct ethtool_link_ksettings
*cmd
)
922 u32 supported
, advertising
;
924 supported
= (SUPPORTED_10baseT_Half
|
925 SUPPORTED_10baseT_Full
|
926 SUPPORTED_100baseT_Half
|
927 SUPPORTED_100baseT_Full
|
931 advertising
= (ADVERTISED_10baseT_Half
|
932 ADVERTISED_10baseT_Full
|
933 ADVERTISED_100baseT_Half
|
934 ADVERTISED_100baseT_Full
|
938 ethtool_convert_legacy_u32_to_link_mode(cmd
->link_modes
.supported
,
940 ethtool_convert_legacy_u32_to_link_mode(cmd
->link_modes
.advertising
,
943 cmd
->base
.port
= PORT_MII
;
944 cmd
->base
.phy_address
= db
->phy_addr
;
946 cmd
->base
.speed
= SPEED_10
;
947 cmd
->base
.duplex
= DUPLEX_HALF
;
949 if(db
->op_mode
==ULI526X_100MHF
|| db
->op_mode
==ULI526X_100MFD
)
951 cmd
->base
.speed
= SPEED_100
;
953 if(db
->op_mode
==ULI526X_10MFD
|| db
->op_mode
==ULI526X_100MFD
)
955 cmd
->base
.duplex
= DUPLEX_FULL
;
959 cmd
->base
.speed
= SPEED_UNKNOWN
;
960 cmd
->base
.duplex
= DUPLEX_UNKNOWN
;
963 if (db
->media_mode
& ULI526X_AUTO
)
965 cmd
->base
.autoneg
= AUTONEG_ENABLE
;
969 static void netdev_get_drvinfo(struct net_device
*dev
,
970 struct ethtool_drvinfo
*info
)
972 struct uli526x_board_info
*np
= netdev_priv(dev
);
974 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
975 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
976 strlcpy(info
->bus_info
, pci_name(np
->pdev
), sizeof(info
->bus_info
));
979 static int netdev_get_link_ksettings(struct net_device
*dev
,
980 struct ethtool_link_ksettings
*cmd
)
982 struct uli526x_board_info
*np
= netdev_priv(dev
);
984 ULi_ethtool_get_link_ksettings(np
, cmd
);
989 static u32
netdev_get_link(struct net_device
*dev
) {
990 struct uli526x_board_info
*np
= netdev_priv(dev
);
998 static void uli526x_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1000 wol
->supported
= WAKE_PHY
| WAKE_MAGIC
;
1004 static const struct ethtool_ops netdev_ethtool_ops
= {
1005 .get_drvinfo
= netdev_get_drvinfo
,
1006 .get_link
= netdev_get_link
,
1007 .get_wol
= uli526x_get_wol
,
1008 .get_link_ksettings
= netdev_get_link_ksettings
,
1012 * A periodic timer routine
1013 * Dynamic media sense, allocate Rx buffer...
1016 static void uli526x_timer(struct timer_list
*t
)
1018 struct uli526x_board_info
*db
= from_timer(db
, t
, timer
);
1019 struct net_device
*dev
= pci_get_drvdata(db
->pdev
);
1020 struct uli_phy_ops
*phy
= &db
->phy
;
1021 void __iomem
*ioaddr
= db
->ioaddr
;
1022 unsigned long flags
;
1026 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1027 spin_lock_irqsave(&db
->lock
, flags
);
1030 /* Dynamic reset ULI526X : system error or transmit time-out */
1031 tmp_cr8
= ur32(DCR8
);
1032 if ( (db
->interval_rx_cnt
==0) && (tmp_cr8
) ) {
1036 db
->interval_rx_cnt
= 0;
1038 /* TX polling kick monitor */
1039 if ( db
->tx_packet_cnt
&&
1040 time_after(jiffies
, dev_trans_start(dev
) + ULI526X_TX_KICK
) ) {
1041 uw32(DCR1
, 0x1); // Tx polling again
1044 if ( time_after(jiffies
, dev_trans_start(dev
) + ULI526X_TX_TIMEOUT
) ) {
1045 db
->reset_TXtimeout
++;
1047 netdev_err(dev
, " Tx timeout - resetting\n");
1051 if (db
->wait_reset
) {
1052 ULI526X_DBUG(0, "Dynamic Reset device", db
->tx_packet_cnt
);
1054 uli526x_dynamic_reset(dev
);
1055 db
->timer
.expires
= ULI526X_TIMER_WUT
;
1056 add_timer(&db
->timer
);
1057 spin_unlock_irqrestore(&db
->lock
, flags
);
1061 /* Link status check, Dynamic media type change */
1062 if ((phy
->read(db
, db
->phy_addr
, 5) & 0x01e0)!=0)
1065 if ( !(tmp_cr12
& 0x3) && !db
->link_failed
) {
1067 ULI526X_DBUG(0, "Link Failed", tmp_cr12
);
1068 netif_carrier_off(dev
);
1069 netdev_info(dev
, "NIC Link is Down\n");
1070 db
->link_failed
= 1;
1072 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1073 /* AUTO don't need */
1074 if ( !(db
->media_mode
& 0x8) )
1075 phy
->write(db
, db
->phy_addr
, 0, 0x1000);
1077 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1078 if (db
->media_mode
& ULI526X_AUTO
) {
1079 db
->cr6_data
&=~0x00000200; /* bit9=0, HD mode */
1080 update_cr6(db
->cr6_data
, db
->ioaddr
);
1083 if ((tmp_cr12
& 0x3) && db
->link_failed
) {
1084 ULI526X_DBUG(0, "Link link OK", tmp_cr12
);
1085 db
->link_failed
= 0;
1087 /* Auto Sense Speed */
1088 if ( (db
->media_mode
& ULI526X_AUTO
) &&
1089 uli526x_sense_speed(db
) )
1090 db
->link_failed
= 1;
1091 uli526x_process_mode(db
);
1093 if(db
->link_failed
==0)
1095 netdev_info(dev
, "NIC Link is Up %d Mbps %s duplex\n",
1096 (db
->op_mode
== ULI526X_100MHF
||
1097 db
->op_mode
== ULI526X_100MFD
)
1099 (db
->op_mode
== ULI526X_10MFD
||
1100 db
->op_mode
== ULI526X_100MFD
)
1102 netif_carrier_on(dev
);
1104 /* SHOW_MEDIA_TYPE(db->op_mode); */
1106 else if(!(tmp_cr12
& 0x3) && db
->link_failed
)
1110 netdev_info(dev
, "NIC Link is Down\n");
1111 netif_carrier_off(dev
);
1116 /* Timer active again */
1117 db
->timer
.expires
= ULI526X_TIMER_WUT
;
1118 add_timer(&db
->timer
);
1119 spin_unlock_irqrestore(&db
->lock
, flags
);
1124 * Stop ULI526X board
1125 * Free Tx/Rx allocated memory
1126 * Init system variable
1129 static void uli526x_reset_prepare(struct net_device
*dev
)
1131 struct uli526x_board_info
*db
= netdev_priv(dev
);
1132 void __iomem
*ioaddr
= db
->ioaddr
;
1134 /* Sopt MAC controller */
1135 db
->cr6_data
&= ~(CR6_RXSC
| CR6_TXSC
); /* Disable Tx/Rx */
1136 update_cr6(db
->cr6_data
, ioaddr
);
1137 uw32(DCR7
, 0); /* Disable Interrupt */
1138 uw32(DCR5
, ur32(DCR5
));
1140 /* Disable upper layer interface */
1141 netif_stop_queue(dev
);
1143 /* Free Rx Allocate buffer */
1144 uli526x_free_rxbuffer(db
);
1146 /* system variable init */
1147 db
->tx_packet_cnt
= 0;
1148 db
->rx_avail_cnt
= 0;
1149 db
->link_failed
= 1;
1156 * Dynamic reset the ULI526X board
1157 * Stop ULI526X board
1158 * Free Tx/Rx allocated memory
1159 * Reset ULI526X board
1160 * Re-initialize ULI526X board
1163 static void uli526x_dynamic_reset(struct net_device
*dev
)
1165 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1167 uli526x_reset_prepare(dev
);
1169 /* Re-initialize ULI526X board */
1172 /* Restart upper layer interface */
1173 netif_wake_queue(dev
);
1180 * Suspend the interface.
1183 static int uli526x_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1185 struct net_device
*dev
= pci_get_drvdata(pdev
);
1186 pci_power_t power_state
;
1189 ULI526X_DBUG(0, "uli526x_suspend", 0);
1191 pci_save_state(pdev
);
1193 if (!netif_running(dev
))
1196 netif_device_detach(dev
);
1197 uli526x_reset_prepare(dev
);
1199 power_state
= pci_choose_state(pdev
, state
);
1200 pci_enable_wake(pdev
, power_state
, 0);
1201 err
= pci_set_power_state(pdev
, power_state
);
1203 netif_device_attach(dev
);
1204 /* Re-initialize ULI526X board */
1206 /* Restart upper layer interface */
1207 netif_wake_queue(dev
);
1214 * Resume the interface.
1217 static int uli526x_resume(struct pci_dev
*pdev
)
1219 struct net_device
*dev
= pci_get_drvdata(pdev
);
1222 ULI526X_DBUG(0, "uli526x_resume", 0);
1224 pci_restore_state(pdev
);
1226 if (!netif_running(dev
))
1229 err
= pci_set_power_state(pdev
, PCI_D0
);
1231 netdev_warn(dev
, "Could not put device into D0\n");
1235 netif_device_attach(dev
);
1236 /* Re-initialize ULI526X board */
1238 /* Restart upper layer interface */
1239 netif_wake_queue(dev
);
1244 #else /* !CONFIG_PM */
1246 #define uli526x_suspend NULL
1247 #define uli526x_resume NULL
1249 #endif /* !CONFIG_PM */
1253 * free all allocated rx buffer
1256 static void uli526x_free_rxbuffer(struct uli526x_board_info
* db
)
1258 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1260 /* free allocated rx buffer */
1261 while (db
->rx_avail_cnt
) {
1262 dev_kfree_skb(db
->rx_ready_ptr
->rx_skb_ptr
);
1263 db
->rx_ready_ptr
= db
->rx_ready_ptr
->next_rx_desc
;
1270 * Reuse the SK buffer
1273 static void uli526x_reuse_skb(struct uli526x_board_info
*db
, struct sk_buff
* skb
)
1275 struct rx_desc
*rxptr
= db
->rx_insert_ptr
;
1277 if (!(rxptr
->rdes0
& cpu_to_le32(0x80000000))) {
1278 rxptr
->rx_skb_ptr
= skb
;
1279 rxptr
->rdes2
= cpu_to_le32(pci_map_single(db
->pdev
,
1280 skb_tail_pointer(skb
),
1282 PCI_DMA_FROMDEVICE
));
1284 rxptr
->rdes0
= cpu_to_le32(0x80000000);
1286 db
->rx_insert_ptr
= rxptr
->next_rx_desc
;
1288 ULI526X_DBUG(0, "SK Buffer reuse method error", db
->rx_avail_cnt
);
1293 * Initialize transmit/Receive descriptor
1294 * Using Chain structure, and allocate Tx/Rx buffer
1297 static void uli526x_descriptor_init(struct net_device
*dev
, void __iomem
*ioaddr
)
1299 struct uli526x_board_info
*db
= netdev_priv(dev
);
1300 struct tx_desc
*tmp_tx
;
1301 struct rx_desc
*tmp_rx
;
1302 unsigned char *tmp_buf
;
1303 dma_addr_t tmp_tx_dma
, tmp_rx_dma
;
1304 dma_addr_t tmp_buf_dma
;
1307 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1309 /* tx descriptor start pointer */
1310 db
->tx_insert_ptr
= db
->first_tx_desc
;
1311 db
->tx_remove_ptr
= db
->first_tx_desc
;
1312 uw32(DCR4
, db
->first_tx_desc_dma
); /* TX DESC address */
1314 /* rx descriptor start pointer */
1315 db
->first_rx_desc
= (void *)db
->first_tx_desc
+ sizeof(struct tx_desc
) * TX_DESC_CNT
;
1316 db
->first_rx_desc_dma
= db
->first_tx_desc_dma
+ sizeof(struct tx_desc
) * TX_DESC_CNT
;
1317 db
->rx_insert_ptr
= db
->first_rx_desc
;
1318 db
->rx_ready_ptr
= db
->first_rx_desc
;
1319 uw32(DCR3
, db
->first_rx_desc_dma
); /* RX DESC address */
1321 /* Init Transmit chain */
1322 tmp_buf
= db
->buf_pool_start
;
1323 tmp_buf_dma
= db
->buf_pool_dma_start
;
1324 tmp_tx_dma
= db
->first_tx_desc_dma
;
1325 for (tmp_tx
= db
->first_tx_desc
, i
= 0; i
< TX_DESC_CNT
; i
++, tmp_tx
++) {
1326 tmp_tx
->tx_buf_ptr
= tmp_buf
;
1327 tmp_tx
->tdes0
= cpu_to_le32(0);
1328 tmp_tx
->tdes1
= cpu_to_le32(0x81000000); /* IC, chain */
1329 tmp_tx
->tdes2
= cpu_to_le32(tmp_buf_dma
);
1330 tmp_tx_dma
+= sizeof(struct tx_desc
);
1331 tmp_tx
->tdes3
= cpu_to_le32(tmp_tx_dma
);
1332 tmp_tx
->next_tx_desc
= tmp_tx
+ 1;
1333 tmp_buf
= tmp_buf
+ TX_BUF_ALLOC
;
1334 tmp_buf_dma
= tmp_buf_dma
+ TX_BUF_ALLOC
;
1336 (--tmp_tx
)->tdes3
= cpu_to_le32(db
->first_tx_desc_dma
);
1337 tmp_tx
->next_tx_desc
= db
->first_tx_desc
;
1339 /* Init Receive descriptor chain */
1340 tmp_rx_dma
=db
->first_rx_desc_dma
;
1341 for (tmp_rx
= db
->first_rx_desc
, i
= 0; i
< RX_DESC_CNT
; i
++, tmp_rx
++) {
1342 tmp_rx
->rdes0
= cpu_to_le32(0);
1343 tmp_rx
->rdes1
= cpu_to_le32(0x01000600);
1344 tmp_rx_dma
+= sizeof(struct rx_desc
);
1345 tmp_rx
->rdes3
= cpu_to_le32(tmp_rx_dma
);
1346 tmp_rx
->next_rx_desc
= tmp_rx
+ 1;
1348 (--tmp_rx
)->rdes3
= cpu_to_le32(db
->first_rx_desc_dma
);
1349 tmp_rx
->next_rx_desc
= db
->first_rx_desc
;
1351 /* pre-allocate Rx buffer */
1352 allocate_rx_buffer(dev
);
1358 * Firstly stop ULI526X, then written value and start
1360 static void update_cr6(u32 cr6_data
, void __iomem
*ioaddr
)
1362 uw32(DCR6
, cr6_data
);
1368 * Send a setup frame for M5261/M5263
1369 * This setup frame initialize ULI526X address filter mode
1373 #define FLT_SHIFT 16
1378 static void send_filter_frame(struct net_device
*dev
, int mc_cnt
)
1380 struct uli526x_board_info
*db
= netdev_priv(dev
);
1381 void __iomem
*ioaddr
= db
->ioaddr
;
1382 struct netdev_hw_addr
*ha
;
1383 struct tx_desc
*txptr
;
1388 ULI526X_DBUG(0, "send_filter_frame()", 0);
1390 txptr
= db
->tx_insert_ptr
;
1391 suptr
= (u32
*) txptr
->tx_buf_ptr
;
1394 addrptr
= (u16
*) dev
->dev_addr
;
1395 *suptr
++ = addrptr
[0] << FLT_SHIFT
;
1396 *suptr
++ = addrptr
[1] << FLT_SHIFT
;
1397 *suptr
++ = addrptr
[2] << FLT_SHIFT
;
1399 /* broadcast address */
1400 *suptr
++ = 0xffff << FLT_SHIFT
;
1401 *suptr
++ = 0xffff << FLT_SHIFT
;
1402 *suptr
++ = 0xffff << FLT_SHIFT
;
1404 /* fit the multicast address */
1405 netdev_for_each_mc_addr(ha
, dev
) {
1406 addrptr
= (u16
*) ha
->addr
;
1407 *suptr
++ = addrptr
[0] << FLT_SHIFT
;
1408 *suptr
++ = addrptr
[1] << FLT_SHIFT
;
1409 *suptr
++ = addrptr
[2] << FLT_SHIFT
;
1412 for (i
= netdev_mc_count(dev
); i
< 14; i
++) {
1413 *suptr
++ = 0xffff << FLT_SHIFT
;
1414 *suptr
++ = 0xffff << FLT_SHIFT
;
1415 *suptr
++ = 0xffff << FLT_SHIFT
;
1418 /* prepare the setup frame */
1419 db
->tx_insert_ptr
= txptr
->next_tx_desc
;
1420 txptr
->tdes1
= cpu_to_le32(0x890000c0);
1422 /* Resource Check and Send the setup packet */
1423 if (db
->tx_packet_cnt
< TX_DESC_CNT
) {
1424 /* Resource Empty */
1425 db
->tx_packet_cnt
++;
1426 txptr
->tdes0
= cpu_to_le32(0x80000000);
1427 update_cr6(db
->cr6_data
| 0x2000, ioaddr
);
1428 uw32(DCR1
, 0x1); /* Issue Tx polling */
1429 update_cr6(db
->cr6_data
, ioaddr
);
1430 netif_trans_update(dev
);
1432 netdev_err(dev
, "No Tx resource - Send_filter_frame!\n");
1437 * Allocate rx buffer,
1438 * As possible as allocate maxiumn Rx buffer
1441 static void allocate_rx_buffer(struct net_device
*dev
)
1443 struct uli526x_board_info
*db
= netdev_priv(dev
);
1444 struct rx_desc
*rxptr
;
1445 struct sk_buff
*skb
;
1447 rxptr
= db
->rx_insert_ptr
;
1449 while(db
->rx_avail_cnt
< RX_DESC_CNT
) {
1450 skb
= netdev_alloc_skb(dev
, RX_ALLOC_SIZE
);
1453 rxptr
->rx_skb_ptr
= skb
; /* FIXME (?) */
1454 rxptr
->rdes2
= cpu_to_le32(pci_map_single(db
->pdev
,
1455 skb_tail_pointer(skb
),
1457 PCI_DMA_FROMDEVICE
));
1459 rxptr
->rdes0
= cpu_to_le32(0x80000000);
1460 rxptr
= rxptr
->next_rx_desc
;
1464 db
->rx_insert_ptr
= rxptr
;
1469 * Read one word data from the serial ROM
1472 static u16
read_srom_word(struct uli526x_board_info
*db
, int offset
)
1474 void __iomem
*ioaddr
= db
->ioaddr
;
1478 uw32(DCR9
, CR9_SROM_READ
);
1479 uw32(DCR9
, CR9_SROM_READ
| CR9_SRCS
);
1481 /* Send the Read Command 110b */
1482 srom_clk_write(db
, SROM_DATA_1
);
1483 srom_clk_write(db
, SROM_DATA_1
);
1484 srom_clk_write(db
, SROM_DATA_0
);
1486 /* Send the offset */
1487 for (i
= 5; i
>= 0; i
--) {
1488 srom_data
= (offset
& (1 << i
)) ? SROM_DATA_1
: SROM_DATA_0
;
1489 srom_clk_write(db
, srom_data
);
1492 uw32(DCR9
, CR9_SROM_READ
| CR9_SRCS
);
1494 for (i
= 16; i
> 0; i
--) {
1495 uw32(DCR9
, CR9_SROM_READ
| CR9_SRCS
| CR9_SRCLK
);
1497 srom_data
= (srom_data
<< 1) |
1498 ((ur32(DCR9
) & CR9_CRDOUT
) ? 1 : 0);
1499 uw32(DCR9
, CR9_SROM_READ
| CR9_SRCS
);
1503 uw32(DCR9
, CR9_SROM_READ
);
1509 * Auto sense the media mode
1512 static u8
uli526x_sense_speed(struct uli526x_board_info
* db
)
1514 struct uli_phy_ops
*phy
= &db
->phy
;
1518 phy_mode
= phy
->read(db
, db
->phy_addr
, 1);
1519 phy_mode
= phy
->read(db
, db
->phy_addr
, 1);
1521 if ( (phy_mode
& 0x24) == 0x24 ) {
1523 phy_mode
= ((phy
->read(db
, db
->phy_addr
, 5) & 0x01e0)<<7);
1526 else if(phy_mode
&0x4000)
1528 else if(phy_mode
&0x2000)
1534 case 0x1000: db
->op_mode
= ULI526X_10MHF
; break;
1535 case 0x2000: db
->op_mode
= ULI526X_10MFD
; break;
1536 case 0x4000: db
->op_mode
= ULI526X_100MHF
; break;
1537 case 0x8000: db
->op_mode
= ULI526X_100MFD
; break;
1538 default: db
->op_mode
= ULI526X_10MHF
; ErrFlag
= 1; break;
1541 db
->op_mode
= ULI526X_10MHF
;
1542 ULI526X_DBUG(0, "Link Failed :", phy_mode
);
1551 * Set 10/100 phyxcer capability
1552 * AUTO mode : phyxcer register4 is NIC capability
1553 * Force mode: phyxcer register4 is the force media
1556 static void uli526x_set_phyxcer(struct uli526x_board_info
*db
)
1558 struct uli_phy_ops
*phy
= &db
->phy
;
1561 /* Phyxcer capability setting */
1562 phy_reg
= phy
->read(db
, db
->phy_addr
, 4) & ~0x01e0;
1564 if (db
->media_mode
& ULI526X_AUTO
) {
1566 phy_reg
|= db
->PHY_reg4
;
1569 switch(db
->media_mode
) {
1570 case ULI526X_10MHF
: phy_reg
|= 0x20; break;
1571 case ULI526X_10MFD
: phy_reg
|= 0x40; break;
1572 case ULI526X_100MHF
: phy_reg
|= 0x80; break;
1573 case ULI526X_100MFD
: phy_reg
|= 0x100; break;
1578 /* Write new capability to Phyxcer Reg4 */
1579 if ( !(phy_reg
& 0x01e0)) {
1580 phy_reg
|=db
->PHY_reg4
;
1581 db
->media_mode
|=ULI526X_AUTO
;
1583 phy
->write(db
, db
->phy_addr
, 4, phy_reg
);
1585 /* Restart Auto-Negotiation */
1586 phy
->write(db
, db
->phy_addr
, 0, 0x1200);
1593 AUTO mode : PHY controller in Auto-negotiation Mode
1594 * Force mode: PHY controller in force mode with HUB
1595 * N-way force capability with SWITCH
1598 static void uli526x_process_mode(struct uli526x_board_info
*db
)
1600 struct uli_phy_ops
*phy
= &db
->phy
;
1603 /* Full Duplex Mode Check */
1604 if (db
->op_mode
& 0x4)
1605 db
->cr6_data
|= CR6_FDM
; /* Set Full Duplex Bit */
1607 db
->cr6_data
&= ~CR6_FDM
; /* Clear Full Duplex Bit */
1609 update_cr6(db
->cr6_data
, db
->ioaddr
);
1611 /* 10/100M phyxcer force mode need */
1612 if (!(db
->media_mode
& 0x8)) {
1614 phy_reg
= phy
->read(db
, db
->phy_addr
, 6);
1615 if (!(phy_reg
& 0x1)) {
1616 /* parter without N-Way capability */
1618 switch(db
->op_mode
) {
1619 case ULI526X_10MHF
: phy_reg
= 0x0; break;
1620 case ULI526X_10MFD
: phy_reg
= 0x100; break;
1621 case ULI526X_100MHF
: phy_reg
= 0x2000; break;
1622 case ULI526X_100MFD
: phy_reg
= 0x2100; break;
1624 phy
->write(db
, db
->phy_addr
, 0, phy_reg
);
1630 /* M5261/M5263 Chip */
1631 static void phy_writeby_cr9(struct uli526x_board_info
*db
, u8 phy_addr
,
1632 u8 offset
, u16 phy_data
)
1636 /* Send 33 synchronization clock to Phy controller */
1637 for (i
= 0; i
< 35; i
++)
1638 phy_write_1bit(db
, PHY_DATA_1
);
1640 /* Send start command(01) to Phy */
1641 phy_write_1bit(db
, PHY_DATA_0
);
1642 phy_write_1bit(db
, PHY_DATA_1
);
1644 /* Send write command(01) to Phy */
1645 phy_write_1bit(db
, PHY_DATA_0
);
1646 phy_write_1bit(db
, PHY_DATA_1
);
1648 /* Send Phy address */
1649 for (i
= 0x10; i
> 0; i
= i
>> 1)
1650 phy_write_1bit(db
, phy_addr
& i
? PHY_DATA_1
: PHY_DATA_0
);
1652 /* Send register address */
1653 for (i
= 0x10; i
> 0; i
= i
>> 1)
1654 phy_write_1bit(db
, offset
& i
? PHY_DATA_1
: PHY_DATA_0
);
1656 /* written trasnition */
1657 phy_write_1bit(db
, PHY_DATA_1
);
1658 phy_write_1bit(db
, PHY_DATA_0
);
1660 /* Write a word data to PHY controller */
1661 for (i
= 0x8000; i
> 0; i
>>= 1)
1662 phy_write_1bit(db
, phy_data
& i
? PHY_DATA_1
: PHY_DATA_0
);
1665 static u16
phy_readby_cr9(struct uli526x_board_info
*db
, u8 phy_addr
, u8 offset
)
1670 /* Send 33 synchronization clock to Phy controller */
1671 for (i
= 0; i
< 35; i
++)
1672 phy_write_1bit(db
, PHY_DATA_1
);
1674 /* Send start command(01) to Phy */
1675 phy_write_1bit(db
, PHY_DATA_0
);
1676 phy_write_1bit(db
, PHY_DATA_1
);
1678 /* Send read command(10) to Phy */
1679 phy_write_1bit(db
, PHY_DATA_1
);
1680 phy_write_1bit(db
, PHY_DATA_0
);
1682 /* Send Phy address */
1683 for (i
= 0x10; i
> 0; i
= i
>> 1)
1684 phy_write_1bit(db
, phy_addr
& i
? PHY_DATA_1
: PHY_DATA_0
);
1686 /* Send register address */
1687 for (i
= 0x10; i
> 0; i
= i
>> 1)
1688 phy_write_1bit(db
, offset
& i
? PHY_DATA_1
: PHY_DATA_0
);
1690 /* Skip transition state */
1693 /* read 16bit data */
1694 for (phy_data
= 0, i
= 0; i
< 16; i
++) {
1696 phy_data
|= phy_read_1bit(db
);
1702 static u16
phy_readby_cr10(struct uli526x_board_info
*db
, u8 phy_addr
,
1705 void __iomem
*ioaddr
= db
->ioaddr
;
1706 u32 cr10_value
= phy_addr
;
1708 cr10_value
= (cr10_value
<< 5) + offset
;
1709 cr10_value
= (cr10_value
<< 16) + 0x08000000;
1710 uw32(DCR10
, cr10_value
);
1713 cr10_value
= ur32(DCR10
);
1714 if (cr10_value
& 0x10000000)
1717 return cr10_value
& 0x0ffff;
1720 static void phy_writeby_cr10(struct uli526x_board_info
*db
, u8 phy_addr
,
1721 u8 offset
, u16 phy_data
)
1723 void __iomem
*ioaddr
= db
->ioaddr
;
1724 u32 cr10_value
= phy_addr
;
1726 cr10_value
= (cr10_value
<< 5) + offset
;
1727 cr10_value
= (cr10_value
<< 16) + 0x04000000 + phy_data
;
1728 uw32(DCR10
, cr10_value
);
1732 * Write one bit data to Phy Controller
1735 static void phy_write_1bit(struct uli526x_board_info
*db
, u32 data
)
1737 void __iomem
*ioaddr
= db
->ioaddr
;
1739 uw32(DCR9
, data
); /* MII Clock Low */
1741 uw32(DCR9
, data
| MDCLKH
); /* MII Clock High */
1743 uw32(DCR9
, data
); /* MII Clock Low */
1749 * Read one bit phy data from PHY controller
1752 static u16
phy_read_1bit(struct uli526x_board_info
*db
)
1754 void __iomem
*ioaddr
= db
->ioaddr
;
1757 uw32(DCR9
, 0x50000);
1759 phy_data
= (ur32(DCR9
) >> 19) & 0x1;
1760 uw32(DCR9
, 0x40000);
1767 static const struct pci_device_id uli526x_pci_tbl
[] = {
1768 { 0x10B9, 0x5261, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, PCI_ULI5261_ID
},
1769 { 0x10B9, 0x5263, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, PCI_ULI5263_ID
},
1772 MODULE_DEVICE_TABLE(pci
, uli526x_pci_tbl
);
1775 static struct pci_driver uli526x_driver
= {
1777 .id_table
= uli526x_pci_tbl
,
1778 .probe
= uli526x_init_one
,
1779 .remove
= uli526x_remove_one
,
1780 .suspend
= uli526x_suspend
,
1781 .resume
= uli526x_resume
,
1784 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1785 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1786 MODULE_LICENSE("GPL");
1788 module_param(debug
, int, 0644);
1789 module_param(mode
, int, 0);
1790 module_param(cr6set
, int, 0);
1791 MODULE_PARM_DESC(debug
, "ULi M5261/M5263 enable debugging (0-1)");
1792 MODULE_PARM_DESC(mode
, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1795 * when user used insmod to add module, system invoked init_module()
1796 * to register the services.
1799 static int __init
uli526x_init_module(void)
1802 pr_info("%s\n", version
);
1803 printed_version
= 1;
1805 ULI526X_DBUG(0, "init_module() ", debug
);
1808 uli526x_debug
= debug
; /* set debug flag */
1810 uli526x_cr6_user_set
= cr6set
;
1814 case ULI526X_100MHF
:
1816 case ULI526X_100MFD
:
1817 uli526x_media_mode
= mode
;
1820 uli526x_media_mode
= ULI526X_AUTO
;
1824 return pci_register_driver(&uli526x_driver
);
1830 * when user used rmmod to delete module, system invoked clean_module()
1831 * to un-register all registered services.
1834 static void __exit
uli526x_cleanup_module(void)
1836 ULI526X_DBUG(0, "uli526x_cleanup_module() ", debug
);
1837 pci_unregister_driver(&uli526x_driver
);
1840 module_init(uli526x_init_module
);
1841 module_exit(uli526x_cleanup_module
);