1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
7 #include <linux/if_vlan.h>
11 #define HNS3_MOD_VERSION "1.0"
13 extern const char hns3_driver_version
[];
16 HNS3_NIC_STATE_TESTING
,
17 HNS3_NIC_STATE_RESETTING
,
18 HNS3_NIC_STATE_INITED
,
20 HNS3_NIC_STATE_DISABLED
,
21 HNS3_NIC_STATE_REMOVING
,
22 HNS3_NIC_STATE_SERVICE_INITED
,
23 HNS3_NIC_STATE_SERVICE_SCHED
,
24 HNS3_NIC_STATE2_RESET_REQUESTED
,
28 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
29 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
30 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
31 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
32 #define HNS3_RING_RX_RING_TAIL_REG 0x00018
33 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C
34 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
35 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
37 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
38 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
39 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
40 #define HNS3_RING_TX_RING_TC_REG 0x00050
41 #define HNS3_RING_TX_RING_TAIL_REG 0x00058
42 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C
43 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
44 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064
45 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
47 #define HNS3_RING_PREFETCH_EN_REG 0x0007C
48 #define HNS3_RING_CFG_VF_NUM_REG 0x00080
49 #define HNS3_RING_ASID_REG 0x0008C
50 #define HNS3_RING_EN_REG 0x00090
51 #define HNS3_RING_T0_BE_RST 0x00094
52 #define HNS3_RING_COULD_BE_RST 0x00098
53 #define HNS3_RING_WRR_WEIGHT_REG 0x0009c
55 #define HNS3_RING_INTMSK_RXWL_REG 0x000A0
56 #define HNS3_RING_INTSTS_RX_RING_REG 0x000A4
57 #define HNS3_RX_RING_INT_STS_REG 0x000A8
58 #define HNS3_RING_INTMSK_TXWL_REG 0x000AC
59 #define HNS3_RING_INTSTS_TX_RING_REG 0x000B0
60 #define HNS3_TX_RING_INT_STS_REG 0x000B4
61 #define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8
62 #define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC
63 #define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4
64 #define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8
66 #define HNS3_RING_MB_CTRL_REG 0x00100
67 #define HNS3_RING_MB_DATA_BASE_REG 0x00200
69 #define HNS3_TX_REG_OFFSET 0x40
71 #define HNS3_RX_HEAD_SIZE 256
73 #define HNS3_TX_TIMEOUT (5 * HZ)
74 #define HNS3_RING_NAME_LEN 16
75 #define HNS3_BUFFER_SIZE_2048 2048
76 #define HNS3_RING_MAX_PENDING 32768
77 #define HNS3_RING_MIN_PENDING 24
78 #define HNS3_RING_BD_MULTIPLE 8
79 /* max frame size of mac */
80 #define HNS3_MAC_MAX_FRAME 9728
81 #define HNS3_MAX_MTU \
82 (HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))
84 #define HNS3_BD_SIZE_512_TYPE 0
85 #define HNS3_BD_SIZE_1024_TYPE 1
86 #define HNS3_BD_SIZE_2048_TYPE 2
87 #define HNS3_BD_SIZE_4096_TYPE 3
89 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
90 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
91 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
92 #define HNS3_RX_FLAG_L4ID_UDP 0x0
93 #define HNS3_RX_FLAG_L4ID_TCP 0x1
95 #define HNS3_RXD_DMAC_S 0
96 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
97 #define HNS3_RXD_VLAN_S 2
98 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
99 #define HNS3_RXD_L3ID_S 4
100 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
101 #define HNS3_RXD_L4ID_S 8
102 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
103 #define HNS3_RXD_FRAG_B 12
104 #define HNS3_RXD_STRP_TAGP_S 13
105 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
107 #define HNS3_RXD_L2E_B 16
108 #define HNS3_RXD_L3E_B 17
109 #define HNS3_RXD_L4E_B 18
110 #define HNS3_RXD_TRUNCAT_B 19
111 #define HNS3_RXD_HOI_B 20
112 #define HNS3_RXD_DOI_B 21
113 #define HNS3_RXD_OL3E_B 22
114 #define HNS3_RXD_OL4E_B 23
115 #define HNS3_RXD_GRO_COUNT_S 24
116 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
117 #define HNS3_RXD_GRO_FIXID_B 30
118 #define HNS3_RXD_GRO_ECN_B 31
120 #define HNS3_RXD_ODMAC_S 0
121 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
122 #define HNS3_RXD_OVLAN_S 2
123 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
124 #define HNS3_RXD_OL3ID_S 4
125 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
126 #define HNS3_RXD_OL4ID_S 8
127 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
128 #define HNS3_RXD_FBHI_S 12
129 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
130 #define HNS3_RXD_FBLI_S 14
131 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
133 #define HNS3_RXD_BDTYPE_S 0
134 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
135 #define HNS3_RXD_VLD_B 4
136 #define HNS3_RXD_UDP0_B 5
137 #define HNS3_RXD_EXTEND_B 7
138 #define HNS3_RXD_FE_B 8
139 #define HNS3_RXD_LUM_B 9
140 #define HNS3_RXD_CRCP_B 10
141 #define HNS3_RXD_L3L4P_B 11
142 #define HNS3_RXD_TSIND_S 12
143 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
144 #define HNS3_RXD_LKBK_B 15
145 #define HNS3_RXD_GRO_SIZE_S 16
146 #define HNS3_RXD_GRO_SIZE_M (0x3ff << HNS3_RXD_GRO_SIZE_S)
148 #define HNS3_TXD_L3T_S 0
149 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
150 #define HNS3_TXD_L4T_S 2
151 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
152 #define HNS3_TXD_L3CS_B 4
153 #define HNS3_TXD_L4CS_B 5
154 #define HNS3_TXD_VLAN_B 6
155 #define HNS3_TXD_TSO_B 7
157 #define HNS3_TXD_L2LEN_S 8
158 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
159 #define HNS3_TXD_L3LEN_S 16
160 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
161 #define HNS3_TXD_L4LEN_S 24
162 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
164 #define HNS3_TXD_OL3T_S 0
165 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
166 #define HNS3_TXD_OVLAN_B 2
167 #define HNS3_TXD_MACSEC_B 3
168 #define HNS3_TXD_TUNTYPE_S 4
169 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
171 #define HNS3_TXD_BDTYPE_S 0
172 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
173 #define HNS3_TXD_FE_B 4
174 #define HNS3_TXD_SC_S 5
175 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
176 #define HNS3_TXD_EXTEND_B 7
177 #define HNS3_TXD_VLD_B 8
178 #define HNS3_TXD_RI_B 9
179 #define HNS3_TXD_RA_B 10
180 #define HNS3_TXD_TSYN_B 11
181 #define HNS3_TXD_DECTTL_S 12
182 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
184 #define HNS3_TXD_MSS_S 0
185 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
187 #define HNS3_TX_LAST_SIZE_M 0xffff
189 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
190 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
192 #define HNS3_VECTOR_NOT_INITED 0
193 #define HNS3_VECTOR_INITED 1
195 #define HNS3_MAX_BD_SIZE 65535
196 #define HNS3_MAX_BD_SIZE_OFFSET 16
197 #define HNS3_MAX_BD_PER_FRAG 8
198 #define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS
200 #define HNS3_VECTOR_GL0_OFFSET 0x100
201 #define HNS3_VECTOR_GL1_OFFSET 0x200
202 #define HNS3_VECTOR_GL2_OFFSET 0x300
203 #define HNS3_VECTOR_RL_OFFSET 0x900
204 #define HNS3_VECTOR_RL_EN_B 6
206 #define HNS3_RING_EN_B 0
208 enum hns3_pkt_l2t_type
{
209 HNS3_L2_TYPE_UNICAST
,
210 HNS3_L2_TYPE_MULTICAST
,
211 HNS3_L2_TYPE_BROADCAST
,
212 HNS3_L2_TYPE_INVALID
,
215 enum hns3_pkt_l3t_type
{
222 enum hns3_pkt_l4t_type
{
229 enum hns3_pkt_ol3t_type
{
232 HNS3_OL3T_IPV4_NO_CSUM
,
236 enum hns3_pkt_tun_type
{
243 /* hardware spec ring buffer format */
244 struct __packed hns3_desc
{
251 __le32 type_cs_vlan_tso_len
;
253 __u8 type_cs_vlan_tso
;
259 __le16 outer_vlan_tag
;
263 __le32 ol_type_vlan_len_msec
;
265 __u8 ol_type_vlan_msec
;
273 __le16 bdtp_fe_sc_vld_ra_ri
;
289 __le16 o_dm_vlan_id_fb
;
299 struct hns3_desc_cb
{
300 dma_addr_t dma
; /* dma address of this desc */
301 void *buf
; /* cpu addr for a desc */
303 /* priv data for the desc, e.g. skb when use with ip stack*/
306 u32 length
; /* length of the buffer */
310 /* desc type, used by the ring user to mark the type of the priv data */
314 enum hns3_pkt_l3type
{
319 HNS3_L3_TYPE_IPV4_OPT
,
320 HNS3_L3_TYPE_IPV6_EXT
,
323 HNS3_L3_TYPE_MAC_PAUSE
,
324 HNS3_L3_TYPE_PFC_PAUSE
,/* 0x9*/
326 /* reserved for 0xA~0xB*/
328 HNS3_L3_TYPE_CNM
= 0xc,
330 /* reserved for 0xD~0xE*/
332 HNS3_L3_TYPE_PARSE_FAIL
= 0xf /* must be last */
335 enum hns3_pkt_l4type
{
343 /* reserved for 0x6~0xE */
345 HNS3_L4_TYPE_PARSE_FAIL
= 0xf /* must be last */
348 enum hns3_pkt_ol3type
{
349 HNS3_OL3_TYPE_IPV4
= 0,
351 /* reserved for 0x2~0x3 */
352 HNS3_OL3_TYPE_IPV4_OPT
= 4,
353 HNS3_OL3_TYPE_IPV6_EXT
,
355 /* reserved for 0x6~0xE*/
357 HNS3_OL3_TYPE_PARSE_FAIL
= 0xf /* must be last */
360 enum hns3_pkt_ol4type
{
361 HNS3_OL4_TYPE_NO_TUN
,
362 HNS3_OL4_TYPE_MAC_IN_UDP
,
364 HNS3_OL4_TYPE_UNKNOWN
394 struct hns3_enet_ring
{
395 u8 __iomem
*io_base
; /* base io address for the ring */
396 struct hns3_desc
*desc
; /* dma map address space */
397 struct hns3_desc_cb
*desc_cb
;
398 struct hns3_enet_ring
*next
;
399 struct hns3_enet_tqp_vector
*tqp_vector
;
400 struct hnae3_queue
*tqp
;
401 char ring_name
[HNS3_RING_NAME_LEN
];
402 struct device
*dev
; /* will be used for DMA mapping of descriptors */
405 struct ring_stats stats
;
406 struct u64_stats_sync syncp
;
408 dma_addr_t desc_dma_addr
;
409 u32 buf_size
; /* size for hnae_desc->addr, preset by AE */
410 u16 desc_num
; /* total number of desc */
411 u16 max_desc_num_per_pkt
;
412 u16 max_raw_data_sz_per_desc
;
414 int next_to_use
; /* idx of next spare desc */
416 /* idx of lastest sent desc, the ring is empty when equal to
421 int pull_len
; /* head length for current packet */
423 unsigned char *va
; /* first buffer address for current packet */
425 u32 flag
; /* ring attribute */
428 cpumask_t affinity_mask
;
432 struct sk_buff
*tail_skb
;
437 struct hns3_nic_ring_data
{
438 struct hns3_enet_ring
*ring
;
439 struct napi_struct napi
;
441 int (*poll_one
)(struct hns3_nic_ring_data
*, int, void *);
442 void (*ex_process
)(struct hns3_nic_ring_data
*, struct sk_buff
*);
443 void (*fini_process
)(struct hns3_nic_ring_data
*);
446 struct hns3_nic_ops
{
447 int (*maybe_stop_tx
)(struct sk_buff
**out_skb
,
448 int *bnum
, struct hns3_enet_ring
*ring
);
451 enum hns3_flow_level_range
{
458 enum hns3_link_mode_bits
{
459 HNS3_LM_FIBRE_BIT
= BIT(0),
460 HNS3_LM_AUTONEG_BIT
= BIT(1),
461 HNS3_LM_TP_BIT
= BIT(2),
462 HNS3_LM_PAUSE_BIT
= BIT(3),
463 HNS3_LM_BACKPLANE_BIT
= BIT(4),
464 HNS3_LM_10BASET_HALF_BIT
= BIT(5),
465 HNS3_LM_10BASET_FULL_BIT
= BIT(6),
466 HNS3_LM_100BASET_HALF_BIT
= BIT(7),
467 HNS3_LM_100BASET_FULL_BIT
= BIT(8),
468 HNS3_LM_1000BASET_FULL_BIT
= BIT(9),
469 HNS3_LM_10000BASEKR_FULL_BIT
= BIT(10),
470 HNS3_LM_25000BASEKR_FULL_BIT
= BIT(11),
471 HNS3_LM_40000BASELR4_FULL_BIT
= BIT(12),
472 HNS3_LM_50000BASEKR2_FULL_BIT
= BIT(13),
473 HNS3_LM_100000BASEKR4_FULL_BIT
= BIT(14),
477 #define HNS3_INT_GL_MAX 0x1FE0
478 #define HNS3_INT_GL_50K 0x0014
479 #define HNS3_INT_GL_20K 0x0032
480 #define HNS3_INT_GL_18K 0x0036
481 #define HNS3_INT_GL_8K 0x007C
483 #define HNS3_INT_RL_MAX 0x00EC
484 #define HNS3_INT_RL_ENABLE_MASK 0x40
486 struct hns3_enet_coalesce
{
489 enum hns3_flow_level_range flow_level
;
492 struct hns3_enet_ring_group
{
493 /* array of pointers to rings */
494 struct hns3_enet_ring
*ring
;
495 u64 total_bytes
; /* total bytes processed this group */
496 u64 total_packets
; /* total packets processed this group */
498 struct hns3_enet_coalesce coal
;
501 struct hns3_enet_tqp_vector
{
502 struct hnae3_handle
*handle
;
503 u8 __iomem
*mask_addr
;
507 u16 idx
; /* index in the TQP vector array per handle. */
509 struct napi_struct napi
;
511 struct hns3_enet_ring_group rx_group
;
512 struct hns3_enet_ring_group tx_group
;
514 cpumask_t affinity_mask
;
515 u16 num_tqps
; /* total number of tqps in TQP vector */
516 struct irq_affinity_notify affinity_notify
;
518 char name
[HNAE3_INT_NAME_LEN
];
520 unsigned long last_jiffies
;
521 } ____cacheline_internodealigned_in_smp
;
523 enum hns3_udp_tnl_type
{
529 struct hns3_udp_tunnel
{
534 struct hns3_nic_priv
{
535 struct hnae3_handle
*ae_handle
;
538 struct net_device
*netdev
;
540 struct hns3_nic_ops ops
;
543 * the cb for nic to manage the ring buffer, the first half of the
544 * array is for tx_ring and vice versa for the second half
546 struct hns3_nic_ring_data
*ring_data
;
547 struct hns3_enet_tqp_vector
*tqp_vector
;
550 /* The most recently read link state */
552 u64 tx_timeout_count
;
556 struct timer_list service_timer
;
558 struct work_struct service_task
;
560 struct notifier_block notifier_block
;
561 /* Vxlan/Geneve information */
562 struct hns3_udp_tunnel udp_tnl
[HNS3_UDP_TNL_MAX
];
563 unsigned long active_vlans
[BITS_TO_LONGS(VLAN_N_VID
)];
564 struct hns3_enet_coalesce tx_coal
;
565 struct hns3_enet_coalesce rx_coal
;
577 struct gre_base_hdr
*gre
;
581 /* the distance between [begin, end) in a ring buffer
582 * note: there is a unuse slot between the begin and the end
584 static inline int ring_dist(struct hns3_enet_ring
*ring
, int begin
, int end
)
586 return (end
- begin
+ ring
->desc_num
) % ring
->desc_num
;
589 static inline int ring_space(struct hns3_enet_ring
*ring
)
591 return ring
->desc_num
-
592 ring_dist(ring
, ring
->next_to_clean
, ring
->next_to_use
) - 1;
595 static inline int is_ring_empty(struct hns3_enet_ring
*ring
)
597 return ring
->next_to_use
== ring
->next_to_clean
;
600 static inline u32
hns3_read_reg(void __iomem
*base
, u32 reg
)
602 return readl(base
+ reg
);
605 static inline void hns3_write_reg(void __iomem
*base
, u32 reg
, u32 value
)
607 u8 __iomem
*reg_addr
= READ_ONCE(base
);
609 writel(value
, reg_addr
+ reg
);
612 static inline bool hns3_dev_ongoing_func_reset(struct hnae3_ae_dev
*ae_dev
)
614 return (ae_dev
&& (ae_dev
->reset_type
== HNAE3_FUNC_RESET
||
615 ae_dev
->reset_type
== HNAE3_FLR_RESET
||
616 ae_dev
->reset_type
== HNAE3_VF_FUNC_RESET
||
617 ae_dev
->reset_type
== HNAE3_VF_FULL_RESET
||
618 ae_dev
->reset_type
== HNAE3_VF_PF_FUNC_RESET
));
621 #define hns3_read_dev(a, reg) \
622 hns3_read_reg((a)->io_base, (reg))
624 static inline bool hns3_nic_resetting(struct net_device
*netdev
)
626 struct hns3_nic_priv
*priv
= netdev_priv(netdev
);
628 return test_bit(HNS3_NIC_STATE_RESETTING
, &priv
->state
);
631 #define hns3_write_dev(a, reg, value) \
632 hns3_write_reg((a)->io_base, (reg), (value))
634 #define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
635 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)
637 #define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev)
639 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
640 DMA_TO_DEVICE : DMA_FROM_DEVICE)
642 #define tx_ring_data(priv, idx) ((priv)->ring_data[idx])
644 #define hnae3_buf_size(_ring) ((_ring)->buf_size)
645 #define hnae3_page_order(_ring) (get_order(hnae3_buf_size(_ring)))
646 #define hnae3_page_size(_ring) (PAGE_SIZE << hnae3_page_order(_ring))
648 /* iterator for handling rings in ring group */
649 #define hns3_for_each_ring(pos, head) \
650 for (pos = (head).ring; pos; pos = pos->next)
652 #define hns3_get_handle(ndev) \
653 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
655 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1)
656 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
658 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2)
659 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
661 void hns3_ethtool_set_ops(struct net_device
*netdev
);
662 int hns3_set_channels(struct net_device
*netdev
,
663 struct ethtool_channels
*ch
);
665 void hns3_clean_tx_ring(struct hns3_enet_ring
*ring
);
666 int hns3_init_all_ring(struct hns3_nic_priv
*priv
);
667 int hns3_uninit_all_ring(struct hns3_nic_priv
*priv
);
668 int hns3_nic_reset_all_ring(struct hnae3_handle
*h
);
669 netdev_tx_t
hns3_nic_net_xmit(struct sk_buff
*skb
, struct net_device
*netdev
);
670 int hns3_clean_rx_ring(
671 struct hns3_enet_ring
*ring
, int budget
,
672 void (*rx_fn
)(struct hns3_enet_ring
*, struct sk_buff
*));
674 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector
*tqp_vector
,
676 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector
*tqp_vector
,
678 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector
*tqp_vector
,
681 void hns3_enable_vlan_filter(struct net_device
*netdev
, bool enable
);
682 int hns3_update_promisc_mode(struct net_device
*netdev
, u8 promisc_flags
);
684 #ifdef CONFIG_HNS3_DCB
685 void hns3_dcbnl_setup(struct hnae3_handle
*handle
);
687 static inline void hns3_dcbnl_setup(struct hnae3_handle
*handle
) {}
690 void hns3_dbg_init(struct hnae3_handle
*handle
);
691 void hns3_dbg_uninit(struct hnae3_handle
*handle
);
692 void hns3_dbg_register_debugfs(const char *debugfs_dir_name
);
693 void hns3_dbg_unregister_debugfs(void);