drivers/net/ethernet/mediatek/mtk_eth_soc.h

   1 /*   This program is free software; you can redistribute it and/or modify
   2  *   it under the terms of the GNU General Public License as published by
   3  *   the Free Software Foundation; version 2 of the License
   4  *
   5  *   This program is distributed in the hope that it will be useful,
   6  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   7  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8  *   GNU General Public License for more details.
   9  *
  10  *   Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
  11  *   Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
  12  *   Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
  13  */
  14
  15 #ifndef MTK_ETH_H
  16 #define MTK_ETH_H
  17
  18 #define MTK_QDMA_PAGE_SIZE      2048
  19 #define MTK_MAX_RX_LENGTH       1536
  20 #define MTK_TX_DMA_BUF_LEN      0x3fff
  21 #define MTK_DMA_SIZE            256
  22 #define MTK_NAPI_WEIGHT         64
  23 #define MTK_MAC_COUNT           2
  24 #define MTK_RX_ETH_HLEN         (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
  25 #define MTK_RX_HLEN             (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
  26 #define MTK_DMA_DUMMY_DESC      0xffffffff
  27 #define MTK_DEFAULT_MSG_ENABLE  (NETIF_MSG_DRV | \
  28                                  NETIF_MSG_PROBE | \
  29                                  NETIF_MSG_LINK | \
  30                                  NETIF_MSG_TIMER | \
  31                                  NETIF_MSG_IFDOWN | \
  32                                  NETIF_MSG_IFUP | \
  33                                  NETIF_MSG_RX_ERR | \
  34                                  NETIF_MSG_TX_ERR)
  35 #define MTK_HW_FEATURES         (NETIF_F_IP_CSUM | \
  36                                  NETIF_F_RXCSUM | \
  37                                  NETIF_F_HW_VLAN_CTAG_TX | \
  38                                  NETIF_F_HW_VLAN_CTAG_RX | \
  39                                  NETIF_F_SG | NETIF_F_TSO | \
  40                                  NETIF_F_TSO6 | \
  41                                  NETIF_F_IPV6_CSUM)
  42 #define NEXT_RX_DESP_IDX(X, Y)  (((X) + 1) & ((Y) - 1))
  43
  44 #define MTK_MAX_RX_RING_NUM     4
  45 #define MTK_HW_LRO_DMA_SIZE     8
  46
  47 #define MTK_MAX_LRO_RX_LENGTH           (4096 * 3)
  48 #define MTK_MAX_LRO_IP_CNT              2
  49 #define MTK_HW_LRO_TIMER_UNIT           1       /* 20 us */
  50 #define MTK_HW_LRO_REFRESH_TIME         50000   /* 1 sec. */
  51 #define MTK_HW_LRO_AGG_TIME             10      /* 200us */
  52 #define MTK_HW_LRO_AGE_TIME             50      /* 1ms */
  53 #define MTK_HW_LRO_MAX_AGG_CNT          64
  54 #define MTK_HW_LRO_BW_THRE              3000
  55 #define MTK_HW_LRO_REPLACE_DELTA        1000
  56 #define MTK_HW_LRO_SDL_REMAIN_ROOM      1522
  57
  58 /* Frame Engine Global Reset Register */
  59 #define MTK_RST_GL              0x04
  60 #define RST_GL_PSE              BIT(0)
  61
  62 /* Frame Engine Interrupt Status Register */
  63 #define MTK_INT_STATUS2         0x08
  64 #define MTK_GDM1_AF             BIT(28)
  65 #define MTK_GDM2_AF             BIT(29)
  66
  67 /* PDMA HW LRO Alter Flow Timer Register */
  68 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER  0x1c
  69
  70 /* Frame Engine Interrupt Grouping Register */
  71 #define MTK_FE_INT_GRP          0x20
  72
  73 /* CDMP Exgress Control Register */
  74 #define MTK_CDMP_EG_CTRL        0x404
  75
  76 /* GDM Exgress Control Register */
  77 #define MTK_GDMA_FWD_CFG(x)     (0x500 + (x * 0x1000))
  78 #define MTK_GDMA_ICS_EN         BIT(22)
  79 #define MTK_GDMA_TCS_EN         BIT(21)
  80 #define MTK_GDMA_UCS_EN         BIT(20)
  81
  82 /* Unicast Filter MAC Address Register - Low */
  83 #define MTK_GDMA_MAC_ADRL(x)    (0x508 + (x * 0x1000))
  84
  85 /* Unicast Filter MAC Address Register - High */
  86 #define MTK_GDMA_MAC_ADRH(x)    (0x50C + (x * 0x1000))
  87
  88 /* PDMA RX Base Pointer Register */
  89 #define MTK_PRX_BASE_PTR0       0x900
  90 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
  91
  92 /* PDMA RX Maximum Count Register */
  93 #define MTK_PRX_MAX_CNT0        0x904
  94 #define MTK_PRX_MAX_CNT_CFG(x)  (MTK_PRX_MAX_CNT0 + (x * 0x10))
  95
  96 /* PDMA RX CPU Pointer Register */
  97 #define MTK_PRX_CRX_IDX0        0x908
  98 #define MTK_PRX_CRX_IDX_CFG(x)  (MTK_PRX_CRX_IDX0 + (x * 0x10))
  99
 100 /* PDMA HW LRO Control Registers */
 101 #define MTK_PDMA_LRO_CTRL_DW0   0x980
 102 #define MTK_LRO_EN                      BIT(0)
 103 #define MTK_L3_CKS_UPD_EN               BIT(7)
 104 #define MTK_LRO_ALT_PKT_CNT_MODE        BIT(21)
 105 #define MTK_LRO_RING_RELINQUISH_REQ     (0x7 << 26)
 106 #define MTK_LRO_RING_RELINQUISH_DONE    (0x7 << 29)
 107
 108 #define MTK_PDMA_LRO_CTRL_DW1   0x984
 109 #define MTK_PDMA_LRO_CTRL_DW2   0x988
 110 #define MTK_PDMA_LRO_CTRL_DW3   0x98c
 111 #define MTK_ADMA_MODE           BIT(15)
 112 #define MTK_LRO_MIN_RXD_SDL     (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
 113
 114 /* PDMA Global Configuration Register */
 115 #define MTK_PDMA_GLO_CFG        0xa04
 116 #define MTK_MULTI_EN            BIT(10)
 117
 118 /* PDMA Reset Index Register */
 119 #define MTK_PDMA_RST_IDX        0xa08
 120 #define MTK_PST_DRX_IDX0        BIT(16)
 121 #define MTK_PST_DRX_IDX_CFG(x)  (MTK_PST_DRX_IDX0 << (x))
 122
 123 /* PDMA Delay Interrupt Register */
 124 #define MTK_PDMA_DELAY_INT      0xa0c
 125
 126 /* PDMA Interrupt Status Register */
 127 #define MTK_PDMA_INT_STATUS     0xa20
 128
 129 /* PDMA Interrupt Mask Register */
 130 #define MTK_PDMA_INT_MASK       0xa28
 131
 132 /* PDMA HW LRO Alter Flow Delta Register */
 133 #define MTK_PDMA_LRO_ALT_SCORE_DELTA    0xa4c
 134
 135 /* PDMA Interrupt grouping registers */
 136 #define MTK_PDMA_INT_GRP1       0xa50
 137 #define MTK_PDMA_INT_GRP2       0xa54
 138
 139 /* PDMA HW LRO IP Setting Registers */
 140 #define MTK_LRO_RX_RING0_DIP_DW0        0xb04
 141 #define MTK_LRO_DIP_DW0_CFG(x)          (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
 142 #define MTK_RING_MYIP_VLD               BIT(9)
 143
 144 /* PDMA HW LRO Ring Control Registers */
 145 #define MTK_LRO_RX_RING0_CTRL_DW1       0xb28
 146 #define MTK_LRO_RX_RING0_CTRL_DW2       0xb2c
 147 #define MTK_LRO_RX_RING0_CTRL_DW3       0xb30
 148 #define MTK_LRO_CTRL_DW1_CFG(x)         (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
 149 #define MTK_LRO_CTRL_DW2_CFG(x)         (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
 150 #define MTK_LRO_CTRL_DW3_CFG(x)         (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
 151 #define MTK_RING_AGE_TIME_L             ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
 152 #define MTK_RING_AGE_TIME_H             ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
 153 #define MTK_RING_AUTO_LERAN_MODE        (3 << 6)
 154 #define MTK_RING_VLD                    BIT(8)
 155 #define MTK_RING_MAX_AGG_TIME           ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
 156 #define MTK_RING_MAX_AGG_CNT_L          ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
 157 #define MTK_RING_MAX_AGG_CNT_H          ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
 158
 159 /* QDMA TX Queue Configuration Registers */
 160 #define MTK_QTX_CFG(x)          (0x1800 + (x * 0x10))
 161 #define QDMA_RES_THRES          4
 162
 163 /* QDMA TX Queue Scheduler Registers */
 164 #define MTK_QTX_SCH(x)          (0x1804 + (x * 0x10))
 165
 166 /* QDMA RX Base Pointer Register */
 167 #define MTK_QRX_BASE_PTR0       0x1900
 168
 169 /* QDMA RX Maximum Count Register */
 170 #define MTK_QRX_MAX_CNT0        0x1904
 171
 172 /* QDMA RX CPU Pointer Register */
 173 #define MTK_QRX_CRX_IDX0        0x1908
 174
 175 /* QDMA RX DMA Pointer Register */
 176 #define MTK_QRX_DRX_IDX0        0x190C
 177
 178 /* QDMA Global Configuration Register */
 179 #define MTK_QDMA_GLO_CFG        0x1A04
 180 #define MTK_RX_2B_OFFSET        BIT(31)
 181 #define MTK_RX_BT_32DWORDS      (3 << 11)
 182 #define MTK_NDP_CO_PRO          BIT(10)
 183 #define MTK_TX_WB_DDONE         BIT(6)
 184 #define MTK_DMA_SIZE_16DWORDS   (2 << 4)
 185 #define MTK_RX_DMA_BUSY         BIT(3)
 186 #define MTK_TX_DMA_BUSY         BIT(1)
 187 #define MTK_RX_DMA_EN           BIT(2)
 188 #define MTK_TX_DMA_EN           BIT(0)
 189 #define MTK_DMA_BUSY_TIMEOUT    HZ
 190
 191 /* QDMA Reset Index Register */
 192 #define MTK_QDMA_RST_IDX        0x1A08
 193
 194 /* QDMA Delay Interrupt Register */
 195 #define MTK_QDMA_DELAY_INT      0x1A0C
 196
 197 /* QDMA Flow Control Register */
 198 #define MTK_QDMA_FC_THRES       0x1A10
 199 #define FC_THRES_DROP_MODE      BIT(20)
 200 #define FC_THRES_DROP_EN        (7 << 16)
 201 #define FC_THRES_MIN            0x4444
 202
 203 /* QDMA Interrupt Status Register */
 204 #define MTK_QMTK_INT_STATUS     0x1A18
 205 #define MTK_RX_DONE_INT3        BIT(19)
 206 #define MTK_RX_DONE_INT2        BIT(18)
 207 #define MTK_RX_DONE_INT1        BIT(17)
 208 #define MTK_RX_DONE_INT0        BIT(16)
 209 #define MTK_TX_DONE_INT3        BIT(3)
 210 #define MTK_TX_DONE_INT2        BIT(2)
 211 #define MTK_TX_DONE_INT1        BIT(1)
 212 #define MTK_TX_DONE_INT0        BIT(0)
 213 #define MTK_RX_DONE_INT         (MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1 | \
 214                                  MTK_RX_DONE_INT2 | MTK_RX_DONE_INT3)
 215 #define MTK_TX_DONE_INT         (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
 216                                  MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
 217
 218 /* QDMA Interrupt grouping registers */
 219 #define MTK_QDMA_INT_GRP1       0x1a20
 220 #define MTK_QDMA_INT_GRP2       0x1a24
 221 #define MTK_RLS_DONE_INT        BIT(0)
 222
 223 /* QDMA Interrupt Status Register */
 224 #define MTK_QDMA_INT_MASK       0x1A1C
 225
 226 /* QDMA Interrupt Mask Register */
 227 #define MTK_QDMA_HRED2          0x1A44
 228
 229 /* QDMA TX Forward CPU Pointer Register */
 230 #define MTK_QTX_CTX_PTR         0x1B00
 231
 232 /* QDMA TX Forward DMA Pointer Register */
 233 #define MTK_QTX_DTX_PTR         0x1B04
 234
 235 /* QDMA TX Release CPU Pointer Register */
 236 #define MTK_QTX_CRX_PTR         0x1B10
 237
 238 /* QDMA TX Release DMA Pointer Register */
 239 #define MTK_QTX_DRX_PTR         0x1B14
 240
 241 /* QDMA FQ Head Pointer Register */
 242 #define MTK_QDMA_FQ_HEAD        0x1B20
 243
 244 /* QDMA FQ Head Pointer Register */
 245 #define MTK_QDMA_FQ_TAIL        0x1B24
 246
 247 /* QDMA FQ Free Page Counter Register */
 248 #define MTK_QDMA_FQ_CNT         0x1B28
 249
 250 /* QDMA FQ Free Page Buffer Length Register */
 251 #define MTK_QDMA_FQ_BLEN        0x1B2C
 252
 253 /* GMA1 Received Good Byte Count Register */
 254 #define MTK_GDM1_TX_GBCNT       0x2400
 255 #define MTK_STAT_OFFSET         0x40
 256
 257 /* QDMA descriptor txd4 */
 258 #define TX_DMA_CHKSUM           (0x7 << 29)
 259 #define TX_DMA_TSO              BIT(28)
 260 #define TX_DMA_FPORT_SHIFT      25
 261 #define TX_DMA_FPORT_MASK       0x7
 262 #define TX_DMA_INS_VLAN         BIT(16)
 263
 264 /* QDMA descriptor txd3 */
 265 #define TX_DMA_OWNER_CPU        BIT(31)
 266 #define TX_DMA_LS0              BIT(30)
 267 #define TX_DMA_PLEN0(_x)        (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
 268 #define TX_DMA_SWC              BIT(14)
 269 #define TX_DMA_SDL(_x)          (((_x) & 0x3fff) << 16)
 270
 271 /* QDMA descriptor rxd2 */
 272 #define RX_DMA_DONE             BIT(31)
 273 #define RX_DMA_PLEN0(_x)        (((_x) & 0x3fff) << 16)
 274 #define RX_DMA_GET_PLEN0(_x)    (((_x) >> 16) & 0x3fff)
 275
 276 /* QDMA descriptor rxd3 */
 277 #define RX_DMA_VID(_x)          ((_x) & 0xfff)
 278
 279 /* QDMA descriptor rxd4 */
 280 #define RX_DMA_L4_VALID         BIT(24)
 281 #define RX_DMA_FPORT_SHIFT      19
 282 #define RX_DMA_FPORT_MASK       0x7
 283
 284 /* PHY Indirect Access Control registers */
 285 #define MTK_PHY_IAC             0x10004
 286 #define PHY_IAC_ACCESS          BIT(31)
 287 #define PHY_IAC_READ            BIT(19)
 288 #define PHY_IAC_WRITE           BIT(18)
 289 #define PHY_IAC_START           BIT(16)
 290 #define PHY_IAC_ADDR_SHIFT      20
 291 #define PHY_IAC_REG_SHIFT       25
 292 #define PHY_IAC_TIMEOUT         HZ
 293
 294 /* Mac control registers */
 295 #define MTK_MAC_MCR(x)          (0x10100 + (x * 0x100))
 296 #define MAC_MCR_MAX_RX_1536     BIT(24)
 297 #define MAC_MCR_IPG_CFG         (BIT(18) | BIT(16))
 298 #define MAC_MCR_FORCE_MODE      BIT(15)
 299 #define MAC_MCR_TX_EN           BIT(14)
 300 #define MAC_MCR_RX_EN           BIT(13)
 301 #define MAC_MCR_BACKOFF_EN      BIT(9)
 302 #define MAC_MCR_BACKPR_EN       BIT(8)
 303 #define MAC_MCR_FORCE_RX_FC     BIT(5)
 304 #define MAC_MCR_FORCE_TX_FC     BIT(4)
 305 #define MAC_MCR_SPEED_1000      BIT(3)
 306 #define MAC_MCR_SPEED_100       BIT(2)
 307 #define MAC_MCR_FORCE_DPX       BIT(1)
 308 #define MAC_MCR_FORCE_LINK      BIT(0)
 309 #define MAC_MCR_FIXED_LINK      (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \
 310                                  MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \
 311                                  MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \
 312                                  MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \
 313                                  MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \
 314                                  MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK)
 315
 316 /* TRGMII RXC control register */
 317 #define TRGMII_RCK_CTRL         0x10300
 318 #define DQSI0(x)                ((x << 0) & GENMASK(6, 0))
 319 #define DQSI1(x)                ((x << 8) & GENMASK(14, 8))
 320 #define RXCTL_DMWTLAT(x)        ((x << 16) & GENMASK(18, 16))
 321 #define RXC_DQSISEL             BIT(30)
 322 #define RCK_CTRL_RGMII_1000     (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
 323 #define RCK_CTRL_RGMII_10_100   RXCTL_DMWTLAT(2)
 324
 325 /* TRGMII RXC control register */
 326 #define TRGMII_TCK_CTRL         0x10340
 327 #define TXCTL_DMWTLAT(x)        ((x << 16) & GENMASK(18, 16))
 328 #define TXC_INV                 BIT(30)
 329 #define TCK_CTRL_RGMII_1000     TXCTL_DMWTLAT(2)
 330 #define TCK_CTRL_RGMII_10_100   (TXC_INV | TXCTL_DMWTLAT(2))
 331
 332 /* TRGMII Interface mode register */
 333 #define INTF_MODE               0x10390
 334 #define TRGMII_INTF_DIS         BIT(0)
 335 #define TRGMII_MODE             BIT(1)
 336 #define TRGMII_CENTRAL_ALIGNED  BIT(2)
 337 #define INTF_MODE_RGMII_1000    (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
 338 #define INTF_MODE_RGMII_10_100  0
 339
 340 /* GPIO port control registers for GMAC 2*/
 341 #define GPIO_OD33_CTRL8         0x4c0
 342 #define GPIO_BIAS_CTRL          0xed0
 343 #define GPIO_DRV_SEL10          0xf00
 344
 345 /* ethernet subsystem chip id register */
 346 #define ETHSYS_CHIPID0_3        0x0
 347 #define ETHSYS_CHIPID4_7        0x4
 348 #define MT7623_ETH              7623
 349
 350 /* ethernet subsystem config register */
 351 #define ETHSYS_SYSCFG0          0x14
 352 #define SYSCFG0_GE_MASK         0x3
 353 #define SYSCFG0_GE_MODE(x, y)   (x << (12 + (y * 2)))
 354
 355 /* ethernet subsystem clock register */
 356 #define ETHSYS_CLKCFG0          0x2c
 357 #define ETHSYS_TRGMII_CLK_SEL362_5      BIT(11)
 358
 359 /* ethernet reset control register */
 360 #define ETHSYS_RSTCTRL          0x34
 361 #define RSTCTRL_FE              BIT(6)
 362 #define RSTCTRL_PPE             BIT(31)
 363
 364 struct mtk_rx_dma {
 365         unsigned int rxd1;
 366         unsigned int rxd2;
 367         unsigned int rxd3;
 368         unsigned int rxd4;
 369 } __packed __aligned(4);
 370
 371 struct mtk_tx_dma {
 372         unsigned int txd1;
 373         unsigned int txd2;
 374         unsigned int txd3;
 375         unsigned int txd4;
 376 } __packed __aligned(4);
 377
 378 struct mtk_eth;
 379 struct mtk_mac;
 380
 381 /* struct mtk_hw_stats - the structure that holds the traffic statistics.
 382  * @stats_lock:         make sure that stats operations are atomic
 383  * @reg_offset:         the status register offset of the SoC
 384  * @syncp:              the refcount
 385  *
 386  * All of the supported SoCs have hardware counters for traffic statistics.
 387  * Whenever the status IRQ triggers we can read the latest stats from these
 388  * counters and store them in this struct.
 389  */
 390 struct mtk_hw_stats {
 391         u64 tx_bytes;
 392         u64 tx_packets;
 393         u64 tx_skip;
 394         u64 tx_collisions;
 395         u64 rx_bytes;
 396         u64 rx_packets;
 397         u64 rx_overflow;
 398         u64 rx_fcs_errors;
 399         u64 rx_short_errors;
 400         u64 rx_long_errors;
 401         u64 rx_checksum_errors;
 402         u64 rx_flow_control_packets;
 403
 404         spinlock_t              stats_lock;
 405         u32                     reg_offset;
 406         struct u64_stats_sync   syncp;
 407 };
 408
 409 /* PDMA descriptor can point at 1-2 segments. This enum allows us to track how
 410  * memory was allocated so that it can be freed properly
 411  */
 412 enum mtk_tx_flags {
 413         MTK_TX_FLAGS_SINGLE0    = 0x01,
 414         MTK_TX_FLAGS_PAGE0      = 0x02,
 415 };
 416
 417 /* This enum allows us to identify how the clock is defined on the array of the
 418  * clock in the order
 419  */
 420 enum mtk_clks_map {
 421         MTK_CLK_ETHIF,
 422         MTK_CLK_ESW,
 423         MTK_CLK_GP1,
 424         MTK_CLK_GP2,
 425         MTK_CLK_TRGPLL,
 426         MTK_CLK_MAX
 427 };
 428
 429 enum mtk_dev_state {
 430         MTK_HW_INIT,
 431         MTK_RESETTING
 432 };
 433
 434 /* struct mtk_tx_buf -  This struct holds the pointers to the memory pointed at
 435  *                      by the TX descriptor    s
 436  * @skb:                The SKB pointer of the packet being sent
 437  * @dma_addr0:          The base addr of the first segment
 438  * @dma_len0:           The length of the first segment
 439  * @dma_addr1:          The base addr of the second segment
 440  * @dma_len1:           The length of the second segment
 441  */
 442 struct mtk_tx_buf {
 443         struct sk_buff *skb;
 444         u32 flags;
 445         DEFINE_DMA_UNMAP_ADDR(dma_addr0);
 446         DEFINE_DMA_UNMAP_LEN(dma_len0);
 447         DEFINE_DMA_UNMAP_ADDR(dma_addr1);
 448         DEFINE_DMA_UNMAP_LEN(dma_len1);
 449 };
 450
 451 /* struct mtk_tx_ring - This struct holds info describing a TX ring
 452  * @dma:                The descriptor ring
 453  * @buf:                The memory pointed at by the ring
 454  * @phys:               The physical addr of tx_buf
 455  * @next_free:          Pointer to the next free descriptor
 456  * @last_free:          Pointer to the last free descriptor
 457  * @thresh:             The threshold of minimum amount of free descriptors
 458  * @free_count:         QDMA uses a linked list. Track how many free descriptors
 459  *                      are present
 460  */
 461 struct mtk_tx_ring {
 462         struct mtk_tx_dma *dma;
 463         struct mtk_tx_buf *buf;
 464         dma_addr_t phys;
 465         struct mtk_tx_dma *next_free;
 466         struct mtk_tx_dma *last_free;
 467         u16 thresh;
 468         atomic_t free_count;
 469 };
 470
 471 /* PDMA rx ring mode */
 472 enum mtk_rx_flags {
 473         MTK_RX_FLAGS_NORMAL = 0,
 474         MTK_RX_FLAGS_HWLRO,
 475 };
 476
 477 /* struct mtk_rx_ring - This struct holds info describing a RX ring
 478  * @dma:                The descriptor ring
 479  * @data:               The memory pointed at by the ring
 480  * @phys:               The physical addr of rx_buf
 481  * @frag_size:          How big can each fragment be
 482  * @buf_size:           The size of each packet buffer
 483  * @calc_idx:           The current head of ring
 484  */
 485 struct mtk_rx_ring {
 486         struct mtk_rx_dma *dma;
 487         u8 **data;
 488         dma_addr_t phys;
 489         u16 frag_size;
 490         u16 buf_size;
 491         u16 dma_size;
 492         bool calc_idx_update;
 493         u16 calc_idx;
 494         u32 crx_idx_reg;
 495 };
 496
 497 /* currently no SoC has more than 2 macs */
 498 #define MTK_MAX_DEVS                    2
 499
 500 /* struct mtk_eth -     This is the main datasructure for holding the state
 501  *                      of the driver
 502  * @dev:                The device pointer
 503  * @base:               The mapped register i/o base
 504  * @page_lock:          Make sure that register operations are atomic
 505  * @dummy_dev:          we run 2 netdevs on 1 physical DMA ring and need a
 506  *                      dummy for NAPI to work
 507  * @netdev:             The netdev instances
 508  * @mac:                Each netdev is linked to a physical MAC
 509  * @irq:                The IRQ that we are using
 510  * @msg_enable:         Ethtool msg level
 511  * @ethsys:             The register map pointing at the range used to setup
 512  *                      MII modes
 513  * @pctl:               The register map pointing at the range used to setup
 514  *                      GMAC port drive/slew values
 515  * @dma_refcnt:         track how many netdevs are using the DMA engine
 516  * @tx_ring:            Pointer to the memore holding info about the TX ring
 517  * @rx_ring:            Pointer to the memore holding info about the RX ring
 518  * @tx_napi:            The TX NAPI struct
 519  * @rx_napi:            The RX NAPI struct
 520  * @scratch_ring:       Newer SoCs need memory for a second HW managed TX ring
 521  * @phy_scratch_ring:   physical address of scratch_ring
 522  * @scratch_head:       The scratch memory that scratch_ring points to.
 523  * @clks:               clock array for all clocks required
 524  * @mii_bus:            If there is a bus we need to create an instance for it
 525  * @pending_work:       The workqueue used to reset the dma ring
 526  * @state               Initialization and runtime state of the device.
 527  */
 528
 529 struct mtk_eth {
 530         struct device                   *dev;
 531         void __iomem                    *base;
 532         spinlock_t                      page_lock;
 533         spinlock_t                      irq_lock;
 534         struct net_device               dummy_dev;
 535         struct net_device               *netdev[MTK_MAX_DEVS];
 536         struct mtk_mac                  *mac[MTK_MAX_DEVS];
 537         int                             irq[3];
 538         u32                             msg_enable;
 539         unsigned long                   sysclk;
 540         struct regmap                   *ethsys;
 541         struct regmap                   *pctl;
 542         u32                             chip_id;
 543         bool                            hwlro;
 544         atomic_t                        dma_refcnt;
 545         struct mtk_tx_ring              tx_ring;
 546         struct mtk_rx_ring              rx_ring[MTK_MAX_RX_RING_NUM];
 547         struct napi_struct              tx_napi;
 548         struct napi_struct              rx_napi;
 549         struct mtk_tx_dma               *scratch_ring;
 550         dma_addr_t                      phy_scratch_ring;
 551         void                            *scratch_head;
 552         struct clk                      *clks[MTK_CLK_MAX];
 553
 554         struct mii_bus                  *mii_bus;
 555         struct work_struct              pending_work;
 556         unsigned long                   state;
 557 };
 558
 559 /* struct mtk_mac -     the structure that holds the info about the MACs of the
 560  *                      SoC
 561  * @id:                 The number of the MAC
 562  * @ge_mode:            Interface mode kept for setup restoring
 563  * @of_node:            Our devicetree node
 564  * @hw:                 Backpointer to our main datastruture
 565  * @hw_stats:           Packet statistics counter
 566  * @trgmii              Indicate if the MAC uses TRGMII connected to internal
 567                         switch
 568  */
 569 struct mtk_mac {
 570         int                             id;
 571         int                             ge_mode;
 572         struct device_node              *of_node;
 573         struct mtk_eth                  *hw;
 574         struct mtk_hw_stats             *hw_stats;
 575         __be32                          hwlro_ip[MTK_MAX_LRO_IP_CNT];
 576         int                             hwlro_ip_cnt;
 577         bool                            trgmii;
 578 };
 579
 580 /* the struct describing the SoC. these are declared in the soc_xyz.c files */
 581 extern const struct of_device_id of_mtk_match[];
 582
 583 /* read the hardware status register */
 584 void mtk_stats_update_mac(struct mtk_mac *mac);
 585
 586 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
 587 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
 588
 589 #endif /* MTK_ETH_H */