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Merge tag 'io_uring-5.7-2020-05-22' of git://git.kernel.dk/linux-block
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / cmd.c
1 /*
2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/eq.h>
44 #include <linux/debugfs.h>
45
46 #include "mlx5_core.h"
47 #include "lib/eq.h"
48
49 enum {
50 CMD_IF_REV = 5,
51 };
52
53 enum {
54 CMD_MODE_POLLING,
55 CMD_MODE_EVENTS
56 };
57
58 enum {
59 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
60 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
61 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
62 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
63 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
64 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
65 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
66 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
67 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
68 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
69 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
70 };
71
72 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
73 struct mlx5_cmd_msg *in,
74 struct mlx5_cmd_msg *out,
75 void *uout, int uout_size,
76 mlx5_cmd_cbk_t cbk,
77 void *context, int page_queue)
78 {
79 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
80 struct mlx5_cmd_work_ent *ent;
81
82 ent = kzalloc(sizeof(*ent), alloc_flags);
83 if (!ent)
84 return ERR_PTR(-ENOMEM);
85
86 ent->in = in;
87 ent->out = out;
88 ent->uout = uout;
89 ent->uout_size = uout_size;
90 ent->callback = cbk;
91 ent->context = context;
92 ent->cmd = cmd;
93 ent->page_queue = page_queue;
94
95 return ent;
96 }
97
98 static u8 alloc_token(struct mlx5_cmd *cmd)
99 {
100 u8 token;
101
102 spin_lock(&cmd->token_lock);
103 cmd->token++;
104 if (cmd->token == 0)
105 cmd->token++;
106 token = cmd->token;
107 spin_unlock(&cmd->token_lock);
108
109 return token;
110 }
111
112 static int alloc_ent(struct mlx5_cmd *cmd)
113 {
114 unsigned long flags;
115 int ret;
116
117 spin_lock_irqsave(&cmd->alloc_lock, flags);
118 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
119 if (ret < cmd->max_reg_cmds)
120 clear_bit(ret, &cmd->bitmask);
121 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
122
123 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
124 }
125
126 static void free_ent(struct mlx5_cmd *cmd, int idx)
127 {
128 unsigned long flags;
129
130 spin_lock_irqsave(&cmd->alloc_lock, flags);
131 set_bit(idx, &cmd->bitmask);
132 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
133 }
134
135 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
136 {
137 return cmd->cmd_buf + (idx << cmd->log_stride);
138 }
139
140 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
141 {
142 int size = msg->len;
143 int blen = size - min_t(int, sizeof(msg->first.data), size);
144
145 return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
146 }
147
148 static u8 xor8_buf(void *buf, size_t offset, int len)
149 {
150 u8 *ptr = buf;
151 u8 sum = 0;
152 int i;
153 int end = len + offset;
154
155 for (i = offset; i < end; i++)
156 sum ^= ptr[i];
157
158 return sum;
159 }
160
161 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
162 {
163 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
164 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
165
166 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
167 return -EINVAL;
168
169 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
170 return -EINVAL;
171
172 return 0;
173 }
174
175 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
176 {
177 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
178 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
179
180 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
181 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
182 }
183
184 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
185 {
186 struct mlx5_cmd_mailbox *next = msg->next;
187 int n = mlx5_calc_cmd_blocks(msg);
188 int i = 0;
189
190 for (i = 0; i < n && next; i++) {
191 calc_block_sig(next->buf);
192 next = next->next;
193 }
194 }
195
196 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
197 {
198 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
199 if (csum) {
200 calc_chain_sig(ent->in);
201 calc_chain_sig(ent->out);
202 }
203 }
204
205 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
206 {
207 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
208 u8 own;
209
210 do {
211 own = READ_ONCE(ent->lay->status_own);
212 if (!(own & CMD_OWNER_HW)) {
213 ent->ret = 0;
214 return;
215 }
216 cond_resched();
217 } while (time_before(jiffies, poll_end));
218
219 ent->ret = -ETIMEDOUT;
220 }
221
222 static void free_cmd(struct mlx5_cmd_work_ent *ent)
223 {
224 kfree(ent);
225 }
226
227 static int verify_signature(struct mlx5_cmd_work_ent *ent)
228 {
229 struct mlx5_cmd_mailbox *next = ent->out->next;
230 int n = mlx5_calc_cmd_blocks(ent->out);
231 int err;
232 u8 sig;
233 int i = 0;
234
235 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
236 if (sig != 0xff)
237 return -EINVAL;
238
239 for (i = 0; i < n && next; i++) {
240 err = verify_block_sig(next->buf);
241 if (err)
242 return err;
243
244 next = next->next;
245 }
246
247 return 0;
248 }
249
250 static void dump_buf(void *buf, int size, int data_only, int offset)
251 {
252 __be32 *p = buf;
253 int i;
254
255 for (i = 0; i < size; i += 16) {
256 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
257 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
258 be32_to_cpu(p[3]));
259 p += 4;
260 offset += 16;
261 }
262 if (!data_only)
263 pr_debug("\n");
264 }
265
266 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
267 u32 *synd, u8 *status)
268 {
269 *synd = 0;
270 *status = 0;
271
272 switch (op) {
273 case MLX5_CMD_OP_TEARDOWN_HCA:
274 case MLX5_CMD_OP_DISABLE_HCA:
275 case MLX5_CMD_OP_MANAGE_PAGES:
276 case MLX5_CMD_OP_DESTROY_MKEY:
277 case MLX5_CMD_OP_DESTROY_EQ:
278 case MLX5_CMD_OP_DESTROY_CQ:
279 case MLX5_CMD_OP_DESTROY_QP:
280 case MLX5_CMD_OP_DESTROY_PSV:
281 case MLX5_CMD_OP_DESTROY_SRQ:
282 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
283 case MLX5_CMD_OP_DESTROY_XRQ:
284 case MLX5_CMD_OP_DESTROY_DCT:
285 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
286 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
287 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
288 case MLX5_CMD_OP_DEALLOC_PD:
289 case MLX5_CMD_OP_DEALLOC_UAR:
290 case MLX5_CMD_OP_DETACH_FROM_MCG:
291 case MLX5_CMD_OP_DEALLOC_XRCD:
292 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
293 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
294 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
295 case MLX5_CMD_OP_DESTROY_LAG:
296 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
297 case MLX5_CMD_OP_DESTROY_TIR:
298 case MLX5_CMD_OP_DESTROY_SQ:
299 case MLX5_CMD_OP_DESTROY_RQ:
300 case MLX5_CMD_OP_DESTROY_RMP:
301 case MLX5_CMD_OP_DESTROY_TIS:
302 case MLX5_CMD_OP_DESTROY_RQT:
303 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
304 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
305 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
306 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
307 case MLX5_CMD_OP_2ERR_QP:
308 case MLX5_CMD_OP_2RST_QP:
309 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
310 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
311 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
312 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
313 case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT:
314 case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
315 case MLX5_CMD_OP_FPGA_DESTROY_QP:
316 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
317 case MLX5_CMD_OP_DEALLOC_MEMIC:
318 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
319 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
320 return MLX5_CMD_STAT_OK;
321
322 case MLX5_CMD_OP_QUERY_HCA_CAP:
323 case MLX5_CMD_OP_QUERY_ADAPTER:
324 case MLX5_CMD_OP_INIT_HCA:
325 case MLX5_CMD_OP_ENABLE_HCA:
326 case MLX5_CMD_OP_QUERY_PAGES:
327 case MLX5_CMD_OP_SET_HCA_CAP:
328 case MLX5_CMD_OP_QUERY_ISSI:
329 case MLX5_CMD_OP_SET_ISSI:
330 case MLX5_CMD_OP_CREATE_MKEY:
331 case MLX5_CMD_OP_QUERY_MKEY:
332 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
333 case MLX5_CMD_OP_CREATE_EQ:
334 case MLX5_CMD_OP_QUERY_EQ:
335 case MLX5_CMD_OP_GEN_EQE:
336 case MLX5_CMD_OP_CREATE_CQ:
337 case MLX5_CMD_OP_QUERY_CQ:
338 case MLX5_CMD_OP_MODIFY_CQ:
339 case MLX5_CMD_OP_CREATE_QP:
340 case MLX5_CMD_OP_RST2INIT_QP:
341 case MLX5_CMD_OP_INIT2RTR_QP:
342 case MLX5_CMD_OP_RTR2RTS_QP:
343 case MLX5_CMD_OP_RTS2RTS_QP:
344 case MLX5_CMD_OP_SQERR2RTS_QP:
345 case MLX5_CMD_OP_QUERY_QP:
346 case MLX5_CMD_OP_SQD_RTS_QP:
347 case MLX5_CMD_OP_INIT2INIT_QP:
348 case MLX5_CMD_OP_CREATE_PSV:
349 case MLX5_CMD_OP_CREATE_SRQ:
350 case MLX5_CMD_OP_QUERY_SRQ:
351 case MLX5_CMD_OP_ARM_RQ:
352 case MLX5_CMD_OP_CREATE_XRC_SRQ:
353 case MLX5_CMD_OP_QUERY_XRC_SRQ:
354 case MLX5_CMD_OP_ARM_XRC_SRQ:
355 case MLX5_CMD_OP_CREATE_XRQ:
356 case MLX5_CMD_OP_QUERY_XRQ:
357 case MLX5_CMD_OP_ARM_XRQ:
358 case MLX5_CMD_OP_CREATE_DCT:
359 case MLX5_CMD_OP_DRAIN_DCT:
360 case MLX5_CMD_OP_QUERY_DCT:
361 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
362 case MLX5_CMD_OP_QUERY_VPORT_STATE:
363 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
364 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
365 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
366 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
367 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
368 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
369 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
370 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
371 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
372 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
373 case MLX5_CMD_OP_QUERY_VNIC_ENV:
374 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
375 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
376 case MLX5_CMD_OP_QUERY_Q_COUNTER:
377 case MLX5_CMD_OP_SET_MONITOR_COUNTER:
378 case MLX5_CMD_OP_ARM_MONITOR_COUNTER:
379 case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
380 case MLX5_CMD_OP_QUERY_RATE_LIMIT:
381 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
382 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
383 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
384 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
385 case MLX5_CMD_OP_ALLOC_PD:
386 case MLX5_CMD_OP_ALLOC_UAR:
387 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
388 case MLX5_CMD_OP_ACCESS_REG:
389 case MLX5_CMD_OP_ATTACH_TO_MCG:
390 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
391 case MLX5_CMD_OP_MAD_IFC:
392 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
393 case MLX5_CMD_OP_SET_MAD_DEMUX:
394 case MLX5_CMD_OP_NOP:
395 case MLX5_CMD_OP_ALLOC_XRCD:
396 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
397 case MLX5_CMD_OP_QUERY_CONG_STATUS:
398 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
399 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
400 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
401 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
402 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
403 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
404 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
405 case MLX5_CMD_OP_CREATE_LAG:
406 case MLX5_CMD_OP_MODIFY_LAG:
407 case MLX5_CMD_OP_QUERY_LAG:
408 case MLX5_CMD_OP_CREATE_VPORT_LAG:
409 case MLX5_CMD_OP_CREATE_TIR:
410 case MLX5_CMD_OP_MODIFY_TIR:
411 case MLX5_CMD_OP_QUERY_TIR:
412 case MLX5_CMD_OP_CREATE_SQ:
413 case MLX5_CMD_OP_MODIFY_SQ:
414 case MLX5_CMD_OP_QUERY_SQ:
415 case MLX5_CMD_OP_CREATE_RQ:
416 case MLX5_CMD_OP_MODIFY_RQ:
417 case MLX5_CMD_OP_QUERY_RQ:
418 case MLX5_CMD_OP_CREATE_RMP:
419 case MLX5_CMD_OP_MODIFY_RMP:
420 case MLX5_CMD_OP_QUERY_RMP:
421 case MLX5_CMD_OP_CREATE_TIS:
422 case MLX5_CMD_OP_MODIFY_TIS:
423 case MLX5_CMD_OP_QUERY_TIS:
424 case MLX5_CMD_OP_CREATE_RQT:
425 case MLX5_CMD_OP_MODIFY_RQT:
426 case MLX5_CMD_OP_QUERY_RQT:
427
428 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
429 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
430 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
431 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
432 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
433 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
434 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
435 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
436 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
437 case MLX5_CMD_OP_FPGA_CREATE_QP:
438 case MLX5_CMD_OP_FPGA_MODIFY_QP:
439 case MLX5_CMD_OP_FPGA_QUERY_QP:
440 case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
441 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
442 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
443 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
444 case MLX5_CMD_OP_CREATE_UCTX:
445 case MLX5_CMD_OP_DESTROY_UCTX:
446 case MLX5_CMD_OP_CREATE_UMEM:
447 case MLX5_CMD_OP_DESTROY_UMEM:
448 case MLX5_CMD_OP_ALLOC_MEMIC:
449 case MLX5_CMD_OP_MODIFY_XRQ:
450 case MLX5_CMD_OP_RELEASE_XRQ_ERROR:
451 *status = MLX5_DRIVER_STATUS_ABORTED;
452 *synd = MLX5_DRIVER_SYND;
453 return -EIO;
454 default:
455 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
456 return -EINVAL;
457 }
458 }
459
460 const char *mlx5_command_str(int command)
461 {
462 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
463
464 switch (command) {
465 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
466 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
467 MLX5_COMMAND_STR_CASE(INIT_HCA);
468 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
469 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
470 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
471 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
472 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
473 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
474 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
475 MLX5_COMMAND_STR_CASE(SET_ISSI);
476 MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
477 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
478 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
479 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
480 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
481 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
482 MLX5_COMMAND_STR_CASE(CREATE_EQ);
483 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
484 MLX5_COMMAND_STR_CASE(QUERY_EQ);
485 MLX5_COMMAND_STR_CASE(GEN_EQE);
486 MLX5_COMMAND_STR_CASE(CREATE_CQ);
487 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
488 MLX5_COMMAND_STR_CASE(QUERY_CQ);
489 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
490 MLX5_COMMAND_STR_CASE(CREATE_QP);
491 MLX5_COMMAND_STR_CASE(DESTROY_QP);
492 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
493 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
494 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
495 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
496 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
497 MLX5_COMMAND_STR_CASE(2ERR_QP);
498 MLX5_COMMAND_STR_CASE(2RST_QP);
499 MLX5_COMMAND_STR_CASE(QUERY_QP);
500 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
501 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
502 MLX5_COMMAND_STR_CASE(CREATE_PSV);
503 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
504 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
505 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
506 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
507 MLX5_COMMAND_STR_CASE(ARM_RQ);
508 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
509 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
510 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
511 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
512 MLX5_COMMAND_STR_CASE(CREATE_DCT);
513 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
514 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
515 MLX5_COMMAND_STR_CASE(QUERY_DCT);
516 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
517 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
518 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
519 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
520 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
521 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
522 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
523 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
524 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
525 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
526 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
527 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
528 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
529 MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
530 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
531 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
532 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
533 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
534 MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER);
535 MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER);
536 MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
537 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
538 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
539 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
540 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
541 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
542 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
543 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
544 MLX5_COMMAND_STR_CASE(ALLOC_PD);
545 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
546 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
547 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
548 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
549 MLX5_COMMAND_STR_CASE(ACCESS_REG);
550 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
551 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
552 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
553 MLX5_COMMAND_STR_CASE(MAD_IFC);
554 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
555 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
556 MLX5_COMMAND_STR_CASE(NOP);
557 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
558 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
559 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
560 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
561 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
562 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
563 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
564 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
565 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
566 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
567 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
568 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
569 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
570 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
571 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
572 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
573 MLX5_COMMAND_STR_CASE(CREATE_LAG);
574 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
575 MLX5_COMMAND_STR_CASE(QUERY_LAG);
576 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
577 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
578 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
579 MLX5_COMMAND_STR_CASE(CREATE_TIR);
580 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
581 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
582 MLX5_COMMAND_STR_CASE(QUERY_TIR);
583 MLX5_COMMAND_STR_CASE(CREATE_SQ);
584 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
585 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
586 MLX5_COMMAND_STR_CASE(QUERY_SQ);
587 MLX5_COMMAND_STR_CASE(CREATE_RQ);
588 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
589 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
590 MLX5_COMMAND_STR_CASE(QUERY_RQ);
591 MLX5_COMMAND_STR_CASE(CREATE_RMP);
592 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
593 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
594 MLX5_COMMAND_STR_CASE(QUERY_RMP);
595 MLX5_COMMAND_STR_CASE(CREATE_TIS);
596 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
597 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
598 MLX5_COMMAND_STR_CASE(QUERY_TIS);
599 MLX5_COMMAND_STR_CASE(CREATE_RQT);
600 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
601 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
602 MLX5_COMMAND_STR_CASE(QUERY_RQT);
603 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
604 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
605 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
606 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
607 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
608 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
609 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
610 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
611 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
612 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
613 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
614 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
615 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
616 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
617 MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT);
618 MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT);
619 MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
620 MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
621 MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
622 MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
623 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
624 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
625 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
626 MLX5_COMMAND_STR_CASE(CREATE_XRQ);
627 MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
628 MLX5_COMMAND_STR_CASE(QUERY_XRQ);
629 MLX5_COMMAND_STR_CASE(ARM_XRQ);
630 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
631 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
632 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
633 MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
634 MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
635 MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
636 MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
637 MLX5_COMMAND_STR_CASE(QUERY_ESW_FUNCTIONS);
638 MLX5_COMMAND_STR_CASE(CREATE_UCTX);
639 MLX5_COMMAND_STR_CASE(DESTROY_UCTX);
640 MLX5_COMMAND_STR_CASE(CREATE_UMEM);
641 MLX5_COMMAND_STR_CASE(DESTROY_UMEM);
642 MLX5_COMMAND_STR_CASE(RELEASE_XRQ_ERROR);
643 MLX5_COMMAND_STR_CASE(MODIFY_XRQ);
644 default: return "unknown command opcode";
645 }
646 }
647
648 static const char *cmd_status_str(u8 status)
649 {
650 switch (status) {
651 case MLX5_CMD_STAT_OK:
652 return "OK";
653 case MLX5_CMD_STAT_INT_ERR:
654 return "internal error";
655 case MLX5_CMD_STAT_BAD_OP_ERR:
656 return "bad operation";
657 case MLX5_CMD_STAT_BAD_PARAM_ERR:
658 return "bad parameter";
659 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
660 return "bad system state";
661 case MLX5_CMD_STAT_BAD_RES_ERR:
662 return "bad resource";
663 case MLX5_CMD_STAT_RES_BUSY:
664 return "resource busy";
665 case MLX5_CMD_STAT_LIM_ERR:
666 return "limits exceeded";
667 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
668 return "bad resource state";
669 case MLX5_CMD_STAT_IX_ERR:
670 return "bad index";
671 case MLX5_CMD_STAT_NO_RES_ERR:
672 return "no resources";
673 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
674 return "bad input length";
675 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
676 return "bad output length";
677 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
678 return "bad QP state";
679 case MLX5_CMD_STAT_BAD_PKT_ERR:
680 return "bad packet (discarded)";
681 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
682 return "bad size too many outstanding CQEs";
683 default:
684 return "unknown status";
685 }
686 }
687
688 static int cmd_status_to_err(u8 status)
689 {
690 switch (status) {
691 case MLX5_CMD_STAT_OK: return 0;
692 case MLX5_CMD_STAT_INT_ERR: return -EIO;
693 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
694 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
695 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
696 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
697 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
698 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
699 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
700 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
701 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
702 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
703 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
704 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
705 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
706 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
707 default: return -EIO;
708 }
709 }
710
711 struct mlx5_ifc_mbox_out_bits {
712 u8 status[0x8];
713 u8 reserved_at_8[0x18];
714
715 u8 syndrome[0x20];
716
717 u8 reserved_at_40[0x40];
718 };
719
720 struct mlx5_ifc_mbox_in_bits {
721 u8 opcode[0x10];
722 u8 uid[0x10];
723
724 u8 reserved_at_20[0x10];
725 u8 op_mod[0x10];
726
727 u8 reserved_at_40[0x40];
728 };
729
730 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
731 {
732 *status = MLX5_GET(mbox_out, out, status);
733 *syndrome = MLX5_GET(mbox_out, out, syndrome);
734 }
735
736 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
737 {
738 u32 syndrome;
739 u8 status;
740 u16 opcode;
741 u16 op_mod;
742 u16 uid;
743
744 mlx5_cmd_mbox_status(out, &status, &syndrome);
745 if (!status)
746 return 0;
747
748 opcode = MLX5_GET(mbox_in, in, opcode);
749 op_mod = MLX5_GET(mbox_in, in, op_mod);
750 uid = MLX5_GET(mbox_in, in, uid);
751
752 if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
753 mlx5_core_err_rl(dev,
754 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
755 mlx5_command_str(opcode), opcode, op_mod,
756 cmd_status_str(status), status, syndrome);
757 else
758 mlx5_core_dbg(dev,
759 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
760 mlx5_command_str(opcode),
761 opcode, op_mod,
762 cmd_status_str(status),
763 status,
764 syndrome);
765
766 return cmd_status_to_err(status);
767 }
768
769 static void dump_command(struct mlx5_core_dev *dev,
770 struct mlx5_cmd_work_ent *ent, int input)
771 {
772 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
773 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
774 struct mlx5_cmd_mailbox *next = msg->next;
775 int n = mlx5_calc_cmd_blocks(msg);
776 int data_only;
777 u32 offset = 0;
778 int dump_len;
779 int i;
780
781 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
782
783 if (data_only)
784 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
785 "dump command data %s(0x%x) %s\n",
786 mlx5_command_str(op), op,
787 input ? "INPUT" : "OUTPUT");
788 else
789 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
790 mlx5_command_str(op), op,
791 input ? "INPUT" : "OUTPUT");
792
793 if (data_only) {
794 if (input) {
795 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
796 offset += sizeof(ent->lay->in);
797 } else {
798 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
799 offset += sizeof(ent->lay->out);
800 }
801 } else {
802 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
803 offset += sizeof(*ent->lay);
804 }
805
806 for (i = 0; i < n && next; i++) {
807 if (data_only) {
808 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
809 dump_buf(next->buf, dump_len, 1, offset);
810 offset += MLX5_CMD_DATA_BLOCK_SIZE;
811 } else {
812 mlx5_core_dbg(dev, "command block:\n");
813 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
814 offset += sizeof(struct mlx5_cmd_prot_block);
815 }
816 next = next->next;
817 }
818
819 if (data_only)
820 pr_debug("\n");
821 }
822
823 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
824 {
825 return MLX5_GET(mbox_in, in->first.data, opcode);
826 }
827
828 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
829
830 static void cb_timeout_handler(struct work_struct *work)
831 {
832 struct delayed_work *dwork = container_of(work, struct delayed_work,
833 work);
834 struct mlx5_cmd_work_ent *ent = container_of(dwork,
835 struct mlx5_cmd_work_ent,
836 cb_timeout_work);
837 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
838 cmd);
839
840 ent->ret = -ETIMEDOUT;
841 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
842 mlx5_command_str(msg_to_opcode(ent->in)),
843 msg_to_opcode(ent->in));
844 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
845 }
846
847 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
848 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
849 struct mlx5_cmd_msg *msg);
850
851 static void cmd_work_handler(struct work_struct *work)
852 {
853 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
854 struct mlx5_cmd *cmd = ent->cmd;
855 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
856 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
857 struct mlx5_cmd_layout *lay;
858 struct semaphore *sem;
859 unsigned long flags;
860 bool poll_cmd = ent->polling;
861 int alloc_ret;
862 int cmd_mode;
863
864 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
865 down(sem);
866 if (!ent->page_queue) {
867 alloc_ret = alloc_ent(cmd);
868 if (alloc_ret < 0) {
869 mlx5_core_err_rl(dev, "failed to allocate command entry\n");
870 if (ent->callback) {
871 ent->callback(-EAGAIN, ent->context);
872 mlx5_free_cmd_msg(dev, ent->out);
873 free_msg(dev, ent->in);
874 free_cmd(ent);
875 } else {
876 ent->ret = -EAGAIN;
877 complete(&ent->done);
878 }
879 up(sem);
880 return;
881 }
882 ent->idx = alloc_ret;
883 } else {
884 ent->idx = cmd->max_reg_cmds;
885 spin_lock_irqsave(&cmd->alloc_lock, flags);
886 clear_bit(ent->idx, &cmd->bitmask);
887 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
888 }
889
890 cmd->ent_arr[ent->idx] = ent;
891 lay = get_inst(cmd, ent->idx);
892 ent->lay = lay;
893 memset(lay, 0, sizeof(*lay));
894 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
895 ent->op = be32_to_cpu(lay->in[0]) >> 16;
896 if (ent->in->next)
897 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
898 lay->inlen = cpu_to_be32(ent->in->len);
899 if (ent->out->next)
900 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
901 lay->outlen = cpu_to_be32(ent->out->len);
902 lay->type = MLX5_PCI_CMD_XPORT;
903 lay->token = ent->token;
904 lay->status_own = CMD_OWNER_HW;
905 set_signature(ent, !cmd->checksum_disabled);
906 dump_command(dev, ent, 1);
907 ent->ts1 = ktime_get_ns();
908 cmd_mode = cmd->mode;
909
910 if (ent->callback)
911 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
912 set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
913
914 /* Skip sending command to fw if internal error */
915 if (pci_channel_offline(dev->pdev) ||
916 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
917 u8 status = 0;
918 u32 drv_synd;
919
920 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
921 MLX5_SET(mbox_out, ent->out, status, status);
922 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
923
924 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
925 /* no doorbell, no need to keep the entry */
926 free_ent(cmd, ent->idx);
927 if (ent->callback)
928 free_cmd(ent);
929 return;
930 }
931
932 /* ring doorbell after the descriptor is valid */
933 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
934 wmb();
935 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
936 /* if not in polling don't use ent after this point */
937 if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
938 poll_timeout(ent);
939 /* make sure we read the descriptor after ownership is SW */
940 rmb();
941 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
942 }
943 }
944
945 static const char *deliv_status_to_str(u8 status)
946 {
947 switch (status) {
948 case MLX5_CMD_DELIVERY_STAT_OK:
949 return "no errors";
950 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
951 return "signature error";
952 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
953 return "token error";
954 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
955 return "bad block number";
956 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
957 return "output pointer not aligned to block size";
958 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
959 return "input pointer not aligned to block size";
960 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
961 return "firmware internal error";
962 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
963 return "command input length error";
964 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
965 return "command output length error";
966 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
967 return "reserved fields not cleared";
968 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
969 return "bad command descriptor type";
970 default:
971 return "unknown status code";
972 }
973 }
974
975 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
976 {
977 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
978 struct mlx5_cmd *cmd = &dev->cmd;
979 int err;
980
981 if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
982 wait_for_completion(&ent->done);
983 } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
984 ent->ret = -ETIMEDOUT;
985 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
986 }
987
988 err = ent->ret;
989
990 if (err == -ETIMEDOUT) {
991 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
992 mlx5_command_str(msg_to_opcode(ent->in)),
993 msg_to_opcode(ent->in));
994 }
995 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
996 err, deliv_status_to_str(ent->status), ent->status);
997
998 return err;
999 }
1000
1001 /* Notes:
1002 * 1. Callback functions may not sleep
1003 * 2. page queue commands do not support asynchrous completion
1004 */
1005 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
1006 struct mlx5_cmd_msg *out, void *uout, int uout_size,
1007 mlx5_cmd_cbk_t callback,
1008 void *context, int page_queue, u8 *status,
1009 u8 token, bool force_polling)
1010 {
1011 struct mlx5_cmd *cmd = &dev->cmd;
1012 struct mlx5_cmd_work_ent *ent;
1013 struct mlx5_cmd_stats *stats;
1014 int err = 0;
1015 s64 ds;
1016 u16 op;
1017
1018 if (callback && page_queue)
1019 return -EINVAL;
1020
1021 ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
1022 page_queue);
1023 if (IS_ERR(ent))
1024 return PTR_ERR(ent);
1025
1026 ent->token = token;
1027 ent->polling = force_polling;
1028
1029 if (!callback)
1030 init_completion(&ent->done);
1031
1032 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
1033 INIT_WORK(&ent->work, cmd_work_handler);
1034 if (page_queue) {
1035 cmd_work_handler(&ent->work);
1036 } else if (!queue_work(cmd->wq, &ent->work)) {
1037 mlx5_core_warn(dev, "failed to queue work\n");
1038 err = -ENOMEM;
1039 goto out_free;
1040 }
1041
1042 if (callback)
1043 goto out;
1044
1045 err = wait_func(dev, ent);
1046 if (err == -ETIMEDOUT)
1047 goto out;
1048
1049 ds = ent->ts2 - ent->ts1;
1050 op = MLX5_GET(mbox_in, in->first.data, opcode);
1051 if (op < ARRAY_SIZE(cmd->stats)) {
1052 stats = &cmd->stats[op];
1053 spin_lock_irq(&stats->lock);
1054 stats->sum += ds;
1055 ++stats->n;
1056 spin_unlock_irq(&stats->lock);
1057 }
1058 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1059 "fw exec time for %s is %lld nsec\n",
1060 mlx5_command_str(op), ds);
1061 *status = ent->status;
1062
1063 out_free:
1064 free_cmd(ent);
1065 out:
1066 return err;
1067 }
1068
1069 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1070 size_t count, loff_t *pos)
1071 {
1072 struct mlx5_core_dev *dev = filp->private_data;
1073 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1074 char lbuf[3];
1075 int err;
1076
1077 if (!dbg->in_msg || !dbg->out_msg)
1078 return -ENOMEM;
1079
1080 if (count < sizeof(lbuf) - 1)
1081 return -EINVAL;
1082
1083 if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1084 return -EFAULT;
1085
1086 lbuf[sizeof(lbuf) - 1] = 0;
1087
1088 if (strcmp(lbuf, "go"))
1089 return -EINVAL;
1090
1091 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1092
1093 return err ? err : count;
1094 }
1095
1096 static const struct file_operations fops = {
1097 .owner = THIS_MODULE,
1098 .open = simple_open,
1099 .write = dbg_write,
1100 };
1101
1102 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1103 u8 token)
1104 {
1105 struct mlx5_cmd_prot_block *block;
1106 struct mlx5_cmd_mailbox *next;
1107 int copy;
1108
1109 if (!to || !from)
1110 return -ENOMEM;
1111
1112 copy = min_t(int, size, sizeof(to->first.data));
1113 memcpy(to->first.data, from, copy);
1114 size -= copy;
1115 from += copy;
1116
1117 next = to->next;
1118 while (size) {
1119 if (!next) {
1120 /* this is a BUG */
1121 return -ENOMEM;
1122 }
1123
1124 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1125 block = next->buf;
1126 memcpy(block->data, from, copy);
1127 from += copy;
1128 size -= copy;
1129 block->token = token;
1130 next = next->next;
1131 }
1132
1133 return 0;
1134 }
1135
1136 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1137 {
1138 struct mlx5_cmd_prot_block *block;
1139 struct mlx5_cmd_mailbox *next;
1140 int copy;
1141
1142 if (!to || !from)
1143 return -ENOMEM;
1144
1145 copy = min_t(int, size, sizeof(from->first.data));
1146 memcpy(to, from->first.data, copy);
1147 size -= copy;
1148 to += copy;
1149
1150 next = from->next;
1151 while (size) {
1152 if (!next) {
1153 /* this is a BUG */
1154 return -ENOMEM;
1155 }
1156
1157 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1158 block = next->buf;
1159
1160 memcpy(to, block->data, copy);
1161 to += copy;
1162 size -= copy;
1163 next = next->next;
1164 }
1165
1166 return 0;
1167 }
1168
1169 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1170 gfp_t flags)
1171 {
1172 struct mlx5_cmd_mailbox *mailbox;
1173
1174 mailbox = kmalloc(sizeof(*mailbox), flags);
1175 if (!mailbox)
1176 return ERR_PTR(-ENOMEM);
1177
1178 mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1179 &mailbox->dma);
1180 if (!mailbox->buf) {
1181 mlx5_core_dbg(dev, "failed allocation\n");
1182 kfree(mailbox);
1183 return ERR_PTR(-ENOMEM);
1184 }
1185 mailbox->next = NULL;
1186
1187 return mailbox;
1188 }
1189
1190 static void free_cmd_box(struct mlx5_core_dev *dev,
1191 struct mlx5_cmd_mailbox *mailbox)
1192 {
1193 dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1194 kfree(mailbox);
1195 }
1196
1197 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1198 gfp_t flags, int size,
1199 u8 token)
1200 {
1201 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1202 struct mlx5_cmd_prot_block *block;
1203 struct mlx5_cmd_msg *msg;
1204 int err;
1205 int n;
1206 int i;
1207
1208 msg = kzalloc(sizeof(*msg), flags);
1209 if (!msg)
1210 return ERR_PTR(-ENOMEM);
1211
1212 msg->len = size;
1213 n = mlx5_calc_cmd_blocks(msg);
1214
1215 for (i = 0; i < n; i++) {
1216 tmp = alloc_cmd_box(dev, flags);
1217 if (IS_ERR(tmp)) {
1218 mlx5_core_warn(dev, "failed allocating block\n");
1219 err = PTR_ERR(tmp);
1220 goto err_alloc;
1221 }
1222
1223 block = tmp->buf;
1224 tmp->next = head;
1225 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1226 block->block_num = cpu_to_be32(n - i - 1);
1227 block->token = token;
1228 head = tmp;
1229 }
1230 msg->next = head;
1231 return msg;
1232
1233 err_alloc:
1234 while (head) {
1235 tmp = head->next;
1236 free_cmd_box(dev, head);
1237 head = tmp;
1238 }
1239 kfree(msg);
1240
1241 return ERR_PTR(err);
1242 }
1243
1244 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1245 struct mlx5_cmd_msg *msg)
1246 {
1247 struct mlx5_cmd_mailbox *head = msg->next;
1248 struct mlx5_cmd_mailbox *next;
1249
1250 while (head) {
1251 next = head->next;
1252 free_cmd_box(dev, head);
1253 head = next;
1254 }
1255 kfree(msg);
1256 }
1257
1258 static ssize_t data_write(struct file *filp, const char __user *buf,
1259 size_t count, loff_t *pos)
1260 {
1261 struct mlx5_core_dev *dev = filp->private_data;
1262 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1263 void *ptr;
1264
1265 if (*pos != 0)
1266 return -EINVAL;
1267
1268 kfree(dbg->in_msg);
1269 dbg->in_msg = NULL;
1270 dbg->inlen = 0;
1271 ptr = memdup_user(buf, count);
1272 if (IS_ERR(ptr))
1273 return PTR_ERR(ptr);
1274 dbg->in_msg = ptr;
1275 dbg->inlen = count;
1276
1277 *pos = count;
1278
1279 return count;
1280 }
1281
1282 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1283 loff_t *pos)
1284 {
1285 struct mlx5_core_dev *dev = filp->private_data;
1286 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1287
1288 if (!dbg->out_msg)
1289 return -ENOMEM;
1290
1291 return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1292 dbg->outlen);
1293 }
1294
1295 static const struct file_operations dfops = {
1296 .owner = THIS_MODULE,
1297 .open = simple_open,
1298 .write = data_write,
1299 .read = data_read,
1300 };
1301
1302 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1303 loff_t *pos)
1304 {
1305 struct mlx5_core_dev *dev = filp->private_data;
1306 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1307 char outlen[8];
1308 int err;
1309
1310 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1311 if (err < 0)
1312 return err;
1313
1314 return simple_read_from_buffer(buf, count, pos, outlen, err);
1315 }
1316
1317 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1318 size_t count, loff_t *pos)
1319 {
1320 struct mlx5_core_dev *dev = filp->private_data;
1321 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1322 char outlen_str[8] = {0};
1323 int outlen;
1324 void *ptr;
1325 int err;
1326
1327 if (*pos != 0 || count > 6)
1328 return -EINVAL;
1329
1330 kfree(dbg->out_msg);
1331 dbg->out_msg = NULL;
1332 dbg->outlen = 0;
1333
1334 if (copy_from_user(outlen_str, buf, count))
1335 return -EFAULT;
1336
1337 err = sscanf(outlen_str, "%d", &outlen);
1338 if (err < 0)
1339 return err;
1340
1341 ptr = kzalloc(outlen, GFP_KERNEL);
1342 if (!ptr)
1343 return -ENOMEM;
1344
1345 dbg->out_msg = ptr;
1346 dbg->outlen = outlen;
1347
1348 *pos = count;
1349
1350 return count;
1351 }
1352
1353 static const struct file_operations olfops = {
1354 .owner = THIS_MODULE,
1355 .open = simple_open,
1356 .write = outlen_write,
1357 .read = outlen_read,
1358 };
1359
1360 static void set_wqname(struct mlx5_core_dev *dev)
1361 {
1362 struct mlx5_cmd *cmd = &dev->cmd;
1363
1364 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1365 dev_name(dev->device));
1366 }
1367
1368 static void clean_debug_files(struct mlx5_core_dev *dev)
1369 {
1370 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1371
1372 if (!mlx5_debugfs_root)
1373 return;
1374
1375 mlx5_cmdif_debugfs_cleanup(dev);
1376 debugfs_remove_recursive(dbg->dbg_root);
1377 }
1378
1379 static void create_debugfs_files(struct mlx5_core_dev *dev)
1380 {
1381 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1382
1383 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1384
1385 debugfs_create_file("in", 0400, dbg->dbg_root, dev, &dfops);
1386 debugfs_create_file("out", 0200, dbg->dbg_root, dev, &dfops);
1387 debugfs_create_file("out_len", 0600, dbg->dbg_root, dev, &olfops);
1388 debugfs_create_u8("status", 0600, dbg->dbg_root, &dbg->status);
1389 debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1390
1391 mlx5_cmdif_debugfs_init(dev);
1392 }
1393
1394 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1395 {
1396 struct mlx5_cmd *cmd = &dev->cmd;
1397 int i;
1398
1399 for (i = 0; i < cmd->max_reg_cmds; i++)
1400 down(&cmd->sem);
1401 down(&cmd->pages_sem);
1402
1403 cmd->mode = mode;
1404
1405 up(&cmd->pages_sem);
1406 for (i = 0; i < cmd->max_reg_cmds; i++)
1407 up(&cmd->sem);
1408 }
1409
1410 static int cmd_comp_notifier(struct notifier_block *nb,
1411 unsigned long type, void *data)
1412 {
1413 struct mlx5_core_dev *dev;
1414 struct mlx5_cmd *cmd;
1415 struct mlx5_eqe *eqe;
1416
1417 cmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb);
1418 dev = container_of(cmd, struct mlx5_core_dev, cmd);
1419 eqe = data;
1420
1421 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
1422
1423 return NOTIFY_OK;
1424 }
1425 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1426 {
1427 MLX5_NB_INIT(&dev->cmd.nb, cmd_comp_notifier, CMD);
1428 mlx5_eq_notifier_register(dev, &dev->cmd.nb);
1429 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1430 }
1431
1432 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1433 {
1434 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1435 mlx5_eq_notifier_unregister(dev, &dev->cmd.nb);
1436 }
1437
1438 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1439 {
1440 unsigned long flags;
1441
1442 if (msg->parent) {
1443 spin_lock_irqsave(&msg->parent->lock, flags);
1444 list_add_tail(&msg->list, &msg->parent->head);
1445 spin_unlock_irqrestore(&msg->parent->lock, flags);
1446 } else {
1447 mlx5_free_cmd_msg(dev, msg);
1448 }
1449 }
1450
1451 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1452 {
1453 struct mlx5_cmd *cmd = &dev->cmd;
1454 struct mlx5_cmd_work_ent *ent;
1455 mlx5_cmd_cbk_t callback;
1456 void *context;
1457 int err;
1458 int i;
1459 s64 ds;
1460 struct mlx5_cmd_stats *stats;
1461 unsigned long flags;
1462 unsigned long vector;
1463
1464 /* there can be at most 32 command queues */
1465 vector = vec & 0xffffffff;
1466 for (i = 0; i < (1 << cmd->log_sz); i++) {
1467 if (test_bit(i, &vector)) {
1468 struct semaphore *sem;
1469
1470 ent = cmd->ent_arr[i];
1471
1472 /* if we already completed the command, ignore it */
1473 if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1474 &ent->state)) {
1475 /* only real completion can free the cmd slot */
1476 if (!forced) {
1477 mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1478 ent->idx);
1479 free_ent(cmd, ent->idx);
1480 free_cmd(ent);
1481 }
1482 continue;
1483 }
1484
1485 if (ent->callback)
1486 cancel_delayed_work(&ent->cb_timeout_work);
1487 if (ent->page_queue)
1488 sem = &cmd->pages_sem;
1489 else
1490 sem = &cmd->sem;
1491 ent->ts2 = ktime_get_ns();
1492 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1493 dump_command(dev, ent, 0);
1494 if (!ent->ret) {
1495 if (!cmd->checksum_disabled)
1496 ent->ret = verify_signature(ent);
1497 else
1498 ent->ret = 0;
1499 if (vec & MLX5_TRIGGERED_CMD_COMP)
1500 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1501 else
1502 ent->status = ent->lay->status_own >> 1;
1503
1504 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1505 ent->ret, deliv_status_to_str(ent->status), ent->status);
1506 }
1507
1508 /* only real completion will free the entry slot */
1509 if (!forced)
1510 free_ent(cmd, ent->idx);
1511
1512 if (ent->callback) {
1513 ds = ent->ts2 - ent->ts1;
1514 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1515 stats = &cmd->stats[ent->op];
1516 spin_lock_irqsave(&stats->lock, flags);
1517 stats->sum += ds;
1518 ++stats->n;
1519 spin_unlock_irqrestore(&stats->lock, flags);
1520 }
1521
1522 callback = ent->callback;
1523 context = ent->context;
1524 err = ent->ret;
1525 if (!err) {
1526 err = mlx5_copy_from_msg(ent->uout,
1527 ent->out,
1528 ent->uout_size);
1529
1530 err = err ? err : mlx5_cmd_check(dev,
1531 ent->in->first.data,
1532 ent->uout);
1533 }
1534
1535 mlx5_free_cmd_msg(dev, ent->out);
1536 free_msg(dev, ent->in);
1537
1538 err = err ? err : ent->status;
1539 if (!forced)
1540 free_cmd(ent);
1541 callback(err, context);
1542 } else {
1543 complete(&ent->done);
1544 }
1545 up(sem);
1546 }
1547 }
1548 }
1549
1550 void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev)
1551 {
1552 unsigned long flags;
1553 u64 vector;
1554
1555 /* wait for pending handlers to complete */
1556 mlx5_eq_synchronize_cmd_irq(dev);
1557 spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
1558 vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
1559 if (!vector)
1560 goto no_trig;
1561
1562 vector |= MLX5_TRIGGERED_CMD_COMP;
1563 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1564
1565 mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
1566 mlx5_cmd_comp_handler(dev, vector, true);
1567 return;
1568
1569 no_trig:
1570 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1571 }
1572
1573 void mlx5_cmd_flush(struct mlx5_core_dev *dev)
1574 {
1575 struct mlx5_cmd *cmd = &dev->cmd;
1576 int i;
1577
1578 for (i = 0; i < cmd->max_reg_cmds; i++)
1579 while (down_trylock(&cmd->sem))
1580 mlx5_cmd_trigger_completions(dev);
1581
1582 while (down_trylock(&cmd->pages_sem))
1583 mlx5_cmd_trigger_completions(dev);
1584
1585 /* Unlock cmdif */
1586 up(&cmd->pages_sem);
1587 for (i = 0; i < cmd->max_reg_cmds; i++)
1588 up(&cmd->sem);
1589 }
1590
1591 static int status_to_err(u8 status)
1592 {
1593 switch (status) {
1594 case MLX5_CMD_DELIVERY_STAT_OK:
1595 case MLX5_DRIVER_STATUS_ABORTED:
1596 return 0;
1597 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1598 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1599 return -EBADR;
1600 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1601 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1602 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1603 return -EFAULT; /* Bad address */
1604 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1605 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1606 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1607 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1608 return -ENOMSG;
1609 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1610 return -EIO;
1611 default:
1612 return -EINVAL;
1613 }
1614 }
1615
1616 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1617 gfp_t gfp)
1618 {
1619 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1620 struct cmd_msg_cache *ch = NULL;
1621 struct mlx5_cmd *cmd = &dev->cmd;
1622 int i;
1623
1624 if (in_size <= 16)
1625 goto cache_miss;
1626
1627 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1628 ch = &cmd->cache[i];
1629 if (in_size > ch->max_inbox_size)
1630 continue;
1631 spin_lock_irq(&ch->lock);
1632 if (list_empty(&ch->head)) {
1633 spin_unlock_irq(&ch->lock);
1634 continue;
1635 }
1636 msg = list_entry(ch->head.next, typeof(*msg), list);
1637 /* For cached lists, we must explicitly state what is
1638 * the real size
1639 */
1640 msg->len = in_size;
1641 list_del(&msg->list);
1642 spin_unlock_irq(&ch->lock);
1643 break;
1644 }
1645
1646 if (!IS_ERR(msg))
1647 return msg;
1648
1649 cache_miss:
1650 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1651 return msg;
1652 }
1653
1654 static int is_manage_pages(void *in)
1655 {
1656 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1657 }
1658
1659 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1660 int out_size, mlx5_cmd_cbk_t callback, void *context,
1661 bool force_polling)
1662 {
1663 struct mlx5_cmd_msg *inb;
1664 struct mlx5_cmd_msg *outb;
1665 int pages_queue;
1666 gfp_t gfp;
1667 int err;
1668 u8 status = 0;
1669 u32 drv_synd;
1670 u8 token;
1671
1672 if (pci_channel_offline(dev->pdev) ||
1673 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1674 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1675
1676 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1677 MLX5_SET(mbox_out, out, status, status);
1678 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1679 return err;
1680 }
1681
1682 pages_queue = is_manage_pages(in);
1683 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1684
1685 inb = alloc_msg(dev, in_size, gfp);
1686 if (IS_ERR(inb)) {
1687 err = PTR_ERR(inb);
1688 return err;
1689 }
1690
1691 token = alloc_token(&dev->cmd);
1692
1693 err = mlx5_copy_to_msg(inb, in, in_size, token);
1694 if (err) {
1695 mlx5_core_warn(dev, "err %d\n", err);
1696 goto out_in;
1697 }
1698
1699 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1700 if (IS_ERR(outb)) {
1701 err = PTR_ERR(outb);
1702 goto out_in;
1703 }
1704
1705 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1706 pages_queue, &status, token, force_polling);
1707 if (err)
1708 goto out_out;
1709
1710 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1711 if (status) {
1712 err = status_to_err(status);
1713 goto out_out;
1714 }
1715
1716 if (!callback)
1717 err = mlx5_copy_from_msg(out, outb, out_size);
1718
1719 out_out:
1720 if (!callback)
1721 mlx5_free_cmd_msg(dev, outb);
1722
1723 out_in:
1724 if (!callback)
1725 free_msg(dev, inb);
1726 return err;
1727 }
1728
1729 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1730 int out_size)
1731 {
1732 int err;
1733
1734 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1735 return err ? : mlx5_cmd_check(dev, in, out);
1736 }
1737 EXPORT_SYMBOL(mlx5_cmd_exec);
1738
1739 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
1740 struct mlx5_async_ctx *ctx)
1741 {
1742 ctx->dev = dev;
1743 /* Starts at 1 to avoid doing wake_up if we are not cleaning up */
1744 atomic_set(&ctx->num_inflight, 1);
1745 init_waitqueue_head(&ctx->wait);
1746 }
1747 EXPORT_SYMBOL(mlx5_cmd_init_async_ctx);
1748
1749 /**
1750 * mlx5_cmd_cleanup_async_ctx - Clean up an async_ctx
1751 * @ctx: The ctx to clean
1752 *
1753 * Upon return all callbacks given to mlx5_cmd_exec_cb() have been called. The
1754 * caller must ensure that mlx5_cmd_exec_cb() is not called during or after
1755 * the call mlx5_cleanup_async_ctx().
1756 */
1757 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx)
1758 {
1759 atomic_dec(&ctx->num_inflight);
1760 wait_event(ctx->wait, atomic_read(&ctx->num_inflight) == 0);
1761 }
1762 EXPORT_SYMBOL(mlx5_cmd_cleanup_async_ctx);
1763
1764 static void mlx5_cmd_exec_cb_handler(int status, void *_work)
1765 {
1766 struct mlx5_async_work *work = _work;
1767 struct mlx5_async_ctx *ctx = work->ctx;
1768
1769 work->user_callback(status, work);
1770 if (atomic_dec_and_test(&ctx->num_inflight))
1771 wake_up(&ctx->wait);
1772 }
1773
1774 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
1775 void *out, int out_size, mlx5_async_cbk_t callback,
1776 struct mlx5_async_work *work)
1777 {
1778 int ret;
1779
1780 work->ctx = ctx;
1781 work->user_callback = callback;
1782 if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight)))
1783 return -EIO;
1784 ret = cmd_exec(ctx->dev, in, in_size, out, out_size,
1785 mlx5_cmd_exec_cb_handler, work, false);
1786 if (ret && atomic_dec_and_test(&ctx->num_inflight))
1787 wake_up(&ctx->wait);
1788
1789 return ret;
1790 }
1791 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1792
1793 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1794 void *out, int out_size)
1795 {
1796 int err;
1797
1798 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1799
1800 return err ? : mlx5_cmd_check(dev, in, out);
1801 }
1802 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1803
1804 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1805 {
1806 struct cmd_msg_cache *ch;
1807 struct mlx5_cmd_msg *msg;
1808 struct mlx5_cmd_msg *n;
1809 int i;
1810
1811 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1812 ch = &dev->cmd.cache[i];
1813 list_for_each_entry_safe(msg, n, &ch->head, list) {
1814 list_del(&msg->list);
1815 mlx5_free_cmd_msg(dev, msg);
1816 }
1817 }
1818 }
1819
1820 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1821 512, 32, 16, 8, 2
1822 };
1823
1824 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1825 16 + MLX5_CMD_DATA_BLOCK_SIZE,
1826 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1827 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1828 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1829 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1830 };
1831
1832 static void create_msg_cache(struct mlx5_core_dev *dev)
1833 {
1834 struct mlx5_cmd *cmd = &dev->cmd;
1835 struct cmd_msg_cache *ch;
1836 struct mlx5_cmd_msg *msg;
1837 int i;
1838 int k;
1839
1840 /* Initialize and fill the caches with initial entries */
1841 for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1842 ch = &cmd->cache[k];
1843 spin_lock_init(&ch->lock);
1844 INIT_LIST_HEAD(&ch->head);
1845 ch->num_ent = cmd_cache_num_ent[k];
1846 ch->max_inbox_size = cmd_cache_ent_size[k];
1847 for (i = 0; i < ch->num_ent; i++) {
1848 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1849 ch->max_inbox_size, 0);
1850 if (IS_ERR(msg))
1851 break;
1852 msg->parent = ch;
1853 list_add_tail(&msg->list, &ch->head);
1854 }
1855 }
1856 }
1857
1858 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1859 {
1860 struct device *ddev = dev->device;
1861
1862 cmd->cmd_alloc_buf = dma_alloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1863 &cmd->alloc_dma, GFP_KERNEL);
1864 if (!cmd->cmd_alloc_buf)
1865 return -ENOMEM;
1866
1867 /* make sure it is aligned to 4K */
1868 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1869 cmd->cmd_buf = cmd->cmd_alloc_buf;
1870 cmd->dma = cmd->alloc_dma;
1871 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1872 return 0;
1873 }
1874
1875 dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1876 cmd->alloc_dma);
1877 cmd->cmd_alloc_buf = dma_alloc_coherent(ddev,
1878 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1879 &cmd->alloc_dma, GFP_KERNEL);
1880 if (!cmd->cmd_alloc_buf)
1881 return -ENOMEM;
1882
1883 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1884 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1885 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1886 return 0;
1887 }
1888
1889 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1890 {
1891 struct device *ddev = dev->device;
1892
1893 dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1894 cmd->alloc_dma);
1895 }
1896
1897 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1898 {
1899 int size = sizeof(struct mlx5_cmd_prot_block);
1900 int align = roundup_pow_of_two(size);
1901 struct mlx5_cmd *cmd = &dev->cmd;
1902 u32 cmd_h, cmd_l;
1903 u16 cmd_if_rev;
1904 int err;
1905 int i;
1906
1907 memset(cmd, 0, sizeof(*cmd));
1908 cmd_if_rev = cmdif_rev(dev);
1909 if (cmd_if_rev != CMD_IF_REV) {
1910 mlx5_core_err(dev,
1911 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1912 CMD_IF_REV, cmd_if_rev);
1913 return -EINVAL;
1914 }
1915
1916 cmd->pool = dma_pool_create("mlx5_cmd", dev->device, size, align, 0);
1917 if (!cmd->pool)
1918 return -ENOMEM;
1919
1920 err = alloc_cmd_page(dev, cmd);
1921 if (err)
1922 goto err_free_pool;
1923
1924 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1925 cmd->log_sz = cmd_l >> 4 & 0xf;
1926 cmd->log_stride = cmd_l & 0xf;
1927 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1928 mlx5_core_err(dev, "firmware reports too many outstanding commands %d\n",
1929 1 << cmd->log_sz);
1930 err = -EINVAL;
1931 goto err_free_page;
1932 }
1933
1934 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1935 mlx5_core_err(dev, "command queue size overflow\n");
1936 err = -EINVAL;
1937 goto err_free_page;
1938 }
1939
1940 cmd->checksum_disabled = 1;
1941 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1942 cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1943
1944 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1945 if (cmd->cmdif_rev > CMD_IF_REV) {
1946 mlx5_core_err(dev, "driver does not support command interface version. driver %d, firmware %d\n",
1947 CMD_IF_REV, cmd->cmdif_rev);
1948 err = -EOPNOTSUPP;
1949 goto err_free_page;
1950 }
1951
1952 spin_lock_init(&cmd->alloc_lock);
1953 spin_lock_init(&cmd->token_lock);
1954 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1955 spin_lock_init(&cmd->stats[i].lock);
1956
1957 sema_init(&cmd->sem, cmd->max_reg_cmds);
1958 sema_init(&cmd->pages_sem, 1);
1959
1960 cmd_h = (u32)((u64)(cmd->dma) >> 32);
1961 cmd_l = (u32)(cmd->dma);
1962 if (cmd_l & 0xfff) {
1963 mlx5_core_err(dev, "invalid command queue address\n");
1964 err = -ENOMEM;
1965 goto err_free_page;
1966 }
1967
1968 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1969 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1970
1971 /* Make sure firmware sees the complete address before we proceed */
1972 wmb();
1973
1974 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1975
1976 cmd->mode = CMD_MODE_POLLING;
1977
1978 create_msg_cache(dev);
1979
1980 set_wqname(dev);
1981 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1982 if (!cmd->wq) {
1983 mlx5_core_err(dev, "failed to create command workqueue\n");
1984 err = -ENOMEM;
1985 goto err_cache;
1986 }
1987
1988 create_debugfs_files(dev);
1989
1990 return 0;
1991
1992 err_cache:
1993 destroy_msg_cache(dev);
1994
1995 err_free_page:
1996 free_cmd_page(dev, cmd);
1997
1998 err_free_pool:
1999 dma_pool_destroy(cmd->pool);
2000
2001 return err;
2002 }
2003 EXPORT_SYMBOL(mlx5_cmd_init);
2004
2005 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
2006 {
2007 struct mlx5_cmd *cmd = &dev->cmd;
2008
2009 clean_debug_files(dev);
2010 destroy_workqueue(cmd->wq);
2011 destroy_msg_cache(dev);
2012 free_cmd_page(dev, cmd);
2013 dma_pool_destroy(cmd->pool);
2014 }
2015 EXPORT_SYMBOL(mlx5_cmd_cleanup);
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