2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/mlx5/fs.h>
48 #include <linux/rhashtable.h>
49 #include <net/switchdev.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
54 #include "mlx5_core.h"
57 #include "lib/hv_vhca.h"
59 extern const struct net_device_ops mlx5e_netdev_ops
;
62 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
63 #define MLX5E_METADATA_ETHER_LEN 8
65 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
67 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
69 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
70 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
72 #define MLX5E_MAX_PRIORITY 8
73 #define MLX5E_MAX_DSCP 64
74 #define MLX5E_MAX_NUM_TC 8
76 #define MLX5_RX_HEADROOM NET_SKB_PAD
77 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
78 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
80 #define MLX5E_RX_MAX_HEAD (256)
82 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
83 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
84 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
85 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
86 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
87 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
89 #define MLX5_MPWRQ_LOG_WQE_SZ 18
90 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
91 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
92 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
94 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
95 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
96 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
97 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
98 #define MLX5E_MAX_RQ_NUM_MTTS \
99 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
100 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
101 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
102 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
103 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
104 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
105 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
107 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
108 #define MLX5E_LOG_MAX_RX_WQE_BULK \
109 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
111 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
112 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
113 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
115 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
116 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
117 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
118 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
120 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
122 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
123 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
124 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
126 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
127 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
128 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
129 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
130 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
131 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
132 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
133 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
135 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
136 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
137 #define MLX5E_MIN_NUM_CHANNELS 0x1
138 #define MLX5E_MAX_NUM_CHANNELS MLX5E_INDIR_RQT_SIZE
139 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
140 #define MLX5E_TX_CQ_POLL_BUDGET 128
141 #define MLX5E_TX_XSK_POLL_BUDGET 64
142 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
144 #define MLX5E_UMR_WQE_INLINE_SZ \
145 (sizeof(struct mlx5e_umr_wqe) + \
146 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
147 MLX5_UMR_MTT_ALIGNMENT))
148 #define MLX5E_UMR_WQEBBS \
149 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
151 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
153 #define mlx5e_dbg(mlevel, priv, format, ...) \
155 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
156 netdev_warn(priv->netdev, format, \
160 enum mlx5e_rq_group
{
161 MLX5E_RQ_GROUP_REGULAR
,
163 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
166 static inline u8
mlx5e_get_num_lag_ports(struct mlx5_core_dev
*mdev
)
168 if (mlx5_lag_is_lacp_owner(mdev
))
171 return clamp_t(u8
, MLX5_CAP_GEN(mdev
, num_lag_ports
), 1, MLX5_MAX_PORTS
);
174 static inline u16
mlx5_min_rx_wqes(int wq_type
, u32 wq_size
)
177 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
178 return min_t(u16
, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW
,
181 return min_t(u16
, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES
,
186 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
187 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev
*mdev
)
189 return is_kdump_kernel() ?
190 MLX5E_MIN_NUM_CHANNELS
:
191 min_t(int, mlx5_comp_vectors_count(mdev
), MLX5E_MAX_NUM_CHANNELS
);
194 struct mlx5e_tx_wqe
{
195 struct mlx5_wqe_ctrl_seg ctrl
;
198 struct mlx5_wqe_eth_seg eth
;
199 struct mlx5_wqe_data_seg data
[0];
201 u8 tls_progress_params_ctx
[0];
205 struct mlx5e_rx_wqe_ll
{
206 struct mlx5_wqe_srq_next_seg next
;
207 struct mlx5_wqe_data_seg data
[];
210 struct mlx5e_rx_wqe_cyc
{
211 struct mlx5_wqe_data_seg data
[0];
214 struct mlx5e_umr_wqe
{
215 struct mlx5_wqe_ctrl_seg ctrl
;
216 struct mlx5_wqe_umr_ctrl_seg uctrl
;
217 struct mlx5_mkey_seg mkc
;
219 struct mlx5_mtt inline_mtts
[0];
220 u8 tls_static_params_ctx
[0];
224 extern const char mlx5e_self_tests
[][ETH_GSTRING_LEN
];
226 enum mlx5e_priv_flag
{
227 MLX5E_PFLAG_RX_CQE_BASED_MODER
,
228 MLX5E_PFLAG_TX_CQE_BASED_MODER
,
229 MLX5E_PFLAG_RX_CQE_COMPRESS
,
230 MLX5E_PFLAG_RX_STRIDING_RQ
,
231 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE
,
232 MLX5E_PFLAG_XDP_TX_MPWQE
,
233 MLX5E_NUM_PFLAGS
, /* Keep last */
236 #define MLX5E_SET_PFLAG(params, pflag, enable) \
239 (params)->pflags |= BIT(pflag); \
241 (params)->pflags &= ~(BIT(pflag)); \
244 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
246 #ifdef CONFIG_MLX5_CORE_EN_DCB
247 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
250 struct mlx5e_params
{
253 u8 log_rq_mtu_frames
;
256 bool rx_cqe_compress_def
;
257 bool tunneled_offload_en
;
258 struct dim_cq_moder rx_cq_moderation
;
259 struct dim_cq_moder tx_cq_moderation
;
261 u8 tx_min_inline_mode
;
262 bool vlan_strip_disable
;
268 struct bpf_prog
*xdp_prog
;
269 struct mlx5e_xsk
*xsk
;
274 #ifdef CONFIG_MLX5_CORE_EN_DCB
275 struct mlx5e_cee_config
{
276 /* bw pct for priority group */
277 u8 pg_bw_pct
[CEE_DCBX_MAX_PGS
];
278 u8 prio_to_pg_map
[CEE_DCBX_MAX_PRIO
];
279 bool pfc_setting
[CEE_DCBX_MAX_PRIO
];
286 MLX5_DCB_CHG_NO_RESET
,
290 enum mlx5_dcbx_oper_mode mode
;
291 struct mlx5e_cee_config cee_cfg
; /* pending configuration */
294 /* The only setting that cannot be read from FW */
295 u8 tc_tsa
[IEEE_8021QAZ_MAX_TCS
];
298 /* Buffer configuration */
304 struct mlx5e_dcbx_dp
{
305 u8 dscp2prio
[MLX5E_MAX_DSCP
];
311 MLX5E_RQ_STATE_ENABLED
,
312 MLX5E_RQ_STATE_RECOVERING
,
314 MLX5E_RQ_STATE_NO_CSUM_COMPLETE
,
315 MLX5E_RQ_STATE_CSUM_FULL
, /* cqe_csum_full hw bit is set */
319 /* data path - accessed per cqe */
322 /* data path - accessed per napi poll */
324 struct napi_struct
*napi
;
325 struct mlx5_core_cq mcq
;
326 struct mlx5e_channel
*channel
;
329 struct mlx5_core_dev
*mdev
;
330 struct mlx5_wq_ctrl wq_ctrl
;
331 } ____cacheline_aligned_in_smp
;
333 struct mlx5e_cq_decomp
{
334 /* cqe decompression */
335 struct mlx5_cqe64 title
;
336 struct mlx5_mini_cqe8 mini_arr
[MLX5_MINI_CQE_ARRAY_SIZE
];
340 } ____cacheline_aligned_in_smp
;
342 struct mlx5e_tx_wqe_info
{
347 #ifdef CONFIG_MLX5_EN_TLS
348 struct page
*resync_dump_frag_page
;
352 enum mlx5e_dma_map_type
{
353 MLX5E_DMA_MAP_SINGLE
,
357 struct mlx5e_sq_dma
{
360 enum mlx5e_dma_map_type type
;
364 MLX5E_SQ_STATE_ENABLED
,
365 MLX5E_SQ_STATE_RECOVERING
,
366 MLX5E_SQ_STATE_IPSEC
,
369 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE
,
370 MLX5E_SQ_STATE_PENDING_XSK_TX
,
373 struct mlx5e_sq_wqe_info
{
377 /* Auxiliary data for different opcodes. */
388 /* dirtied @completion */
391 struct dim dim
; /* Adaptive Moderation */
394 u16 pc ____cacheline_aligned_in_smp
;
400 struct mlx5_wq_cyc wq
;
402 struct mlx5e_sq_stats
*stats
;
404 struct mlx5e_sq_dma
*dma_fifo
;
405 struct mlx5e_tx_wqe_info
*wqe_info
;
407 void __iomem
*uar_map
;
408 struct netdev_queue
*txq
;
416 struct hwtstamp_config
*tstamp
;
417 struct mlx5_clock
*clock
;
420 struct mlx5_wq_ctrl wq_ctrl
;
421 struct mlx5e_channel
*channel
;
425 struct work_struct recover_work
;
426 } ____cacheline_aligned_in_smp
;
428 struct mlx5e_dma_info
{
439 /* XDP packets can be transmitted in different ways. On completion, we need to
440 * distinguish between them to clean up things in a proper way.
442 enum mlx5e_xdp_xmit_mode
{
443 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
444 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
447 MLX5E_XDP_XMIT_MODE_FRAME
,
449 /* The xdp_frame was created in place as a result of XDP_TX from a
450 * regular RQ. No DMA remapping happened, and the page belongs to us.
452 MLX5E_XDP_XMIT_MODE_PAGE
,
454 /* No xdp_frame was created at all, the transmit happened from a UMEM
455 * page. The UMEM Completion Ring producer pointer has to be increased.
457 MLX5E_XDP_XMIT_MODE_XSK
,
460 struct mlx5e_xdp_info
{
461 enum mlx5e_xdp_xmit_mode mode
;
464 struct xdp_frame
*xdpf
;
469 struct mlx5e_dma_info di
;
474 struct mlx5e_xdp_xmit_data
{
480 struct mlx5e_xdp_info_fifo
{
481 struct mlx5e_xdp_info
*xi
;
487 struct mlx5e_xdp_wqe_info
{
492 struct mlx5e_xdp_mpwqe
{
493 /* Current MPWQE session */
494 struct mlx5e_tx_wqe
*wqe
;
501 typedef int (*mlx5e_fp_xmit_xdp_frame_check
)(struct mlx5e_xdpsq
*);
502 typedef bool (*mlx5e_fp_xmit_xdp_frame
)(struct mlx5e_xdpsq
*,
503 struct mlx5e_xdp_xmit_data
*,
504 struct mlx5e_xdp_info
*,
510 /* dirtied @completion */
515 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp
;
517 struct mlx5_wqe_ctrl_seg
*doorbell_cseg
;
518 struct mlx5e_xdp_mpwqe mpwqe
;
523 struct xdp_umem
*umem
;
524 struct mlx5_wq_cyc wq
;
525 struct mlx5e_xdpsq_stats
*stats
;
526 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check
;
527 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame
;
529 struct mlx5e_xdp_wqe_info
*wqe_info
;
530 struct mlx5e_xdp_info_fifo xdpi_fifo
;
532 void __iomem
*uar_map
;
541 struct mlx5_wq_ctrl wq_ctrl
;
542 struct mlx5e_channel
*channel
;
543 } ____cacheline_aligned_in_smp
;
550 struct mlx5_wqe_ctrl_seg
*doorbell_cseg
;
553 /* write@xmit, read@completion */
555 struct mlx5e_sq_wqe_info
*ico_wqe
;
559 struct mlx5_wq_cyc wq
;
560 void __iomem
*uar_map
;
565 struct mlx5_wq_ctrl wq_ctrl
;
566 struct mlx5e_channel
*channel
;
568 struct work_struct recover_work
;
569 } ____cacheline_aligned_in_smp
;
571 struct mlx5e_wqe_frag_info
{
572 struct mlx5e_dma_info
*di
;
577 struct mlx5e_umr_dma_info
{
578 struct mlx5e_dma_info dma_info
[MLX5_MPWRQ_PAGES_PER_WQE
];
581 struct mlx5e_mpw_info
{
582 struct mlx5e_umr_dma_info umr
;
583 u16 consumed_strides
;
584 DECLARE_BITMAP(xdp_xmit_bitmap
, MLX5_MPWRQ_PAGES_PER_WQE
);
587 #define MLX5E_MAX_RX_FRAGS 4
589 /* a single cache unit is capable to serve one napi call (for non-striding rq)
590 * or a MPWQE (for striding rq).
592 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
593 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
594 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
595 struct mlx5e_page_cache
{
598 struct mlx5e_dma_info page_cache
[MLX5E_CACHE_SIZE
];
602 typedef void (*mlx5e_fp_handle_rx_cqe
)(struct mlx5e_rq
*, struct mlx5_cqe64
*);
603 typedef struct sk_buff
*
604 (*mlx5e_fp_skb_from_cqe_mpwrq
)(struct mlx5e_rq
*rq
, struct mlx5e_mpw_info
*wi
,
605 u16 cqe_bcnt
, u32 head_offset
, u32 page_idx
);
606 typedef struct sk_buff
*
607 (*mlx5e_fp_skb_from_cqe
)(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
,
608 struct mlx5e_wqe_frag_info
*wi
, u32 cqe_bcnt
);
609 typedef bool (*mlx5e_fp_post_rx_wqes
)(struct mlx5e_rq
*rq
);
610 typedef void (*mlx5e_fp_dealloc_wqe
)(struct mlx5e_rq
*, u16
);
613 MLX5E_RQ_FLAG_XDP_XMIT
,
614 MLX5E_RQ_FLAG_XDP_REDIRECT
,
617 struct mlx5e_rq_frag_info
{
622 struct mlx5e_rq_frags_info
{
623 struct mlx5e_rq_frag_info arr
[MLX5E_MAX_RX_FRAGS
];
633 struct mlx5_wq_cyc wq
;
634 struct mlx5e_wqe_frag_info
*frags
;
635 struct mlx5e_dma_info
*di
;
636 struct mlx5e_rq_frags_info info
;
637 mlx5e_fp_skb_from_cqe skb_from_cqe
;
640 struct mlx5_wq_ll wq
;
641 struct mlx5e_umr_wqe umr_wqe
;
642 struct mlx5e_mpw_info
*info
;
643 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq
;
655 u8 map_dir
; /* dma map direction */
658 struct mlx5e_channel
*channel
;
660 struct net_device
*netdev
;
661 struct mlx5e_rq_stats
*stats
;
663 struct mlx5e_cq_decomp cqd
;
664 struct mlx5e_page_cache page_cache
;
665 struct hwtstamp_config
*tstamp
;
666 struct mlx5_clock
*clock
;
668 mlx5e_fp_handle_rx_cqe handle_rx_cqe
;
669 mlx5e_fp_post_rx_wqes post_wqes
;
670 mlx5e_fp_dealloc_wqe dealloc_wqe
;
676 struct dim dim
; /* Dynamic Interrupt Moderation */
679 struct bpf_prog
*xdp_prog
;
680 struct mlx5e_xdpsq
*xdpsq
;
681 DECLARE_BITMAP(flags
, 8);
682 struct page_pool
*page_pool
;
684 /* AF_XDP zero-copy */
685 struct zero_copy_allocator zca
;
686 struct xdp_umem
*umem
;
688 struct work_struct recover_work
;
691 struct mlx5_wq_ctrl wq_ctrl
;
695 struct mlx5_core_dev
*mdev
;
696 struct mlx5_core_mkey umr_mkey
;
698 /* XDP read-mostly */
699 struct xdp_rxq_info xdp_rxq
;
700 } ____cacheline_aligned_in_smp
;
702 enum mlx5e_channel_state
{
703 MLX5E_CHANNEL_STATE_XSK
,
704 MLX5E_CHANNEL_NUM_STATES
707 struct mlx5e_channel
{
710 struct mlx5e_xdpsq rq_xdpsq
;
711 struct mlx5e_txqsq sq
[MLX5E_MAX_NUM_TC
];
712 struct mlx5e_icosq icosq
; /* internal control operations */
714 struct napi_struct napi
;
716 struct net_device
*netdev
;
722 struct mlx5e_xdpsq xdpsq
;
724 /* AF_XDP zero-copy */
725 struct mlx5e_rq xskrq
;
726 struct mlx5e_xdpsq xsksq
;
727 struct mlx5e_icosq xskicosq
;
728 /* xskicosq can be accessed from any CPU - the spinlock protects it. */
729 spinlock_t xskicosq_lock
;
731 /* data path - accessed per napi poll */
732 struct irq_desc
*irq_desc
;
733 struct mlx5e_ch_stats
*stats
;
736 struct mlx5e_priv
*priv
;
737 struct mlx5_core_dev
*mdev
;
738 struct hwtstamp_config
*tstamp
;
739 DECLARE_BITMAP(state
, MLX5E_CHANNEL_NUM_STATES
);
744 struct mlx5e_channels
{
745 struct mlx5e_channel
**c
;
747 struct mlx5e_params params
;
750 struct mlx5e_channel_stats
{
751 struct mlx5e_ch_stats ch
;
752 struct mlx5e_sq_stats sq
[MLX5E_MAX_NUM_TC
];
753 struct mlx5e_rq_stats rq
;
754 struct mlx5e_rq_stats xskrq
;
755 struct mlx5e_xdpsq_stats rq_xdpsq
;
756 struct mlx5e_xdpsq_stats xdpsq
;
757 struct mlx5e_xdpsq_stats xsksq
;
758 } ____cacheline_aligned_in_smp
;
762 MLX5E_STATE_DESTROYING
,
763 MLX5E_STATE_XDP_TX_ENABLED
,
764 MLX5E_STATE_XDP_ACTIVE
,
774 struct mlx5e_rqt rqt
;
775 struct list_head list
;
783 struct mlx5e_rss_params
{
784 u32 indirection_rqt
[MLX5E_INDIR_RQT_SIZE
];
785 u32 rx_hash_fields
[MLX5E_NUM_INDIR_TIRS
];
786 u8 toeplitz_hash_key
[40];
790 struct mlx5e_modify_sq_param
{
797 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
798 struct mlx5e_hv_vhca_stats_agent
{
799 struct mlx5_hv_vhca_agent
*agent
;
800 struct delayed_work work
;
807 /* UMEMs are stored separately from channels, because we don't want to
808 * lose them when channels are recreated. The kernel also stores UMEMs,
809 * but it doesn't distinguish between zero-copy and non-zero-copy UMEMs,
810 * so rely on our mechanism.
812 struct xdp_umem
**umems
;
817 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
818 * initialized, and used where we can't allocate them because that functions
819 * must not fail. Use with care and make sure the same variable is not used
820 * simultaneously by multiple users.
822 struct mlx5e_scratchpad
{
823 cpumask_var_t cpumask
;
827 /* priv data path fields - start */
828 struct mlx5e_txqsq
*txq2sq
[MLX5E_MAX_NUM_CHANNELS
* MLX5E_MAX_NUM_TC
];
829 int channel_tc2realtxq
[MLX5E_MAX_NUM_CHANNELS
][MLX5E_MAX_NUM_TC
];
830 #ifdef CONFIG_MLX5_CORE_EN_DCB
831 struct mlx5e_dcbx_dp dcbx_dp
;
833 /* priv data path fields - end */
837 struct mutex state_lock
; /* Protects Interface state */
838 struct mlx5e_rq drop_rq
;
840 struct mlx5e_channels channels
;
841 u32 tisn
[MLX5_MAX_PORTS
][MLX5E_MAX_NUM_TC
];
842 struct mlx5e_rqt indir_rqt
;
843 struct mlx5e_tir indir_tir
[MLX5E_NUM_INDIR_TIRS
];
844 struct mlx5e_tir inner_indir_tir
[MLX5E_NUM_INDIR_TIRS
];
845 struct mlx5e_tir direct_tir
[MLX5E_MAX_NUM_CHANNELS
];
846 struct mlx5e_tir xsk_tir
[MLX5E_MAX_NUM_CHANNELS
];
847 struct mlx5e_rss_params rss_params
;
848 u32 tx_rates
[MLX5E_MAX_NUM_SQS
];
850 struct mlx5e_flow_steering fs
;
852 struct workqueue_struct
*wq
;
853 struct work_struct update_carrier_work
;
854 struct work_struct set_rx_mode_work
;
855 struct work_struct tx_timeout_work
;
856 struct work_struct update_stats_work
;
857 struct work_struct monitor_counters_work
;
858 struct mlx5_nb monitor_counters_nb
;
860 struct mlx5_core_dev
*mdev
;
861 struct net_device
*netdev
;
862 struct mlx5e_stats stats
;
863 struct mlx5e_channel_stats channel_stats
[MLX5E_MAX_NUM_CHANNELS
];
866 struct hwtstamp_config tstamp
;
868 u16 drop_rq_q_counter
;
869 struct notifier_block events_nb
;
871 #ifdef CONFIG_MLX5_CORE_EN_DCB
872 struct mlx5e_dcbx dcbx
;
875 const struct mlx5e_profile
*profile
;
877 #ifdef CONFIG_MLX5_EN_IPSEC
878 struct mlx5e_ipsec
*ipsec
;
880 #ifdef CONFIG_MLX5_EN_TLS
881 struct mlx5e_tls
*tls
;
883 struct devlink_health_reporter
*tx_reporter
;
884 struct devlink_health_reporter
*rx_reporter
;
885 struct devlink_port dl_port
;
886 struct mlx5e_xsk xsk
;
887 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
888 struct mlx5e_hv_vhca_stats_agent stats_agent
;
890 struct mlx5e_scratchpad scratchpad
;
893 struct mlx5e_profile
{
894 int (*init
)(struct mlx5_core_dev
*mdev
,
895 struct net_device
*netdev
,
896 const struct mlx5e_profile
*profile
, void *ppriv
);
897 void (*cleanup
)(struct mlx5e_priv
*priv
);
898 int (*init_rx
)(struct mlx5e_priv
*priv
);
899 void (*cleanup_rx
)(struct mlx5e_priv
*priv
);
900 int (*init_tx
)(struct mlx5e_priv
*priv
);
901 void (*cleanup_tx
)(struct mlx5e_priv
*priv
);
902 void (*enable
)(struct mlx5e_priv
*priv
);
903 void (*disable
)(struct mlx5e_priv
*priv
);
904 int (*update_rx
)(struct mlx5e_priv
*priv
);
905 void (*update_stats
)(struct mlx5e_priv
*priv
);
906 void (*update_carrier
)(struct mlx5e_priv
*priv
);
907 unsigned int (*stats_grps_num
)(struct mlx5e_priv
*priv
);
908 mlx5e_stats_grp_t
*stats_grps
;
910 mlx5e_fp_handle_rx_cqe handle_rx_cqe
;
911 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe
;
917 void mlx5e_build_ptys2ethtool_map(void);
919 u16
mlx5e_select_queue(struct net_device
*dev
, struct sk_buff
*skb
,
920 struct net_device
*sb_dev
);
921 netdev_tx_t
mlx5e_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
922 netdev_tx_t
mlx5e_sq_xmit(struct mlx5e_txqsq
*sq
, struct sk_buff
*skb
,
923 struct mlx5e_tx_wqe
*wqe
, u16 pi
, bool xmit_more
);
925 void mlx5e_trigger_irq(struct mlx5e_icosq
*sq
);
926 void mlx5e_completion_event(struct mlx5_core_cq
*mcq
, struct mlx5_eqe
*eqe
);
927 void mlx5e_cq_error_event(struct mlx5_core_cq
*mcq
, enum mlx5_event event
);
928 int mlx5e_napi_poll(struct napi_struct
*napi
, int budget
);
929 bool mlx5e_poll_tx_cq(struct mlx5e_cq
*cq
, int napi_budget
);
930 int mlx5e_poll_rx_cq(struct mlx5e_cq
*cq
, int budget
);
931 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq
*sq
);
933 static inline u32
mlx5e_rqwq_get_size(struct mlx5e_rq
*rq
)
935 switch (rq
->wq_type
) {
936 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
937 return mlx5_wq_ll_get_size(&rq
->mpwqe
.wq
);
939 return mlx5_wq_cyc_get_size(&rq
->wqe
.wq
);
943 static inline u32
mlx5e_rqwq_get_cur_sz(struct mlx5e_rq
*rq
)
945 switch (rq
->wq_type
) {
946 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
947 return rq
->mpwqe
.wq
.cur_sz
;
949 return rq
->wqe
.wq
.cur_sz
;
953 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev
*mdev
);
954 bool mlx5e_striding_rq_possible(struct mlx5_core_dev
*mdev
,
955 struct mlx5e_params
*params
);
957 void mlx5e_page_dma_unmap(struct mlx5e_rq
*rq
, struct mlx5e_dma_info
*dma_info
);
958 void mlx5e_page_release_dynamic(struct mlx5e_rq
*rq
,
959 struct mlx5e_dma_info
*dma_info
,
961 void mlx5e_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
);
962 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
);
963 bool mlx5e_post_rx_wqes(struct mlx5e_rq
*rq
);
964 int mlx5e_poll_ico_cq(struct mlx5e_cq
*cq
);
965 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq
*rq
);
966 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq
*rq
, u16 ix
);
967 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq
*rq
, u16 ix
);
969 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq
*rq
, struct mlx5e_mpw_info
*wi
,
970 u16 cqe_bcnt
, u32 head_offset
, u32 page_idx
);
972 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq
*rq
, struct mlx5e_mpw_info
*wi
,
973 u16 cqe_bcnt
, u32 head_offset
, u32 page_idx
);
975 mlx5e_skb_from_cqe_linear(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
,
976 struct mlx5e_wqe_frag_info
*wi
, u32 cqe_bcnt
);
978 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
,
979 struct mlx5e_wqe_frag_info
*wi
, u32 cqe_bcnt
);
981 void mlx5e_get_stats(struct net_device
*dev
, struct rtnl_link_stats64
*stats
);
982 void mlx5e_fold_sw_stats64(struct mlx5e_priv
*priv
, struct rtnl_link_stats64
*s
);
984 void mlx5e_init_l2_addr(struct mlx5e_priv
*priv
);
985 int mlx5e_self_test_num(struct mlx5e_priv
*priv
);
986 void mlx5e_self_test(struct net_device
*ndev
, struct ethtool_test
*etest
,
988 void mlx5e_set_rx_mode_work(struct work_struct
*work
);
990 int mlx5e_hwstamp_set(struct mlx5e_priv
*priv
, struct ifreq
*ifr
);
991 int mlx5e_hwstamp_get(struct mlx5e_priv
*priv
, struct ifreq
*ifr
);
992 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv
*priv
, bool val
);
994 int mlx5e_vlan_rx_add_vid(struct net_device
*dev
, __always_unused __be16 proto
,
996 int mlx5e_vlan_rx_kill_vid(struct net_device
*dev
, __always_unused __be16 proto
,
998 void mlx5e_timestamp_init(struct mlx5e_priv
*priv
);
1000 struct mlx5e_redirect_rqt_param
{
1003 u32 rqn
; /* Direct RQN (Non-RSS) */
1006 struct mlx5e_channels
*channels
;
1007 } rss
; /* RSS data */
1011 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, u32 rqtn
, int sz
,
1012 struct mlx5e_redirect_rqt_param rrp
);
1013 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params
*rss_params
,
1014 const struct mlx5e_tirc_config
*ttconfig
,
1015 void *tirc
, bool inner
);
1016 void mlx5e_modify_tirs_hash(struct mlx5e_priv
*priv
, void *in
, int inlen
);
1017 struct mlx5e_tirc_config
mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt
);
1019 struct mlx5e_xsk_param
;
1021 struct mlx5e_rq_param
;
1022 int mlx5e_open_rq(struct mlx5e_channel
*c
, struct mlx5e_params
*params
,
1023 struct mlx5e_rq_param
*param
, struct mlx5e_xsk_param
*xsk
,
1024 struct xdp_umem
*umem
, struct mlx5e_rq
*rq
);
1025 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq
*rq
, int wait_time
);
1026 void mlx5e_deactivate_rq(struct mlx5e_rq
*rq
);
1027 void mlx5e_close_rq(struct mlx5e_rq
*rq
);
1029 struct mlx5e_sq_param
;
1030 int mlx5e_open_icosq(struct mlx5e_channel
*c
, struct mlx5e_params
*params
,
1031 struct mlx5e_sq_param
*param
, struct mlx5e_icosq
*sq
);
1032 void mlx5e_close_icosq(struct mlx5e_icosq
*sq
);
1033 int mlx5e_open_xdpsq(struct mlx5e_channel
*c
, struct mlx5e_params
*params
,
1034 struct mlx5e_sq_param
*param
, struct xdp_umem
*umem
,
1035 struct mlx5e_xdpsq
*sq
, bool is_redirect
);
1036 void mlx5e_close_xdpsq(struct mlx5e_xdpsq
*sq
);
1038 struct mlx5e_cq_param
;
1039 int mlx5e_open_cq(struct mlx5e_channel
*c
, struct dim_cq_moder moder
,
1040 struct mlx5e_cq_param
*param
, struct mlx5e_cq
*cq
);
1041 void mlx5e_close_cq(struct mlx5e_cq
*cq
);
1043 int mlx5e_open_locked(struct net_device
*netdev
);
1044 int mlx5e_close_locked(struct net_device
*netdev
);
1046 int mlx5e_open_channels(struct mlx5e_priv
*priv
,
1047 struct mlx5e_channels
*chs
);
1048 void mlx5e_close_channels(struct mlx5e_channels
*chs
);
1050 /* Function pointer to be used to modify HW or kernel settings while
1051 * switching channels
1053 typedef int (*mlx5e_fp_preactivate
)(struct mlx5e_priv
*priv
, void *context
);
1054 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1055 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1059 int mlx5e_safe_reopen_channels(struct mlx5e_priv
*priv
);
1060 int mlx5e_safe_switch_channels(struct mlx5e_priv
*priv
,
1061 struct mlx5e_channels
*new_chs
,
1062 mlx5e_fp_preactivate preactivate
,
1064 int mlx5e_num_channels_changed(struct mlx5e_priv
*priv
);
1065 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv
*priv
, void *context
);
1066 void mlx5e_activate_priv_channels(struct mlx5e_priv
*priv
);
1067 void mlx5e_deactivate_priv_channels(struct mlx5e_priv
*priv
);
1069 void mlx5e_build_default_indir_rqt(u32
*indirection_rqt
, int len
,
1071 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params
*params
,
1073 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params
*params
,
1075 void mlx5e_set_rq_type(struct mlx5_core_dev
*mdev
, struct mlx5e_params
*params
);
1076 void mlx5e_init_rq_type_params(struct mlx5_core_dev
*mdev
,
1077 struct mlx5e_params
*params
);
1078 int mlx5e_modify_rq_state(struct mlx5e_rq
*rq
, int curr_state
, int next_state
);
1079 void mlx5e_activate_rq(struct mlx5e_rq
*rq
);
1080 void mlx5e_deactivate_rq(struct mlx5e_rq
*rq
);
1081 void mlx5e_free_rx_descs(struct mlx5e_rq
*rq
);
1082 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq
*rq
);
1083 void mlx5e_activate_icosq(struct mlx5e_icosq
*icosq
);
1084 void mlx5e_deactivate_icosq(struct mlx5e_icosq
*icosq
);
1086 int mlx5e_modify_sq(struct mlx5_core_dev
*mdev
, u32 sqn
,
1087 struct mlx5e_modify_sq_param
*p
);
1088 void mlx5e_activate_txqsq(struct mlx5e_txqsq
*sq
);
1089 void mlx5e_tx_disable_queue(struct netdev_queue
*txq
);
1091 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev
*mdev
)
1093 return MLX5_CAP_ETH(mdev
, swp
) &&
1094 MLX5_CAP_ETH(mdev
, swp_csum
) && MLX5_CAP_ETH(mdev
, swp_lso
);
1097 extern const struct ethtool_ops mlx5e_ethtool_ops
;
1098 #ifdef CONFIG_MLX5_CORE_EN_DCB
1099 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops
;
1100 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv
*priv
, struct ieee_ets
*ets
);
1101 void mlx5e_dcbnl_initialize(struct mlx5e_priv
*priv
);
1102 void mlx5e_dcbnl_init_app(struct mlx5e_priv
*priv
);
1103 void mlx5e_dcbnl_delete_app(struct mlx5e_priv
*priv
);
1106 int mlx5e_create_tir(struct mlx5_core_dev
*mdev
,
1107 struct mlx5e_tir
*tir
, u32
*in
, int inlen
);
1108 void mlx5e_destroy_tir(struct mlx5_core_dev
*mdev
,
1109 struct mlx5e_tir
*tir
);
1110 int mlx5e_create_mdev_resources(struct mlx5_core_dev
*mdev
);
1111 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev
*mdev
);
1112 int mlx5e_refresh_tirs(struct mlx5e_priv
*priv
, bool enable_uc_lb
);
1114 /* common netdev helpers */
1115 void mlx5e_create_q_counters(struct mlx5e_priv
*priv
);
1116 void mlx5e_destroy_q_counters(struct mlx5e_priv
*priv
);
1117 int mlx5e_open_drop_rq(struct mlx5e_priv
*priv
,
1118 struct mlx5e_rq
*drop_rq
);
1119 void mlx5e_close_drop_rq(struct mlx5e_rq
*drop_rq
);
1121 int mlx5e_create_indirect_rqt(struct mlx5e_priv
*priv
);
1123 int mlx5e_create_indirect_tirs(struct mlx5e_priv
*priv
, bool inner_ttc
);
1124 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv
*priv
, bool inner_ttc
);
1126 int mlx5e_create_direct_rqts(struct mlx5e_priv
*priv
, struct mlx5e_tir
*tirs
);
1127 void mlx5e_destroy_direct_rqts(struct mlx5e_priv
*priv
, struct mlx5e_tir
*tirs
);
1128 int mlx5e_create_direct_tirs(struct mlx5e_priv
*priv
, struct mlx5e_tir
*tirs
);
1129 void mlx5e_destroy_direct_tirs(struct mlx5e_priv
*priv
, struct mlx5e_tir
*tirs
);
1130 void mlx5e_destroy_rqt(struct mlx5e_priv
*priv
, struct mlx5e_rqt
*rqt
);
1132 int mlx5e_create_tis(struct mlx5_core_dev
*mdev
, void *in
, u32
*tisn
);
1133 void mlx5e_destroy_tis(struct mlx5_core_dev
*mdev
, u32 tisn
);
1135 int mlx5e_create_tises(struct mlx5e_priv
*priv
);
1136 void mlx5e_destroy_tises(struct mlx5e_priv
*priv
);
1137 int mlx5e_update_nic_rx(struct mlx5e_priv
*priv
);
1138 void mlx5e_update_carrier(struct mlx5e_priv
*priv
);
1139 int mlx5e_close(struct net_device
*netdev
);
1140 int mlx5e_open(struct net_device
*netdev
);
1141 void mlx5e_update_ndo_stats(struct mlx5e_priv
*priv
);
1143 void mlx5e_queue_update_stats(struct mlx5e_priv
*priv
);
1144 int mlx5e_bits_invert(unsigned long a
, int size
);
1146 int mlx5e_set_dev_port_mtu(struct mlx5e_priv
*priv
);
1147 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv
*priv
, void *context
);
1148 int mlx5e_change_mtu(struct net_device
*netdev
, int new_mtu
,
1149 mlx5e_fp_preactivate preactivate
);
1151 /* ethtool helpers */
1152 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv
*priv
,
1153 struct ethtool_drvinfo
*drvinfo
);
1154 void mlx5e_ethtool_get_strings(struct mlx5e_priv
*priv
,
1155 uint32_t stringset
, uint8_t *data
);
1156 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv
*priv
, int sset
);
1157 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv
*priv
,
1158 struct ethtool_stats
*stats
, u64
*data
);
1159 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv
*priv
,
1160 struct ethtool_ringparam
*param
);
1161 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv
*priv
,
1162 struct ethtool_ringparam
*param
);
1163 void mlx5e_ethtool_get_channels(struct mlx5e_priv
*priv
,
1164 struct ethtool_channels
*ch
);
1165 int mlx5e_ethtool_set_channels(struct mlx5e_priv
*priv
,
1166 struct ethtool_channels
*ch
);
1167 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv
*priv
,
1168 struct ethtool_coalesce
*coal
);
1169 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv
*priv
,
1170 struct ethtool_coalesce
*coal
);
1171 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv
*priv
,
1172 struct ethtool_link_ksettings
*link_ksettings
);
1173 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv
*priv
,
1174 const struct ethtool_link_ksettings
*link_ksettings
);
1175 int mlx5e_get_rxfh(struct net_device
*netdev
, u32
*indir
, u8
*key
, u8
*hfunc
);
1176 int mlx5e_set_rxfh(struct net_device
*dev
, const u32
*indir
, const u8
*key
,
1178 int mlx5e_get_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*info
,
1180 int mlx5e_set_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
);
1181 u32
mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv
*priv
);
1182 u32
mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv
*priv
);
1183 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv
*priv
,
1184 struct ethtool_ts_info
*info
);
1185 int mlx5e_ethtool_flash_device(struct mlx5e_priv
*priv
,
1186 struct ethtool_flash
*flash
);
1187 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv
*priv
,
1188 struct ethtool_pauseparam
*pauseparam
);
1189 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv
*priv
,
1190 struct ethtool_pauseparam
*pauseparam
);
1192 /* mlx5e generic netdev management API */
1193 int mlx5e_netdev_init(struct net_device
*netdev
,
1194 struct mlx5e_priv
*priv
,
1195 struct mlx5_core_dev
*mdev
,
1196 const struct mlx5e_profile
*profile
,
1198 void mlx5e_netdev_cleanup(struct net_device
*netdev
, struct mlx5e_priv
*priv
);
1200 mlx5e_create_netdev(struct mlx5_core_dev
*mdev
, const struct mlx5e_profile
*profile
,
1201 int nch
, void *ppriv
);
1202 int mlx5e_attach_netdev(struct mlx5e_priv
*priv
);
1203 void mlx5e_detach_netdev(struct mlx5e_priv
*priv
);
1204 void mlx5e_destroy_netdev(struct mlx5e_priv
*priv
);
1205 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv
*priv
);
1206 void mlx5e_build_nic_params(struct mlx5e_priv
*priv
,
1207 struct mlx5e_xsk
*xsk
,
1208 struct mlx5e_rss_params
*rss_params
,
1209 struct mlx5e_params
*params
,
1211 void mlx5e_build_rq_params(struct mlx5_core_dev
*mdev
,
1212 struct mlx5e_params
*params
);
1213 void mlx5e_build_rss_params(struct mlx5e_rss_params
*rss_params
,
1215 void mlx5e_rx_dim_work(struct work_struct
*work
);
1216 void mlx5e_tx_dim_work(struct work_struct
*work
);
1218 void mlx5e_add_vxlan_port(struct net_device
*netdev
, struct udp_tunnel_info
*ti
);
1219 void mlx5e_del_vxlan_port(struct net_device
*netdev
, struct udp_tunnel_info
*ti
);
1220 netdev_features_t
mlx5e_features_check(struct sk_buff
*skb
,
1221 struct net_device
*netdev
,
1222 netdev_features_t features
);
1223 int mlx5e_set_features(struct net_device
*netdev
, netdev_features_t features
);
1224 #ifdef CONFIG_MLX5_ESWITCH
1225 int mlx5e_set_vf_mac(struct net_device
*dev
, int vf
, u8
*mac
);
1226 int mlx5e_set_vf_rate(struct net_device
*dev
, int vf
, int min_tx_rate
, int max_tx_rate
);
1227 int mlx5e_get_vf_config(struct net_device
*dev
, int vf
, struct ifla_vf_info
*ivi
);
1228 int mlx5e_get_vf_stats(struct net_device
*dev
, int vf
, struct ifla_vf_stats
*vf_stats
);
1230 #endif /* __MLX5_EN_H__ */