drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c

   1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2 /* Copyright (c) 2020, Mellanox Technologies inc.  All rights reserved. */
   3
   4 #include <devlink.h>
   5
   6 #include "fw_reset.h"
   7 #include "diag/fw_tracer.h"
   8 #include "lib/tout.h"
   9
  10 enum {
  11         MLX5_FW_RESET_FLAGS_RESET_REQUESTED,
  12         MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
  13         MLX5_FW_RESET_FLAGS_PENDING_COMP,
  14         MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS,
  15         MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED
  16 };
  17
  18 struct mlx5_fw_reset {
  19         struct mlx5_core_dev *dev;
  20         struct mlx5_nb nb;
  21         struct workqueue_struct *wq;
  22         struct work_struct fw_live_patch_work;
  23         struct work_struct reset_request_work;
  24         struct work_struct reset_unload_work;
  25         struct work_struct reset_reload_work;
  26         struct work_struct reset_now_work;
  27         struct work_struct reset_abort_work;
  28         unsigned long reset_flags;
  29         struct timer_list timer;
  30         struct completion done;
  31         int ret;
  32 };
  33
  34 enum {
  35         MLX5_FW_RST_STATE_IDLE = 0,
  36         MLX5_FW_RST_STATE_TOGGLE_REQ = 4,
  37 };
  38
  39 enum {
  40         MLX5_RST_STATE_BIT_NUM = 12,
  41         MLX5_RST_ACK_BIT_NUM = 22,
  42 };
  43
  44 static u8 mlx5_get_fw_rst_state(struct mlx5_core_dev *dev)
  45 {
  46         return (ioread32be(&dev->iseg->initializing) >> MLX5_RST_STATE_BIT_NUM) & 0xF;
  47 }
  48
  49 static void mlx5_set_fw_rst_ack(struct mlx5_core_dev *dev)
  50 {
  51         iowrite32be(BIT(MLX5_RST_ACK_BIT_NUM), &dev->iseg->initializing);
  52 }
  53
  54 static int mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink *devlink, u32 id,
  55                                                      struct devlink_param_gset_ctx *ctx)
  56 {
  57         struct mlx5_core_dev *dev = devlink_priv(devlink);
  58         struct mlx5_fw_reset *fw_reset;
  59
  60         fw_reset = dev->priv.fw_reset;
  61
  62         if (ctx->val.vbool)
  63                 clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
  64         else
  65                 set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
  66         return 0;
  67 }
  68
  69 static int mlx5_fw_reset_enable_remote_dev_reset_get(struct devlink *devlink, u32 id,
  70                                                      struct devlink_param_gset_ctx *ctx)
  71 {
  72         struct mlx5_core_dev *dev = devlink_priv(devlink);
  73         struct mlx5_fw_reset *fw_reset;
  74
  75         fw_reset = dev->priv.fw_reset;
  76
  77         ctx->val.vbool = !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
  78                                    &fw_reset->reset_flags);
  79         return 0;
  80 }
  81
  82 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level,
  83                              u8 reset_type_sel, u8 sync_resp, bool sync_start)
  84 {
  85         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
  86         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
  87
  88         MLX5_SET(mfrl_reg, in, reset_level, reset_level);
  89         MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
  90         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp);
  91         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start);
  92
  93         return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1);
  94 }
  95
  96 static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level,
  97                                u8 *reset_type, u8 *reset_state)
  98 {
  99         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 100         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 101         int err;
 102
 103         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0);
 104         if (err)
 105                 return err;
 106
 107         if (reset_level)
 108                 *reset_level = MLX5_GET(mfrl_reg, out, reset_level);
 109         if (reset_type)
 110                 *reset_type = MLX5_GET(mfrl_reg, out, reset_type);
 111         if (reset_state)
 112                 *reset_state = MLX5_GET(mfrl_reg, out, reset_state);
 113
 114         return 0;
 115 }
 116
 117 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type)
 118 {
 119         return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL);
 120 }
 121
 122 static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev,
 123                                              struct netlink_ext_ack *extack)
 124 {
 125         u8 reset_state;
 126
 127         if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state))
 128                 goto out;
 129
 130         if (!reset_state)
 131                 return 0;
 132
 133         switch (reset_state) {
 134         case MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION:
 135         case MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS:
 136                 NL_SET_ERR_MSG_MOD(extack, "Sync reset still in progress");
 137                 return -EBUSY;
 138         case MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT:
 139                 NL_SET_ERR_MSG_MOD(extack, "Sync reset negotiation timeout");
 140                 return -ETIMEDOUT;
 141         case MLX5_MFRL_REG_RESET_STATE_NACK:
 142                 NL_SET_ERR_MSG_MOD(extack, "One of the hosts disabled reset");
 143                 return -EPERM;
 144         case MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT:
 145                 NL_SET_ERR_MSG_MOD(extack, "Sync reset unload timeout");
 146                 return -ETIMEDOUT;
 147         }
 148
 149 out:
 150         NL_SET_ERR_MSG_MOD(extack, "Sync reset failed");
 151         return -EIO;
 152 }
 153
 154 int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel,
 155                                  struct netlink_ext_ack *extack)
 156 {
 157         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 158         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 159         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 160         int err, rst_res;
 161
 162         set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 163
 164         MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3);
 165         MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
 166         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1);
 167         err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out),
 168                               MLX5_REG_MFRL, 0, 1, false);
 169         if (!err)
 170                 return 0;
 171
 172         clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 173         if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state)) {
 174                 rst_res = mlx5_fw_reset_get_reset_state_err(dev, extack);
 175                 return rst_res ? rst_res : err;
 176         }
 177
 178         NL_SET_ERR_MSG_MOD(extack, "Sync reset command failed");
 179         return mlx5_cmd_check(dev, err, in, out);
 180 }
 181
 182 int mlx5_fw_reset_verify_fw_complete(struct mlx5_core_dev *dev,
 183                                      struct netlink_ext_ack *extack)
 184 {
 185         u8 rst_state;
 186         int err;
 187
 188         err = mlx5_fw_reset_get_reset_state_err(dev, extack);
 189         if (err)
 190                 return err;
 191
 192         rst_state = mlx5_get_fw_rst_state(dev);
 193         if (!rst_state)
 194                 return 0;
 195
 196         mlx5_core_err(dev, "Sync reset did not complete, state=%d\n", rst_state);
 197         NL_SET_ERR_MSG_MOD(extack, "Sync reset did not complete successfully");
 198         return rst_state;
 199 }
 200
 201 int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev)
 202 {
 203         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false);
 204 }
 205
 206 static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev, bool unloaded)
 207 {
 208         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 209
 210         /* if this is the driver that initiated the fw reset, devlink completed the reload */
 211         if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
 212                 complete(&fw_reset->done);
 213         } else {
 214                 if (!unloaded)
 215                         mlx5_unload_one(dev, false);
 216                 if (mlx5_health_wait_pci_up(dev))
 217                         mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
 218                 else
 219                         mlx5_load_one(dev, true);
 220                 devlink_remote_reload_actions_performed(priv_to_devlink(dev), 0,
 221                                                         BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
 222                                                         BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));
 223         }
 224 }
 225
 226 static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
 227 {
 228         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 229
 230         del_timer_sync(&fw_reset->timer);
 231 }
 232
 233 static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health)
 234 {
 235         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 236
 237         if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
 238                 mlx5_core_warn(dev, "Reset request was already cleared\n");
 239                 return -EALREADY;
 240         }
 241
 242         mlx5_stop_sync_reset_poll(dev);
 243         if (poll_health)
 244                 mlx5_start_health_poll(dev);
 245         return 0;
 246 }
 247
 248 static void mlx5_sync_reset_reload_work(struct work_struct *work)
 249 {
 250         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 251                                                       reset_reload_work);
 252         struct mlx5_core_dev *dev = fw_reset->dev;
 253
 254         mlx5_sync_reset_clear_reset_requested(dev, false);
 255         mlx5_enter_error_state(dev, true);
 256         mlx5_fw_reset_complete_reload(dev, false);
 257 }
 258
 259 #define MLX5_RESET_POLL_INTERVAL        (HZ / 10)
 260 static void poll_sync_reset(struct timer_list *t)
 261 {
 262         struct mlx5_fw_reset *fw_reset = from_timer(fw_reset, t, timer);
 263         struct mlx5_core_dev *dev = fw_reset->dev;
 264         u32 fatal_error;
 265
 266         if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
 267                 return;
 268
 269         fatal_error = mlx5_health_check_fatal_sensors(dev);
 270
 271         if (fatal_error) {
 272                 mlx5_core_warn(dev, "Got Device Reset\n");
 273                 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
 274                         queue_work(fw_reset->wq, &fw_reset->reset_reload_work);
 275                 else
 276                         mlx5_core_err(dev, "Device is being removed, Drop new reset work\n");
 277                 return;
 278         }
 279
 280         mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL));
 281 }
 282
 283 static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev)
 284 {
 285         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 286
 287         timer_setup(&fw_reset->timer, poll_sync_reset, 0);
 288         fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL);
 289         add_timer(&fw_reset->timer);
 290 }
 291
 292 static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev)
 293 {
 294         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false);
 295 }
 296
 297 static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev)
 298 {
 299         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false);
 300 }
 301
 302 static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev)
 303 {
 304         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 305
 306         if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
 307                 mlx5_core_warn(dev, "Reset request was already set\n");
 308                 return -EALREADY;
 309         }
 310         mlx5_stop_health_poll(dev, true);
 311         mlx5_start_sync_reset_poll(dev);
 312         return 0;
 313 }
 314
 315 static void mlx5_fw_live_patch_event(struct work_struct *work)
 316 {
 317         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 318                                                       fw_live_patch_work);
 319         struct mlx5_core_dev *dev = fw_reset->dev;
 320
 321         mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev),
 322                        fw_rev_min(dev), fw_rev_sub(dev));
 323
 324         if (mlx5_fw_tracer_reload(dev->tracer))
 325                 mlx5_core_err(dev, "Failed to reload FW tracer\n");
 326 }
 327
 328 #if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)
 329 static int mlx5_check_hotplug_interrupt(struct mlx5_core_dev *dev)
 330 {
 331         struct pci_dev *bridge = dev->pdev->bus->self;
 332         u16 reg16;
 333         int err;
 334
 335         if (!bridge)
 336                 return -EOPNOTSUPP;
 337
 338         err = pcie_capability_read_word(bridge, PCI_EXP_SLTCTL, &reg16);
 339         if (err)
 340                 return err;
 341
 342         if ((reg16 & PCI_EXP_SLTCTL_HPIE) && (reg16 & PCI_EXP_SLTCTL_DLLSCE)) {
 343                 mlx5_core_warn(dev, "FW reset is not supported as HotPlug is enabled\n");
 344                 return -EOPNOTSUPP;
 345         }
 346
 347         return 0;
 348 }
 349 #endif
 350
 351 static int mlx5_check_dev_ids(struct mlx5_core_dev *dev, u16 dev_id)
 352 {
 353         struct pci_bus *bridge_bus = dev->pdev->bus;
 354         struct pci_dev *sdev;
 355         u16 sdev_id;
 356         int err;
 357
 358         /* Check that all functions under the pci bridge are PFs of
 359          * this device otherwise fail this function.
 360          */
 361         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 362                 err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id);
 363                 if (err)
 364                         return pcibios_err_to_errno(err);
 365                 if (sdev_id != dev_id) {
 366                         mlx5_core_warn(dev, "unrecognized dev_id (0x%x)\n", sdev_id);
 367                         return -EPERM;
 368                 }
 369         }
 370         return 0;
 371 }
 372
 373 static bool mlx5_is_reset_now_capable(struct mlx5_core_dev *dev)
 374 {
 375         u16 dev_id;
 376         int err;
 377
 378         if (!MLX5_CAP_GEN(dev, fast_teardown)) {
 379                 mlx5_core_warn(dev, "fast teardown is not supported by firmware\n");
 380                 return false;
 381         }
 382
 383 #if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)
 384         err = mlx5_check_hotplug_interrupt(dev);
 385         if (err)
 386                 return false;
 387 #endif
 388
 389         err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
 390         if (err)
 391                 return false;
 392         return (!mlx5_check_dev_ids(dev, dev_id));
 393 }
 394
 395 static void mlx5_sync_reset_request_event(struct work_struct *work)
 396 {
 397         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 398                                                       reset_request_work);
 399         struct mlx5_core_dev *dev = fw_reset->dev;
 400         int err;
 401
 402         if (test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags) ||
 403             !mlx5_is_reset_now_capable(dev)) {
 404                 err = mlx5_fw_reset_set_reset_sync_nack(dev);
 405                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s",
 406                                err ? "Failed" : "Sent");
 407                 return;
 408         }
 409         if (mlx5_sync_reset_set_reset_requested(dev))
 410                 return;
 411
 412         err = mlx5_fw_reset_set_reset_sync_ack(dev);
 413         if (err)
 414                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err);
 415         else
 416                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n");
 417 }
 418
 419 static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev)
 420 {
 421         struct pci_bus *bridge_bus = dev->pdev->bus;
 422         struct pci_dev *bridge = bridge_bus->self;
 423         unsigned long timeout;
 424         struct pci_dev *sdev;
 425         u16 reg16, dev_id;
 426         int cap, err;
 427
 428         err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
 429         if (err)
 430                 return pcibios_err_to_errno(err);
 431         err = mlx5_check_dev_ids(dev, dev_id);
 432         if (err)
 433                 return err;
 434         cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
 435         if (!cap)
 436                 return -EOPNOTSUPP;
 437
 438         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 439                 pci_save_state(sdev);
 440                 pci_cfg_access_lock(sdev);
 441         }
 442         /* PCI link toggle */
 443         err = pcie_capability_set_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD);
 444         if (err)
 445                 return pcibios_err_to_errno(err);
 446         msleep(500);
 447         err = pcie_capability_clear_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD);
 448         if (err)
 449                 return pcibios_err_to_errno(err);
 450
 451         /* Check link */
 452         if (!bridge->link_active_reporting) {
 453                 mlx5_core_warn(dev, "No PCI link reporting capability\n");
 454                 msleep(1000);
 455                 goto restore;
 456         }
 457
 458         timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, PCI_TOGGLE));
 459         do {
 460                 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, &reg16);
 461                 if (err)
 462                         return pcibios_err_to_errno(err);
 463                 if (reg16 & PCI_EXP_LNKSTA_DLLLA)
 464                         break;
 465                 msleep(20);
 466         } while (!time_after(jiffies, timeout));
 467
 468         if (reg16 & PCI_EXP_LNKSTA_DLLLA) {
 469                 mlx5_core_info(dev, "PCI Link up\n");
 470         } else {
 471                 mlx5_core_err(dev, "PCI link not ready (0x%04x) after %llu ms\n",
 472                               reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
 473                 err = -ETIMEDOUT;
 474                 goto restore;
 475         }
 476
 477         do {
 478                 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &reg16);
 479                 if (err)
 480                         return pcibios_err_to_errno(err);
 481                 if (reg16 == dev_id)
 482                         break;
 483                 msleep(20);
 484         } while (!time_after(jiffies, timeout));
 485
 486         if (reg16 == dev_id) {
 487                 mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n");
 488         } else {
 489                 mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n",
 490                               reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
 491                 err = -ETIMEDOUT;
 492         }
 493
 494 restore:
 495         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 496                 pci_cfg_access_unlock(sdev);
 497                 pci_restore_state(sdev);
 498         }
 499
 500         return err;
 501 }
 502
 503 static void mlx5_sync_reset_now_event(struct work_struct *work)
 504 {
 505         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 506                                                       reset_now_work);
 507         struct mlx5_core_dev *dev = fw_reset->dev;
 508         int err;
 509
 510         if (mlx5_sync_reset_clear_reset_requested(dev, false))
 511                 return;
 512
 513         mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n");
 514
 515         err = mlx5_cmd_fast_teardown_hca(dev);
 516         if (err) {
 517                 mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err);
 518                 goto done;
 519         }
 520
 521         err = mlx5_pci_link_toggle(dev);
 522         if (err) {
 523                 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, no reset done, err %d\n", err);
 524                 set_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags);
 525         }
 526
 527         mlx5_enter_error_state(dev, true);
 528 done:
 529         fw_reset->ret = err;
 530         mlx5_fw_reset_complete_reload(dev, false);
 531 }
 532
 533 static void mlx5_sync_reset_unload_event(struct work_struct *work)
 534 {
 535         struct mlx5_fw_reset *fw_reset;
 536         struct mlx5_core_dev *dev;
 537         unsigned long timeout;
 538         bool reset_action;
 539         u8 rst_state;
 540         int err;
 541
 542         fw_reset = container_of(work, struct mlx5_fw_reset, reset_unload_work);
 543         dev = fw_reset->dev;
 544
 545         if (mlx5_sync_reset_clear_reset_requested(dev, false))
 546                 return;
 547
 548         mlx5_core_warn(dev, "Sync Reset Unload. Function is forced down.\n");
 549
 550         err = mlx5_cmd_fast_teardown_hca(dev);
 551         if (err)
 552                 mlx5_core_warn(dev, "Fast teardown failed, unloading, err %d\n", err);
 553         else
 554                 mlx5_enter_error_state(dev, true);
 555
 556         if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags))
 557                 mlx5_unload_one_devl_locked(dev, false);
 558         else
 559                 mlx5_unload_one(dev, false);
 560
 561         mlx5_set_fw_rst_ack(dev);
 562         mlx5_core_warn(dev, "Sync Reset Unload done, device reset expected\n");
 563
 564         reset_action = false;
 565         timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, RESET_UNLOAD));
 566         do {
 567                 rst_state = mlx5_get_fw_rst_state(dev);
 568                 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ ||
 569                     rst_state == MLX5_FW_RST_STATE_IDLE) {
 570                         reset_action = true;
 571                         break;
 572                 }
 573                 msleep(20);
 574         } while (!time_after(jiffies, timeout));
 575
 576         if (!reset_action) {
 577                 mlx5_core_err(dev, "Got timeout waiting for sync reset action, state = %u\n",
 578                               rst_state);
 579                 fw_reset->ret = -ETIMEDOUT;
 580                 goto done;
 581         }
 582
 583         mlx5_core_warn(dev, "Sync Reset, got reset action. rst_state = %u\n", rst_state);
 584         if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ) {
 585                 err = mlx5_pci_link_toggle(dev);
 586                 if (err) {
 587                         mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, err %d\n", err);
 588                         fw_reset->ret = err;
 589                 }
 590         }
 591
 592 done:
 593         mlx5_fw_reset_complete_reload(dev, true);
 594 }
 595
 596 static void mlx5_sync_reset_abort_event(struct work_struct *work)
 597 {
 598         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 599                                                       reset_abort_work);
 600         struct mlx5_core_dev *dev = fw_reset->dev;
 601
 602         if (mlx5_sync_reset_clear_reset_requested(dev, true))
 603                 return;
 604         mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n");
 605 }
 606
 607 static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe)
 608 {
 609         struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe;
 610         u8 sync_event_rst_type;
 611
 612         sync_fw_update_eqe = &eqe->data.sync_fw_update;
 613         sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK;
 614         switch (sync_event_rst_type) {
 615         case MLX5_SYNC_RST_STATE_RESET_REQUEST:
 616                 queue_work(fw_reset->wq, &fw_reset->reset_request_work);
 617                 break;
 618         case MLX5_SYNC_RST_STATE_RESET_UNLOAD:
 619                 queue_work(fw_reset->wq, &fw_reset->reset_unload_work);
 620                 break;
 621         case MLX5_SYNC_RST_STATE_RESET_NOW:
 622                 queue_work(fw_reset->wq, &fw_reset->reset_now_work);
 623                 break;
 624         case MLX5_SYNC_RST_STATE_RESET_ABORT:
 625                 queue_work(fw_reset->wq, &fw_reset->reset_abort_work);
 626                 break;
 627         }
 628 }
 629
 630 static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data)
 631 {
 632         struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb);
 633         struct mlx5_eqe *eqe = data;
 634
 635         if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
 636                 return NOTIFY_DONE;
 637
 638         switch (eqe->sub_type) {
 639         case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT:
 640                 queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work);
 641                 break;
 642         case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT:
 643                 mlx5_sync_reset_events_handle(fw_reset, eqe);
 644                 break;
 645         default:
 646                 return NOTIFY_DONE;
 647         }
 648
 649         return NOTIFY_OK;
 650 }
 651
 652 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev)
 653 {
 654         unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE);
 655         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 656         unsigned long timeout;
 657         int err;
 658
 659         if (MLX5_CAP_GEN(dev, pci_sync_for_fw_update_with_driver_unload))
 660                 pci_sync_update_timeout += mlx5_tout_ms(dev, RESET_UNLOAD);
 661         timeout = msecs_to_jiffies(pci_sync_update_timeout);
 662         if (!wait_for_completion_timeout(&fw_reset->done, timeout)) {
 663                 mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n",
 664                                pci_sync_update_timeout / 1000);
 665                 err = -ETIMEDOUT;
 666                 goto out;
 667         }
 668         err = fw_reset->ret;
 669         if (test_and_clear_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags)) {
 670                 mlx5_unload_one_devl_locked(dev, false);
 671                 mlx5_load_one_devl_locked(dev, true);
 672         }
 673 out:
 674         clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 675         return err;
 676 }
 677
 678 void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev)
 679 {
 680         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 681
 682         MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT);
 683         mlx5_eq_notifier_register(dev, &fw_reset->nb);
 684 }
 685
 686 void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev)
 687 {
 688         mlx5_eq_notifier_unregister(dev, &dev->priv.fw_reset->nb);
 689 }
 690
 691 void mlx5_drain_fw_reset(struct mlx5_core_dev *dev)
 692 {
 693         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 694
 695         set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags);
 696         cancel_work_sync(&fw_reset->fw_live_patch_work);
 697         cancel_work_sync(&fw_reset->reset_request_work);
 698         cancel_work_sync(&fw_reset->reset_unload_work);
 699         cancel_work_sync(&fw_reset->reset_reload_work);
 700         cancel_work_sync(&fw_reset->reset_now_work);
 701         cancel_work_sync(&fw_reset->reset_abort_work);
 702 }
 703
 704 static const struct devlink_param mlx5_fw_reset_devlink_params[] = {
 705         DEVLINK_PARAM_GENERIC(ENABLE_REMOTE_DEV_RESET, BIT(DEVLINK_PARAM_CMODE_RUNTIME),
 706                               mlx5_fw_reset_enable_remote_dev_reset_get,
 707                               mlx5_fw_reset_enable_remote_dev_reset_set, NULL),
 708 };
 709
 710 int mlx5_fw_reset_init(struct mlx5_core_dev *dev)
 711 {
 712         struct mlx5_fw_reset *fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL);
 713         int err;
 714
 715         if (!fw_reset)
 716                 return -ENOMEM;
 717         fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events");
 718         if (!fw_reset->wq) {
 719                 kfree(fw_reset);
 720                 return -ENOMEM;
 721         }
 722
 723         fw_reset->dev = dev;
 724         dev->priv.fw_reset = fw_reset;
 725
 726         err = devl_params_register(priv_to_devlink(dev),
 727                                    mlx5_fw_reset_devlink_params,
 728                                    ARRAY_SIZE(mlx5_fw_reset_devlink_params));
 729         if (err) {
 730                 destroy_workqueue(fw_reset->wq);
 731                 kfree(fw_reset);
 732                 return err;
 733         }
 734
 735         INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event);
 736         INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event);
 737         INIT_WORK(&fw_reset->reset_unload_work, mlx5_sync_reset_unload_event);
 738         INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work);
 739         INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event);
 740         INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event);
 741
 742         init_completion(&fw_reset->done);
 743         return 0;
 744 }
 745
 746 void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev)
 747 {
 748         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 749
 750         devl_params_unregister(priv_to_devlink(dev),
 751                                mlx5_fw_reset_devlink_params,
 752                                ARRAY_SIZE(mlx5_fw_reset_devlink_params));
 753         destroy_workqueue(fw_reset->wq);
 754         kfree(dev->priv.fw_reset);
 755 }