]> git.ipfire.org Git - thirdparty/kernel/linux.git/blob - drivers/net/ethernet/mellanox/mlx5/core/main.c
projects / thirdparty / kernel / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'sg_nents' into rdma.git for-next
[thirdparty/kernel/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
52 #endif
53 #include <linux/version.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
56 #include "lib/eq.h"
57 #include "fs_core.h"
58 #include "lib/mpfs.h"
59 #include "eswitch.h"
60 #include "devlink.h"
61 #include "fw_reset.h"
62 #include "lib/mlx5.h"
63 #include "fpga/core.h"
64 #include "fpga/ipsec.h"
65 #include "accel/ipsec.h"
66 #include "accel/tls.h"
67 #include "lib/clock.h"
68 #include "lib/vxlan.h"
69 #include "lib/geneve.h"
70 #include "lib/devcom.h"
71 #include "lib/pci_vsc.h"
72 #include "diag/fw_tracer.h"
73 #include "ecpf.h"
74 #include "lib/hv_vhca.h"
75 #include "diag/rsc_dump.h"
76 #include "sf/vhca_event.h"
77 #include "sf/dev/dev.h"
78 #include "sf/sf.h"
79 #include "mlx5_irq.h"
80
81 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
82 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
83 MODULE_LICENSE("Dual BSD/GPL");
84
85 unsigned int mlx5_core_debug_mask;
86 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
87 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
88
89 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
90 module_param_named(prof_sel, prof_sel, uint, 0444);
91 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
92
93 static u32 sw_owner_id[4];
94
95 enum {
96 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
97 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
98 };
99
100 static struct mlx5_profile profile[] = {
101 [0] = {
102 .mask = 0,
103 },
104 [1] = {
105 .mask = MLX5_PROF_MASK_QP_SIZE,
106 .log_max_qp = 12,
107 },
108 [2] = {
109 .mask = MLX5_PROF_MASK_QP_SIZE |
110 MLX5_PROF_MASK_MR_CACHE,
111 .log_max_qp = 18,
112 .mr_cache[0] = {
113 .size = 500,
114 .limit = 250
115 },
116 .mr_cache[1] = {
117 .size = 500,
118 .limit = 250
119 },
120 .mr_cache[2] = {
121 .size = 500,
122 .limit = 250
123 },
124 .mr_cache[3] = {
125 .size = 500,
126 .limit = 250
127 },
128 .mr_cache[4] = {
129 .size = 500,
130 .limit = 250
131 },
132 .mr_cache[5] = {
133 .size = 500,
134 .limit = 250
135 },
136 .mr_cache[6] = {
137 .size = 500,
138 .limit = 250
139 },
140 .mr_cache[7] = {
141 .size = 500,
142 .limit = 250
143 },
144 .mr_cache[8] = {
145 .size = 500,
146 .limit = 250
147 },
148 .mr_cache[9] = {
149 .size = 500,
150 .limit = 250
151 },
152 .mr_cache[10] = {
153 .size = 500,
154 .limit = 250
155 },
156 .mr_cache[11] = {
157 .size = 500,
158 .limit = 250
159 },
160 .mr_cache[12] = {
161 .size = 64,
162 .limit = 32
163 },
164 .mr_cache[13] = {
165 .size = 32,
166 .limit = 16
167 },
168 .mr_cache[14] = {
169 .size = 16,
170 .limit = 8
171 },
172 .mr_cache[15] = {
173 .size = 8,
174 .limit = 4
175 },
176 },
177 };
178
179 #define FW_INIT_TIMEOUT_MILI 2000
180 #define FW_INIT_WAIT_MS 2
181 #define FW_PRE_INIT_TIMEOUT_MILI 120000
182 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
183
184 static int fw_initializing(struct mlx5_core_dev *dev)
185 {
186 return ioread32be(&dev->iseg->initializing) >> 31;
187 }
188
189 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
190 u32 warn_time_mili)
191 {
192 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
193 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
194 int err = 0;
195
196 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL);
197
198 while (fw_initializing(dev)) {
199 if (time_after(jiffies, end)) {
200 err = -EBUSY;
201 break;
202 }
203 if (warn_time_mili && time_after(jiffies, warn)) {
204 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
205 jiffies_to_msecs(end - warn) / 1000);
206 warn = jiffies + msecs_to_jiffies(warn_time_mili);
207 }
208 msleep(FW_INIT_WAIT_MS);
209 }
210
211 return err;
212 }
213
214 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
215 {
216 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
217 driver_version);
218 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
219 int remaining_size = driver_ver_sz;
220 char *string;
221
222 if (!MLX5_CAP_GEN(dev, driver_version))
223 return;
224
225 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
226
227 strncpy(string, "Linux", remaining_size);
228
229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
230 strncat(string, ",", remaining_size);
231
232 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
233 strncat(string, KBUILD_MODNAME, remaining_size);
234
235 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
236 strncat(string, ",", remaining_size);
237
238 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
239
240 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
241 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
242 LINUX_VERSION_SUBLEVEL);
243
244 /*Send the command*/
245 MLX5_SET(set_driver_version_in, in, opcode,
246 MLX5_CMD_OP_SET_DRIVER_VERSION);
247
248 mlx5_cmd_exec_in(dev, set_driver_version, in);
249 }
250
251 static int set_dma_caps(struct pci_dev *pdev)
252 {
253 int err;
254
255 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
256 if (err) {
257 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
258 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
259 if (err) {
260 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
261 return err;
262 }
263 }
264
265 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
266 if (err) {
267 dev_warn(&pdev->dev,
268 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
269 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
270 if (err) {
271 dev_err(&pdev->dev,
272 "Can't set consistent PCI DMA mask, aborting\n");
273 return err;
274 }
275 }
276
277 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
278 return err;
279 }
280
281 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
282 {
283 struct pci_dev *pdev = dev->pdev;
284 int err = 0;
285
286 mutex_lock(&dev->pci_status_mutex);
287 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
288 err = pci_enable_device(pdev);
289 if (!err)
290 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
291 }
292 mutex_unlock(&dev->pci_status_mutex);
293
294 return err;
295 }
296
297 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
298 {
299 struct pci_dev *pdev = dev->pdev;
300
301 mutex_lock(&dev->pci_status_mutex);
302 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
303 pci_disable_device(pdev);
304 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
305 }
306 mutex_unlock(&dev->pci_status_mutex);
307 }
308
309 static int request_bar(struct pci_dev *pdev)
310 {
311 int err = 0;
312
313 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
314 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
315 return -ENODEV;
316 }
317
318 err = pci_request_regions(pdev, KBUILD_MODNAME);
319 if (err)
320 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
321
322 return err;
323 }
324
325 static void release_bar(struct pci_dev *pdev)
326 {
327 pci_release_regions(pdev);
328 }
329
330 struct mlx5_reg_host_endianness {
331 u8 he;
332 u8 rsvd[15];
333 };
334
335 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
336
337 enum {
338 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
339 MLX5_DEV_CAP_FLAG_DCT,
340 };
341
342 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
343 {
344 switch (size) {
345 case 128:
346 return 0;
347 case 256:
348 return 1;
349 case 512:
350 return 2;
351 case 1024:
352 return 3;
353 case 2048:
354 return 4;
355 case 4096:
356 return 5;
357 default:
358 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
359 return 0;
360 }
361 }
362
363 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
364 enum mlx5_cap_type cap_type,
365 enum mlx5_cap_mode cap_mode)
366 {
367 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
368 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
369 void *out, *hca_caps;
370 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
371 int err;
372
373 memset(in, 0, sizeof(in));
374 out = kzalloc(out_sz, GFP_KERNEL);
375 if (!out)
376 return -ENOMEM;
377
378 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
379 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
380 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
381 if (err) {
382 mlx5_core_warn(dev,
383 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
384 cap_type, cap_mode, err);
385 goto query_ex;
386 }
387
388 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
389
390 switch (cap_mode) {
391 case HCA_CAP_OPMOD_GET_MAX:
392 memcpy(dev->caps.hca_max[cap_type], hca_caps,
393 MLX5_UN_SZ_BYTES(hca_cap_union));
394 break;
395 case HCA_CAP_OPMOD_GET_CUR:
396 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
397 MLX5_UN_SZ_BYTES(hca_cap_union));
398 break;
399 default:
400 mlx5_core_warn(dev,
401 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
402 cap_type, cap_mode);
403 err = -EINVAL;
404 break;
405 }
406 query_ex:
407 kfree(out);
408 return err;
409 }
410
411 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
412 {
413 int ret;
414
415 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
416 if (ret)
417 return ret;
418 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
419 }
420
421 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
422 {
423 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
424 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
425 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
426 }
427
428 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
429 {
430 void *set_hca_cap;
431 int req_endianness;
432 int err;
433
434 if (!MLX5_CAP_GEN(dev, atomic))
435 return 0;
436
437 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
438 if (err)
439 return err;
440
441 req_endianness =
442 MLX5_CAP_ATOMIC(dev,
443 supported_atomic_req_8B_endianness_mode_1);
444
445 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
446 return 0;
447
448 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
449
450 /* Set requestor to host endianness */
451 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
452 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
453
454 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
455 }
456
457 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
458 {
459 void *set_hca_cap;
460 bool do_set = false;
461 int err;
462
463 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
464 !MLX5_CAP_GEN(dev, pg))
465 return 0;
466
467 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
468 if (err)
469 return err;
470
471 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
472 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP],
473 MLX5_ST_SZ_BYTES(odp_cap));
474
475 #define ODP_CAP_SET_MAX(dev, field) \
476 do { \
477 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
478 if (_res) { \
479 do_set = true; \
480 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
481 } \
482 } while (0)
483
484 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
485 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
486 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
487 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
488 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
489 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
490 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
491 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
492 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
493 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
494 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
495 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
496 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
497 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
498
499 if (!do_set)
500 return 0;
501
502 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
503 }
504
505 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
506 {
507 struct mlx5_profile *prof = &dev->profile;
508 void *set_hca_cap;
509 int err;
510
511 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
512 if (err)
513 return err;
514
515 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
516 capability);
517 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
518 MLX5_ST_SZ_BYTES(cmd_hca_cap));
519
520 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
521 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
522 128);
523 /* we limit the size of the pkey table to 128 entries for now */
524 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
525 to_fw_pkey_sz(dev, 128));
526
527 /* Check log_max_qp from HCA caps to set in current profile */
528 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
529 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
530 prof->log_max_qp,
531 MLX5_CAP_GEN_MAX(dev, log_max_qp));
532 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
533 }
534 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
535 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
536 prof->log_max_qp);
537
538 /* disable cmdif checksum */
539 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
540
541 /* Enable 4K UAR only when HCA supports it and page size is bigger
542 * than 4K.
543 */
544 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
545 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
546
547 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
548
549 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
550 MLX5_SET(cmd_hca_cap,
551 set_hca_cap,
552 cache_line_128byte,
553 cache_line_size() >= 128 ? 1 : 0);
554
555 if (MLX5_CAP_GEN_MAX(dev, dct))
556 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
557
558 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
559 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
560
561 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
562 MLX5_SET(cmd_hca_cap,
563 set_hca_cap,
564 num_vhca_ports,
565 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
566
567 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
568 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
569
570 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
571 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
572
573 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
574
575 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
576 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
577 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
578
579 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
580 }
581
582 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
583 {
584 void *set_hca_cap;
585 int err;
586
587 if (!MLX5_CAP_GEN(dev, roce))
588 return 0;
589
590 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
591 if (err)
592 return err;
593
594 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
595 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
596 return 0;
597
598 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
599 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE],
600 MLX5_ST_SZ_BYTES(roce_cap));
601 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
602
603 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
604 return err;
605 }
606
607 static int set_hca_cap(struct mlx5_core_dev *dev)
608 {
609 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
610 void *set_ctx;
611 int err;
612
613 set_ctx = kzalloc(set_sz, GFP_KERNEL);
614 if (!set_ctx)
615 return -ENOMEM;
616
617 err = handle_hca_cap(dev, set_ctx);
618 if (err) {
619 mlx5_core_err(dev, "handle_hca_cap failed\n");
620 goto out;
621 }
622
623 memset(set_ctx, 0, set_sz);
624 err = handle_hca_cap_atomic(dev, set_ctx);
625 if (err) {
626 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
627 goto out;
628 }
629
630 memset(set_ctx, 0, set_sz);
631 err = handle_hca_cap_odp(dev, set_ctx);
632 if (err) {
633 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
634 goto out;
635 }
636
637 memset(set_ctx, 0, set_sz);
638 err = handle_hca_cap_roce(dev, set_ctx);
639 if (err) {
640 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
641 goto out;
642 }
643
644 out:
645 kfree(set_ctx);
646 return err;
647 }
648
649 static int set_hca_ctrl(struct mlx5_core_dev *dev)
650 {
651 struct mlx5_reg_host_endianness he_in;
652 struct mlx5_reg_host_endianness he_out;
653 int err;
654
655 if (!mlx5_core_is_pf(dev))
656 return 0;
657
658 memset(&he_in, 0, sizeof(he_in));
659 he_in.he = MLX5_SET_HOST_ENDIANNESS;
660 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
661 &he_out, sizeof(he_out),
662 MLX5_REG_HOST_ENDIANNESS, 0, 1);
663 return err;
664 }
665
666 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
667 {
668 int ret = 0;
669
670 /* Disable local_lb by default */
671 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
672 ret = mlx5_nic_vport_update_local_lb(dev, false);
673
674 return ret;
675 }
676
677 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
678 {
679 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
680
681 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
682 MLX5_SET(enable_hca_in, in, function_id, func_id);
683 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
684 dev->caps.embedded_cpu);
685 return mlx5_cmd_exec_in(dev, enable_hca, in);
686 }
687
688 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
689 {
690 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
691
692 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
693 MLX5_SET(disable_hca_in, in, function_id, func_id);
694 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
695 dev->caps.embedded_cpu);
696 return mlx5_cmd_exec_in(dev, disable_hca, in);
697 }
698
699 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
700 {
701 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
702 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
703 u32 sup_issi;
704 int err;
705
706 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
707 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
708 if (err) {
709 u32 syndrome;
710 u8 status;
711
712 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
713 if (!status || syndrome == MLX5_DRIVER_SYND) {
714 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
715 err, status, syndrome);
716 return err;
717 }
718
719 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
720 dev->issi = 0;
721 return 0;
722 }
723
724 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
725
726 if (sup_issi & (1 << 1)) {
727 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
728
729 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
730 MLX5_SET(set_issi_in, set_in, current_issi, 1);
731 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
732 if (err) {
733 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
734 err);
735 return err;
736 }
737
738 dev->issi = 1;
739
740 return 0;
741 } else if (sup_issi & (1 << 0) || !sup_issi) {
742 return 0;
743 }
744
745 return -EOPNOTSUPP;
746 }
747
748 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
749 const struct pci_device_id *id)
750 {
751 struct mlx5_priv *priv = &dev->priv;
752 int err = 0;
753
754 mutex_init(&dev->pci_status_mutex);
755 pci_set_drvdata(dev->pdev, dev);
756
757 dev->bar_addr = pci_resource_start(pdev, 0);
758 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
759
760 err = mlx5_pci_enable_device(dev);
761 if (err) {
762 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
763 return err;
764 }
765
766 err = request_bar(pdev);
767 if (err) {
768 mlx5_core_err(dev, "error requesting BARs, aborting\n");
769 goto err_disable;
770 }
771
772 pci_set_master(pdev);
773
774 err = set_dma_caps(pdev);
775 if (err) {
776 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
777 goto err_clr_master;
778 }
779
780 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
781 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
782 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
783 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
784
785 dev->iseg_base = dev->bar_addr;
786 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
787 if (!dev->iseg) {
788 err = -ENOMEM;
789 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
790 goto err_clr_master;
791 }
792
793 mlx5_pci_vsc_init(dev);
794 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
795 return 0;
796
797 err_clr_master:
798 pci_clear_master(dev->pdev);
799 release_bar(dev->pdev);
800 err_disable:
801 mlx5_pci_disable_device(dev);
802 return err;
803 }
804
805 static void mlx5_pci_close(struct mlx5_core_dev *dev)
806 {
807 /* health work might still be active, and it needs pci bar in
808 * order to know the NIC state. Therefore, drain the health WQ
809 * before removing the pci bars
810 */
811 mlx5_drain_health_wq(dev);
812 iounmap(dev->iseg);
813 pci_clear_master(dev->pdev);
814 release_bar(dev->pdev);
815 mlx5_pci_disable_device(dev);
816 }
817
818 static int mlx5_init_once(struct mlx5_core_dev *dev)
819 {
820 int err;
821
822 dev->priv.devcom = mlx5_devcom_register_device(dev);
823 if (IS_ERR(dev->priv.devcom))
824 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
825 dev->priv.devcom);
826
827 err = mlx5_query_board_id(dev);
828 if (err) {
829 mlx5_core_err(dev, "query board id failed\n");
830 goto err_devcom;
831 }
832
833 err = mlx5_irq_table_init(dev);
834 if (err) {
835 mlx5_core_err(dev, "failed to initialize irq table\n");
836 goto err_devcom;
837 }
838
839 err = mlx5_eq_table_init(dev);
840 if (err) {
841 mlx5_core_err(dev, "failed to initialize eq\n");
842 goto err_irq_cleanup;
843 }
844
845 err = mlx5_events_init(dev);
846 if (err) {
847 mlx5_core_err(dev, "failed to initialize events\n");
848 goto err_eq_cleanup;
849 }
850
851 err = mlx5_fw_reset_init(dev);
852 if (err) {
853 mlx5_core_err(dev, "failed to initialize fw reset events\n");
854 goto err_events_cleanup;
855 }
856
857 mlx5_cq_debugfs_init(dev);
858
859 mlx5_init_reserved_gids(dev);
860
861 mlx5_init_clock(dev);
862
863 dev->vxlan = mlx5_vxlan_create(dev);
864 dev->geneve = mlx5_geneve_create(dev);
865
866 err = mlx5_init_rl_table(dev);
867 if (err) {
868 mlx5_core_err(dev, "Failed to init rate limiting\n");
869 goto err_tables_cleanup;
870 }
871
872 err = mlx5_mpfs_init(dev);
873 if (err) {
874 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
875 goto err_rl_cleanup;
876 }
877
878 err = mlx5_sriov_init(dev);
879 if (err) {
880 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
881 goto err_mpfs_cleanup;
882 }
883
884 err = mlx5_eswitch_init(dev);
885 if (err) {
886 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
887 goto err_sriov_cleanup;
888 }
889
890 err = mlx5_fpga_init(dev);
891 if (err) {
892 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
893 goto err_eswitch_cleanup;
894 }
895
896 err = mlx5_vhca_event_init(dev);
897 if (err) {
898 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
899 goto err_fpga_cleanup;
900 }
901
902 err = mlx5_sf_hw_table_init(dev);
903 if (err) {
904 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
905 goto err_sf_hw_table_cleanup;
906 }
907
908 err = mlx5_sf_table_init(dev);
909 if (err) {
910 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
911 goto err_sf_table_cleanup;
912 }
913
914 dev->dm = mlx5_dm_create(dev);
915 if (IS_ERR(dev->dm))
916 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
917
918 dev->tracer = mlx5_fw_tracer_create(dev);
919 dev->hv_vhca = mlx5_hv_vhca_create(dev);
920 dev->rsc_dump = mlx5_rsc_dump_create(dev);
921
922 return 0;
923
924 err_sf_table_cleanup:
925 mlx5_sf_hw_table_cleanup(dev);
926 err_sf_hw_table_cleanup:
927 mlx5_vhca_event_cleanup(dev);
928 err_fpga_cleanup:
929 mlx5_fpga_cleanup(dev);
930 err_eswitch_cleanup:
931 mlx5_eswitch_cleanup(dev->priv.eswitch);
932 err_sriov_cleanup:
933 mlx5_sriov_cleanup(dev);
934 err_mpfs_cleanup:
935 mlx5_mpfs_cleanup(dev);
936 err_rl_cleanup:
937 mlx5_cleanup_rl_table(dev);
938 err_tables_cleanup:
939 mlx5_geneve_destroy(dev->geneve);
940 mlx5_vxlan_destroy(dev->vxlan);
941 mlx5_cq_debugfs_cleanup(dev);
942 mlx5_fw_reset_cleanup(dev);
943 err_events_cleanup:
944 mlx5_events_cleanup(dev);
945 err_eq_cleanup:
946 mlx5_eq_table_cleanup(dev);
947 err_irq_cleanup:
948 mlx5_irq_table_cleanup(dev);
949 err_devcom:
950 mlx5_devcom_unregister_device(dev->priv.devcom);
951
952 return err;
953 }
954
955 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
956 {
957 mlx5_rsc_dump_destroy(dev);
958 mlx5_hv_vhca_destroy(dev->hv_vhca);
959 mlx5_fw_tracer_destroy(dev->tracer);
960 mlx5_dm_cleanup(dev);
961 mlx5_sf_table_cleanup(dev);
962 mlx5_sf_hw_table_cleanup(dev);
963 mlx5_vhca_event_cleanup(dev);
964 mlx5_fpga_cleanup(dev);
965 mlx5_eswitch_cleanup(dev->priv.eswitch);
966 mlx5_sriov_cleanup(dev);
967 mlx5_mpfs_cleanup(dev);
968 mlx5_cleanup_rl_table(dev);
969 mlx5_geneve_destroy(dev->geneve);
970 mlx5_vxlan_destroy(dev->vxlan);
971 mlx5_cleanup_clock(dev);
972 mlx5_cleanup_reserved_gids(dev);
973 mlx5_cq_debugfs_cleanup(dev);
974 mlx5_fw_reset_cleanup(dev);
975 mlx5_events_cleanup(dev);
976 mlx5_eq_table_cleanup(dev);
977 mlx5_irq_table_cleanup(dev);
978 mlx5_devcom_unregister_device(dev->priv.devcom);
979 }
980
981 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
982 {
983 int err;
984
985 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
986 fw_rev_min(dev), fw_rev_sub(dev));
987
988 /* Only PFs hold the relevant PCIe information for this query */
989 if (mlx5_core_is_pf(dev))
990 pcie_print_link_status(dev->pdev);
991
992 /* wait for firmware to accept initialization segments configurations
993 */
994 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL);
995 if (err) {
996 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n",
997 FW_PRE_INIT_TIMEOUT_MILI);
998 return err;
999 }
1000
1001 err = mlx5_cmd_init(dev);
1002 if (err) {
1003 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1004 return err;
1005 }
1006
1007 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
1008 if (err) {
1009 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n",
1010 FW_INIT_TIMEOUT_MILI);
1011 goto err_cmd_cleanup;
1012 }
1013
1014 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1015
1016 err = mlx5_core_enable_hca(dev, 0);
1017 if (err) {
1018 mlx5_core_err(dev, "enable hca failed\n");
1019 goto err_cmd_cleanup;
1020 }
1021
1022 err = mlx5_core_set_issi(dev);
1023 if (err) {
1024 mlx5_core_err(dev, "failed to set issi\n");
1025 goto err_disable_hca;
1026 }
1027
1028 err = mlx5_satisfy_startup_pages(dev, 1);
1029 if (err) {
1030 mlx5_core_err(dev, "failed to allocate boot pages\n");
1031 goto err_disable_hca;
1032 }
1033
1034 err = set_hca_ctrl(dev);
1035 if (err) {
1036 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1037 goto reclaim_boot_pages;
1038 }
1039
1040 err = set_hca_cap(dev);
1041 if (err) {
1042 mlx5_core_err(dev, "set_hca_cap failed\n");
1043 goto reclaim_boot_pages;
1044 }
1045
1046 err = mlx5_satisfy_startup_pages(dev, 0);
1047 if (err) {
1048 mlx5_core_err(dev, "failed to allocate init pages\n");
1049 goto reclaim_boot_pages;
1050 }
1051
1052 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1053 if (err) {
1054 mlx5_core_err(dev, "init hca failed\n");
1055 goto reclaim_boot_pages;
1056 }
1057
1058 mlx5_set_driver_version(dev);
1059
1060 mlx5_start_health_poll(dev);
1061
1062 err = mlx5_query_hca_caps(dev);
1063 if (err) {
1064 mlx5_core_err(dev, "query hca failed\n");
1065 goto stop_health;
1066 }
1067
1068 return 0;
1069
1070 stop_health:
1071 mlx5_stop_health_poll(dev, boot);
1072 reclaim_boot_pages:
1073 mlx5_reclaim_startup_pages(dev);
1074 err_disable_hca:
1075 mlx5_core_disable_hca(dev, 0);
1076 err_cmd_cleanup:
1077 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1078 mlx5_cmd_cleanup(dev);
1079
1080 return err;
1081 }
1082
1083 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1084 {
1085 int err;
1086
1087 mlx5_stop_health_poll(dev, boot);
1088 err = mlx5_cmd_teardown_hca(dev);
1089 if (err) {
1090 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1091 return err;
1092 }
1093 mlx5_reclaim_startup_pages(dev);
1094 mlx5_core_disable_hca(dev, 0);
1095 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1096 mlx5_cmd_cleanup(dev);
1097
1098 return 0;
1099 }
1100
1101 static int mlx5_load(struct mlx5_core_dev *dev)
1102 {
1103 int err;
1104
1105 dev->priv.uar = mlx5_get_uars_page(dev);
1106 if (IS_ERR(dev->priv.uar)) {
1107 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1108 err = PTR_ERR(dev->priv.uar);
1109 return err;
1110 }
1111
1112 mlx5_events_start(dev);
1113 mlx5_pagealloc_start(dev);
1114
1115 err = mlx5_irq_table_create(dev);
1116 if (err) {
1117 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1118 goto err_irq_table;
1119 }
1120
1121 err = mlx5_eq_table_create(dev);
1122 if (err) {
1123 mlx5_core_err(dev, "Failed to create EQs\n");
1124 goto err_eq_table;
1125 }
1126
1127 err = mlx5_fw_tracer_init(dev->tracer);
1128 if (err) {
1129 mlx5_core_err(dev, "Failed to init FW tracer\n");
1130 goto err_fw_tracer;
1131 }
1132
1133 mlx5_fw_reset_events_start(dev);
1134 mlx5_hv_vhca_init(dev->hv_vhca);
1135
1136 err = mlx5_rsc_dump_init(dev);
1137 if (err) {
1138 mlx5_core_err(dev, "Failed to init Resource dump\n");
1139 goto err_rsc_dump;
1140 }
1141
1142 err = mlx5_fpga_device_start(dev);
1143 if (err) {
1144 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1145 goto err_fpga_start;
1146 }
1147
1148 mlx5_accel_ipsec_init(dev);
1149
1150 err = mlx5_accel_tls_init(dev);
1151 if (err) {
1152 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1153 goto err_tls_start;
1154 }
1155
1156 err = mlx5_init_fs(dev);
1157 if (err) {
1158 mlx5_core_err(dev, "Failed to init flow steering\n");
1159 goto err_fs;
1160 }
1161
1162 err = mlx5_core_set_hca_defaults(dev);
1163 if (err) {
1164 mlx5_core_err(dev, "Failed to set hca defaults\n");
1165 goto err_set_hca;
1166 }
1167
1168 mlx5_vhca_event_start(dev);
1169
1170 err = mlx5_sf_hw_table_create(dev);
1171 if (err) {
1172 mlx5_core_err(dev, "sf table create failed %d\n", err);
1173 goto err_vhca;
1174 }
1175
1176 err = mlx5_ec_init(dev);
1177 if (err) {
1178 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1179 goto err_ec;
1180 }
1181
1182 mlx5_lag_add_mdev(dev);
1183 err = mlx5_sriov_attach(dev);
1184 if (err) {
1185 mlx5_core_err(dev, "sriov init failed %d\n", err);
1186 goto err_sriov;
1187 }
1188
1189 mlx5_sf_dev_table_create(dev);
1190
1191 return 0;
1192
1193 err_sriov:
1194 mlx5_lag_remove_mdev(dev);
1195 mlx5_ec_cleanup(dev);
1196 err_ec:
1197 mlx5_sf_hw_table_destroy(dev);
1198 err_vhca:
1199 mlx5_vhca_event_stop(dev);
1200 err_set_hca:
1201 mlx5_cleanup_fs(dev);
1202 err_fs:
1203 mlx5_accel_tls_cleanup(dev);
1204 err_tls_start:
1205 mlx5_accel_ipsec_cleanup(dev);
1206 mlx5_fpga_device_stop(dev);
1207 err_fpga_start:
1208 mlx5_rsc_dump_cleanup(dev);
1209 err_rsc_dump:
1210 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1211 mlx5_fw_reset_events_stop(dev);
1212 mlx5_fw_tracer_cleanup(dev->tracer);
1213 err_fw_tracer:
1214 mlx5_eq_table_destroy(dev);
1215 err_eq_table:
1216 mlx5_irq_table_destroy(dev);
1217 err_irq_table:
1218 mlx5_pagealloc_stop(dev);
1219 mlx5_events_stop(dev);
1220 mlx5_put_uars_page(dev, dev->priv.uar);
1221 return err;
1222 }
1223
1224 static void mlx5_unload(struct mlx5_core_dev *dev)
1225 {
1226 mlx5_sf_dev_table_destroy(dev);
1227 mlx5_sriov_detach(dev);
1228 mlx5_lag_remove_mdev(dev);
1229 mlx5_ec_cleanup(dev);
1230 mlx5_sf_hw_table_destroy(dev);
1231 mlx5_vhca_event_stop(dev);
1232 mlx5_cleanup_fs(dev);
1233 mlx5_accel_ipsec_cleanup(dev);
1234 mlx5_accel_tls_cleanup(dev);
1235 mlx5_fpga_device_stop(dev);
1236 mlx5_rsc_dump_cleanup(dev);
1237 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1238 mlx5_fw_reset_events_stop(dev);
1239 mlx5_fw_tracer_cleanup(dev->tracer);
1240 mlx5_eq_table_destroy(dev);
1241 mlx5_irq_table_destroy(dev);
1242 mlx5_pagealloc_stop(dev);
1243 mlx5_events_stop(dev);
1244 mlx5_put_uars_page(dev, dev->priv.uar);
1245 }
1246
1247 int mlx5_init_one(struct mlx5_core_dev *dev)
1248 {
1249 int err = 0;
1250
1251 mutex_lock(&dev->intf_state_mutex);
1252 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1253 mlx5_core_warn(dev, "interface is up, NOP\n");
1254 goto out;
1255 }
1256 /* remove any previous indication of internal error */
1257 dev->state = MLX5_DEVICE_STATE_UP;
1258
1259 err = mlx5_function_setup(dev, true);
1260 if (err)
1261 goto err_function;
1262
1263 err = mlx5_init_once(dev);
1264 if (err) {
1265 mlx5_core_err(dev, "sw objs init failed\n");
1266 goto function_teardown;
1267 }
1268
1269 err = mlx5_load(dev);
1270 if (err)
1271 goto err_load;
1272
1273 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1274
1275 err = mlx5_devlink_register(priv_to_devlink(dev), dev->device);
1276 if (err)
1277 goto err_devlink_reg;
1278
1279 err = mlx5_register_device(dev);
1280 if (err)
1281 goto err_register;
1282
1283 mutex_unlock(&dev->intf_state_mutex);
1284 return 0;
1285
1286 err_register:
1287 mlx5_devlink_unregister(priv_to_devlink(dev));
1288 err_devlink_reg:
1289 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1290 mlx5_unload(dev);
1291 err_load:
1292 mlx5_cleanup_once(dev);
1293 function_teardown:
1294 mlx5_function_teardown(dev, true);
1295 err_function:
1296 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1297 out:
1298 mutex_unlock(&dev->intf_state_mutex);
1299 return err;
1300 }
1301
1302 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1303 {
1304 mutex_lock(&dev->intf_state_mutex);
1305
1306 mlx5_unregister_device(dev);
1307 mlx5_devlink_unregister(priv_to_devlink(dev));
1308
1309 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1310 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1311 __func__);
1312 mlx5_cleanup_once(dev);
1313 goto out;
1314 }
1315
1316 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1317 mlx5_unload(dev);
1318 mlx5_cleanup_once(dev);
1319 mlx5_function_teardown(dev, true);
1320 out:
1321 mutex_unlock(&dev->intf_state_mutex);
1322 }
1323
1324 int mlx5_load_one(struct mlx5_core_dev *dev)
1325 {
1326 int err = 0;
1327
1328 mutex_lock(&dev->intf_state_mutex);
1329 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1330 mlx5_core_warn(dev, "interface is up, NOP\n");
1331 goto out;
1332 }
1333 /* remove any previous indication of internal error */
1334 dev->state = MLX5_DEVICE_STATE_UP;
1335
1336 err = mlx5_function_setup(dev, false);
1337 if (err)
1338 goto err_function;
1339
1340 err = mlx5_load(dev);
1341 if (err)
1342 goto err_load;
1343
1344 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1345
1346 err = mlx5_attach_device(dev);
1347 if (err)
1348 goto err_attach;
1349
1350 mutex_unlock(&dev->intf_state_mutex);
1351 return 0;
1352
1353 err_attach:
1354 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1355 mlx5_unload(dev);
1356 err_load:
1357 mlx5_function_teardown(dev, false);
1358 err_function:
1359 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1360 out:
1361 mutex_unlock(&dev->intf_state_mutex);
1362 return err;
1363 }
1364
1365 void mlx5_unload_one(struct mlx5_core_dev *dev)
1366 {
1367 mutex_lock(&dev->intf_state_mutex);
1368
1369 mlx5_detach_device(dev);
1370
1371 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1372 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1373 __func__);
1374 goto out;
1375 }
1376
1377 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1378 mlx5_unload(dev);
1379 mlx5_function_teardown(dev, false);
1380 out:
1381 mutex_unlock(&dev->intf_state_mutex);
1382 }
1383
1384 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1385 {
1386 struct mlx5_priv *priv = &dev->priv;
1387 int err;
1388
1389 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1390 INIT_LIST_HEAD(&priv->ctx_list);
1391 spin_lock_init(&priv->ctx_lock);
1392 mutex_init(&dev->intf_state_mutex);
1393
1394 mutex_init(&priv->bfregs.reg_head.lock);
1395 mutex_init(&priv->bfregs.wc_head.lock);
1396 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1397 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1398
1399 mutex_init(&priv->alloc_mutex);
1400 mutex_init(&priv->pgdir_mutex);
1401 INIT_LIST_HEAD(&priv->pgdir_list);
1402
1403 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1404 mlx5_debugfs_root);
1405 INIT_LIST_HEAD(&priv->traps);
1406
1407 err = mlx5_health_init(dev);
1408 if (err)
1409 goto err_health_init;
1410
1411 err = mlx5_pagealloc_init(dev);
1412 if (err)
1413 goto err_pagealloc_init;
1414
1415 err = mlx5_adev_init(dev);
1416 if (err)
1417 goto err_adev_init;
1418
1419 return 0;
1420
1421 err_adev_init:
1422 mlx5_pagealloc_cleanup(dev);
1423 err_pagealloc_init:
1424 mlx5_health_cleanup(dev);
1425 err_health_init:
1426 debugfs_remove(dev->priv.dbg_root);
1427 mutex_destroy(&priv->pgdir_mutex);
1428 mutex_destroy(&priv->alloc_mutex);
1429 mutex_destroy(&priv->bfregs.wc_head.lock);
1430 mutex_destroy(&priv->bfregs.reg_head.lock);
1431 mutex_destroy(&dev->intf_state_mutex);
1432 return err;
1433 }
1434
1435 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1436 {
1437 struct mlx5_priv *priv = &dev->priv;
1438
1439 mlx5_adev_cleanup(dev);
1440 mlx5_pagealloc_cleanup(dev);
1441 mlx5_health_cleanup(dev);
1442 debugfs_remove_recursive(dev->priv.dbg_root);
1443 mutex_destroy(&priv->pgdir_mutex);
1444 mutex_destroy(&priv->alloc_mutex);
1445 mutex_destroy(&priv->bfregs.wc_head.lock);
1446 mutex_destroy(&priv->bfregs.reg_head.lock);
1447 mutex_destroy(&dev->intf_state_mutex);
1448 }
1449
1450 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1451 {
1452 struct mlx5_core_dev *dev;
1453 struct devlink *devlink;
1454 int err;
1455
1456 devlink = mlx5_devlink_alloc();
1457 if (!devlink) {
1458 dev_err(&pdev->dev, "devlink alloc failed\n");
1459 return -ENOMEM;
1460 }
1461
1462 dev = devlink_priv(devlink);
1463 dev->device = &pdev->dev;
1464 dev->pdev = pdev;
1465
1466 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1467 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1468
1469 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1470 if (dev->priv.adev_idx < 0) {
1471 err = dev->priv.adev_idx;
1472 goto adev_init_err;
1473 }
1474
1475 err = mlx5_mdev_init(dev, prof_sel);
1476 if (err)
1477 goto mdev_init_err;
1478
1479 err = mlx5_pci_init(dev, pdev, id);
1480 if (err) {
1481 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1482 err);
1483 goto pci_init_err;
1484 }
1485
1486 err = mlx5_init_one(dev);
1487 if (err) {
1488 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1489 err);
1490 goto err_init_one;
1491 }
1492
1493 err = mlx5_crdump_enable(dev);
1494 if (err)
1495 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1496
1497 pci_save_state(pdev);
1498 if (!mlx5_core_is_mp_slave(dev))
1499 devlink_reload_enable(devlink);
1500 return 0;
1501
1502 err_init_one:
1503 mlx5_pci_close(dev);
1504 pci_init_err:
1505 mlx5_mdev_uninit(dev);
1506 mdev_init_err:
1507 mlx5_adev_idx_free(dev->priv.adev_idx);
1508 adev_init_err:
1509 mlx5_devlink_free(devlink);
1510
1511 return err;
1512 }
1513
1514 static void remove_one(struct pci_dev *pdev)
1515 {
1516 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1517 struct devlink *devlink = priv_to_devlink(dev);
1518
1519 devlink_reload_disable(devlink);
1520 mlx5_crdump_disable(dev);
1521 mlx5_drain_health_wq(dev);
1522 mlx5_uninit_one(dev);
1523 mlx5_pci_close(dev);
1524 mlx5_mdev_uninit(dev);
1525 mlx5_adev_idx_free(dev->priv.adev_idx);
1526 mlx5_devlink_free(devlink);
1527 }
1528
1529 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1530 pci_channel_state_t state)
1531 {
1532 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1533
1534 mlx5_core_info(dev, "%s was called\n", __func__);
1535
1536 mlx5_enter_error_state(dev, false);
1537 mlx5_error_sw_reset(dev);
1538 mlx5_unload_one(dev);
1539 mlx5_drain_health_wq(dev);
1540 mlx5_pci_disable_device(dev);
1541
1542 return state == pci_channel_io_perm_failure ?
1543 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1544 }
1545
1546 /* wait for the device to show vital signs by waiting
1547 * for the health counter to start counting.
1548 */
1549 static int wait_vital(struct pci_dev *pdev)
1550 {
1551 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1552 struct mlx5_core_health *health = &dev->priv.health;
1553 const int niter = 100;
1554 u32 last_count = 0;
1555 u32 count;
1556 int i;
1557
1558 for (i = 0; i < niter; i++) {
1559 count = ioread32be(health->health_counter);
1560 if (count && count != 0xffffffff) {
1561 if (last_count && last_count != count) {
1562 mlx5_core_info(dev,
1563 "wait vital counter value 0x%x after %d iterations\n",
1564 count, i);
1565 return 0;
1566 }
1567 last_count = count;
1568 }
1569 msleep(50);
1570 }
1571
1572 return -ETIMEDOUT;
1573 }
1574
1575 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1576 {
1577 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1578 int err;
1579
1580 mlx5_core_info(dev, "%s was called\n", __func__);
1581
1582 err = mlx5_pci_enable_device(dev);
1583 if (err) {
1584 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1585 __func__, err);
1586 return PCI_ERS_RESULT_DISCONNECT;
1587 }
1588
1589 pci_set_master(pdev);
1590 pci_restore_state(pdev);
1591 pci_save_state(pdev);
1592
1593 if (wait_vital(pdev)) {
1594 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__);
1595 return PCI_ERS_RESULT_DISCONNECT;
1596 }
1597
1598 return PCI_ERS_RESULT_RECOVERED;
1599 }
1600
1601 static void mlx5_pci_resume(struct pci_dev *pdev)
1602 {
1603 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1604 int err;
1605
1606 mlx5_core_info(dev, "%s was called\n", __func__);
1607
1608 err = mlx5_load_one(dev);
1609 if (err)
1610 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n",
1611 __func__, err);
1612 else
1613 mlx5_core_info(dev, "%s: device recovered\n", __func__);
1614 }
1615
1616 static const struct pci_error_handlers mlx5_err_handler = {
1617 .error_detected = mlx5_pci_err_detected,
1618 .slot_reset = mlx5_pci_slot_reset,
1619 .resume = mlx5_pci_resume
1620 };
1621
1622 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1623 {
1624 bool fast_teardown = false, force_teardown = false;
1625 int ret = 1;
1626
1627 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1628 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1629
1630 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1631 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1632
1633 if (!fast_teardown && !force_teardown)
1634 return -EOPNOTSUPP;
1635
1636 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1637 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1638 return -EAGAIN;
1639 }
1640
1641 /* Panic tear down fw command will stop the PCI bus communication
1642 * with the HCA, so the health polll is no longer needed.
1643 */
1644 mlx5_drain_health_wq(dev);
1645 mlx5_stop_health_poll(dev, false);
1646
1647 ret = mlx5_cmd_fast_teardown_hca(dev);
1648 if (!ret)
1649 goto succeed;
1650
1651 ret = mlx5_cmd_force_teardown_hca(dev);
1652 if (!ret)
1653 goto succeed;
1654
1655 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1656 mlx5_start_health_poll(dev);
1657 return ret;
1658
1659 succeed:
1660 mlx5_enter_error_state(dev, true);
1661
1662 /* Some platforms requiring freeing the IRQ's in the shutdown
1663 * flow. If they aren't freed they can't be allocated after
1664 * kexec. There is no need to cleanup the mlx5_core software
1665 * contexts.
1666 */
1667 mlx5_core_eq_free_irqs(dev);
1668
1669 return 0;
1670 }
1671
1672 static void shutdown(struct pci_dev *pdev)
1673 {
1674 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1675 int err;
1676
1677 mlx5_core_info(dev, "Shutdown was called\n");
1678 err = mlx5_try_fast_unload(dev);
1679 if (err)
1680 mlx5_unload_one(dev);
1681 mlx5_pci_disable_device(dev);
1682 }
1683
1684 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1685 {
1686 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1687
1688 mlx5_unload_one(dev);
1689
1690 return 0;
1691 }
1692
1693 static int mlx5_resume(struct pci_dev *pdev)
1694 {
1695 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1696
1697 return mlx5_load_one(dev);
1698 }
1699
1700 static const struct pci_device_id mlx5_core_pci_table[] = {
1701 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1702 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1703 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1704 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1705 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1706 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1707 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1708 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1709 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1710 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1711 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1712 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1713 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1714 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1715 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1716 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1717 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1718 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1719 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1720 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
1721 { 0, }
1722 };
1723
1724 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1725
1726 void mlx5_disable_device(struct mlx5_core_dev *dev)
1727 {
1728 mlx5_error_sw_reset(dev);
1729 mlx5_unload_one(dev);
1730 }
1731
1732 int mlx5_recover_device(struct mlx5_core_dev *dev)
1733 {
1734 int ret = -EIO;
1735
1736 mlx5_pci_disable_device(dev);
1737 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1738 ret = mlx5_load_one(dev);
1739 return ret;
1740 }
1741
1742 static struct pci_driver mlx5_core_driver = {
1743 .name = KBUILD_MODNAME,
1744 .id_table = mlx5_core_pci_table,
1745 .probe = probe_one,
1746 .remove = remove_one,
1747 .suspend = mlx5_suspend,
1748 .resume = mlx5_resume,
1749 .shutdown = shutdown,
1750 .err_handler = &mlx5_err_handler,
1751 .sriov_configure = mlx5_core_sriov_configure,
1752 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
1753 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
1754 };
1755
1756 static void mlx5_core_verify_params(void)
1757 {
1758 if (prof_sel >= ARRAY_SIZE(profile)) {
1759 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1760 prof_sel,
1761 ARRAY_SIZE(profile) - 1,
1762 MLX5_DEFAULT_PROF);
1763 prof_sel = MLX5_DEFAULT_PROF;
1764 }
1765 }
1766
1767 static int __init init(void)
1768 {
1769 int err;
1770
1771 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
1772 "mlx5_core name not in sync with kernel module name");
1773
1774 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1775
1776 mlx5_core_verify_params();
1777 mlx5_fpga_ipsec_build_fs_cmds();
1778 mlx5_register_debugfs();
1779
1780 err = pci_register_driver(&mlx5_core_driver);
1781 if (err)
1782 goto err_debug;
1783
1784 err = mlx5_sf_driver_register();
1785 if (err)
1786 goto err_sf;
1787
1788 err = mlx5e_init();
1789 if (err)
1790 goto err_en;
1791
1792 return 0;
1793
1794 err_en:
1795 mlx5_sf_driver_unregister();
1796 err_sf:
1797 pci_unregister_driver(&mlx5_core_driver);
1798 err_debug:
1799 mlx5_unregister_debugfs();
1800 return err;
1801 }
1802
1803 static void __exit cleanup(void)
1804 {
1805 mlx5e_cleanup();
1806 mlx5_sf_driver_unregister();
1807 pci_unregister_driver(&mlx5_core_driver);
1808 mlx5_unregister_debugfs();
1809 }
1810
1811 module_init(init);
1812 module_exit(cleanup);
A mirror of Linus' kernel repository