2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/mlx5/mlx5_ifc.h>
50 #include <linux/mlx5/vport.h>
51 #ifdef CONFIG_RFS_ACCEL
52 #include <linux/cpu_rmap.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
60 #include "fpga/core.h"
61 #include "accel/ipsec.h"
63 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
64 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
65 MODULE_LICENSE("Dual BSD/GPL");
66 MODULE_VERSION(DRIVER_VERSION
);
68 unsigned int mlx5_core_debug_mask
;
69 module_param_named(debug_mask
, mlx5_core_debug_mask
, uint
, 0644);
70 MODULE_PARM_DESC(debug_mask
, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
72 #define MLX5_DEFAULT_PROF 2
73 static unsigned int prof_sel
= MLX5_DEFAULT_PROF
;
74 module_param_named(prof_sel
, prof_sel
, uint
, 0444);
75 MODULE_PARM_DESC(prof_sel
, "profile selector. Valid range 0 - 2");
78 MLX5_ATOMIC_REQ_MODE_BE
= 0x0,
79 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
= 0x1,
82 static struct mlx5_profile profile
[] = {
87 .mask
= MLX5_PROF_MASK_QP_SIZE
,
91 .mask
= MLX5_PROF_MASK_QP_SIZE
|
92 MLX5_PROF_MASK_MR_CACHE
,
181 #define FW_INIT_TIMEOUT_MILI 2000
182 #define FW_INIT_WAIT_MS 2
183 #define FW_PRE_INIT_TIMEOUT_MILI 10000
185 static int wait_fw_init(struct mlx5_core_dev
*dev
, u32 max_wait_mili
)
187 unsigned long end
= jiffies
+ msecs_to_jiffies(max_wait_mili
);
190 while (fw_initializing(dev
)) {
191 if (time_after(jiffies
, end
)) {
195 msleep(FW_INIT_WAIT_MS
);
201 static void mlx5_set_driver_version(struct mlx5_core_dev
*dev
)
203 int driver_ver_sz
= MLX5_FLD_SZ_BYTES(set_driver_version_in
,
205 u8 in
[MLX5_ST_SZ_BYTES(set_driver_version_in
)] = {0};
206 u8 out
[MLX5_ST_SZ_BYTES(set_driver_version_out
)] = {0};
207 int remaining_size
= driver_ver_sz
;
210 if (!MLX5_CAP_GEN(dev
, driver_version
))
213 string
= MLX5_ADDR_OF(set_driver_version_in
, in
, driver_version
);
215 strncpy(string
, "Linux", remaining_size
);
217 remaining_size
= max_t(int, 0, driver_ver_sz
- strlen(string
));
218 strncat(string
, ",", remaining_size
);
220 remaining_size
= max_t(int, 0, driver_ver_sz
- strlen(string
));
221 strncat(string
, DRIVER_NAME
, remaining_size
);
223 remaining_size
= max_t(int, 0, driver_ver_sz
- strlen(string
));
224 strncat(string
, ",", remaining_size
);
226 remaining_size
= max_t(int, 0, driver_ver_sz
- strlen(string
));
227 strncat(string
, DRIVER_VERSION
, remaining_size
);
230 MLX5_SET(set_driver_version_in
, in
, opcode
,
231 MLX5_CMD_OP_SET_DRIVER_VERSION
);
233 mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, sizeof(out
));
236 static int set_dma_caps(struct pci_dev
*pdev
)
240 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
242 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask\n");
243 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
245 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting\n");
250 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
253 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
254 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
257 "Can't set consistent PCI DMA mask, aborting\n");
262 dma_set_max_seg_size(&pdev
->dev
, 2u * 1024 * 1024 * 1024);
266 static int mlx5_pci_enable_device(struct mlx5_core_dev
*dev
)
268 struct pci_dev
*pdev
= dev
->pdev
;
271 mutex_lock(&dev
->pci_status_mutex
);
272 if (dev
->pci_status
== MLX5_PCI_STATUS_DISABLED
) {
273 err
= pci_enable_device(pdev
);
275 dev
->pci_status
= MLX5_PCI_STATUS_ENABLED
;
277 mutex_unlock(&dev
->pci_status_mutex
);
282 static void mlx5_pci_disable_device(struct mlx5_core_dev
*dev
)
284 struct pci_dev
*pdev
= dev
->pdev
;
286 mutex_lock(&dev
->pci_status_mutex
);
287 if (dev
->pci_status
== MLX5_PCI_STATUS_ENABLED
) {
288 pci_disable_device(pdev
);
289 dev
->pci_status
= MLX5_PCI_STATUS_DISABLED
;
291 mutex_unlock(&dev
->pci_status_mutex
);
294 static int request_bar(struct pci_dev
*pdev
)
298 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
299 dev_err(&pdev
->dev
, "Missing registers BAR, aborting\n");
303 err
= pci_request_regions(pdev
, DRIVER_NAME
);
305 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
310 static void release_bar(struct pci_dev
*pdev
)
312 pci_release_regions(pdev
);
315 static int mlx5_alloc_irq_vectors(struct mlx5_core_dev
*dev
)
317 struct mlx5_priv
*priv
= &dev
->priv
;
318 struct mlx5_eq_table
*table
= &priv
->eq_table
;
319 struct irq_affinity irqdesc
= {
320 .pre_vectors
= MLX5_EQ_VEC_COMP_BASE
,
322 int num_eqs
= 1 << MLX5_CAP_GEN(dev
, log_max_eq
);
325 nvec
= MLX5_CAP_GEN(dev
, num_ports
) * num_online_cpus() +
326 MLX5_EQ_VEC_COMP_BASE
;
327 nvec
= min_t(int, nvec
, num_eqs
);
328 if (nvec
<= MLX5_EQ_VEC_COMP_BASE
)
331 priv
->irq_info
= kcalloc(nvec
, sizeof(*priv
->irq_info
), GFP_KERNEL
);
335 nvec
= pci_alloc_irq_vectors_affinity(dev
->pdev
,
336 MLX5_EQ_VEC_COMP_BASE
+ 1, nvec
,
337 PCI_IRQ_MSIX
| PCI_IRQ_AFFINITY
,
342 table
->num_comp_vectors
= nvec
- MLX5_EQ_VEC_COMP_BASE
;
347 kfree(priv
->irq_info
);
351 static void mlx5_free_irq_vectors(struct mlx5_core_dev
*dev
)
353 struct mlx5_priv
*priv
= &dev
->priv
;
355 pci_free_irq_vectors(dev
->pdev
);
356 kfree(priv
->irq_info
);
359 struct mlx5_reg_host_endianness
{
364 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
367 MLX5_CAP_BITS_RW_MASK
= CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM
, 2) |
368 MLX5_DEV_CAP_FLAG_DCT
,
371 static u16
to_fw_pkey_sz(struct mlx5_core_dev
*dev
, u32 size
)
387 mlx5_core_warn(dev
, "invalid pkey table size %d\n", size
);
392 static int mlx5_core_get_caps_mode(struct mlx5_core_dev
*dev
,
393 enum mlx5_cap_type cap_type
,
394 enum mlx5_cap_mode cap_mode
)
396 u8 in
[MLX5_ST_SZ_BYTES(query_hca_cap_in
)];
397 int out_sz
= MLX5_ST_SZ_BYTES(query_hca_cap_out
);
398 void *out
, *hca_caps
;
399 u16 opmod
= (cap_type
<< 1) | (cap_mode
& 0x01);
402 memset(in
, 0, sizeof(in
));
403 out
= kzalloc(out_sz
, GFP_KERNEL
);
407 MLX5_SET(query_hca_cap_in
, in
, opcode
, MLX5_CMD_OP_QUERY_HCA_CAP
);
408 MLX5_SET(query_hca_cap_in
, in
, op_mod
, opmod
);
409 err
= mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, out_sz
);
412 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
413 cap_type
, cap_mode
, err
);
417 hca_caps
= MLX5_ADDR_OF(query_hca_cap_out
, out
, capability
);
420 case HCA_CAP_OPMOD_GET_MAX
:
421 memcpy(dev
->caps
.hca_max
[cap_type
], hca_caps
,
422 MLX5_UN_SZ_BYTES(hca_cap_union
));
424 case HCA_CAP_OPMOD_GET_CUR
:
425 memcpy(dev
->caps
.hca_cur
[cap_type
], hca_caps
,
426 MLX5_UN_SZ_BYTES(hca_cap_union
));
430 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
440 int mlx5_core_get_caps(struct mlx5_core_dev
*dev
, enum mlx5_cap_type cap_type
)
444 ret
= mlx5_core_get_caps_mode(dev
, cap_type
, HCA_CAP_OPMOD_GET_CUR
);
447 return mlx5_core_get_caps_mode(dev
, cap_type
, HCA_CAP_OPMOD_GET_MAX
);
450 static int set_caps(struct mlx5_core_dev
*dev
, void *in
, int in_sz
, int opmod
)
452 u32 out
[MLX5_ST_SZ_DW(set_hca_cap_out
)] = {0};
454 MLX5_SET(set_hca_cap_in
, in
, opcode
, MLX5_CMD_OP_SET_HCA_CAP
);
455 MLX5_SET(set_hca_cap_in
, in
, op_mod
, opmod
<< 1);
456 return mlx5_cmd_exec(dev
, in
, in_sz
, out
, sizeof(out
));
459 static int handle_hca_cap_atomic(struct mlx5_core_dev
*dev
)
463 int set_sz
= MLX5_ST_SZ_BYTES(set_hca_cap_in
);
467 if (MLX5_CAP_GEN(dev
, atomic
)) {
468 err
= mlx5_core_get_caps(dev
, MLX5_CAP_ATOMIC
);
477 supported_atomic_req_8B_endianness_mode_1
);
479 if (req_endianness
!= MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
)
482 set_ctx
= kzalloc(set_sz
, GFP_KERNEL
);
486 set_hca_cap
= MLX5_ADDR_OF(set_hca_cap_in
, set_ctx
, capability
);
488 /* Set requestor to host endianness */
489 MLX5_SET(atomic_caps
, set_hca_cap
, atomic_req_8B_endianness_mode
,
490 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
);
492 err
= set_caps(dev
, set_ctx
, set_sz
, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC
);
498 static int handle_hca_cap(struct mlx5_core_dev
*dev
)
500 void *set_ctx
= NULL
;
501 struct mlx5_profile
*prof
= dev
->profile
;
503 int set_sz
= MLX5_ST_SZ_BYTES(set_hca_cap_in
);
506 set_ctx
= kzalloc(set_sz
, GFP_KERNEL
);
510 err
= mlx5_core_get_caps(dev
, MLX5_CAP_GENERAL
);
514 set_hca_cap
= MLX5_ADDR_OF(set_hca_cap_in
, set_ctx
,
516 memcpy(set_hca_cap
, dev
->caps
.hca_cur
[MLX5_CAP_GENERAL
],
517 MLX5_ST_SZ_BYTES(cmd_hca_cap
));
519 mlx5_core_dbg(dev
, "Current Pkey table size %d Setting new size %d\n",
520 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev
, pkey_table_size
)),
522 /* we limit the size of the pkey table to 128 entries for now */
523 MLX5_SET(cmd_hca_cap
, set_hca_cap
, pkey_table_size
,
524 to_fw_pkey_sz(dev
, 128));
526 /* Check log_max_qp from HCA caps to set in current profile */
527 if (MLX5_CAP_GEN_MAX(dev
, log_max_qp
) < profile
[prof_sel
].log_max_qp
) {
528 mlx5_core_warn(dev
, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
529 profile
[prof_sel
].log_max_qp
,
530 MLX5_CAP_GEN_MAX(dev
, log_max_qp
));
531 profile
[prof_sel
].log_max_qp
= MLX5_CAP_GEN_MAX(dev
, log_max_qp
);
533 if (prof
->mask
& MLX5_PROF_MASK_QP_SIZE
)
534 MLX5_SET(cmd_hca_cap
, set_hca_cap
, log_max_qp
,
537 /* disable cmdif checksum */
538 MLX5_SET(cmd_hca_cap
, set_hca_cap
, cmdif_checksum
, 0);
540 /* Enable 4K UAR only when HCA supports it and page size is bigger
543 if (MLX5_CAP_GEN_MAX(dev
, uar_4k
) && PAGE_SIZE
> 4096)
544 MLX5_SET(cmd_hca_cap
, set_hca_cap
, uar_4k
, 1);
546 MLX5_SET(cmd_hca_cap
, set_hca_cap
, log_uar_page_sz
, PAGE_SHIFT
- 12);
548 if (MLX5_CAP_GEN_MAX(dev
, cache_line_128byte
))
549 MLX5_SET(cmd_hca_cap
,
552 cache_line_size() == 128 ? 1 : 0);
554 err
= set_caps(dev
, set_ctx
, set_sz
,
555 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE
);
562 static int set_hca_ctrl(struct mlx5_core_dev
*dev
)
564 struct mlx5_reg_host_endianness he_in
;
565 struct mlx5_reg_host_endianness he_out
;
568 if (!mlx5_core_is_pf(dev
))
571 memset(&he_in
, 0, sizeof(he_in
));
572 he_in
.he
= MLX5_SET_HOST_ENDIANNESS
;
573 err
= mlx5_core_access_reg(dev
, &he_in
, sizeof(he_in
),
574 &he_out
, sizeof(he_out
),
575 MLX5_REG_HOST_ENDIANNESS
, 0, 1);
579 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev
*dev
)
583 /* Disable local_lb by default */
584 if ((MLX5_CAP_GEN(dev
, port_type
) == MLX5_CAP_PORT_TYPE_ETH
) &&
585 MLX5_CAP_GEN(dev
, disable_local_lb
))
586 ret
= mlx5_nic_vport_update_local_lb(dev
, false);
591 int mlx5_core_enable_hca(struct mlx5_core_dev
*dev
, u16 func_id
)
593 u32 out
[MLX5_ST_SZ_DW(enable_hca_out
)] = {0};
594 u32 in
[MLX5_ST_SZ_DW(enable_hca_in
)] = {0};
596 MLX5_SET(enable_hca_in
, in
, opcode
, MLX5_CMD_OP_ENABLE_HCA
);
597 MLX5_SET(enable_hca_in
, in
, function_id
, func_id
);
598 return mlx5_cmd_exec(dev
, &in
, sizeof(in
), &out
, sizeof(out
));
601 int mlx5_core_disable_hca(struct mlx5_core_dev
*dev
, u16 func_id
)
603 u32 out
[MLX5_ST_SZ_DW(disable_hca_out
)] = {0};
604 u32 in
[MLX5_ST_SZ_DW(disable_hca_in
)] = {0};
606 MLX5_SET(disable_hca_in
, in
, opcode
, MLX5_CMD_OP_DISABLE_HCA
);
607 MLX5_SET(disable_hca_in
, in
, function_id
, func_id
);
608 return mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, sizeof(out
));
611 u64
mlx5_read_internal_timer(struct mlx5_core_dev
*dev
)
613 u32 timer_h
, timer_h1
, timer_l
;
615 timer_h
= ioread32be(&dev
->iseg
->internal_timer_h
);
616 timer_l
= ioread32be(&dev
->iseg
->internal_timer_l
);
617 timer_h1
= ioread32be(&dev
->iseg
->internal_timer_h
);
618 if (timer_h
!= timer_h1
) /* wrap around */
619 timer_l
= ioread32be(&dev
->iseg
->internal_timer_l
);
621 return (u64
)timer_l
| (u64
)timer_h1
<< 32;
624 int mlx5_vector2eqn(struct mlx5_core_dev
*dev
, int vector
, int *eqn
,
627 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
628 struct mlx5_eq
*eq
, *n
;
631 spin_lock(&table
->lock
);
632 list_for_each_entry_safe(eq
, n
, &table
->comp_eqs_list
, list
) {
633 if (eq
->index
== vector
) {
640 spin_unlock(&table
->lock
);
644 EXPORT_SYMBOL(mlx5_vector2eqn
);
646 struct mlx5_eq
*mlx5_eqn2eq(struct mlx5_core_dev
*dev
, int eqn
)
648 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
651 spin_lock(&table
->lock
);
652 list_for_each_entry(eq
, &table
->comp_eqs_list
, list
)
653 if (eq
->eqn
== eqn
) {
654 spin_unlock(&table
->lock
);
658 spin_unlock(&table
->lock
);
660 return ERR_PTR(-ENOENT
);
663 static void free_comp_eqs(struct mlx5_core_dev
*dev
)
665 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
666 struct mlx5_eq
*eq
, *n
;
668 #ifdef CONFIG_RFS_ACCEL
670 free_irq_cpu_rmap(dev
->rmap
);
674 spin_lock(&table
->lock
);
675 list_for_each_entry_safe(eq
, n
, &table
->comp_eqs_list
, list
) {
677 spin_unlock(&table
->lock
);
678 if (mlx5_destroy_unmap_eq(dev
, eq
))
679 mlx5_core_warn(dev
, "failed to destroy EQ 0x%x\n",
682 spin_lock(&table
->lock
);
684 spin_unlock(&table
->lock
);
687 static int alloc_comp_eqs(struct mlx5_core_dev
*dev
)
689 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
690 char name
[MLX5_MAX_IRQ_NAME
];
697 INIT_LIST_HEAD(&table
->comp_eqs_list
);
698 ncomp_vec
= table
->num_comp_vectors
;
699 nent
= MLX5_COMP_EQ_SIZE
;
700 #ifdef CONFIG_RFS_ACCEL
701 dev
->rmap
= alloc_irq_cpu_rmap(ncomp_vec
);
705 for (i
= 0; i
< ncomp_vec
; i
++) {
706 eq
= kzalloc(sizeof(*eq
), GFP_KERNEL
);
712 #ifdef CONFIG_RFS_ACCEL
713 irq_cpu_rmap_add(dev
->rmap
, pci_irq_vector(dev
->pdev
,
714 MLX5_EQ_VEC_COMP_BASE
+ i
));
716 snprintf(name
, MLX5_MAX_IRQ_NAME
, "mlx5_comp%d", i
);
717 err
= mlx5_create_map_eq(dev
, eq
,
718 i
+ MLX5_EQ_VEC_COMP_BASE
, nent
, 0,
719 name
, MLX5_EQ_TYPE_COMP
);
724 mlx5_core_dbg(dev
, "allocated completion EQN %d\n", eq
->eqn
);
726 spin_lock(&table
->lock
);
727 list_add_tail(&eq
->list
, &table
->comp_eqs_list
);
728 spin_unlock(&table
->lock
);
738 static int mlx5_core_set_issi(struct mlx5_core_dev
*dev
)
740 u32 query_in
[MLX5_ST_SZ_DW(query_issi_in
)] = {0};
741 u32 query_out
[MLX5_ST_SZ_DW(query_issi_out
)] = {0};
745 MLX5_SET(query_issi_in
, query_in
, opcode
, MLX5_CMD_OP_QUERY_ISSI
);
746 err
= mlx5_cmd_exec(dev
, query_in
, sizeof(query_in
),
747 query_out
, sizeof(query_out
));
752 mlx5_cmd_mbox_status(query_out
, &status
, &syndrome
);
753 if (!status
|| syndrome
== MLX5_DRIVER_SYND
) {
754 mlx5_core_err(dev
, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
755 err
, status
, syndrome
);
759 mlx5_core_warn(dev
, "Query ISSI is not supported by FW, ISSI is 0\n");
764 sup_issi
= MLX5_GET(query_issi_out
, query_out
, supported_issi_dw0
);
766 if (sup_issi
& (1 << 1)) {
767 u32 set_in
[MLX5_ST_SZ_DW(set_issi_in
)] = {0};
768 u32 set_out
[MLX5_ST_SZ_DW(set_issi_out
)] = {0};
770 MLX5_SET(set_issi_in
, set_in
, opcode
, MLX5_CMD_OP_SET_ISSI
);
771 MLX5_SET(set_issi_in
, set_in
, current_issi
, 1);
772 err
= mlx5_cmd_exec(dev
, set_in
, sizeof(set_in
),
773 set_out
, sizeof(set_out
));
775 mlx5_core_err(dev
, "Failed to set ISSI to 1 err(%d)\n",
783 } else if (sup_issi
& (1 << 0) || !sup_issi
) {
790 static int mlx5_pci_init(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
792 struct pci_dev
*pdev
= dev
->pdev
;
795 pci_set_drvdata(dev
->pdev
, dev
);
796 strncpy(priv
->name
, dev_name(&pdev
->dev
), MLX5_MAX_NAME_LEN
);
797 priv
->name
[MLX5_MAX_NAME_LEN
- 1] = 0;
799 mutex_init(&priv
->pgdir_mutex
);
800 INIT_LIST_HEAD(&priv
->pgdir_list
);
801 spin_lock_init(&priv
->mkey_lock
);
803 mutex_init(&priv
->alloc_mutex
);
805 priv
->numa_node
= dev_to_node(&dev
->pdev
->dev
);
807 priv
->dbg_root
= debugfs_create_dir(dev_name(&pdev
->dev
), mlx5_debugfs_root
);
811 err
= mlx5_pci_enable_device(dev
);
813 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
817 err
= request_bar(pdev
);
819 dev_err(&pdev
->dev
, "error requesting BARs, aborting\n");
823 pci_set_master(pdev
);
825 err
= set_dma_caps(pdev
);
827 dev_err(&pdev
->dev
, "Failed setting DMA capabilities mask, aborting\n");
831 dev
->iseg_base
= pci_resource_start(dev
->pdev
, 0);
832 dev
->iseg
= ioremap(dev
->iseg_base
, sizeof(*dev
->iseg
));
835 dev_err(&pdev
->dev
, "Failed mapping initialization segment, aborting\n");
842 pci_clear_master(dev
->pdev
);
843 release_bar(dev
->pdev
);
845 mlx5_pci_disable_device(dev
);
848 debugfs_remove(priv
->dbg_root
);
852 static void mlx5_pci_close(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
855 pci_clear_master(dev
->pdev
);
856 release_bar(dev
->pdev
);
857 mlx5_pci_disable_device(dev
);
858 debugfs_remove(priv
->dbg_root
);
861 static int mlx5_init_once(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
863 struct pci_dev
*pdev
= dev
->pdev
;
866 err
= mlx5_query_board_id(dev
);
868 dev_err(&pdev
->dev
, "query board id failed\n");
872 err
= mlx5_eq_init(dev
);
874 dev_err(&pdev
->dev
, "failed to initialize eq\n");
878 err
= mlx5_init_cq_table(dev
);
880 dev_err(&pdev
->dev
, "failed to initialize cq table\n");
884 mlx5_init_qp_table(dev
);
886 mlx5_init_srq_table(dev
);
888 mlx5_init_mkey_table(dev
);
890 mlx5_init_reserved_gids(dev
);
892 err
= mlx5_init_rl_table(dev
);
894 dev_err(&pdev
->dev
, "Failed to init rate limiting\n");
895 goto err_tables_cleanup
;
898 err
= mlx5_mpfs_init(dev
);
900 dev_err(&pdev
->dev
, "Failed to init l2 table %d\n", err
);
904 err
= mlx5_eswitch_init(dev
);
906 dev_err(&pdev
->dev
, "Failed to init eswitch %d\n", err
);
907 goto err_mpfs_cleanup
;
910 err
= mlx5_sriov_init(dev
);
912 dev_err(&pdev
->dev
, "Failed to init sriov %d\n", err
);
913 goto err_eswitch_cleanup
;
916 err
= mlx5_fpga_init(dev
);
918 dev_err(&pdev
->dev
, "Failed to init fpga device %d\n", err
);
919 goto err_sriov_cleanup
;
925 mlx5_sriov_cleanup(dev
);
927 mlx5_eswitch_cleanup(dev
->priv
.eswitch
);
929 mlx5_mpfs_cleanup(dev
);
931 mlx5_cleanup_rl_table(dev
);
933 mlx5_cleanup_mkey_table(dev
);
934 mlx5_cleanup_srq_table(dev
);
935 mlx5_cleanup_qp_table(dev
);
936 mlx5_cleanup_cq_table(dev
);
939 mlx5_eq_cleanup(dev
);
945 static void mlx5_cleanup_once(struct mlx5_core_dev
*dev
)
947 mlx5_fpga_cleanup(dev
);
948 mlx5_sriov_cleanup(dev
);
949 mlx5_eswitch_cleanup(dev
->priv
.eswitch
);
950 mlx5_mpfs_cleanup(dev
);
951 mlx5_cleanup_rl_table(dev
);
952 mlx5_cleanup_reserved_gids(dev
);
953 mlx5_cleanup_mkey_table(dev
);
954 mlx5_cleanup_srq_table(dev
);
955 mlx5_cleanup_qp_table(dev
);
956 mlx5_cleanup_cq_table(dev
);
957 mlx5_eq_cleanup(dev
);
960 static int mlx5_load_one(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
,
963 struct pci_dev
*pdev
= dev
->pdev
;
966 mutex_lock(&dev
->intf_state_mutex
);
967 if (test_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
)) {
968 dev_warn(&dev
->pdev
->dev
, "%s: interface is up, NOP\n",
973 dev_info(&pdev
->dev
, "firmware version: %d.%d.%d\n", fw_rev_maj(dev
),
974 fw_rev_min(dev
), fw_rev_sub(dev
));
976 /* on load removing any previous indication of internal error, device is
979 dev
->state
= MLX5_DEVICE_STATE_UP
;
981 /* wait for firmware to accept initialization segments configurations
983 err
= wait_fw_init(dev
, FW_PRE_INIT_TIMEOUT_MILI
);
985 dev_err(&dev
->pdev
->dev
, "Firmware over %d MS in pre-initializing state, aborting\n",
986 FW_PRE_INIT_TIMEOUT_MILI
);
990 err
= mlx5_cmd_init(dev
);
992 dev_err(&pdev
->dev
, "Failed initializing command interface, aborting\n");
996 err
= wait_fw_init(dev
, FW_INIT_TIMEOUT_MILI
);
998 dev_err(&dev
->pdev
->dev
, "Firmware over %d MS in initializing state, aborting\n",
999 FW_INIT_TIMEOUT_MILI
);
1000 goto err_cmd_cleanup
;
1003 err
= mlx5_core_enable_hca(dev
, 0);
1005 dev_err(&pdev
->dev
, "enable hca failed\n");
1006 goto err_cmd_cleanup
;
1009 err
= mlx5_core_set_issi(dev
);
1011 dev_err(&pdev
->dev
, "failed to set issi\n");
1012 goto err_disable_hca
;
1015 err
= mlx5_satisfy_startup_pages(dev
, 1);
1017 dev_err(&pdev
->dev
, "failed to allocate boot pages\n");
1018 goto err_disable_hca
;
1021 err
= set_hca_ctrl(dev
);
1023 dev_err(&pdev
->dev
, "set_hca_ctrl failed\n");
1024 goto reclaim_boot_pages
;
1027 err
= handle_hca_cap(dev
);
1029 dev_err(&pdev
->dev
, "handle_hca_cap failed\n");
1030 goto reclaim_boot_pages
;
1033 err
= handle_hca_cap_atomic(dev
);
1035 dev_err(&pdev
->dev
, "handle_hca_cap_atomic failed\n");
1036 goto reclaim_boot_pages
;
1039 err
= mlx5_satisfy_startup_pages(dev
, 0);
1041 dev_err(&pdev
->dev
, "failed to allocate init pages\n");
1042 goto reclaim_boot_pages
;
1045 err
= mlx5_pagealloc_start(dev
);
1047 dev_err(&pdev
->dev
, "mlx5_pagealloc_start failed\n");
1048 goto reclaim_boot_pages
;
1051 err
= mlx5_cmd_init_hca(dev
);
1053 dev_err(&pdev
->dev
, "init hca failed\n");
1054 goto err_pagealloc_stop
;
1057 mlx5_set_driver_version(dev
);
1059 mlx5_start_health_poll(dev
);
1061 err
= mlx5_query_hca_caps(dev
);
1063 dev_err(&pdev
->dev
, "query hca failed\n");
1067 if (boot
&& mlx5_init_once(dev
, priv
)) {
1068 dev_err(&pdev
->dev
, "sw objs init failed\n");
1072 err
= mlx5_alloc_irq_vectors(dev
);
1074 dev_err(&pdev
->dev
, "alloc irq vectors failed\n");
1075 goto err_cleanup_once
;
1078 dev
->priv
.uar
= mlx5_get_uars_page(dev
);
1079 if (!dev
->priv
.uar
) {
1080 dev_err(&pdev
->dev
, "Failed allocating uar, aborting\n");
1081 goto err_disable_msix
;
1084 err
= mlx5_start_eqs(dev
);
1086 dev_err(&pdev
->dev
, "Failed to start pages and async EQs\n");
1090 err
= alloc_comp_eqs(dev
);
1092 dev_err(&pdev
->dev
, "Failed to alloc completion EQs\n");
1096 err
= mlx5_init_fs(dev
);
1098 dev_err(&pdev
->dev
, "Failed to init flow steering\n");
1102 err
= mlx5_core_set_hca_defaults(dev
);
1104 dev_err(&pdev
->dev
, "Failed to set hca defaults\n");
1108 err
= mlx5_sriov_attach(dev
);
1110 dev_err(&pdev
->dev
, "sriov init failed %d\n", err
);
1114 err
= mlx5_fpga_device_start(dev
);
1116 dev_err(&pdev
->dev
, "fpga device start failed %d\n", err
);
1117 goto err_fpga_start
;
1119 err
= mlx5_accel_ipsec_init(dev
);
1121 dev_err(&pdev
->dev
, "IPSec device start failed %d\n", err
);
1122 goto err_ipsec_start
;
1125 if (mlx5_device_registered(dev
)) {
1126 mlx5_attach_device(dev
);
1128 err
= mlx5_register_device(dev
);
1130 dev_err(&pdev
->dev
, "mlx5_register_device failed %d\n", err
);
1135 set_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
);
1137 mutex_unlock(&dev
->intf_state_mutex
);
1142 mlx5_accel_ipsec_cleanup(dev
);
1144 mlx5_fpga_device_stop(dev
);
1147 mlx5_sriov_detach(dev
);
1150 mlx5_cleanup_fs(dev
);
1159 mlx5_put_uars_page(dev
, priv
->uar
);
1162 mlx5_free_irq_vectors(dev
);
1166 mlx5_cleanup_once(dev
);
1169 mlx5_stop_health_poll(dev
);
1170 if (mlx5_cmd_teardown_hca(dev
)) {
1171 dev_err(&dev
->pdev
->dev
, "tear_down_hca failed, skip cleanup\n");
1176 mlx5_pagealloc_stop(dev
);
1179 mlx5_reclaim_startup_pages(dev
);
1182 mlx5_core_disable_hca(dev
, 0);
1185 mlx5_cmd_cleanup(dev
);
1188 dev
->state
= MLX5_DEVICE_STATE_INTERNAL_ERROR
;
1189 mutex_unlock(&dev
->intf_state_mutex
);
1194 static int mlx5_unload_one(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
,
1200 mlx5_drain_health_recovery(dev
);
1202 mutex_lock(&dev
->intf_state_mutex
);
1203 if (!test_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
)) {
1204 dev_warn(&dev
->pdev
->dev
, "%s: interface is down, NOP\n",
1207 mlx5_cleanup_once(dev
);
1211 clear_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
);
1213 if (mlx5_device_registered(dev
))
1214 mlx5_detach_device(dev
);
1216 mlx5_accel_ipsec_cleanup(dev
);
1217 mlx5_fpga_device_stop(dev
);
1219 mlx5_sriov_detach(dev
);
1220 mlx5_cleanup_fs(dev
);
1223 mlx5_put_uars_page(dev
, priv
->uar
);
1224 mlx5_free_irq_vectors(dev
);
1226 mlx5_cleanup_once(dev
);
1227 mlx5_stop_health_poll(dev
);
1228 err
= mlx5_cmd_teardown_hca(dev
);
1230 dev_err(&dev
->pdev
->dev
, "tear_down_hca failed, skip cleanup\n");
1233 mlx5_pagealloc_stop(dev
);
1234 mlx5_reclaim_startup_pages(dev
);
1235 mlx5_core_disable_hca(dev
, 0);
1236 mlx5_cmd_cleanup(dev
);
1239 mutex_unlock(&dev
->intf_state_mutex
);
1243 struct mlx5_core_event_handler
{
1244 void (*event
)(struct mlx5_core_dev
*dev
,
1245 enum mlx5_dev_event event
,
1249 static const struct devlink_ops mlx5_devlink_ops
= {
1250 #ifdef CONFIG_MLX5_ESWITCH
1251 .eswitch_mode_set
= mlx5_devlink_eswitch_mode_set
,
1252 .eswitch_mode_get
= mlx5_devlink_eswitch_mode_get
,
1253 .eswitch_inline_mode_set
= mlx5_devlink_eswitch_inline_mode_set
,
1254 .eswitch_inline_mode_get
= mlx5_devlink_eswitch_inline_mode_get
,
1255 .eswitch_encap_mode_set
= mlx5_devlink_eswitch_encap_mode_set
,
1256 .eswitch_encap_mode_get
= mlx5_devlink_eswitch_encap_mode_get
,
1260 #define MLX5_IB_MOD "mlx5_ib"
1261 static int init_one(struct pci_dev
*pdev
,
1262 const struct pci_device_id
*id
)
1264 struct mlx5_core_dev
*dev
;
1265 struct devlink
*devlink
;
1266 struct mlx5_priv
*priv
;
1269 devlink
= devlink_alloc(&mlx5_devlink_ops
, sizeof(*dev
));
1271 dev_err(&pdev
->dev
, "kzalloc failed\n");
1275 dev
= devlink_priv(devlink
);
1277 priv
->pci_dev_data
= id
->driver_data
;
1279 pci_set_drvdata(pdev
, dev
);
1282 dev
->event
= mlx5_core_event
;
1283 dev
->profile
= &profile
[prof_sel
];
1285 INIT_LIST_HEAD(&priv
->ctx_list
);
1286 spin_lock_init(&priv
->ctx_lock
);
1287 mutex_init(&dev
->pci_status_mutex
);
1288 mutex_init(&dev
->intf_state_mutex
);
1290 INIT_LIST_HEAD(&priv
->waiting_events_list
);
1291 priv
->is_accum_events
= false;
1293 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1294 err
= init_srcu_struct(&priv
->pfault_srcu
);
1296 dev_err(&pdev
->dev
, "init_srcu_struct failed with error code %d\n",
1301 mutex_init(&priv
->bfregs
.reg_head
.lock
);
1302 mutex_init(&priv
->bfregs
.wc_head
.lock
);
1303 INIT_LIST_HEAD(&priv
->bfregs
.reg_head
.list
);
1304 INIT_LIST_HEAD(&priv
->bfregs
.wc_head
.list
);
1306 err
= mlx5_pci_init(dev
, priv
);
1308 dev_err(&pdev
->dev
, "mlx5_pci_init failed with error code %d\n", err
);
1312 err
= mlx5_health_init(dev
);
1314 dev_err(&pdev
->dev
, "mlx5_health_init failed with error code %d\n", err
);
1318 mlx5_pagealloc_init(dev
);
1320 err
= mlx5_load_one(dev
, priv
, true);
1322 dev_err(&pdev
->dev
, "mlx5_load_one failed with error code %d\n", err
);
1326 request_module_nowait(MLX5_IB_MOD
);
1328 err
= devlink_register(devlink
, &pdev
->dev
);
1332 pci_save_state(pdev
);
1336 mlx5_unload_one(dev
, priv
, true);
1338 mlx5_pagealloc_cleanup(dev
);
1339 mlx5_health_cleanup(dev
);
1341 mlx5_pci_close(dev
, priv
);
1343 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1344 cleanup_srcu_struct(&priv
->pfault_srcu
);
1347 devlink_free(devlink
);
1352 static void remove_one(struct pci_dev
*pdev
)
1354 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1355 struct devlink
*devlink
= priv_to_devlink(dev
);
1356 struct mlx5_priv
*priv
= &dev
->priv
;
1358 devlink_unregister(devlink
);
1359 mlx5_unregister_device(dev
);
1361 if (mlx5_unload_one(dev
, priv
, true)) {
1362 dev_err(&dev
->pdev
->dev
, "mlx5_unload_one failed\n");
1363 mlx5_health_cleanup(dev
);
1367 mlx5_pagealloc_cleanup(dev
);
1368 mlx5_health_cleanup(dev
);
1369 mlx5_pci_close(dev
, priv
);
1370 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1371 cleanup_srcu_struct(&priv
->pfault_srcu
);
1373 devlink_free(devlink
);
1376 static pci_ers_result_t
mlx5_pci_err_detected(struct pci_dev
*pdev
,
1377 pci_channel_state_t state
)
1379 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1380 struct mlx5_priv
*priv
= &dev
->priv
;
1382 dev_info(&pdev
->dev
, "%s was called\n", __func__
);
1384 mlx5_enter_error_state(dev
, false);
1385 mlx5_unload_one(dev
, priv
, false);
1386 /* In case of kernel call drain the health wq */
1388 mlx5_drain_health_wq(dev
);
1389 mlx5_pci_disable_device(dev
);
1392 return state
== pci_channel_io_perm_failure
?
1393 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
1396 /* wait for the device to show vital signs by waiting
1397 * for the health counter to start counting.
1399 static int wait_vital(struct pci_dev
*pdev
)
1401 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1402 struct mlx5_core_health
*health
= &dev
->priv
.health
;
1403 const int niter
= 100;
1408 for (i
= 0; i
< niter
; i
++) {
1409 count
= ioread32be(health
->health_counter
);
1410 if (count
&& count
!= 0xffffffff) {
1411 if (last_count
&& last_count
!= count
) {
1412 dev_info(&pdev
->dev
, "Counter value 0x%x after %d iterations\n", count
, i
);
1423 static pci_ers_result_t
mlx5_pci_slot_reset(struct pci_dev
*pdev
)
1425 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1428 dev_info(&pdev
->dev
, "%s was called\n", __func__
);
1430 err
= mlx5_pci_enable_device(dev
);
1432 dev_err(&pdev
->dev
, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1434 return PCI_ERS_RESULT_DISCONNECT
;
1437 pci_set_master(pdev
);
1438 pci_restore_state(pdev
);
1439 pci_save_state(pdev
);
1441 if (wait_vital(pdev
)) {
1442 dev_err(&pdev
->dev
, "%s: wait_vital timed out\n", __func__
);
1443 return PCI_ERS_RESULT_DISCONNECT
;
1446 return PCI_ERS_RESULT_RECOVERED
;
1449 static void mlx5_pci_resume(struct pci_dev
*pdev
)
1451 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1452 struct mlx5_priv
*priv
= &dev
->priv
;
1455 dev_info(&pdev
->dev
, "%s was called\n", __func__
);
1457 err
= mlx5_load_one(dev
, priv
, false);
1459 dev_err(&pdev
->dev
, "%s: mlx5_load_one failed with error code: %d\n"
1462 dev_info(&pdev
->dev
, "%s: device recovered\n", __func__
);
1465 static const struct pci_error_handlers mlx5_err_handler
= {
1466 .error_detected
= mlx5_pci_err_detected
,
1467 .slot_reset
= mlx5_pci_slot_reset
,
1468 .resume
= mlx5_pci_resume
1471 static int mlx5_try_fast_unload(struct mlx5_core_dev
*dev
)
1475 if (!MLX5_CAP_GEN(dev
, force_teardown
)) {
1476 mlx5_core_dbg(dev
, "force teardown is not supported in the firmware\n");
1480 if (dev
->state
== MLX5_DEVICE_STATE_INTERNAL_ERROR
) {
1481 mlx5_core_dbg(dev
, "Device in internal error state, giving up\n");
1485 /* Panic tear down fw command will stop the PCI bus communication
1486 * with the HCA, so the health polll is no longer needed.
1488 mlx5_drain_health_wq(dev
);
1489 mlx5_stop_health_poll(dev
);
1491 ret
= mlx5_cmd_force_teardown_hca(dev
);
1493 mlx5_core_dbg(dev
, "Firmware couldn't do fast unload error: %d\n", ret
);
1494 mlx5_start_health_poll(dev
);
1498 mlx5_enter_error_state(dev
, true);
1503 static void shutdown(struct pci_dev
*pdev
)
1505 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1506 struct mlx5_priv
*priv
= &dev
->priv
;
1509 dev_info(&pdev
->dev
, "Shutdown was called\n");
1510 err
= mlx5_try_fast_unload(dev
);
1512 mlx5_unload_one(dev
, priv
, false);
1513 mlx5_pci_disable_device(dev
);
1516 static const struct pci_device_id mlx5_core_pci_table
[] = {
1517 { PCI_VDEVICE(MELLANOX
, PCI_DEVICE_ID_MELLANOX_CONNECTIB
) },
1518 { PCI_VDEVICE(MELLANOX
, 0x1012), MLX5_PCI_DEV_IS_VF
}, /* Connect-IB VF */
1519 { PCI_VDEVICE(MELLANOX
, PCI_DEVICE_ID_MELLANOX_CONNECTX4
) },
1520 { PCI_VDEVICE(MELLANOX
, 0x1014), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-4 VF */
1521 { PCI_VDEVICE(MELLANOX
, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX
) },
1522 { PCI_VDEVICE(MELLANOX
, 0x1016), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-4LX VF */
1523 { PCI_VDEVICE(MELLANOX
, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1524 { PCI_VDEVICE(MELLANOX
, 0x1018), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-5 VF */
1525 { PCI_VDEVICE(MELLANOX
, 0x1019) }, /* ConnectX-5 Ex */
1526 { PCI_VDEVICE(MELLANOX
, 0x101a), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-5 Ex VF */
1527 { PCI_VDEVICE(MELLANOX
, 0x101b) }, /* ConnectX-6 */
1528 { PCI_VDEVICE(MELLANOX
, 0x101c), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-6 VF */
1529 { PCI_VDEVICE(MELLANOX
, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1530 { PCI_VDEVICE(MELLANOX
, 0xa2d3), MLX5_PCI_DEV_IS_VF
}, /* BlueField integrated ConnectX-5 network controller VF */
1534 MODULE_DEVICE_TABLE(pci
, mlx5_core_pci_table
);
1536 void mlx5_disable_device(struct mlx5_core_dev
*dev
)
1538 mlx5_pci_err_detected(dev
->pdev
, 0);
1541 void mlx5_recover_device(struct mlx5_core_dev
*dev
)
1543 mlx5_pci_disable_device(dev
);
1544 if (mlx5_pci_slot_reset(dev
->pdev
) == PCI_ERS_RESULT_RECOVERED
)
1545 mlx5_pci_resume(dev
->pdev
);
1548 static struct pci_driver mlx5_core_driver
= {
1549 .name
= DRIVER_NAME
,
1550 .id_table
= mlx5_core_pci_table
,
1552 .remove
= remove_one
,
1553 .shutdown
= shutdown
,
1554 .err_handler
= &mlx5_err_handler
,
1555 .sriov_configure
= mlx5_core_sriov_configure
,
1558 static void mlx5_core_verify_params(void)
1560 if (prof_sel
>= ARRAY_SIZE(profile
)) {
1561 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1563 ARRAY_SIZE(profile
) - 1,
1565 prof_sel
= MLX5_DEFAULT_PROF
;
1569 static int __init
init(void)
1573 mlx5_core_verify_params();
1574 mlx5_register_debugfs();
1576 err
= pci_register_driver(&mlx5_core_driver
);
1580 #ifdef CONFIG_MLX5_CORE_EN
1587 mlx5_unregister_debugfs();
1591 static void __exit
cleanup(void)
1593 #ifdef CONFIG_MLX5_CORE_EN
1596 pci_unregister_driver(&mlx5_core_driver
);
1597 mlx5_unregister_debugfs();
1601 module_exit(cleanup
);