2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_CORE_H__
34 #define __MLX5_CORE_H__
36 #include <linux/types.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/if_link.h>
40 #include <linux/firmware.h>
41 #include <linux/ptp_clock_kernel.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/fs.h>
45 #define DRIVER_NAME "mlx5_core"
46 #define DRIVER_VERSION "5.0-0"
48 extern uint mlx5_core_debug_mask
;
50 #define mlx5_core_dbg(__dev, format, ...) \
51 dev_dbg(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \
52 __func__, __LINE__, current->pid, \
55 #define mlx5_core_dbg_once(__dev, format, ...) \
56 dev_dbg_once(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \
57 __func__, __LINE__, current->pid, \
60 #define mlx5_core_dbg_mask(__dev, mask, format, ...) \
62 if ((mask) & mlx5_core_debug_mask) \
63 mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \
66 #define mlx5_core_err(__dev, format, ...) \
67 dev_err(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \
68 __func__, __LINE__, current->pid, \
71 #define mlx5_core_err_rl(__dev, format, ...) \
72 dev_err_ratelimited(&(__dev)->pdev->dev, \
73 "%s:%d:(pid %d): " format, \
74 __func__, __LINE__, current->pid, \
77 #define mlx5_core_warn(__dev, format, ...) \
78 dev_warn(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \
79 __func__, __LINE__, current->pid, \
82 #define mlx5_core_warn_once(__dev, format, ...) \
83 dev_warn_once(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \
84 __func__, __LINE__, current->pid, \
87 #define mlx5_core_info(__dev, format, ...) \
88 dev_info(&(__dev)->pdev->dev, format, ##__VA_ARGS__)
91 MLX5_CMD_DATA
, /* print command payload only */
92 MLX5_CMD_TIME
, /* print command execution time */
96 MLX5_DRIVER_STATUS_ABORTED
= 0xfe,
97 MLX5_DRIVER_SYND
= 0xbadd00de,
100 int mlx5_query_hca_caps(struct mlx5_core_dev
*dev
);
101 int mlx5_query_board_id(struct mlx5_core_dev
*dev
);
102 int mlx5_cmd_init_hca(struct mlx5_core_dev
*dev
, uint32_t *sw_owner_id
);
103 int mlx5_cmd_teardown_hca(struct mlx5_core_dev
*dev
);
104 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev
*dev
);
105 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev
*dev
);
106 void mlx5_enter_error_state(struct mlx5_core_dev
*dev
, bool force
);
107 void mlx5_disable_device(struct mlx5_core_dev
*dev
);
108 void mlx5_recover_device(struct mlx5_core_dev
*dev
);
109 int mlx5_sriov_init(struct mlx5_core_dev
*dev
);
110 void mlx5_sriov_cleanup(struct mlx5_core_dev
*dev
);
111 int mlx5_sriov_attach(struct mlx5_core_dev
*dev
);
112 void mlx5_sriov_detach(struct mlx5_core_dev
*dev
);
113 int mlx5_core_sriov_configure(struct pci_dev
*dev
, int num_vfs
);
114 bool mlx5_sriov_is_enabled(struct mlx5_core_dev
*dev
);
115 int mlx5_core_enable_hca(struct mlx5_core_dev
*dev
, u16 func_id
);
116 int mlx5_core_disable_hca(struct mlx5_core_dev
*dev
, u16 func_id
);
117 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev
*dev
, u8 hierarchy
,
118 void *context
, u32
*element_id
);
119 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev
*dev
, u8 hierarchy
,
120 void *context
, u32 element_id
,
122 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev
*dev
, u8 hierarchy
,
124 int mlx5_wait_for_vf_pages(struct mlx5_core_dev
*dev
);
125 u64
mlx5_read_internal_timer(struct mlx5_core_dev
*dev
,
126 struct ptp_system_timestamp
*sts
);
128 void mlx5_cmd_trigger_completions(struct mlx5_core_dev
*dev
);
129 int mlx5_cq_debugfs_init(struct mlx5_core_dev
*dev
);
130 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev
*dev
);
132 int mlx5_query_pcam_reg(struct mlx5_core_dev
*dev
, u32
*pcam
, u8 feature_group
,
133 u8 access_reg_group
);
134 int mlx5_query_mcam_reg(struct mlx5_core_dev
*dev
, u32
*mcap
, u8 feature_group
,
135 u8 access_reg_group
);
136 int mlx5_query_qcam_reg(struct mlx5_core_dev
*mdev
, u32
*qcam
,
137 u8 feature_group
, u8 access_reg_group
);
139 void mlx5_lag_add(struct mlx5_core_dev
*dev
, struct net_device
*netdev
);
140 void mlx5_lag_remove(struct mlx5_core_dev
*dev
);
142 int mlx5_events_init(struct mlx5_core_dev
*dev
);
143 void mlx5_events_cleanup(struct mlx5_core_dev
*dev
);
144 void mlx5_events_start(struct mlx5_core_dev
*dev
);
145 void mlx5_events_stop(struct mlx5_core_dev
*dev
);
147 void mlx5_add_device(struct mlx5_interface
*intf
, struct mlx5_priv
*priv
);
148 void mlx5_remove_device(struct mlx5_interface
*intf
, struct mlx5_priv
*priv
);
149 void mlx5_attach_device(struct mlx5_core_dev
*dev
);
150 void mlx5_detach_device(struct mlx5_core_dev
*dev
);
151 bool mlx5_device_registered(struct mlx5_core_dev
*dev
);
152 int mlx5_register_device(struct mlx5_core_dev
*dev
);
153 void mlx5_unregister_device(struct mlx5_core_dev
*dev
);
154 void mlx5_add_dev_by_protocol(struct mlx5_core_dev
*dev
, int protocol
);
155 void mlx5_remove_dev_by_protocol(struct mlx5_core_dev
*dev
, int protocol
);
156 struct mlx5_core_dev
*mlx5_get_next_phys_dev(struct mlx5_core_dev
*dev
);
157 void mlx5_dev_list_lock(void);
158 void mlx5_dev_list_unlock(void);
159 int mlx5_dev_list_trylock(void);
161 bool mlx5_lag_intf_add(struct mlx5_interface
*intf
, struct mlx5_priv
*priv
);
163 int mlx5_query_mtpps(struct mlx5_core_dev
*dev
, u32
*mtpps
, u32 mtpps_size
);
164 int mlx5_set_mtpps(struct mlx5_core_dev
*mdev
, u32
*mtpps
, u32 mtpps_size
);
165 int mlx5_query_mtppse(struct mlx5_core_dev
*mdev
, u8 pin
, u8
*arm
, u8
*mode
);
166 int mlx5_set_mtppse(struct mlx5_core_dev
*mdev
, u8 pin
, u8 arm
, u8 mode
);
168 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \
169 MLX5_CAP_GEN((mdev), pps_modify) && \
170 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \
171 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))
173 int mlx5_firmware_flash(struct mlx5_core_dev
*dev
, const struct firmware
*fw
);
175 void mlx5e_init(void);
176 void mlx5e_cleanup(void);
178 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev
*dev
)
180 /* LACP owner conditions:
181 * 1) Function is physical.
182 * 2) LAG is supported by FW.
183 * 3) LAG is managed by driver (currently the only option).
185 return MLX5_CAP_GEN(dev
, vport_group_manager
) &&
186 (MLX5_CAP_GEN(dev
, num_lag_ports
) > 1) &&
187 MLX5_CAP_GEN(dev
, lag_master
);
190 int mlx5_lag_get_pf_num(struct mlx5_core_dev
*dev
, int *pf_num
);
192 void mlx5_reload_interface(struct mlx5_core_dev
*mdev
, int protocol
);
193 void mlx5_lag_update(struct mlx5_core_dev
*dev
);
196 MLX5_NIC_IFC_FULL
= 0,
197 MLX5_NIC_IFC_DISABLED
= 1,
198 MLX5_NIC_IFC_NO_DRAM_NIC
= 2,
199 MLX5_NIC_IFC_INVALID
= 3
202 u8
mlx5_get_nic_state(struct mlx5_core_dev
*dev
);
203 void mlx5_set_nic_state(struct mlx5_core_dev
*dev
, u8 state
);
204 #endif /* __MLX5_CORE_H__ */