2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/cmd.h>
37 #include "mlx5_core.h"
39 /* Scheduling element fw management */
40 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev
*dev
, u8 hierarchy
,
41 void *ctx
, u32
*element_id
)
43 u32 in
[MLX5_ST_SZ_DW(create_scheduling_element_in
)] = {0};
44 u32 out
[MLX5_ST_SZ_DW(create_scheduling_element_in
)] = {0};
48 schedc
= MLX5_ADDR_OF(create_scheduling_element_in
, in
,
50 MLX5_SET(create_scheduling_element_in
, in
, opcode
,
51 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT
);
52 MLX5_SET(create_scheduling_element_in
, in
, scheduling_hierarchy
,
54 memcpy(schedc
, ctx
, MLX5_ST_SZ_BYTES(scheduling_context
));
56 err
= mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, sizeof(out
));
60 *element_id
= MLX5_GET(create_scheduling_element_out
, out
,
61 scheduling_element_id
);
65 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev
*dev
, u8 hierarchy
,
66 void *ctx
, u32 element_id
,
69 u32 in
[MLX5_ST_SZ_DW(modify_scheduling_element_in
)] = {0};
70 u32 out
[MLX5_ST_SZ_DW(modify_scheduling_element_in
)] = {0};
73 schedc
= MLX5_ADDR_OF(modify_scheduling_element_in
, in
,
75 MLX5_SET(modify_scheduling_element_in
, in
, opcode
,
76 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT
);
77 MLX5_SET(modify_scheduling_element_in
, in
, scheduling_element_id
,
79 MLX5_SET(modify_scheduling_element_in
, in
, modify_bitmask
,
81 MLX5_SET(modify_scheduling_element_in
, in
, scheduling_hierarchy
,
83 memcpy(schedc
, ctx
, MLX5_ST_SZ_BYTES(scheduling_context
));
85 return mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, sizeof(out
));
88 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev
*dev
, u8 hierarchy
,
91 u32 in
[MLX5_ST_SZ_DW(destroy_scheduling_element_in
)] = {0};
92 u32 out
[MLX5_ST_SZ_DW(destroy_scheduling_element_in
)] = {0};
94 MLX5_SET(destroy_scheduling_element_in
, in
, opcode
,
95 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT
);
96 MLX5_SET(destroy_scheduling_element_in
, in
, scheduling_element_id
,
98 MLX5_SET(destroy_scheduling_element_in
, in
, scheduling_hierarchy
,
101 return mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, sizeof(out
));
104 /* Finds an entry where we can register the given rate
105 * If the rate already exists, return the entry where it is registered,
106 * otherwise return the first available entry.
107 * If the table is full, return NULL
109 static struct mlx5_rl_entry
*find_rl_entry(struct mlx5_rl_table
*table
,
110 struct mlx5_rate_limit
*rl
)
112 struct mlx5_rl_entry
*ret_entry
= NULL
;
113 bool empty_found
= false;
116 for (i
= 0; i
< table
->max_size
; i
++) {
117 if (mlx5_rl_are_equal(&table
->rl_entry
[i
].rl
, rl
))
118 return &table
->rl_entry
[i
];
119 if (!empty_found
&& !table
->rl_entry
[i
].rl
.rate
) {
121 ret_entry
= &table
->rl_entry
[i
];
128 static int mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev
*dev
,
130 struct mlx5_rate_limit
*rl
)
132 u32 in
[MLX5_ST_SZ_DW(set_pp_rate_limit_in
)] = {0};
133 u32 out
[MLX5_ST_SZ_DW(set_pp_rate_limit_out
)] = {0};
135 MLX5_SET(set_pp_rate_limit_in
, in
, opcode
,
136 MLX5_CMD_OP_SET_PP_RATE_LIMIT
);
137 MLX5_SET(set_pp_rate_limit_in
, in
, rate_limit_index
, index
);
138 MLX5_SET(set_pp_rate_limit_in
, in
, rate_limit
, rl
->rate
);
139 MLX5_SET(set_pp_rate_limit_in
, in
, burst_upper_bound
, rl
->max_burst_sz
);
140 MLX5_SET(set_pp_rate_limit_in
, in
, typical_packet_size
, rl
->typical_pkt_sz
);
141 return mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, sizeof(out
));
144 bool mlx5_rl_is_in_range(struct mlx5_core_dev
*dev
, u32 rate
)
146 struct mlx5_rl_table
*table
= &dev
->priv
.rl_table
;
148 return (rate
<= table
->max_rate
&& rate
>= table
->min_rate
);
150 EXPORT_SYMBOL(mlx5_rl_is_in_range
);
152 bool mlx5_rl_are_equal(struct mlx5_rate_limit
*rl_0
,
153 struct mlx5_rate_limit
*rl_1
)
155 return ((rl_0
->rate
== rl_1
->rate
) &&
156 (rl_0
->max_burst_sz
== rl_1
->max_burst_sz
) &&
157 (rl_0
->typical_pkt_sz
== rl_1
->typical_pkt_sz
));
159 EXPORT_SYMBOL(mlx5_rl_are_equal
);
161 int mlx5_rl_add_rate(struct mlx5_core_dev
*dev
, u16
*index
,
162 struct mlx5_rate_limit
*rl
)
164 struct mlx5_rl_table
*table
= &dev
->priv
.rl_table
;
165 struct mlx5_rl_entry
*entry
;
168 mutex_lock(&table
->rl_lock
);
170 if (!rl
->rate
|| !mlx5_rl_is_in_range(dev
, rl
->rate
)) {
171 mlx5_core_err(dev
, "Invalid rate: %u, should be %u to %u\n",
172 rl
->rate
, table
->min_rate
, table
->max_rate
);
177 entry
= find_rl_entry(table
, rl
);
179 mlx5_core_err(dev
, "Max number of %u rates reached\n",
184 if (entry
->refcount
) {
185 /* rate already configured */
189 err
= mlx5_set_pp_rate_limit_cmd(dev
, entry
->index
, rl
);
191 mlx5_core_err(dev
, "Failed configuring rate limit(err %d): \
192 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
193 err
, rl
->rate
, rl
->max_burst_sz
,
200 *index
= entry
->index
;
203 mutex_unlock(&table
->rl_lock
);
206 EXPORT_SYMBOL(mlx5_rl_add_rate
);
208 void mlx5_rl_remove_rate(struct mlx5_core_dev
*dev
, struct mlx5_rate_limit
*rl
)
210 struct mlx5_rl_table
*table
= &dev
->priv
.rl_table
;
211 struct mlx5_rl_entry
*entry
= NULL
;
212 struct mlx5_rate_limit reset_rl
= {0};
214 /* 0 is a reserved value for unlimited rate */
218 mutex_lock(&table
->rl_lock
);
219 entry
= find_rl_entry(table
, rl
);
220 if (!entry
|| !entry
->refcount
) {
221 mlx5_core_warn(dev
, "Rate %u, max_burst_sz %u typical_pkt_sz %u \
222 are not configured\n",
223 rl
->rate
, rl
->max_burst_sz
, rl
->typical_pkt_sz
);
228 if (!entry
->refcount
) {
229 /* need to remove rate */
230 mlx5_set_pp_rate_limit_cmd(dev
, entry
->index
, &reset_rl
);
231 entry
->rl
= reset_rl
;
235 mutex_unlock(&table
->rl_lock
);
237 EXPORT_SYMBOL(mlx5_rl_remove_rate
);
239 int mlx5_init_rl_table(struct mlx5_core_dev
*dev
)
241 struct mlx5_rl_table
*table
= &dev
->priv
.rl_table
;
244 mutex_init(&table
->rl_lock
);
245 if (!MLX5_CAP_GEN(dev
, qos
) || !MLX5_CAP_QOS(dev
, packet_pacing
)) {
250 /* First entry is reserved for unlimited rate */
251 table
->max_size
= MLX5_CAP_QOS(dev
, packet_pacing_rate_table_size
) - 1;
252 table
->max_rate
= MLX5_CAP_QOS(dev
, packet_pacing_max_rate
);
253 table
->min_rate
= MLX5_CAP_QOS(dev
, packet_pacing_min_rate
);
255 table
->rl_entry
= kcalloc(table
->max_size
, sizeof(struct mlx5_rl_entry
),
257 if (!table
->rl_entry
)
260 /* The index represents the index in HW rate limit table
261 * Index 0 is reserved for unlimited rate
263 for (i
= 0; i
< table
->max_size
; i
++)
264 table
->rl_entry
[i
].index
= i
+ 1;
266 /* Index 0 is reserved */
267 mlx5_core_info(dev
, "Rate limit: %u rates are supported, range: %uMbps to %uMbps\n",
269 table
->min_rate
>> 10,
270 table
->max_rate
>> 10);
275 void mlx5_cleanup_rl_table(struct mlx5_core_dev
*dev
)
277 struct mlx5_rl_table
*table
= &dev
->priv
.rl_table
;
278 struct mlx5_rate_limit rl
= {0};
281 /* Clear all configured rates */
282 for (i
= 0; i
< table
->max_size
; i
++)
283 if (table
->rl_entry
[i
].rl
.rate
)
284 mlx5_set_pp_rate_limit_cmd(dev
, table
->rl_entry
[i
].index
,
287 kfree(dev
->priv
.rl_table
.rl_entry
);