1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
7 #include <linux/etherdevice.h>
8 #include <linux/ethtool.h>
9 #include <linux/if_bridge.h>
10 #include <linux/if_ether.h>
11 #include <linux/if_vlan.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/phy.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/skbuff.h>
19 #include <linux/iopoll.h>
21 #include <net/netevent.h>
22 #include <net/rtnetlink.h>
23 #include <net/switchdev.h>
26 #include "ocelot_ace.h"
28 #define TABLE_UPDATE_SLEEP_US 10
29 #define TABLE_UPDATE_TIMEOUT_US 100000
31 /* MAC table entry types.
32 * ENTRYTYPE_NORMAL is subject to aging.
33 * ENTRYTYPE_LOCKED is not subject to aging.
34 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
35 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
37 enum macaccess_entry_type
{
44 struct ocelot_mact_entry
{
47 enum macaccess_entry_type type
;
50 static inline u32
ocelot_mact_read_macaccess(struct ocelot
*ocelot
)
52 return ocelot_read(ocelot
, ANA_TABLES_MACACCESS
);
55 static inline int ocelot_mact_wait_for_completion(struct ocelot
*ocelot
)
59 return readx_poll_timeout(ocelot_mact_read_macaccess
,
61 (val
& ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M
) ==
63 TABLE_UPDATE_SLEEP_US
, TABLE_UPDATE_TIMEOUT_US
);
66 static void ocelot_mact_select(struct ocelot
*ocelot
,
67 const unsigned char mac
[ETH_ALEN
],
70 u32 macl
= 0, mach
= 0;
72 /* Set the MAC address to handle and the vlan associated in a format
73 * understood by the hardware.
83 ocelot_write(ocelot
, macl
, ANA_TABLES_MACLDATA
);
84 ocelot_write(ocelot
, mach
, ANA_TABLES_MACHDATA
);
88 static int ocelot_mact_learn(struct ocelot
*ocelot
, int port
,
89 const unsigned char mac
[ETH_ALEN
],
91 enum macaccess_entry_type type
)
93 ocelot_mact_select(ocelot
, mac
, vid
);
95 /* Issue a write command */
96 ocelot_write(ocelot
, ANA_TABLES_MACACCESS_VALID
|
97 ANA_TABLES_MACACCESS_DEST_IDX(port
) |
98 ANA_TABLES_MACACCESS_ENTRYTYPE(type
) |
99 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN
),
100 ANA_TABLES_MACACCESS
);
102 return ocelot_mact_wait_for_completion(ocelot
);
105 static int ocelot_mact_forget(struct ocelot
*ocelot
,
106 const unsigned char mac
[ETH_ALEN
],
109 ocelot_mact_select(ocelot
, mac
, vid
);
111 /* Issue a forget command */
113 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET
),
114 ANA_TABLES_MACACCESS
);
116 return ocelot_mact_wait_for_completion(ocelot
);
119 static void ocelot_mact_init(struct ocelot
*ocelot
)
121 /* Configure the learning mode entries attributes:
122 * - Do not copy the frame to the CPU extraction queues.
123 * - Use the vlan and mac_cpoy for dmac lookup.
125 ocelot_rmw(ocelot
, 0,
126 ANA_AGENCTRL_LEARN_CPU_COPY
| ANA_AGENCTRL_IGNORE_DMAC_FLAGS
127 | ANA_AGENCTRL_LEARN_FWD_KILL
128 | ANA_AGENCTRL_LEARN_IGNORE_VLAN
,
131 /* Clear the MAC table */
132 ocelot_write(ocelot
, MACACCESS_CMD_INIT
, ANA_TABLES_MACACCESS
);
135 static void ocelot_vcap_enable(struct ocelot
*ocelot
, int port
)
137 ocelot_write_gix(ocelot
, ANA_PORT_VCAP_S2_CFG_S2_ENA
|
138 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
139 ANA_PORT_VCAP_S2_CFG
, port
);
142 static inline u32
ocelot_vlant_read_vlanaccess(struct ocelot
*ocelot
)
144 return ocelot_read(ocelot
, ANA_TABLES_VLANACCESS
);
147 static inline int ocelot_vlant_wait_for_completion(struct ocelot
*ocelot
)
151 return readx_poll_timeout(ocelot_vlant_read_vlanaccess
,
154 (val
& ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M
) ==
155 ANA_TABLES_VLANACCESS_CMD_IDLE
,
156 TABLE_UPDATE_SLEEP_US
, TABLE_UPDATE_TIMEOUT_US
);
159 static int ocelot_vlant_set_mask(struct ocelot
*ocelot
, u16 vid
, u32 mask
)
161 /* Select the VID to configure */
162 ocelot_write(ocelot
, ANA_TABLES_VLANTIDX_V_INDEX(vid
),
163 ANA_TABLES_VLANTIDX
);
164 /* Set the vlan port members mask and issue a write command */
165 ocelot_write(ocelot
, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask
) |
166 ANA_TABLES_VLANACCESS_CMD_WRITE
,
167 ANA_TABLES_VLANACCESS
);
169 return ocelot_vlant_wait_for_completion(ocelot
);
172 static void ocelot_vlan_mode(struct ocelot
*ocelot
, int port
,
173 netdev_features_t features
)
178 val
= ocelot_read(ocelot
, ANA_VLANMASK
);
179 if (features
& NETIF_F_HW_VLAN_CTAG_FILTER
)
183 ocelot_write(ocelot
, val
, ANA_VLANMASK
);
186 static int ocelot_port_set_native_vlan(struct ocelot
*ocelot
, int port
,
189 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
192 if (ocelot_port
->vid
!= vid
) {
193 /* Always permit deleting the native VLAN (vid = 0) */
194 if (ocelot_port
->vid
&& vid
) {
196 "Port already has a native VLAN: %d\n",
200 ocelot_port
->vid
= vid
;
203 ocelot_rmw_gix(ocelot
, REW_PORT_VLAN_CFG_PORT_VID(vid
),
204 REW_PORT_VLAN_CFG_PORT_VID_M
,
205 REW_PORT_VLAN_CFG
, port
);
207 if (ocelot_port
->vlan_aware
&& !ocelot_port
->vid
)
208 /* If port is vlan-aware and tagged, drop untagged and priority
211 val
= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA
|
212 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA
|
213 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA
;
214 ocelot_rmw_gix(ocelot
, val
,
215 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA
|
216 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA
|
217 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA
,
218 ANA_PORT_DROP_CFG
, port
);
220 if (ocelot_port
->vlan_aware
) {
221 if (ocelot_port
->vid
)
222 /* Tag all frames except when VID == DEFAULT_VLAN */
223 val
= REW_TAG_CFG_TAG_CFG(1);
226 val
= REW_TAG_CFG_TAG_CFG(3);
228 /* Port tagging disabled. */
229 val
= REW_TAG_CFG_TAG_CFG(0);
231 ocelot_rmw_gix(ocelot
, val
,
232 REW_TAG_CFG_TAG_CFG_M
,
238 void ocelot_port_vlan_filtering(struct ocelot
*ocelot
, int port
,
241 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
244 ocelot_port
->vlan_aware
= vlan_aware
;
247 val
= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA
|
248 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
251 ocelot_rmw_gix(ocelot
, val
,
252 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA
|
253 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M
,
254 ANA_PORT_VLAN_CFG
, port
);
256 ocelot_port_set_native_vlan(ocelot
, port
, ocelot_port
->vid
);
258 EXPORT_SYMBOL(ocelot_port_vlan_filtering
);
260 /* Default vlan to clasify for untagged frames (may be zero) */
261 static void ocelot_port_set_pvid(struct ocelot
*ocelot
, int port
, u16 pvid
)
263 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
265 ocelot_rmw_gix(ocelot
,
266 ANA_PORT_VLAN_CFG_VLAN_VID(pvid
),
267 ANA_PORT_VLAN_CFG_VLAN_VID_M
,
268 ANA_PORT_VLAN_CFG
, port
);
270 ocelot_port
->pvid
= pvid
;
273 int ocelot_vlan_add(struct ocelot
*ocelot
, int port
, u16 vid
, bool pvid
,
278 /* Make the port a member of the VLAN */
279 ocelot
->vlan_mask
[vid
] |= BIT(port
);
280 ret
= ocelot_vlant_set_mask(ocelot
, vid
, ocelot
->vlan_mask
[vid
]);
284 /* Default ingress vlan classification */
286 ocelot_port_set_pvid(ocelot
, port
, vid
);
288 /* Untagged egress vlan clasification */
290 ret
= ocelot_port_set_native_vlan(ocelot
, port
, vid
);
297 EXPORT_SYMBOL(ocelot_vlan_add
);
299 static int ocelot_vlan_vid_add(struct net_device
*dev
, u16 vid
, bool pvid
,
302 struct ocelot_port_private
*priv
= netdev_priv(dev
);
303 struct ocelot_port
*ocelot_port
= &priv
->port
;
304 struct ocelot
*ocelot
= ocelot_port
->ocelot
;
305 int port
= priv
->chip_port
;
308 ret
= ocelot_vlan_add(ocelot
, port
, vid
, pvid
, untagged
);
312 /* Add the port MAC address to with the right VLAN information */
313 ocelot_mact_learn(ocelot
, PGID_CPU
, dev
->dev_addr
, vid
,
319 int ocelot_vlan_del(struct ocelot
*ocelot
, int port
, u16 vid
)
321 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
324 /* Stop the port from being a member of the vlan */
325 ocelot
->vlan_mask
[vid
] &= ~BIT(port
);
326 ret
= ocelot_vlant_set_mask(ocelot
, vid
, ocelot
->vlan_mask
[vid
]);
331 if (ocelot_port
->pvid
== vid
)
332 ocelot_port_set_pvid(ocelot
, port
, 0);
335 if (ocelot_port
->vid
== vid
)
336 ocelot_port_set_native_vlan(ocelot
, port
, 0);
340 EXPORT_SYMBOL(ocelot_vlan_del
);
342 static int ocelot_vlan_vid_del(struct net_device
*dev
, u16 vid
)
344 struct ocelot_port_private
*priv
= netdev_priv(dev
);
345 struct ocelot
*ocelot
= priv
->port
.ocelot
;
346 int port
= priv
->chip_port
;
349 /* 8021q removes VID 0 on module unload for all interfaces
350 * with VLAN filtering feature. We need to keep it to receive
356 ret
= ocelot_vlan_del(ocelot
, port
, vid
);
360 /* Del the port MAC address to with the right VLAN information */
361 ocelot_mact_forget(ocelot
, dev
->dev_addr
, vid
);
366 static void ocelot_vlan_init(struct ocelot
*ocelot
)
370 /* Clear VLAN table, by default all ports are members of all VLANs */
371 ocelot_write(ocelot
, ANA_TABLES_VLANACCESS_CMD_INIT
,
372 ANA_TABLES_VLANACCESS
);
373 ocelot_vlant_wait_for_completion(ocelot
);
375 /* Configure the port VLAN memberships */
376 for (vid
= 1; vid
< VLAN_N_VID
; vid
++) {
377 ocelot
->vlan_mask
[vid
] = 0;
378 ocelot_vlant_set_mask(ocelot
, vid
, ocelot
->vlan_mask
[vid
]);
381 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
382 * traffic. It is added automatically if 8021q module is loaded, but
383 * we can't rely on it since module may be not loaded.
385 ocelot
->vlan_mask
[0] = GENMASK(ocelot
->num_phys_ports
- 1, 0);
386 ocelot_vlant_set_mask(ocelot
, 0, ocelot
->vlan_mask
[0]);
388 /* Set vlan ingress filter mask to all ports but the CPU port by
391 ocelot_write(ocelot
, GENMASK(ocelot
->num_phys_ports
- 1, 0),
394 for (port
= 0; port
< ocelot
->num_phys_ports
; port
++) {
395 ocelot_write_gix(ocelot
, 0, REW_PORT_VLAN_CFG
, port
);
396 ocelot_write_gix(ocelot
, 0, REW_TAG_CFG
, port
);
401 * Bit 8: Unit; 0:1, 1:16
402 * Bit 7-0: Value to be multiplied with unit
404 static u16
ocelot_wm_enc(u16 value
)
407 return BIT(8) | (value
/ 16);
412 void ocelot_adjust_link(struct ocelot
*ocelot
, int port
,
413 struct phy_device
*phydev
)
415 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
418 switch (phydev
->speed
) {
420 speed
= OCELOT_SPEED_10
;
423 speed
= OCELOT_SPEED_100
;
426 speed
= OCELOT_SPEED_1000
;
427 mode
= DEV_MAC_MODE_CFG_GIGA_MODE_ENA
;
430 speed
= OCELOT_SPEED_2500
;
431 mode
= DEV_MAC_MODE_CFG_GIGA_MODE_ENA
;
434 dev_err(ocelot
->dev
, "Unsupported PHY speed on port %d: %d\n",
435 port
, phydev
->speed
);
439 phy_print_status(phydev
);
444 /* Only full duplex supported for now */
445 ocelot_port_writel(ocelot_port
, DEV_MAC_MODE_CFG_FDX_ENA
|
446 mode
, DEV_MAC_MODE_CFG
);
448 /* Disable HDX fast control */
449 ocelot_port_writel(ocelot_port
, DEV_PORT_MISC_HDX_FAST_DIS
,
452 /* SGMII only for now */
453 ocelot_port_writel(ocelot_port
, PCS1G_MODE_CFG_SGMII_MODE_ENA
,
455 ocelot_port_writel(ocelot_port
, PCS1G_SD_CFG_SD_SEL
, PCS1G_SD_CFG
);
458 ocelot_port_writel(ocelot_port
, PCS1G_CFG_PCS_ENA
, PCS1G_CFG
);
460 /* No aneg on SGMII */
461 ocelot_port_writel(ocelot_port
, 0, PCS1G_ANEG_CFG
);
464 ocelot_port_writel(ocelot_port
, 0, PCS1G_LB_CFG
);
466 /* Enable MAC module */
467 ocelot_port_writel(ocelot_port
, DEV_MAC_ENA_CFG_RX_ENA
|
468 DEV_MAC_ENA_CFG_TX_ENA
, DEV_MAC_ENA_CFG
);
470 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
472 ocelot_port_writel(ocelot_port
, DEV_CLOCK_CFG_LINK_SPEED(speed
),
476 ocelot_write_gix(ocelot
, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed
),
477 ANA_PFC_PFC_CFG
, port
);
479 /* Core: Enable port for frame transfer */
480 ocelot_write_rix(ocelot
, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE
|
481 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
482 QSYS_SWITCH_PORT_MODE_PORT_ENA
,
483 QSYS_SWITCH_PORT_MODE
, port
);
486 ocelot_write_rix(ocelot
, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
487 SYS_MAC_FC_CFG_RX_FC_ENA
| SYS_MAC_FC_CFG_TX_FC_ENA
|
488 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA
|
489 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
490 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed
),
491 SYS_MAC_FC_CFG
, port
);
492 ocelot_write_rix(ocelot
, 0, ANA_POL_FLOWC
, port
);
494 EXPORT_SYMBOL(ocelot_adjust_link
);
496 static void ocelot_port_adjust_link(struct net_device
*dev
)
498 struct ocelot_port_private
*priv
= netdev_priv(dev
);
499 struct ocelot
*ocelot
= priv
->port
.ocelot
;
500 int port
= priv
->chip_port
;
502 ocelot_adjust_link(ocelot
, port
, dev
->phydev
);
505 void ocelot_port_enable(struct ocelot
*ocelot
, int port
,
506 struct phy_device
*phy
)
508 /* Enable receiving frames on the port, and activate auto-learning of
511 ocelot_write_gix(ocelot
, ANA_PORT_PORT_CFG_LEARNAUTO
|
512 ANA_PORT_PORT_CFG_RECV_ENA
|
513 ANA_PORT_PORT_CFG_PORTID_VAL(port
),
514 ANA_PORT_PORT_CFG
, port
);
516 EXPORT_SYMBOL(ocelot_port_enable
);
518 static int ocelot_port_open(struct net_device
*dev
)
520 struct ocelot_port_private
*priv
= netdev_priv(dev
);
521 struct ocelot_port
*ocelot_port
= &priv
->port
;
522 struct ocelot
*ocelot
= ocelot_port
->ocelot
;
523 int port
= priv
->chip_port
;
527 err
= phy_set_mode_ext(priv
->serdes
, PHY_MODE_ETHERNET
,
528 ocelot_port
->phy_mode
);
530 netdev_err(dev
, "Could not set mode of SerDes\n");
535 err
= phy_connect_direct(dev
, priv
->phy
, &ocelot_port_adjust_link
,
536 ocelot_port
->phy_mode
);
538 netdev_err(dev
, "Could not attach to PHY\n");
542 dev
->phydev
= priv
->phy
;
544 phy_attached_info(priv
->phy
);
545 phy_start(priv
->phy
);
547 ocelot_port_enable(ocelot
, port
, priv
->phy
);
552 void ocelot_port_disable(struct ocelot
*ocelot
, int port
)
554 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
556 ocelot_port_writel(ocelot_port
, 0, DEV_MAC_ENA_CFG
);
557 ocelot_rmw_rix(ocelot
, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA
,
558 QSYS_SWITCH_PORT_MODE
, port
);
560 EXPORT_SYMBOL(ocelot_port_disable
);
562 static int ocelot_port_stop(struct net_device
*dev
)
564 struct ocelot_port_private
*priv
= netdev_priv(dev
);
565 struct ocelot
*ocelot
= priv
->port
.ocelot
;
566 int port
= priv
->chip_port
;
568 phy_disconnect(priv
->phy
);
572 ocelot_port_disable(ocelot
, port
);
577 /* Generate the IFH for frame injection
579 * The IFH is a 128bit-value
580 * bit 127: bypass the analyzer processing
581 * bit 56-67: destination mask
582 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
583 * bit 20-27: cpu extraction queue mask
584 * bit 16: tag type 0: C-tag, 1: S-tag
587 static int ocelot_gen_ifh(u32
*ifh
, struct frame_info
*info
)
589 ifh
[0] = IFH_INJ_BYPASS
| ((0x1ff & info
->rew_op
) << 21);
590 ifh
[1] = (0xf00 & info
->port
) >> 8;
591 ifh
[2] = (0xff & info
->port
) << 24;
592 ifh
[3] = (info
->tag_type
<< 16) | info
->vid
;
597 int ocelot_port_add_txtstamp_skb(struct ocelot_port
*ocelot_port
,
600 struct skb_shared_info
*shinfo
= skb_shinfo(skb
);
601 struct ocelot
*ocelot
= ocelot_port
->ocelot
;
603 if (ocelot
->ptp
&& shinfo
->tx_flags
& SKBTX_HW_TSTAMP
&&
604 ocelot_port
->ptp_cmd
== IFH_REW_OP_TWO_STEP_PTP
) {
605 shinfo
->tx_flags
|= SKBTX_IN_PROGRESS
;
606 /* Store timestamp ID in cb[0] of sk_buff */
607 skb
->cb
[0] = ocelot_port
->ts_id
% 4;
608 skb_queue_tail(&ocelot_port
->tx_skbs
, skb
);
613 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb
);
615 static int ocelot_port_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
617 struct ocelot_port_private
*priv
= netdev_priv(dev
);
618 struct skb_shared_info
*shinfo
= skb_shinfo(skb
);
619 struct ocelot_port
*ocelot_port
= &priv
->port
;
620 struct ocelot
*ocelot
= ocelot_port
->ocelot
;
621 u32 val
, ifh
[OCELOT_TAG_LEN
/ 4];
622 struct frame_info info
= {};
623 u8 grp
= 0; /* Send everything on CPU group 0 */
624 unsigned int i
, count
, last
;
625 int port
= priv
->chip_port
;
627 val
= ocelot_read(ocelot
, QS_INJ_STATUS
);
628 if (!(val
& QS_INJ_STATUS_FIFO_RDY(BIT(grp
))) ||
629 (val
& QS_INJ_STATUS_WMARK_REACHED(BIT(grp
))))
630 return NETDEV_TX_BUSY
;
632 ocelot_write_rix(ocelot
, QS_INJ_CTRL_GAP_SIZE(1) |
633 QS_INJ_CTRL_SOF
, QS_INJ_CTRL
, grp
);
635 info
.port
= BIT(port
);
636 info
.tag_type
= IFH_TAG_TYPE_C
;
637 info
.vid
= skb_vlan_tag_get(skb
);
639 /* Check if timestamping is needed */
640 if (ocelot
->ptp
&& shinfo
->tx_flags
& SKBTX_HW_TSTAMP
) {
641 info
.rew_op
= ocelot_port
->ptp_cmd
;
642 if (ocelot_port
->ptp_cmd
== IFH_REW_OP_TWO_STEP_PTP
)
643 info
.rew_op
|= (ocelot_port
->ts_id
% 4) << 3;
646 ocelot_gen_ifh(ifh
, &info
);
648 for (i
= 0; i
< OCELOT_TAG_LEN
/ 4; i
++)
649 ocelot_write_rix(ocelot
, (__force u32
)cpu_to_be32(ifh
[i
]),
652 count
= (skb
->len
+ 3) / 4;
654 for (i
= 0; i
< count
; i
++) {
655 ocelot_write_rix(ocelot
, ((u32
*)skb
->data
)[i
], QS_INJ_WR
, grp
);
659 while (i
< (OCELOT_BUFFER_CELL_SZ
/ 4)) {
660 ocelot_write_rix(ocelot
, 0, QS_INJ_WR
, grp
);
664 /* Indicate EOF and valid bytes in last word */
665 ocelot_write_rix(ocelot
, QS_INJ_CTRL_GAP_SIZE(1) |
666 QS_INJ_CTRL_VLD_BYTES(skb
->len
< OCELOT_BUFFER_CELL_SZ
? 0 : last
) |
671 ocelot_write_rix(ocelot
, 0, QS_INJ_WR
, grp
);
672 skb_tx_timestamp(skb
);
674 dev
->stats
.tx_packets
++;
675 dev
->stats
.tx_bytes
+= skb
->len
;
677 if (!ocelot_port_add_txtstamp_skb(ocelot_port
, skb
)) {
678 ocelot_port
->ts_id
++;
682 dev_kfree_skb_any(skb
);
686 static void ocelot_get_hwtimestamp(struct ocelot
*ocelot
,
687 struct timespec64
*ts
)
692 spin_lock_irqsave(&ocelot
->ptp_clock_lock
, flags
);
694 /* Read current PTP time to get seconds */
695 val
= ocelot_read_rix(ocelot
, PTP_PIN_CFG
, TOD_ACC_PIN
);
697 val
&= ~(PTP_PIN_CFG_SYNC
| PTP_PIN_CFG_ACTION_MASK
| PTP_PIN_CFG_DOM
);
698 val
|= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE
);
699 ocelot_write_rix(ocelot
, val
, PTP_PIN_CFG
, TOD_ACC_PIN
);
700 ts
->tv_sec
= ocelot_read_rix(ocelot
, PTP_PIN_TOD_SEC_LSB
, TOD_ACC_PIN
);
702 /* Read packet HW timestamp from FIFO */
703 val
= ocelot_read(ocelot
, SYS_PTP_TXSTAMP
);
704 ts
->tv_nsec
= SYS_PTP_TXSTAMP_PTP_TXSTAMP(val
);
706 /* Sec has incremented since the ts was registered */
707 if ((ts
->tv_sec
& 0x1) != !!(val
& SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC
))
710 spin_unlock_irqrestore(&ocelot
->ptp_clock_lock
, flags
);
713 void ocelot_get_txtstamp(struct ocelot
*ocelot
)
715 int budget
= OCELOT_PTP_QUEUE_SZ
;
718 struct sk_buff
*skb
, *skb_tmp
, *skb_match
= NULL
;
719 struct skb_shared_hwtstamps shhwtstamps
;
720 struct ocelot_port
*port
;
721 struct timespec64 ts
;
725 val
= ocelot_read(ocelot
, SYS_PTP_STATUS
);
727 /* Check if a timestamp can be retrieved */
728 if (!(val
& SYS_PTP_STATUS_PTP_MESS_VLD
))
731 WARN_ON(val
& SYS_PTP_STATUS_PTP_OVFL
);
733 /* Retrieve the ts ID and Tx port */
734 id
= SYS_PTP_STATUS_PTP_MESS_ID_X(val
);
735 txport
= SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val
);
737 /* Retrieve its associated skb */
738 port
= ocelot
->ports
[txport
];
740 spin_lock_irqsave(&port
->tx_skbs
.lock
, flags
);
742 skb_queue_walk_safe(&port
->tx_skbs
, skb
, skb_tmp
) {
743 if (skb
->cb
[0] != id
)
745 __skb_unlink(skb
, &port
->tx_skbs
);
750 spin_unlock_irqrestore(&port
->tx_skbs
.lock
, flags
);
753 ocelot_write(ocelot
, SYS_PTP_NXT_PTP_NXT
, SYS_PTP_NXT
);
755 if (unlikely(!skb_match
))
758 /* Get the h/w timestamp */
759 ocelot_get_hwtimestamp(ocelot
, &ts
);
761 /* Set the timestamp into the skb */
762 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
763 shhwtstamps
.hwtstamp
= ktime_set(ts
.tv_sec
, ts
.tv_nsec
);
764 skb_tstamp_tx(skb_match
, &shhwtstamps
);
766 dev_kfree_skb_any(skb_match
);
769 EXPORT_SYMBOL(ocelot_get_txtstamp
);
771 static int ocelot_mc_unsync(struct net_device
*dev
, const unsigned char *addr
)
773 struct ocelot_port_private
*priv
= netdev_priv(dev
);
774 struct ocelot_port
*ocelot_port
= &priv
->port
;
775 struct ocelot
*ocelot
= ocelot_port
->ocelot
;
777 return ocelot_mact_forget(ocelot
, addr
, ocelot_port
->pvid
);
780 static int ocelot_mc_sync(struct net_device
*dev
, const unsigned char *addr
)
782 struct ocelot_port_private
*priv
= netdev_priv(dev
);
783 struct ocelot_port
*ocelot_port
= &priv
->port
;
784 struct ocelot
*ocelot
= ocelot_port
->ocelot
;
786 return ocelot_mact_learn(ocelot
, PGID_CPU
, addr
, ocelot_port
->pvid
,
790 static void ocelot_set_rx_mode(struct net_device
*dev
)
792 struct ocelot_port_private
*priv
= netdev_priv(dev
);
793 struct ocelot
*ocelot
= priv
->port
.ocelot
;
797 /* This doesn't handle promiscuous mode because the bridge core is
798 * setting IFF_PROMISC on all slave interfaces and all frames would be
799 * forwarded to the CPU port.
801 val
= GENMASK(ocelot
->num_phys_ports
- 1, 0);
802 for (i
= ocelot
->num_phys_ports
+ 1; i
< PGID_CPU
; i
++)
803 ocelot_write_rix(ocelot
, val
, ANA_PGID_PGID
, i
);
805 __dev_mc_sync(dev
, ocelot_mc_sync
, ocelot_mc_unsync
);
808 static int ocelot_port_get_phys_port_name(struct net_device
*dev
,
809 char *buf
, size_t len
)
811 struct ocelot_port_private
*priv
= netdev_priv(dev
);
812 int port
= priv
->chip_port
;
815 ret
= snprintf(buf
, len
, "p%d", port
);
822 static int ocelot_port_set_mac_address(struct net_device
*dev
, void *p
)
824 struct ocelot_port_private
*priv
= netdev_priv(dev
);
825 struct ocelot_port
*ocelot_port
= &priv
->port
;
826 struct ocelot
*ocelot
= ocelot_port
->ocelot
;
827 const struct sockaddr
*addr
= p
;
829 /* Learn the new net device MAC address in the mac table. */
830 ocelot_mact_learn(ocelot
, PGID_CPU
, addr
->sa_data
, ocelot_port
->pvid
,
832 /* Then forget the previous one. */
833 ocelot_mact_forget(ocelot
, dev
->dev_addr
, ocelot_port
->pvid
);
835 ether_addr_copy(dev
->dev_addr
, addr
->sa_data
);
839 static void ocelot_get_stats64(struct net_device
*dev
,
840 struct rtnl_link_stats64
*stats
)
842 struct ocelot_port_private
*priv
= netdev_priv(dev
);
843 struct ocelot
*ocelot
= priv
->port
.ocelot
;
844 int port
= priv
->chip_port
;
846 /* Configure the port to read the stats from */
847 ocelot_write(ocelot
, SYS_STAT_CFG_STAT_VIEW(port
),
851 stats
->rx_bytes
= ocelot_read(ocelot
, SYS_COUNT_RX_OCTETS
);
852 stats
->rx_packets
= ocelot_read(ocelot
, SYS_COUNT_RX_SHORTS
) +
853 ocelot_read(ocelot
, SYS_COUNT_RX_FRAGMENTS
) +
854 ocelot_read(ocelot
, SYS_COUNT_RX_JABBERS
) +
855 ocelot_read(ocelot
, SYS_COUNT_RX_LONGS
) +
856 ocelot_read(ocelot
, SYS_COUNT_RX_64
) +
857 ocelot_read(ocelot
, SYS_COUNT_RX_65_127
) +
858 ocelot_read(ocelot
, SYS_COUNT_RX_128_255
) +
859 ocelot_read(ocelot
, SYS_COUNT_RX_256_1023
) +
860 ocelot_read(ocelot
, SYS_COUNT_RX_1024_1526
) +
861 ocelot_read(ocelot
, SYS_COUNT_RX_1527_MAX
);
862 stats
->multicast
= ocelot_read(ocelot
, SYS_COUNT_RX_MULTICAST
);
863 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
866 stats
->tx_bytes
= ocelot_read(ocelot
, SYS_COUNT_TX_OCTETS
);
867 stats
->tx_packets
= ocelot_read(ocelot
, SYS_COUNT_TX_64
) +
868 ocelot_read(ocelot
, SYS_COUNT_TX_65_127
) +
869 ocelot_read(ocelot
, SYS_COUNT_TX_128_511
) +
870 ocelot_read(ocelot
, SYS_COUNT_TX_512_1023
) +
871 ocelot_read(ocelot
, SYS_COUNT_TX_1024_1526
) +
872 ocelot_read(ocelot
, SYS_COUNT_TX_1527_MAX
);
873 stats
->tx_dropped
= ocelot_read(ocelot
, SYS_COUNT_TX_DROPS
) +
874 ocelot_read(ocelot
, SYS_COUNT_TX_AGING
);
875 stats
->collisions
= ocelot_read(ocelot
, SYS_COUNT_TX_COLLISION
);
878 int ocelot_fdb_add(struct ocelot
*ocelot
, int port
,
879 const unsigned char *addr
, u16 vid
)
881 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
884 if (!ocelot_port
->vlan_aware
)
885 /* If the bridge is not VLAN aware and no VID was
886 * provided, set it to pvid to ensure the MAC entry
887 * matches incoming untagged packets
889 vid
= ocelot_port
->pvid
;
891 /* If the bridge is VLAN aware a VID must be provided as
892 * otherwise the learnt entry wouldn't match any frame.
897 return ocelot_mact_learn(ocelot
, port
, addr
, vid
, ENTRYTYPE_LOCKED
);
899 EXPORT_SYMBOL(ocelot_fdb_add
);
901 static int ocelot_port_fdb_add(struct ndmsg
*ndm
, struct nlattr
*tb
[],
902 struct net_device
*dev
,
903 const unsigned char *addr
,
905 struct netlink_ext_ack
*extack
)
907 struct ocelot_port_private
*priv
= netdev_priv(dev
);
908 struct ocelot
*ocelot
= priv
->port
.ocelot
;
909 int port
= priv
->chip_port
;
911 return ocelot_fdb_add(ocelot
, port
, addr
, vid
);
914 int ocelot_fdb_del(struct ocelot
*ocelot
, int port
,
915 const unsigned char *addr
, u16 vid
)
917 return ocelot_mact_forget(ocelot
, addr
, vid
);
919 EXPORT_SYMBOL(ocelot_fdb_del
);
921 static int ocelot_port_fdb_del(struct ndmsg
*ndm
, struct nlattr
*tb
[],
922 struct net_device
*dev
,
923 const unsigned char *addr
, u16 vid
)
925 struct ocelot_port_private
*priv
= netdev_priv(dev
);
926 struct ocelot
*ocelot
= priv
->port
.ocelot
;
927 int port
= priv
->chip_port
;
929 return ocelot_fdb_del(ocelot
, port
, addr
, vid
);
932 struct ocelot_dump_ctx
{
933 struct net_device
*dev
;
935 struct netlink_callback
*cb
;
939 static int ocelot_port_fdb_do_dump(const unsigned char *addr
, u16 vid
,
940 bool is_static
, void *data
)
942 struct ocelot_dump_ctx
*dump
= data
;
943 u32 portid
= NETLINK_CB(dump
->cb
->skb
).portid
;
944 u32 seq
= dump
->cb
->nlh
->nlmsg_seq
;
945 struct nlmsghdr
*nlh
;
948 if (dump
->idx
< dump
->cb
->args
[2])
951 nlh
= nlmsg_put(dump
->skb
, portid
, seq
, RTM_NEWNEIGH
,
952 sizeof(*ndm
), NLM_F_MULTI
);
956 ndm
= nlmsg_data(nlh
);
957 ndm
->ndm_family
= AF_BRIDGE
;
960 ndm
->ndm_flags
= NTF_SELF
;
962 ndm
->ndm_ifindex
= dump
->dev
->ifindex
;
963 ndm
->ndm_state
= is_static
? NUD_NOARP
: NUD_REACHABLE
;
965 if (nla_put(dump
->skb
, NDA_LLADDR
, ETH_ALEN
, addr
))
966 goto nla_put_failure
;
968 if (vid
&& nla_put_u16(dump
->skb
, NDA_VLAN
, vid
))
969 goto nla_put_failure
;
971 nlmsg_end(dump
->skb
, nlh
);
978 nlmsg_cancel(dump
->skb
, nlh
);
982 static int ocelot_mact_read(struct ocelot
*ocelot
, int port
, int row
, int col
,
983 struct ocelot_mact_entry
*entry
)
985 u32 val
, dst
, macl
, mach
;
988 /* Set row and column to read from */
989 ocelot_field_write(ocelot
, ANA_TABLES_MACTINDX_M_INDEX
, row
);
990 ocelot_field_write(ocelot
, ANA_TABLES_MACTINDX_BUCKET
, col
);
992 /* Issue a read command */
994 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ
),
995 ANA_TABLES_MACACCESS
);
997 if (ocelot_mact_wait_for_completion(ocelot
))
1000 /* Read the entry flags */
1001 val
= ocelot_read(ocelot
, ANA_TABLES_MACACCESS
);
1002 if (!(val
& ANA_TABLES_MACACCESS_VALID
))
1005 /* If the entry read has another port configured as its destination,
1008 dst
= (val
& ANA_TABLES_MACACCESS_DEST_IDX_M
) >> 3;
1012 /* Get the entry's MAC address and VLAN id */
1013 macl
= ocelot_read(ocelot
, ANA_TABLES_MACLDATA
);
1014 mach
= ocelot_read(ocelot
, ANA_TABLES_MACHDATA
);
1016 mac
[0] = (mach
>> 8) & 0xff;
1017 mac
[1] = (mach
>> 0) & 0xff;
1018 mac
[2] = (macl
>> 24) & 0xff;
1019 mac
[3] = (macl
>> 16) & 0xff;
1020 mac
[4] = (macl
>> 8) & 0xff;
1021 mac
[5] = (macl
>> 0) & 0xff;
1023 entry
->vid
= (mach
>> 16) & 0xfff;
1024 ether_addr_copy(entry
->mac
, mac
);
1029 int ocelot_fdb_dump(struct ocelot
*ocelot
, int port
,
1030 dsa_fdb_dump_cb_t
*cb
, void *data
)
1034 /* Loop through all the mac tables entries. */
1035 for (i
= 0; i
< ocelot
->num_mact_rows
; i
++) {
1036 for (j
= 0; j
< 4; j
++) {
1037 struct ocelot_mact_entry entry
;
1041 ret
= ocelot_mact_read(ocelot
, port
, i
, j
, &entry
);
1042 /* If the entry is invalid (wrong port, invalid...),
1050 is_static
= (entry
.type
== ENTRYTYPE_LOCKED
);
1052 ret
= cb(entry
.mac
, entry
.vid
, is_static
, data
);
1060 EXPORT_SYMBOL(ocelot_fdb_dump
);
1062 static int ocelot_port_fdb_dump(struct sk_buff
*skb
,
1063 struct netlink_callback
*cb
,
1064 struct net_device
*dev
,
1065 struct net_device
*filter_dev
, int *idx
)
1067 struct ocelot_port_private
*priv
= netdev_priv(dev
);
1068 struct ocelot
*ocelot
= priv
->port
.ocelot
;
1069 struct ocelot_dump_ctx dump
= {
1075 int port
= priv
->chip_port
;
1078 ret
= ocelot_fdb_dump(ocelot
, port
, ocelot_port_fdb_do_dump
, &dump
);
1085 static int ocelot_vlan_rx_add_vid(struct net_device
*dev
, __be16 proto
,
1088 return ocelot_vlan_vid_add(dev
, vid
, false, false);
1091 static int ocelot_vlan_rx_kill_vid(struct net_device
*dev
, __be16 proto
,
1094 return ocelot_vlan_vid_del(dev
, vid
);
1097 static int ocelot_set_features(struct net_device
*dev
,
1098 netdev_features_t features
)
1100 netdev_features_t changed
= dev
->features
^ features
;
1101 struct ocelot_port_private
*priv
= netdev_priv(dev
);
1102 struct ocelot
*ocelot
= priv
->port
.ocelot
;
1103 int port
= priv
->chip_port
;
1105 if ((dev
->features
& NETIF_F_HW_TC
) > (features
& NETIF_F_HW_TC
) &&
1106 priv
->tc
.offload_cnt
) {
1108 "Cannot disable HW TC offload while offloads active\n");
1112 if (changed
& NETIF_F_HW_VLAN_CTAG_FILTER
)
1113 ocelot_vlan_mode(ocelot
, port
, features
);
1118 static int ocelot_get_port_parent_id(struct net_device
*dev
,
1119 struct netdev_phys_item_id
*ppid
)
1121 struct ocelot_port_private
*priv
= netdev_priv(dev
);
1122 struct ocelot
*ocelot
= priv
->port
.ocelot
;
1124 ppid
->id_len
= sizeof(ocelot
->base_mac
);
1125 memcpy(&ppid
->id
, &ocelot
->base_mac
, ppid
->id_len
);
1130 int ocelot_hwstamp_get(struct ocelot
*ocelot
, int port
, struct ifreq
*ifr
)
1132 return copy_to_user(ifr
->ifr_data
, &ocelot
->hwtstamp_config
,
1133 sizeof(ocelot
->hwtstamp_config
)) ? -EFAULT
: 0;
1135 EXPORT_SYMBOL(ocelot_hwstamp_get
);
1137 int ocelot_hwstamp_set(struct ocelot
*ocelot
, int port
, struct ifreq
*ifr
)
1139 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
1140 struct hwtstamp_config cfg
;
1142 if (copy_from_user(&cfg
, ifr
->ifr_data
, sizeof(cfg
)))
1145 /* reserved for future extensions */
1149 /* Tx type sanity check */
1150 switch (cfg
.tx_type
) {
1151 case HWTSTAMP_TX_ON
:
1152 ocelot_port
->ptp_cmd
= IFH_REW_OP_TWO_STEP_PTP
;
1154 case HWTSTAMP_TX_ONESTEP_SYNC
:
1155 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
1156 * need to update the origin time.
1158 ocelot_port
->ptp_cmd
= IFH_REW_OP_ORIGIN_PTP
;
1160 case HWTSTAMP_TX_OFF
:
1161 ocelot_port
->ptp_cmd
= 0;
1167 mutex_lock(&ocelot
->ptp_lock
);
1169 switch (cfg
.rx_filter
) {
1170 case HWTSTAMP_FILTER_NONE
:
1172 case HWTSTAMP_FILTER_ALL
:
1173 case HWTSTAMP_FILTER_SOME
:
1174 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
1175 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
1176 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
1177 case HWTSTAMP_FILTER_NTP_ALL
:
1178 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
1179 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
1180 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
1181 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
1182 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
1183 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
1184 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
1185 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
1186 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
1187 cfg
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
1190 mutex_unlock(&ocelot
->ptp_lock
);
1194 /* Commit back the result & save it */
1195 memcpy(&ocelot
->hwtstamp_config
, &cfg
, sizeof(cfg
));
1196 mutex_unlock(&ocelot
->ptp_lock
);
1198 return copy_to_user(ifr
->ifr_data
, &cfg
, sizeof(cfg
)) ? -EFAULT
: 0;
1200 EXPORT_SYMBOL(ocelot_hwstamp_set
);
1202 static int ocelot_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1204 struct ocelot_port_private
*priv
= netdev_priv(dev
);
1205 struct ocelot
*ocelot
= priv
->port
.ocelot
;
1206 int port
= priv
->chip_port
;
1208 /* The function is only used for PTP operations for now */
1214 return ocelot_hwstamp_set(ocelot
, port
, ifr
);
1216 return ocelot_hwstamp_get(ocelot
, port
, ifr
);
1222 static const struct net_device_ops ocelot_port_netdev_ops
= {
1223 .ndo_open
= ocelot_port_open
,
1224 .ndo_stop
= ocelot_port_stop
,
1225 .ndo_start_xmit
= ocelot_port_xmit
,
1226 .ndo_set_rx_mode
= ocelot_set_rx_mode
,
1227 .ndo_get_phys_port_name
= ocelot_port_get_phys_port_name
,
1228 .ndo_set_mac_address
= ocelot_port_set_mac_address
,
1229 .ndo_get_stats64
= ocelot_get_stats64
,
1230 .ndo_fdb_add
= ocelot_port_fdb_add
,
1231 .ndo_fdb_del
= ocelot_port_fdb_del
,
1232 .ndo_fdb_dump
= ocelot_port_fdb_dump
,
1233 .ndo_vlan_rx_add_vid
= ocelot_vlan_rx_add_vid
,
1234 .ndo_vlan_rx_kill_vid
= ocelot_vlan_rx_kill_vid
,
1235 .ndo_set_features
= ocelot_set_features
,
1236 .ndo_get_port_parent_id
= ocelot_get_port_parent_id
,
1237 .ndo_setup_tc
= ocelot_setup_tc
,
1238 .ndo_do_ioctl
= ocelot_ioctl
,
1241 void ocelot_get_strings(struct ocelot
*ocelot
, int port
, u32 sset
, u8
*data
)
1245 if (sset
!= ETH_SS_STATS
)
1248 for (i
= 0; i
< ocelot
->num_stats
; i
++)
1249 memcpy(data
+ i
* ETH_GSTRING_LEN
, ocelot
->stats_layout
[i
].name
,
1252 EXPORT_SYMBOL(ocelot_get_strings
);
1254 static void ocelot_port_get_strings(struct net_device
*netdev
, u32 sset
,
1257 struct ocelot_port_private
*priv
= netdev_priv(netdev
);
1258 struct ocelot
*ocelot
= priv
->port
.ocelot
;
1259 int port
= priv
->chip_port
;
1261 ocelot_get_strings(ocelot
, port
, sset
, data
);
1264 static void ocelot_update_stats(struct ocelot
*ocelot
)
1268 mutex_lock(&ocelot
->stats_lock
);
1270 for (i
= 0; i
< ocelot
->num_phys_ports
; i
++) {
1271 /* Configure the port to read the stats from */
1272 ocelot_write(ocelot
, SYS_STAT_CFG_STAT_VIEW(i
), SYS_STAT_CFG
);
1274 for (j
= 0; j
< ocelot
->num_stats
; j
++) {
1276 unsigned int idx
= i
* ocelot
->num_stats
+ j
;
1278 val
= ocelot_read_rix(ocelot
, SYS_COUNT_RX_OCTETS
,
1279 ocelot
->stats_layout
[j
].offset
);
1281 if (val
< (ocelot
->stats
[idx
] & U32_MAX
))
1282 ocelot
->stats
[idx
] += (u64
)1 << 32;
1284 ocelot
->stats
[idx
] = (ocelot
->stats
[idx
] &
1285 ~(u64
)U32_MAX
) + val
;
1289 mutex_unlock(&ocelot
->stats_lock
);
1292 static void ocelot_check_stats_work(struct work_struct
*work
)
1294 struct delayed_work
*del_work
= to_delayed_work(work
);
1295 struct ocelot
*ocelot
= container_of(del_work
, struct ocelot
,
1298 ocelot_update_stats(ocelot
);
1300 queue_delayed_work(ocelot
->stats_queue
, &ocelot
->stats_work
,
1301 OCELOT_STATS_CHECK_DELAY
);
1304 void ocelot_get_ethtool_stats(struct ocelot
*ocelot
, int port
, u64
*data
)
1308 /* check and update now */
1309 ocelot_update_stats(ocelot
);
1311 /* Copy all counters */
1312 for (i
= 0; i
< ocelot
->num_stats
; i
++)
1313 *data
++ = ocelot
->stats
[port
* ocelot
->num_stats
+ i
];
1315 EXPORT_SYMBOL(ocelot_get_ethtool_stats
);
1317 static void ocelot_port_get_ethtool_stats(struct net_device
*dev
,
1318 struct ethtool_stats
*stats
,
1321 struct ocelot_port_private
*priv
= netdev_priv(dev
);
1322 struct ocelot
*ocelot
= priv
->port
.ocelot
;
1323 int port
= priv
->chip_port
;
1325 ocelot_get_ethtool_stats(ocelot
, port
, data
);
1328 int ocelot_get_sset_count(struct ocelot
*ocelot
, int port
, int sset
)
1330 if (sset
!= ETH_SS_STATS
)
1333 return ocelot
->num_stats
;
1335 EXPORT_SYMBOL(ocelot_get_sset_count
);
1337 static int ocelot_port_get_sset_count(struct net_device
*dev
, int sset
)
1339 struct ocelot_port_private
*priv
= netdev_priv(dev
);
1340 struct ocelot
*ocelot
= priv
->port
.ocelot
;
1341 int port
= priv
->chip_port
;
1343 return ocelot_get_sset_count(ocelot
, port
, sset
);
1346 int ocelot_get_ts_info(struct ocelot
*ocelot
, int port
,
1347 struct ethtool_ts_info
*info
)
1349 info
->phc_index
= ocelot
->ptp_clock
?
1350 ptp_clock_index(ocelot
->ptp_clock
) : -1;
1351 info
->so_timestamping
|= SOF_TIMESTAMPING_TX_SOFTWARE
|
1352 SOF_TIMESTAMPING_RX_SOFTWARE
|
1353 SOF_TIMESTAMPING_SOFTWARE
|
1354 SOF_TIMESTAMPING_TX_HARDWARE
|
1355 SOF_TIMESTAMPING_RX_HARDWARE
|
1356 SOF_TIMESTAMPING_RAW_HARDWARE
;
1357 info
->tx_types
= BIT(HWTSTAMP_TX_OFF
) | BIT(HWTSTAMP_TX_ON
) |
1358 BIT(HWTSTAMP_TX_ONESTEP_SYNC
);
1359 info
->rx_filters
= BIT(HWTSTAMP_FILTER_NONE
) | BIT(HWTSTAMP_FILTER_ALL
);
1363 EXPORT_SYMBOL(ocelot_get_ts_info
);
1365 static int ocelot_port_get_ts_info(struct net_device
*dev
,
1366 struct ethtool_ts_info
*info
)
1368 struct ocelot_port_private
*priv
= netdev_priv(dev
);
1369 struct ocelot
*ocelot
= priv
->port
.ocelot
;
1370 int port
= priv
->chip_port
;
1373 return ethtool_op_get_ts_info(dev
, info
);
1375 return ocelot_get_ts_info(ocelot
, port
, info
);
1378 static const struct ethtool_ops ocelot_ethtool_ops
= {
1379 .get_strings
= ocelot_port_get_strings
,
1380 .get_ethtool_stats
= ocelot_port_get_ethtool_stats
,
1381 .get_sset_count
= ocelot_port_get_sset_count
,
1382 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
1383 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
1384 .get_ts_info
= ocelot_port_get_ts_info
,
1387 void ocelot_bridge_stp_state_set(struct ocelot
*ocelot
, int port
, u8 state
)
1392 if (!(BIT(port
) & ocelot
->bridge_mask
))
1395 port_cfg
= ocelot_read_gix(ocelot
, ANA_PORT_PORT_CFG
, port
);
1398 case BR_STATE_FORWARDING
:
1399 ocelot
->bridge_fwd_mask
|= BIT(port
);
1401 case BR_STATE_LEARNING
:
1402 port_cfg
|= ANA_PORT_PORT_CFG_LEARN_ENA
;
1406 port_cfg
&= ~ANA_PORT_PORT_CFG_LEARN_ENA
;
1407 ocelot
->bridge_fwd_mask
&= ~BIT(port
);
1411 ocelot_write_gix(ocelot
, port_cfg
, ANA_PORT_PORT_CFG
, port
);
1413 /* Apply FWD mask. The loop is needed to add/remove the current port as
1414 * a source for the other ports.
1416 for (p
= 0; p
< ocelot
->num_phys_ports
; p
++) {
1417 if (ocelot
->bridge_fwd_mask
& BIT(p
)) {
1418 unsigned long mask
= ocelot
->bridge_fwd_mask
& ~BIT(p
);
1420 for (i
= 0; i
< ocelot
->num_phys_ports
; i
++) {
1421 unsigned long bond_mask
= ocelot
->lags
[i
];
1426 if (bond_mask
& BIT(p
)) {
1432 ocelot_write_rix(ocelot
, mask
,
1433 ANA_PGID_PGID
, PGID_SRC
+ p
);
1435 ocelot_write_rix(ocelot
, 0,
1436 ANA_PGID_PGID
, PGID_SRC
+ p
);
1440 EXPORT_SYMBOL(ocelot_bridge_stp_state_set
);
1442 static void ocelot_port_attr_stp_state_set(struct ocelot
*ocelot
, int port
,
1443 struct switchdev_trans
*trans
,
1446 if (switchdev_trans_ph_prepare(trans
))
1449 ocelot_bridge_stp_state_set(ocelot
, port
, state
);
1452 void ocelot_set_ageing_time(struct ocelot
*ocelot
, unsigned int msecs
)
1454 unsigned int age_period
= ANA_AUTOAGE_AGE_PERIOD(msecs
/ 2000);
1456 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
1457 * which is clearly not what our intention is. So avoid that.
1462 ocelot_rmw(ocelot
, age_period
, ANA_AUTOAGE_AGE_PERIOD_M
, ANA_AUTOAGE
);
1464 EXPORT_SYMBOL(ocelot_set_ageing_time
);
1466 static void ocelot_port_attr_ageing_set(struct ocelot
*ocelot
, int port
,
1467 unsigned long ageing_clock_t
)
1469 unsigned long ageing_jiffies
= clock_t_to_jiffies(ageing_clock_t
);
1470 u32 ageing_time
= jiffies_to_msecs(ageing_jiffies
) / 1000;
1472 ocelot_set_ageing_time(ocelot
, ageing_time
);
1475 static void ocelot_port_attr_mc_set(struct ocelot
*ocelot
, int port
, bool mc
)
1477 u32 cpu_fwd_mcast
= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA
|
1478 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA
|
1479 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA
;
1483 val
= cpu_fwd_mcast
;
1485 ocelot_rmw_gix(ocelot
, val
, cpu_fwd_mcast
,
1486 ANA_PORT_CPU_FWD_CFG
, port
);
1489 static int ocelot_port_attr_set(struct net_device
*dev
,
1490 const struct switchdev_attr
*attr
,
1491 struct switchdev_trans
*trans
)
1493 struct ocelot_port_private
*priv
= netdev_priv(dev
);
1494 struct ocelot
*ocelot
= priv
->port
.ocelot
;
1495 int port
= priv
->chip_port
;
1499 case SWITCHDEV_ATTR_ID_PORT_STP_STATE
:
1500 ocelot_port_attr_stp_state_set(ocelot
, port
, trans
,
1503 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME
:
1504 ocelot_port_attr_ageing_set(ocelot
, port
, attr
->u
.ageing_time
);
1506 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING
:
1507 ocelot_port_vlan_filtering(ocelot
, port
,
1508 attr
->u
.vlan_filtering
);
1510 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED
:
1511 ocelot_port_attr_mc_set(ocelot
, port
, !attr
->u
.mc_disabled
);
1521 static int ocelot_port_obj_add_vlan(struct net_device
*dev
,
1522 const struct switchdev_obj_port_vlan
*vlan
,
1523 struct switchdev_trans
*trans
)
1528 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; vid
++) {
1529 ret
= ocelot_vlan_vid_add(dev
, vid
,
1530 vlan
->flags
& BRIDGE_VLAN_INFO_PVID
,
1531 vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
);
1539 static int ocelot_port_vlan_del_vlan(struct net_device
*dev
,
1540 const struct switchdev_obj_port_vlan
*vlan
)
1545 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; vid
++) {
1546 ret
= ocelot_vlan_vid_del(dev
, vid
);
1555 static struct ocelot_multicast
*ocelot_multicast_get(struct ocelot
*ocelot
,
1556 const unsigned char *addr
,
1559 struct ocelot_multicast
*mc
;
1561 list_for_each_entry(mc
, &ocelot
->multicast
, list
) {
1562 if (ether_addr_equal(mc
->addr
, addr
) && mc
->vid
== vid
)
1569 static int ocelot_port_obj_add_mdb(struct net_device
*dev
,
1570 const struct switchdev_obj_port_mdb
*mdb
,
1571 struct switchdev_trans
*trans
)
1573 struct ocelot_port_private
*priv
= netdev_priv(dev
);
1574 struct ocelot_port
*ocelot_port
= &priv
->port
;
1575 struct ocelot
*ocelot
= ocelot_port
->ocelot
;
1576 unsigned char addr
[ETH_ALEN
];
1577 struct ocelot_multicast
*mc
;
1578 int port
= priv
->chip_port
;
1583 vid
= ocelot_port
->pvid
;
1585 mc
= ocelot_multicast_get(ocelot
, mdb
->addr
, vid
);
1587 mc
= devm_kzalloc(ocelot
->dev
, sizeof(*mc
), GFP_KERNEL
);
1591 memcpy(mc
->addr
, mdb
->addr
, ETH_ALEN
);
1594 list_add_tail(&mc
->list
, &ocelot
->multicast
);
1598 memcpy(addr
, mc
->addr
, ETH_ALEN
);
1602 addr
[2] = mc
->ports
<< 0;
1603 addr
[1] = mc
->ports
<< 8;
1604 ocelot_mact_forget(ocelot
, addr
, vid
);
1607 mc
->ports
|= BIT(port
);
1608 addr
[2] = mc
->ports
<< 0;
1609 addr
[1] = mc
->ports
<< 8;
1611 return ocelot_mact_learn(ocelot
, 0, addr
, vid
, ENTRYTYPE_MACv4
);
1614 static int ocelot_port_obj_del_mdb(struct net_device
*dev
,
1615 const struct switchdev_obj_port_mdb
*mdb
)
1617 struct ocelot_port_private
*priv
= netdev_priv(dev
);
1618 struct ocelot_port
*ocelot_port
= &priv
->port
;
1619 struct ocelot
*ocelot
= ocelot_port
->ocelot
;
1620 unsigned char addr
[ETH_ALEN
];
1621 struct ocelot_multicast
*mc
;
1622 int port
= priv
->chip_port
;
1626 vid
= ocelot_port
->pvid
;
1628 mc
= ocelot_multicast_get(ocelot
, mdb
->addr
, vid
);
1632 memcpy(addr
, mc
->addr
, ETH_ALEN
);
1633 addr
[2] = mc
->ports
<< 0;
1634 addr
[1] = mc
->ports
<< 8;
1636 ocelot_mact_forget(ocelot
, addr
, vid
);
1638 mc
->ports
&= ~BIT(port
);
1640 list_del(&mc
->list
);
1641 devm_kfree(ocelot
->dev
, mc
);
1645 addr
[2] = mc
->ports
<< 0;
1646 addr
[1] = mc
->ports
<< 8;
1648 return ocelot_mact_learn(ocelot
, 0, addr
, vid
, ENTRYTYPE_MACv4
);
1651 static int ocelot_port_obj_add(struct net_device
*dev
,
1652 const struct switchdev_obj
*obj
,
1653 struct switchdev_trans
*trans
,
1654 struct netlink_ext_ack
*extack
)
1659 case SWITCHDEV_OBJ_ID_PORT_VLAN
:
1660 ret
= ocelot_port_obj_add_vlan(dev
,
1661 SWITCHDEV_OBJ_PORT_VLAN(obj
),
1664 case SWITCHDEV_OBJ_ID_PORT_MDB
:
1665 ret
= ocelot_port_obj_add_mdb(dev
, SWITCHDEV_OBJ_PORT_MDB(obj
),
1675 static int ocelot_port_obj_del(struct net_device
*dev
,
1676 const struct switchdev_obj
*obj
)
1681 case SWITCHDEV_OBJ_ID_PORT_VLAN
:
1682 ret
= ocelot_port_vlan_del_vlan(dev
,
1683 SWITCHDEV_OBJ_PORT_VLAN(obj
));
1685 case SWITCHDEV_OBJ_ID_PORT_MDB
:
1686 ret
= ocelot_port_obj_del_mdb(dev
, SWITCHDEV_OBJ_PORT_MDB(obj
));
1695 int ocelot_port_bridge_join(struct ocelot
*ocelot
, int port
,
1696 struct net_device
*bridge
)
1698 if (!ocelot
->bridge_mask
) {
1699 ocelot
->hw_bridge_dev
= bridge
;
1701 if (ocelot
->hw_bridge_dev
!= bridge
)
1702 /* This is adding the port to a second bridge, this is
1707 ocelot
->bridge_mask
|= BIT(port
);
1711 EXPORT_SYMBOL(ocelot_port_bridge_join
);
1713 int ocelot_port_bridge_leave(struct ocelot
*ocelot
, int port
,
1714 struct net_device
*bridge
)
1716 ocelot
->bridge_mask
&= ~BIT(port
);
1718 if (!ocelot
->bridge_mask
)
1719 ocelot
->hw_bridge_dev
= NULL
;
1721 ocelot_port_vlan_filtering(ocelot
, port
, 0);
1722 ocelot_port_set_pvid(ocelot
, port
, 0);
1723 return ocelot_port_set_native_vlan(ocelot
, port
, 0);
1725 EXPORT_SYMBOL(ocelot_port_bridge_leave
);
1727 static void ocelot_set_aggr_pgids(struct ocelot
*ocelot
)
1731 /* Reset destination and aggregation PGIDS */
1732 for (port
= 0; port
< ocelot
->num_phys_ports
; port
++)
1733 ocelot_write_rix(ocelot
, BIT(port
), ANA_PGID_PGID
, port
);
1735 for (i
= PGID_AGGR
; i
< PGID_SRC
; i
++)
1736 ocelot_write_rix(ocelot
, GENMASK(ocelot
->num_phys_ports
- 1, 0),
1739 /* Now, set PGIDs for each LAG */
1740 for (lag
= 0; lag
< ocelot
->num_phys_ports
; lag
++) {
1741 unsigned long bond_mask
;
1745 bond_mask
= ocelot
->lags
[lag
];
1749 for_each_set_bit(port
, &bond_mask
, ocelot
->num_phys_ports
) {
1751 ocelot_write_rix(ocelot
, bond_mask
,
1752 ANA_PGID_PGID
, port
);
1753 aggr_idx
[aggr_count
] = port
;
1757 for (i
= PGID_AGGR
; i
< PGID_SRC
; i
++) {
1760 ac
= ocelot_read_rix(ocelot
, ANA_PGID_PGID
, i
);
1762 ac
|= BIT(aggr_idx
[i
% aggr_count
]);
1763 ocelot_write_rix(ocelot
, ac
, ANA_PGID_PGID
, i
);
1768 static void ocelot_setup_lag(struct ocelot
*ocelot
, int lag
)
1770 unsigned long bond_mask
= ocelot
->lags
[lag
];
1773 for_each_set_bit(p
, &bond_mask
, ocelot
->num_phys_ports
) {
1774 u32 port_cfg
= ocelot_read_gix(ocelot
, ANA_PORT_PORT_CFG
, p
);
1776 port_cfg
&= ~ANA_PORT_PORT_CFG_PORTID_VAL_M
;
1778 /* Use lag port as logical port for port i */
1779 ocelot_write_gix(ocelot
, port_cfg
|
1780 ANA_PORT_PORT_CFG_PORTID_VAL(lag
),
1781 ANA_PORT_PORT_CFG
, p
);
1785 static int ocelot_port_lag_join(struct ocelot
*ocelot
, int port
,
1786 struct net_device
*bond
)
1788 struct net_device
*ndev
;
1793 for_each_netdev_in_bond_rcu(bond
, ndev
) {
1794 struct ocelot_port_private
*priv
= netdev_priv(ndev
);
1796 bond_mask
|= BIT(priv
->chip_port
);
1800 lp
= __ffs(bond_mask
);
1802 /* If the new port is the lowest one, use it as the logical port from
1807 ocelot
->lags
[port
] = bond_mask
;
1808 bond_mask
&= ~BIT(port
);
1810 lp
= __ffs(bond_mask
);
1811 ocelot
->lags
[lp
] = 0;
1815 ocelot
->lags
[lp
] |= BIT(port
);
1818 ocelot_setup_lag(ocelot
, lag
);
1819 ocelot_set_aggr_pgids(ocelot
);
1824 static void ocelot_port_lag_leave(struct ocelot
*ocelot
, int port
,
1825 struct net_device
*bond
)
1830 /* Remove port from any lag */
1831 for (i
= 0; i
< ocelot
->num_phys_ports
; i
++)
1832 ocelot
->lags
[i
] &= ~BIT(port
);
1834 /* if it was the logical port of the lag, move the lag config to the
1837 if (ocelot
->lags
[port
]) {
1838 int n
= __ffs(ocelot
->lags
[port
]);
1840 ocelot
->lags
[n
] = ocelot
->lags
[port
];
1841 ocelot
->lags
[port
] = 0;
1843 ocelot_setup_lag(ocelot
, n
);
1846 port_cfg
= ocelot_read_gix(ocelot
, ANA_PORT_PORT_CFG
, port
);
1847 port_cfg
&= ~ANA_PORT_PORT_CFG_PORTID_VAL_M
;
1848 ocelot_write_gix(ocelot
, port_cfg
| ANA_PORT_PORT_CFG_PORTID_VAL(port
),
1849 ANA_PORT_PORT_CFG
, port
);
1851 ocelot_set_aggr_pgids(ocelot
);
1854 /* Checks if the net_device instance given to us originate from our driver. */
1855 static bool ocelot_netdevice_dev_check(const struct net_device
*dev
)
1857 return dev
->netdev_ops
== &ocelot_port_netdev_ops
;
1860 static int ocelot_netdevice_port_event(struct net_device
*dev
,
1861 unsigned long event
,
1862 struct netdev_notifier_changeupper_info
*info
)
1864 struct ocelot_port_private
*priv
= netdev_priv(dev
);
1865 struct ocelot_port
*ocelot_port
= &priv
->port
;
1866 struct ocelot
*ocelot
= ocelot_port
->ocelot
;
1867 int port
= priv
->chip_port
;
1871 case NETDEV_CHANGEUPPER
:
1872 if (netif_is_bridge_master(info
->upper_dev
)) {
1873 if (info
->linking
) {
1874 err
= ocelot_port_bridge_join(ocelot
, port
,
1877 err
= ocelot_port_bridge_leave(ocelot
, port
,
1881 if (netif_is_lag_master(info
->upper_dev
)) {
1883 err
= ocelot_port_lag_join(ocelot
, port
,
1886 ocelot_port_lag_leave(ocelot
, port
,
1897 static int ocelot_netdevice_event(struct notifier_block
*unused
,
1898 unsigned long event
, void *ptr
)
1900 struct netdev_notifier_changeupper_info
*info
= ptr
;
1901 struct net_device
*dev
= netdev_notifier_info_to_dev(ptr
);
1904 if (!ocelot_netdevice_dev_check(dev
))
1907 if (event
== NETDEV_PRECHANGEUPPER
&&
1908 netif_is_lag_master(info
->upper_dev
)) {
1909 struct netdev_lag_upper_info
*lag_upper_info
= info
->upper_info
;
1910 struct netlink_ext_ack
*extack
;
1912 if (lag_upper_info
&&
1913 lag_upper_info
->tx_type
!= NETDEV_LAG_TX_TYPE_HASH
) {
1914 extack
= netdev_notifier_info_to_extack(&info
->info
);
1915 NL_SET_ERR_MSG_MOD(extack
, "LAG device using unsupported Tx type");
1922 if (netif_is_lag_master(dev
)) {
1923 struct net_device
*slave
;
1924 struct list_head
*iter
;
1926 netdev_for_each_lower_dev(dev
, slave
, iter
) {
1927 ret
= ocelot_netdevice_port_event(slave
, event
, info
);
1932 ret
= ocelot_netdevice_port_event(dev
, event
, info
);
1936 return notifier_from_errno(ret
);
1939 struct notifier_block ocelot_netdevice_nb __read_mostly
= {
1940 .notifier_call
= ocelot_netdevice_event
,
1942 EXPORT_SYMBOL(ocelot_netdevice_nb
);
1944 static int ocelot_switchdev_event(struct notifier_block
*unused
,
1945 unsigned long event
, void *ptr
)
1947 struct net_device
*dev
= switchdev_notifier_info_to_dev(ptr
);
1951 case SWITCHDEV_PORT_ATTR_SET
:
1952 err
= switchdev_handle_port_attr_set(dev
, ptr
,
1953 ocelot_netdevice_dev_check
,
1954 ocelot_port_attr_set
);
1955 return notifier_from_errno(err
);
1961 struct notifier_block ocelot_switchdev_nb __read_mostly
= {
1962 .notifier_call
= ocelot_switchdev_event
,
1964 EXPORT_SYMBOL(ocelot_switchdev_nb
);
1966 static int ocelot_switchdev_blocking_event(struct notifier_block
*unused
,
1967 unsigned long event
, void *ptr
)
1969 struct net_device
*dev
= switchdev_notifier_info_to_dev(ptr
);
1973 /* Blocking events. */
1974 case SWITCHDEV_PORT_OBJ_ADD
:
1975 err
= switchdev_handle_port_obj_add(dev
, ptr
,
1976 ocelot_netdevice_dev_check
,
1977 ocelot_port_obj_add
);
1978 return notifier_from_errno(err
);
1979 case SWITCHDEV_PORT_OBJ_DEL
:
1980 err
= switchdev_handle_port_obj_del(dev
, ptr
,
1981 ocelot_netdevice_dev_check
,
1982 ocelot_port_obj_del
);
1983 return notifier_from_errno(err
);
1984 case SWITCHDEV_PORT_ATTR_SET
:
1985 err
= switchdev_handle_port_attr_set(dev
, ptr
,
1986 ocelot_netdevice_dev_check
,
1987 ocelot_port_attr_set
);
1988 return notifier_from_errno(err
);
1994 struct notifier_block ocelot_switchdev_blocking_nb __read_mostly
= {
1995 .notifier_call
= ocelot_switchdev_blocking_event
,
1997 EXPORT_SYMBOL(ocelot_switchdev_blocking_nb
);
1999 int ocelot_ptp_gettime64(struct ptp_clock_info
*ptp
, struct timespec64
*ts
)
2001 struct ocelot
*ocelot
= container_of(ptp
, struct ocelot
, ptp_info
);
2002 unsigned long flags
;
2007 spin_lock_irqsave(&ocelot
->ptp_clock_lock
, flags
);
2009 val
= ocelot_read_rix(ocelot
, PTP_PIN_CFG
, TOD_ACC_PIN
);
2010 val
&= ~(PTP_PIN_CFG_SYNC
| PTP_PIN_CFG_ACTION_MASK
| PTP_PIN_CFG_DOM
);
2011 val
|= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE
);
2012 ocelot_write_rix(ocelot
, val
, PTP_PIN_CFG
, TOD_ACC_PIN
);
2014 s
= ocelot_read_rix(ocelot
, PTP_PIN_TOD_SEC_MSB
, TOD_ACC_PIN
) & 0xffff;
2016 s
+= ocelot_read_rix(ocelot
, PTP_PIN_TOD_SEC_LSB
, TOD_ACC_PIN
);
2017 ns
= ocelot_read_rix(ocelot
, PTP_PIN_TOD_NSEC
, TOD_ACC_PIN
);
2019 spin_unlock_irqrestore(&ocelot
->ptp_clock_lock
, flags
);
2021 /* Deal with negative values */
2022 if (ns
>= 0x3ffffff0 && ns
<= 0x3fffffff) {
2028 set_normalized_timespec64(ts
, s
, ns
);
2031 EXPORT_SYMBOL(ocelot_ptp_gettime64
);
2033 static int ocelot_ptp_settime64(struct ptp_clock_info
*ptp
,
2034 const struct timespec64
*ts
)
2036 struct ocelot
*ocelot
= container_of(ptp
, struct ocelot
, ptp_info
);
2037 unsigned long flags
;
2040 spin_lock_irqsave(&ocelot
->ptp_clock_lock
, flags
);
2042 val
= ocelot_read_rix(ocelot
, PTP_PIN_CFG
, TOD_ACC_PIN
);
2043 val
&= ~(PTP_PIN_CFG_SYNC
| PTP_PIN_CFG_ACTION_MASK
| PTP_PIN_CFG_DOM
);
2044 val
|= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE
);
2046 ocelot_write_rix(ocelot
, val
, PTP_PIN_CFG
, TOD_ACC_PIN
);
2048 ocelot_write_rix(ocelot
, lower_32_bits(ts
->tv_sec
), PTP_PIN_TOD_SEC_LSB
,
2050 ocelot_write_rix(ocelot
, upper_32_bits(ts
->tv_sec
), PTP_PIN_TOD_SEC_MSB
,
2052 ocelot_write_rix(ocelot
, ts
->tv_nsec
, PTP_PIN_TOD_NSEC
, TOD_ACC_PIN
);
2054 val
= ocelot_read_rix(ocelot
, PTP_PIN_CFG
, TOD_ACC_PIN
);
2055 val
&= ~(PTP_PIN_CFG_SYNC
| PTP_PIN_CFG_ACTION_MASK
| PTP_PIN_CFG_DOM
);
2056 val
|= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_LOAD
);
2058 ocelot_write_rix(ocelot
, val
, PTP_PIN_CFG
, TOD_ACC_PIN
);
2060 spin_unlock_irqrestore(&ocelot
->ptp_clock_lock
, flags
);
2064 static int ocelot_ptp_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
2066 if (delta
> -(NSEC_PER_SEC
/ 2) && delta
< (NSEC_PER_SEC
/ 2)) {
2067 struct ocelot
*ocelot
= container_of(ptp
, struct ocelot
, ptp_info
);
2068 unsigned long flags
;
2071 spin_lock_irqsave(&ocelot
->ptp_clock_lock
, flags
);
2073 val
= ocelot_read_rix(ocelot
, PTP_PIN_CFG
, TOD_ACC_PIN
);
2074 val
&= ~(PTP_PIN_CFG_SYNC
| PTP_PIN_CFG_ACTION_MASK
| PTP_PIN_CFG_DOM
);
2075 val
|= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE
);
2077 ocelot_write_rix(ocelot
, val
, PTP_PIN_CFG
, TOD_ACC_PIN
);
2079 ocelot_write_rix(ocelot
, 0, PTP_PIN_TOD_SEC_LSB
, TOD_ACC_PIN
);
2080 ocelot_write_rix(ocelot
, 0, PTP_PIN_TOD_SEC_MSB
, TOD_ACC_PIN
);
2081 ocelot_write_rix(ocelot
, delta
, PTP_PIN_TOD_NSEC
, TOD_ACC_PIN
);
2083 val
= ocelot_read_rix(ocelot
, PTP_PIN_CFG
, TOD_ACC_PIN
);
2084 val
&= ~(PTP_PIN_CFG_SYNC
| PTP_PIN_CFG_ACTION_MASK
| PTP_PIN_CFG_DOM
);
2085 val
|= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_DELTA
);
2087 ocelot_write_rix(ocelot
, val
, PTP_PIN_CFG
, TOD_ACC_PIN
);
2089 spin_unlock_irqrestore(&ocelot
->ptp_clock_lock
, flags
);
2091 /* Fall back using ocelot_ptp_settime64 which is not exact. */
2092 struct timespec64 ts
;
2095 ocelot_ptp_gettime64(ptp
, &ts
);
2097 now
= ktime_to_ns(timespec64_to_ktime(ts
));
2098 ts
= ns_to_timespec64(now
+ delta
);
2100 ocelot_ptp_settime64(ptp
, &ts
);
2105 static int ocelot_ptp_adjfine(struct ptp_clock_info
*ptp
, long scaled_ppm
)
2107 struct ocelot
*ocelot
= container_of(ptp
, struct ocelot
, ptp_info
);
2108 u32 unit
= 0, direction
= 0;
2109 unsigned long flags
;
2112 spin_lock_irqsave(&ocelot
->ptp_clock_lock
, flags
);
2117 if (scaled_ppm
< 0) {
2118 direction
= PTP_CFG_CLK_ADJ_CFG_DIR
;
2119 scaled_ppm
= -scaled_ppm
;
2122 adj
= PSEC_PER_SEC
<< 16;
2123 do_div(adj
, scaled_ppm
);
2126 /* If the adjustment value is too large, use ns instead */
2127 if (adj
>= (1L << 30)) {
2128 unit
= PTP_CFG_CLK_ADJ_FREQ_NS
;
2133 if (adj
>= (1L << 30))
2136 ocelot_write(ocelot
, unit
| adj
, PTP_CLK_CFG_ADJ_FREQ
);
2137 ocelot_write(ocelot
, PTP_CFG_CLK_ADJ_CFG_ENA
| direction
,
2138 PTP_CLK_CFG_ADJ_CFG
);
2140 spin_unlock_irqrestore(&ocelot
->ptp_clock_lock
, flags
);
2144 ocelot_write(ocelot
, 0, PTP_CLK_CFG_ADJ_CFG
);
2146 spin_unlock_irqrestore(&ocelot
->ptp_clock_lock
, flags
);
2150 static struct ptp_clock_info ocelot_ptp_clock_info
= {
2151 .owner
= THIS_MODULE
,
2152 .name
= "ocelot ptp",
2153 .max_adj
= 0x7fffffff,
2159 .gettime64
= ocelot_ptp_gettime64
,
2160 .settime64
= ocelot_ptp_settime64
,
2161 .adjtime
= ocelot_ptp_adjtime
,
2162 .adjfine
= ocelot_ptp_adjfine
,
2165 static int ocelot_init_timestamp(struct ocelot
*ocelot
)
2167 struct ptp_clock
*ptp_clock
;
2169 ocelot
->ptp_info
= ocelot_ptp_clock_info
;
2170 ptp_clock
= ptp_clock_register(&ocelot
->ptp_info
, ocelot
->dev
);
2171 if (IS_ERR(ptp_clock
))
2172 return PTR_ERR(ptp_clock
);
2173 /* Check if PHC support is missing at the configuration level */
2177 ocelot
->ptp_clock
= ptp_clock
;
2179 ocelot_write(ocelot
, SYS_PTP_CFG_PTP_STAMP_WID(30), SYS_PTP_CFG
);
2180 ocelot_write(ocelot
, 0xffffffff, ANA_TABLES_PTP_ID_LOW
);
2181 ocelot_write(ocelot
, 0xffffffff, ANA_TABLES_PTP_ID_HIGH
);
2183 ocelot_write(ocelot
, PTP_CFG_MISC_PTP_EN
, PTP_CFG_MISC
);
2185 /* There is no device reconfiguration, PTP Rx stamping is always
2188 ocelot
->hwtstamp_config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
2193 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
2194 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
2195 * In the special case that it's the NPI port that we're configuring, the
2196 * length of the tag and optional prefix needs to be accounted for privately,
2197 * in order to be able to sustain communication at the requested @sdu.
2199 void ocelot_port_set_maxlen(struct ocelot
*ocelot
, int port
, size_t sdu
)
2201 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
2202 int maxlen
= sdu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2205 if (port
== ocelot
->npi
) {
2206 maxlen
+= OCELOT_TAG_LEN
;
2208 if (ocelot
->inj_prefix
== OCELOT_TAG_PREFIX_SHORT
)
2209 maxlen
+= OCELOT_SHORT_PREFIX_LEN
;
2210 else if (ocelot
->inj_prefix
== OCELOT_TAG_PREFIX_LONG
)
2211 maxlen
+= OCELOT_LONG_PREFIX_LEN
;
2214 ocelot_port_writel(ocelot_port
, maxlen
, DEV_MAC_MAXLEN_CFG
);
2216 /* Set Pause WM hysteresis
2217 * 152 = 6 * maxlen / OCELOT_BUFFER_CELL_SZ
2218 * 101 = 4 * maxlen / OCELOT_BUFFER_CELL_SZ
2220 ocelot_write_rix(ocelot
, SYS_PAUSE_CFG_PAUSE_ENA
|
2221 SYS_PAUSE_CFG_PAUSE_STOP(101) |
2222 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG
, port
);
2224 /* Tail dropping watermark */
2225 atop_wm
= (ocelot
->shared_queue_sz
- 9 * maxlen
) /
2226 OCELOT_BUFFER_CELL_SZ
;
2227 ocelot_write_rix(ocelot
, ocelot_wm_enc(9 * maxlen
),
2229 ocelot_write(ocelot
, ocelot_wm_enc(atop_wm
), SYS_ATOP_TOT_CFG
);
2231 EXPORT_SYMBOL(ocelot_port_set_maxlen
);
2233 int ocelot_get_max_mtu(struct ocelot
*ocelot
, int port
)
2235 int max_mtu
= 65535 - ETH_HLEN
- ETH_FCS_LEN
;
2237 if (port
== ocelot
->npi
) {
2238 max_mtu
-= OCELOT_TAG_LEN
;
2240 if (ocelot
->inj_prefix
== OCELOT_TAG_PREFIX_SHORT
)
2241 max_mtu
-= OCELOT_SHORT_PREFIX_LEN
;
2242 else if (ocelot
->inj_prefix
== OCELOT_TAG_PREFIX_LONG
)
2243 max_mtu
-= OCELOT_LONG_PREFIX_LEN
;
2248 EXPORT_SYMBOL(ocelot_get_max_mtu
);
2250 void ocelot_init_port(struct ocelot
*ocelot
, int port
)
2252 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
2254 skb_queue_head_init(&ocelot_port
->tx_skbs
);
2256 /* Basic L2 initialization */
2259 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
2260 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
2262 ocelot_port_writel(ocelot_port
, DEV_MAC_IFG_CFG_TX_IFG(5),
2265 /* Load seed (0) and set MAC HDX late collision */
2266 ocelot_port_writel(ocelot_port
, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
2267 DEV_MAC_HDX_CFG_SEED_LOAD
,
2270 ocelot_port_writel(ocelot_port
, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
2273 /* Set Max Length and maximum tags allowed */
2274 ocelot_port_set_maxlen(ocelot
, port
, ETH_DATA_LEN
);
2275 ocelot_port_writel(ocelot_port
, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD
) |
2276 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA
|
2277 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA
|
2278 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA
,
2281 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
2282 ocelot_port_writel(ocelot_port
, 0, DEV_MAC_FC_MAC_HIGH_CFG
);
2283 ocelot_port_writel(ocelot_port
, 0, DEV_MAC_FC_MAC_LOW_CFG
);
2285 /* Drop frames with multicast source address */
2286 ocelot_rmw_gix(ocelot
, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA
,
2287 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA
,
2288 ANA_PORT_DROP_CFG
, port
);
2290 /* Set default VLAN and tag type to 8021Q. */
2291 ocelot_rmw_gix(ocelot
, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q
),
2292 REW_PORT_VLAN_CFG_PORT_TPID_M
,
2293 REW_PORT_VLAN_CFG
, port
);
2295 /* Enable vcap lookups */
2296 ocelot_vcap_enable(ocelot
, port
);
2298 EXPORT_SYMBOL(ocelot_init_port
);
2300 int ocelot_probe_port(struct ocelot
*ocelot
, u8 port
,
2302 struct phy_device
*phy
)
2304 struct ocelot_port_private
*priv
;
2305 struct ocelot_port
*ocelot_port
;
2306 struct net_device
*dev
;
2309 dev
= alloc_etherdev(sizeof(struct ocelot_port_private
));
2312 SET_NETDEV_DEV(dev
, ocelot
->dev
);
2313 priv
= netdev_priv(dev
);
2316 priv
->chip_port
= port
;
2317 ocelot_port
= &priv
->port
;
2318 ocelot_port
->ocelot
= ocelot
;
2319 ocelot_port
->regs
= regs
;
2320 ocelot
->ports
[port
] = ocelot_port
;
2322 dev
->netdev_ops
= &ocelot_port_netdev_ops
;
2323 dev
->ethtool_ops
= &ocelot_ethtool_ops
;
2325 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
| NETIF_F_RXFCS
|
2327 dev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
| NETIF_F_HW_TC
;
2329 memcpy(dev
->dev_addr
, ocelot
->base_mac
, ETH_ALEN
);
2330 dev
->dev_addr
[ETH_ALEN
- 1] += port
;
2331 ocelot_mact_learn(ocelot
, PGID_CPU
, dev
->dev_addr
, ocelot_port
->pvid
,
2334 ocelot_init_port(ocelot
, port
);
2336 err
= register_netdev(dev
);
2338 dev_err(ocelot
->dev
, "register_netdev failed\n");
2344 EXPORT_SYMBOL(ocelot_probe_port
);
2346 /* Configure and enable the CPU port module, which is a set of queues.
2347 * If @npi contains a valid port index, the CPU port module is connected
2348 * to the Node Processor Interface (NPI). This is the mode through which
2349 * frames can be injected from and extracted to an external CPU,
2352 void ocelot_configure_cpu(struct ocelot
*ocelot
, int npi
,
2353 enum ocelot_tag_prefix injection
,
2354 enum ocelot_tag_prefix extraction
)
2356 int cpu
= ocelot
->num_phys_ports
;
2359 ocelot
->inj_prefix
= injection
;
2360 ocelot
->xtr_prefix
= extraction
;
2362 /* The unicast destination PGID for the CPU port module is unused */
2363 ocelot_write_rix(ocelot
, 0, ANA_PGID_PGID
, cpu
);
2364 /* Instead set up a multicast destination PGID for traffic copied to
2365 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
2366 * addresses will be copied to the CPU via this PGID.
2368 ocelot_write_rix(ocelot
, BIT(cpu
), ANA_PGID_PGID
, PGID_CPU
);
2369 ocelot_write_gix(ocelot
, ANA_PORT_PORT_CFG_RECV_ENA
|
2370 ANA_PORT_PORT_CFG_PORTID_VAL(cpu
),
2371 ANA_PORT_PORT_CFG
, cpu
);
2373 if (npi
>= 0 && npi
< ocelot
->num_phys_ports
) {
2374 ocelot_write(ocelot
, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M
|
2375 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(npi
),
2378 /* Enable NPI port */
2379 ocelot_write_rix(ocelot
,
2380 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE
|
2381 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
2382 QSYS_SWITCH_PORT_MODE_PORT_ENA
,
2383 QSYS_SWITCH_PORT_MODE
, npi
);
2384 /* NPI port Injection/Extraction configuration */
2385 ocelot_write_rix(ocelot
,
2386 SYS_PORT_MODE_INCL_XTR_HDR(extraction
) |
2387 SYS_PORT_MODE_INCL_INJ_HDR(injection
),
2388 SYS_PORT_MODE
, npi
);
2391 /* Enable CPU port module */
2392 ocelot_write_rix(ocelot
, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE
|
2393 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
2394 QSYS_SWITCH_PORT_MODE_PORT_ENA
,
2395 QSYS_SWITCH_PORT_MODE
, cpu
);
2396 /* CPU port Injection/Extraction configuration */
2397 ocelot_write_rix(ocelot
, SYS_PORT_MODE_INCL_XTR_HDR(extraction
) |
2398 SYS_PORT_MODE_INCL_INJ_HDR(injection
),
2399 SYS_PORT_MODE
, cpu
);
2401 /* Configure the CPU port to be VLAN aware */
2402 ocelot_write_gix(ocelot
, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
2403 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA
|
2404 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
2405 ANA_PORT_VLAN_CFG
, cpu
);
2407 EXPORT_SYMBOL(ocelot_configure_cpu
);
2409 int ocelot_init(struct ocelot
*ocelot
)
2411 char queue_name
[32];
2415 if (ocelot
->ops
->reset
) {
2416 ret
= ocelot
->ops
->reset(ocelot
);
2418 dev_err(ocelot
->dev
, "Switch reset failed\n");
2423 ocelot
->lags
= devm_kcalloc(ocelot
->dev
, ocelot
->num_phys_ports
,
2424 sizeof(u32
), GFP_KERNEL
);
2428 ocelot
->stats
= devm_kcalloc(ocelot
->dev
,
2429 ocelot
->num_phys_ports
* ocelot
->num_stats
,
2430 sizeof(u64
), GFP_KERNEL
);
2434 mutex_init(&ocelot
->stats_lock
);
2435 mutex_init(&ocelot
->ptp_lock
);
2436 spin_lock_init(&ocelot
->ptp_clock_lock
);
2437 snprintf(queue_name
, sizeof(queue_name
), "%s-stats",
2438 dev_name(ocelot
->dev
));
2439 ocelot
->stats_queue
= create_singlethread_workqueue(queue_name
);
2440 if (!ocelot
->stats_queue
)
2443 INIT_LIST_HEAD(&ocelot
->multicast
);
2444 ocelot_mact_init(ocelot
);
2445 ocelot_vlan_init(ocelot
);
2446 ocelot_ace_init(ocelot
);
2448 for (port
= 0; port
< ocelot
->num_phys_ports
; port
++) {
2449 /* Clear all counters (5 groups) */
2450 ocelot_write(ocelot
, SYS_STAT_CFG_STAT_VIEW(port
) |
2451 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
2455 /* Only use S-Tag */
2456 ocelot_write(ocelot
, ETH_P_8021AD
, SYS_VLAN_ETYPE_CFG
);
2458 /* Aggregation mode */
2459 ocelot_write(ocelot
, ANA_AGGR_CFG_AC_SMAC_ENA
|
2460 ANA_AGGR_CFG_AC_DMAC_ENA
|
2461 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA
|
2462 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA
, ANA_AGGR_CFG
);
2464 /* Set MAC age time to default value. The entry is aged after
2467 ocelot_write(ocelot
,
2468 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME
/ 2 / HZ
),
2471 /* Disable learning for frames discarded by VLAN ingress filtering */
2472 regmap_field_write(ocelot
->regfields
[ANA_ADVLEARN_VLAN_CHK
], 1);
2474 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
2475 ocelot_write(ocelot
, SYS_FRM_AGING_AGE_TX_ENA
|
2476 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING
);
2478 /* Setup flooding PGIDs */
2479 ocelot_write_rix(ocelot
, ANA_FLOODING_FLD_MULTICAST(PGID_MC
) |
2480 ANA_FLOODING_FLD_BROADCAST(PGID_MC
) |
2481 ANA_FLOODING_FLD_UNICAST(PGID_UC
),
2483 ocelot_write(ocelot
, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6
) |
2484 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC
) |
2485 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4
) |
2486 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC
),
2489 for (port
= 0; port
< ocelot
->num_phys_ports
; port
++) {
2490 /* Transmit the frame to the local port. */
2491 ocelot_write_rix(ocelot
, BIT(port
), ANA_PGID_PGID
, port
);
2492 /* Do not forward BPDU frames to the front ports. */
2493 ocelot_write_gix(ocelot
,
2494 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2495 ANA_PORT_CPU_FWD_BPDU_CFG
,
2497 /* Ensure bridging is disabled */
2498 ocelot_write_rix(ocelot
, 0, ANA_PGID_PGID
, PGID_SRC
+ port
);
2501 /* Allow broadcast MAC frames. */
2502 for (i
= ocelot
->num_phys_ports
+ 1; i
< PGID_CPU
; i
++) {
2503 u32 val
= ANA_PGID_PGID_PGID(GENMASK(ocelot
->num_phys_ports
- 1, 0));
2505 ocelot_write_rix(ocelot
, val
, ANA_PGID_PGID
, i
);
2507 ocelot_write_rix(ocelot
,
2508 ANA_PGID_PGID_PGID(GENMASK(ocelot
->num_phys_ports
, 0)),
2509 ANA_PGID_PGID
, PGID_MC
);
2510 ocelot_write_rix(ocelot
, 0, ANA_PGID_PGID
, PGID_MCIPV4
);
2511 ocelot_write_rix(ocelot
, 0, ANA_PGID_PGID
, PGID_MCIPV6
);
2513 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
2514 * registers endianness.
2516 ocelot_write_rix(ocelot
, QS_INJ_GRP_CFG_BYTE_SWAP
|
2517 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG
, 0);
2518 ocelot_write_rix(ocelot
, QS_XTR_GRP_CFG_BYTE_SWAP
|
2519 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG
, 0);
2520 ocelot_write(ocelot
, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
2521 ANA_CPUQ_CFG_CPUQ_LRN(2) |
2522 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
2523 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
2524 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
2525 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
2526 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
2527 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
2528 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG
);
2529 for (i
= 0; i
< 16; i
++)
2530 ocelot_write_rix(ocelot
, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
2531 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
2532 ANA_CPUQ_8021_CFG
, i
);
2534 INIT_DELAYED_WORK(&ocelot
->stats_work
, ocelot_check_stats_work
);
2535 queue_delayed_work(ocelot
->stats_queue
, &ocelot
->stats_work
,
2536 OCELOT_STATS_CHECK_DELAY
);
2539 ret
= ocelot_init_timestamp(ocelot
);
2541 dev_err(ocelot
->dev
,
2542 "Timestamp initialization failed\n");
2549 EXPORT_SYMBOL(ocelot_init
);
2551 void ocelot_deinit(struct ocelot
*ocelot
)
2553 struct ocelot_port
*port
;
2556 cancel_delayed_work(&ocelot
->stats_work
);
2557 destroy_workqueue(ocelot
->stats_queue
);
2558 mutex_destroy(&ocelot
->stats_lock
);
2559 if (ocelot
->ptp_clock
)
2560 ptp_clock_unregister(ocelot
->ptp_clock
);
2562 for (i
= 0; i
< ocelot
->num_phys_ports
; i
++) {
2563 port
= ocelot
->ports
[i
];
2564 skb_queue_purge(&port
->tx_skbs
);
2567 EXPORT_SYMBOL(ocelot_deinit
);
2569 MODULE_LICENSE("Dual MIT/GPL");