drivers/net/ethernet/mscc/ocelot_regs.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Microsemi Ocelot Switch driver
   4  *
   5  * Copyright (c) 2017 Microsemi Corporation
   6  */
   7 #include "ocelot.h"
   8 #include <soc/mscc/ocelot_hsio.h>
   9
  10 static const u32 ocelot_ana_regmap[] = {
  11         REG(ANA_ADVLEARN,                  0x009000),
  12         REG(ANA_VLANMASK,                  0x009004),
  13         REG(ANA_PORT_B_DOMAIN,             0x009008),
  14         REG(ANA_ANAGEFIL,                  0x00900c),
  15         REG(ANA_ANEVENTS,                  0x009010),
  16         REG(ANA_STORMLIMIT_BURST,          0x009014),
  17         REG(ANA_STORMLIMIT_CFG,            0x009018),
  18         REG(ANA_ISOLATED_PORTS,            0x009028),
  19         REG(ANA_COMMUNITY_PORTS,           0x00902c),
  20         REG(ANA_AUTOAGE,                   0x009030),
  21         REG(ANA_MACTOPTIONS,               0x009034),
  22         REG(ANA_LEARNDISC,                 0x009038),
  23         REG(ANA_AGENCTRL,                  0x00903c),
  24         REG(ANA_MIRRORPORTS,               0x009040),
  25         REG(ANA_EMIRRORPORTS,              0x009044),
  26         REG(ANA_FLOODING,                  0x009048),
  27         REG(ANA_FLOODING_IPMC,             0x00904c),
  28         REG(ANA_SFLOW_CFG,                 0x009050),
  29         REG(ANA_PORT_MODE,                 0x009080),
  30         REG(ANA_PGID_PGID,                 0x008c00),
  31         REG(ANA_TABLES_ANMOVED,            0x008b30),
  32         REG(ANA_TABLES_MACHDATA,           0x008b34),
  33         REG(ANA_TABLES_MACLDATA,           0x008b38),
  34         REG(ANA_TABLES_MACACCESS,          0x008b3c),
  35         REG(ANA_TABLES_MACTINDX,           0x008b40),
  36         REG(ANA_TABLES_VLANACCESS,         0x008b44),
  37         REG(ANA_TABLES_VLANTIDX,           0x008b48),
  38         REG(ANA_TABLES_ISDXACCESS,         0x008b4c),
  39         REG(ANA_TABLES_ISDXTIDX,           0x008b50),
  40         REG(ANA_TABLES_ENTRYLIM,           0x008b00),
  41         REG(ANA_TABLES_PTP_ID_HIGH,        0x008b54),
  42         REG(ANA_TABLES_PTP_ID_LOW,         0x008b58),
  43         REG(ANA_MSTI_STATE,                0x008e00),
  44         REG(ANA_PORT_VLAN_CFG,             0x007000),
  45         REG(ANA_PORT_DROP_CFG,             0x007004),
  46         REG(ANA_PORT_QOS_CFG,              0x007008),
  47         REG(ANA_PORT_VCAP_CFG,             0x00700c),
  48         REG(ANA_PORT_VCAP_S1_KEY_CFG,      0x007010),
  49         REG(ANA_PORT_VCAP_S2_CFG,          0x00701c),
  50         REG(ANA_PORT_PCP_DEI_MAP,          0x007020),
  51         REG(ANA_PORT_CPU_FWD_CFG,          0x007060),
  52         REG(ANA_PORT_CPU_FWD_BPDU_CFG,     0x007064),
  53         REG(ANA_PORT_CPU_FWD_GARP_CFG,     0x007068),
  54         REG(ANA_PORT_CPU_FWD_CCM_CFG,      0x00706c),
  55         REG(ANA_PORT_PORT_CFG,             0x007070),
  56         REG(ANA_PORT_POL_CFG,              0x007074),
  57         REG(ANA_PORT_PTP_CFG,              0x007078),
  58         REG(ANA_PORT_PTP_DLY1_CFG,         0x00707c),
  59         REG(ANA_OAM_UPM_LM_CNT,            0x007c00),
  60         REG(ANA_PORT_PTP_DLY2_CFG,         0x007080),
  61         REG(ANA_PFC_PFC_CFG,               0x008800),
  62         REG(ANA_PFC_PFC_TIMER,             0x008804),
  63         REG(ANA_IPT_OAM_MEP_CFG,           0x008000),
  64         REG(ANA_IPT_IPT,                   0x008004),
  65         REG(ANA_PPT_PPT,                   0x008ac0),
  66         REG(ANA_FID_MAP_FID_MAP,           0x000000),
  67         REG(ANA_AGGR_CFG,                  0x0090b4),
  68         REG(ANA_CPUQ_CFG,                  0x0090b8),
  69         REG(ANA_CPUQ_CFG2,                 0x0090bc),
  70         REG(ANA_CPUQ_8021_CFG,             0x0090c0),
  71         REG(ANA_DSCP_CFG,                  0x009100),
  72         REG(ANA_DSCP_REWR_CFG,             0x009200),
  73         REG(ANA_VCAP_RNG_TYPE_CFG,         0x009240),
  74         REG(ANA_VCAP_RNG_VAL_CFG,          0x009260),
  75         REG(ANA_VRAP_CFG,                  0x009280),
  76         REG(ANA_VRAP_HDR_DATA,             0x009284),
  77         REG(ANA_VRAP_HDR_MASK,             0x009288),
  78         REG(ANA_DISCARD_CFG,               0x00928c),
  79         REG(ANA_FID_CFG,                   0x009290),
  80         REG(ANA_POL_PIR_CFG,               0x004000),
  81         REG(ANA_POL_CIR_CFG,               0x004004),
  82         REG(ANA_POL_MODE_CFG,              0x004008),
  83         REG(ANA_POL_PIR_STATE,             0x00400c),
  84         REG(ANA_POL_CIR_STATE,             0x004010),
  85         REG(ANA_POL_STATE,                 0x004014),
  86         REG(ANA_POL_FLOWC,                 0x008b80),
  87         REG(ANA_POL_HYST,                  0x008bec),
  88         REG(ANA_POL_MISC_CFG,              0x008bf0),
  89 };
  90
  91 static const u32 ocelot_qs_regmap[] = {
  92         REG(QS_XTR_GRP_CFG,                0x000000),
  93         REG(QS_XTR_RD,                     0x000008),
  94         REG(QS_XTR_FRM_PRUNING,            0x000010),
  95         REG(QS_XTR_FLUSH,                  0x000018),
  96         REG(QS_XTR_DATA_PRESENT,           0x00001c),
  97         REG(QS_XTR_CFG,                    0x000020),
  98         REG(QS_INJ_GRP_CFG,                0x000024),
  99         REG(QS_INJ_WR,                     0x00002c),
 100         REG(QS_INJ_CTRL,                   0x000034),
 101         REG(QS_INJ_STATUS,                 0x00003c),
 102         REG(QS_INJ_ERR,                    0x000040),
 103         REG(QS_INH_DBG,                    0x000048),
 104 };
 105
 106 static const u32 ocelot_qsys_regmap[] = {
 107         REG(QSYS_PORT_MODE,                0x011200),
 108         REG(QSYS_SWITCH_PORT_MODE,         0x011234),
 109         REG(QSYS_STAT_CNT_CFG,             0x011264),
 110         REG(QSYS_EEE_CFG,                  0x011268),
 111         REG(QSYS_EEE_THRES,                0x011294),
 112         REG(QSYS_IGR_NO_SHARING,           0x011298),
 113         REG(QSYS_EGR_NO_SHARING,           0x01129c),
 114         REG(QSYS_SW_STATUS,                0x0112a0),
 115         REG(QSYS_EXT_CPU_CFG,              0x0112d0),
 116         REG(QSYS_PAD_CFG,                  0x0112d4),
 117         REG(QSYS_CPU_GROUP_MAP,            0x0112d8),
 118         REG(QSYS_QMAP,                     0x0112dc),
 119         REG(QSYS_ISDX_SGRP,                0x011400),
 120         REG(QSYS_TIMED_FRAME_ENTRY,        0x014000),
 121         REG(QSYS_TFRM_MISC,                0x011310),
 122         REG(QSYS_TFRM_PORT_DLY,            0x011314),
 123         REG(QSYS_TFRM_TIMER_CFG_1,         0x011318),
 124         REG(QSYS_TFRM_TIMER_CFG_2,         0x01131c),
 125         REG(QSYS_TFRM_TIMER_CFG_3,         0x011320),
 126         REG(QSYS_TFRM_TIMER_CFG_4,         0x011324),
 127         REG(QSYS_TFRM_TIMER_CFG_5,         0x011328),
 128         REG(QSYS_TFRM_TIMER_CFG_6,         0x01132c),
 129         REG(QSYS_TFRM_TIMER_CFG_7,         0x011330),
 130         REG(QSYS_TFRM_TIMER_CFG_8,         0x011334),
 131         REG(QSYS_RED_PROFILE,              0x011338),
 132         REG(QSYS_RES_QOS_MODE,             0x011378),
 133         REG(QSYS_RES_CFG,                  0x012000),
 134         REG(QSYS_RES_STAT,                 0x012004),
 135         REG(QSYS_EGR_DROP_MODE,            0x01137c),
 136         REG(QSYS_EQ_CTRL,                  0x011380),
 137         REG(QSYS_EVENTS_CORE,              0x011384),
 138         REG(QSYS_CIR_CFG,                  0x000000),
 139         REG(QSYS_EIR_CFG,                  0x000004),
 140         REG(QSYS_SE_CFG,                   0x000008),
 141         REG(QSYS_SE_DWRR_CFG,              0x00000c),
 142         REG(QSYS_SE_CONNECT,               0x00003c),
 143         REG(QSYS_SE_DLB_SENSE,             0x000040),
 144         REG(QSYS_CIR_STATE,                0x000044),
 145         REG(QSYS_EIR_STATE,                0x000048),
 146         REG(QSYS_SE_STATE,                 0x00004c),
 147         REG(QSYS_HSCH_MISC_CFG,            0x011388),
 148 };
 149
 150 static const u32 ocelot_rew_regmap[] = {
 151         REG(REW_PORT_VLAN_CFG,             0x000000),
 152         REG(REW_TAG_CFG,                   0x000004),
 153         REG(REW_PORT_CFG,                  0x000008),
 154         REG(REW_DSCP_CFG,                  0x00000c),
 155         REG(REW_PCP_DEI_QOS_MAP_CFG,       0x000010),
 156         REG(REW_PTP_CFG,                   0x000050),
 157         REG(REW_PTP_DLY1_CFG,              0x000054),
 158         REG(REW_DSCP_REMAP_DP1_CFG,        0x000690),
 159         REG(REW_DSCP_REMAP_CFG,            0x000790),
 160         REG(REW_STAT_CFG,                  0x000890),
 161         REG(REW_PPT,                       0x000680),
 162 };
 163
 164 static const u32 ocelot_sys_regmap[] = {
 165         REG(SYS_COUNT_RX_OCTETS,           0x000000),
 166         REG(SYS_COUNT_RX_UNICAST,          0x000004),
 167         REG(SYS_COUNT_RX_MULTICAST,        0x000008),
 168         REG(SYS_COUNT_RX_BROADCAST,        0x00000c),
 169         REG(SYS_COUNT_RX_SHORTS,           0x000010),
 170         REG(SYS_COUNT_RX_FRAGMENTS,        0x000014),
 171         REG(SYS_COUNT_RX_JABBERS,          0x000018),
 172         REG(SYS_COUNT_RX_CRC_ALIGN_ERRS,   0x00001c),
 173         REG(SYS_COUNT_RX_SYM_ERRS,         0x000020),
 174         REG(SYS_COUNT_RX_64,               0x000024),
 175         REG(SYS_COUNT_RX_65_127,           0x000028),
 176         REG(SYS_COUNT_RX_128_255,          0x00002c),
 177         REG(SYS_COUNT_RX_256_1023,         0x000030),
 178         REG(SYS_COUNT_RX_1024_1526,        0x000034),
 179         REG(SYS_COUNT_RX_1527_MAX,         0x000038),
 180         REG(SYS_COUNT_RX_PAUSE,            0x00003c),
 181         REG(SYS_COUNT_RX_CONTROL,          0x000040),
 182         REG(SYS_COUNT_RX_LONGS,            0x000044),
 183         REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048),
 184         REG(SYS_COUNT_TX_OCTETS,           0x000100),
 185         REG(SYS_COUNT_TX_UNICAST,          0x000104),
 186         REG(SYS_COUNT_TX_MULTICAST,        0x000108),
 187         REG(SYS_COUNT_TX_BROADCAST,        0x00010c),
 188         REG(SYS_COUNT_TX_COLLISION,        0x000110),
 189         REG(SYS_COUNT_TX_DROPS,            0x000114),
 190         REG(SYS_COUNT_TX_PAUSE,            0x000118),
 191         REG(SYS_COUNT_TX_64,               0x00011c),
 192         REG(SYS_COUNT_TX_65_127,           0x000120),
 193         REG(SYS_COUNT_TX_128_511,          0x000124),
 194         REG(SYS_COUNT_TX_512_1023,         0x000128),
 195         REG(SYS_COUNT_TX_1024_1526,        0x00012c),
 196         REG(SYS_COUNT_TX_1527_MAX,         0x000130),
 197         REG(SYS_COUNT_TX_AGING,            0x000170),
 198         REG(SYS_RESET_CFG,                 0x000508),
 199         REG(SYS_CMID,                      0x00050c),
 200         REG(SYS_VLAN_ETYPE_CFG,            0x000510),
 201         REG(SYS_PORT_MODE,                 0x000514),
 202         REG(SYS_FRONT_PORT_MODE,           0x000548),
 203         REG(SYS_FRM_AGING,                 0x000574),
 204         REG(SYS_STAT_CFG,                  0x000578),
 205         REG(SYS_SW_STATUS,                 0x00057c),
 206         REG(SYS_MISC_CFG,                  0x0005ac),
 207         REG(SYS_REW_MAC_HIGH_CFG,          0x0005b0),
 208         REG(SYS_REW_MAC_LOW_CFG,           0x0005dc),
 209         REG(SYS_CM_ADDR,                   0x000500),
 210         REG(SYS_CM_DATA,                   0x000504),
 211         REG(SYS_PAUSE_CFG,                 0x000608),
 212         REG(SYS_PAUSE_TOT_CFG,             0x000638),
 213         REG(SYS_ATOP,                      0x00063c),
 214         REG(SYS_ATOP_TOT_CFG,              0x00066c),
 215         REG(SYS_MAC_FC_CFG,                0x000670),
 216         REG(SYS_MMGT,                      0x00069c),
 217         REG(SYS_MMGT_FAST,                 0x0006a0),
 218         REG(SYS_EVENTS_DIF,                0x0006a4),
 219         REG(SYS_EVENTS_CORE,               0x0006b4),
 220         REG(SYS_CNT,                       0x000000),
 221         REG(SYS_PTP_STATUS,                0x0006b8),
 222         REG(SYS_PTP_TXSTAMP,               0x0006bc),
 223         REG(SYS_PTP_NXT,                   0x0006c0),
 224         REG(SYS_PTP_CFG,                   0x0006c4),
 225 };
 226
 227 static const u32 ocelot_s2_regmap[] = {
 228         REG(S2_CORE_UPDATE_CTRL,           0x000000),
 229         REG(S2_CORE_MV_CFG,                0x000004),
 230         REG(S2_CACHE_ENTRY_DAT,            0x000008),
 231         REG(S2_CACHE_MASK_DAT,             0x000108),
 232         REG(S2_CACHE_ACTION_DAT,           0x000208),
 233         REG(S2_CACHE_CNT_DAT,              0x000308),
 234         REG(S2_CACHE_TG_DAT,               0x000388),
 235 };
 236
 237 static const u32 ocelot_ptp_regmap[] = {
 238         REG(PTP_PIN_CFG,                   0x000000),
 239         REG(PTP_PIN_TOD_SEC_MSB,           0x000004),
 240         REG(PTP_PIN_TOD_SEC_LSB,           0x000008),
 241         REG(PTP_PIN_TOD_NSEC,              0x00000c),
 242         REG(PTP_CFG_MISC,                  0x0000a0),
 243         REG(PTP_CLK_CFG_ADJ_CFG,           0x0000a4),
 244         REG(PTP_CLK_CFG_ADJ_FREQ,          0x0000a8),
 245 };
 246
 247 static const u32 *ocelot_regmap[] = {
 248         [ANA] = ocelot_ana_regmap,
 249         [QS] = ocelot_qs_regmap,
 250         [QSYS] = ocelot_qsys_regmap,
 251         [REW] = ocelot_rew_regmap,
 252         [SYS] = ocelot_sys_regmap,
 253         [S2] = ocelot_s2_regmap,
 254         [PTP] = ocelot_ptp_regmap,
 255 };
 256
 257 static const struct reg_field ocelot_regfields[] = {
 258         [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11),
 259         [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10),
 260         [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27),
 261         [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26),
 262         [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25),
 263         [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24),
 264         [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23),
 265         [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22),
 266         [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21),
 267         [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20),
 268         [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19),
 269         [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
 270         [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17),
 271         [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16),
 272         [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15),
 273         [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14),
 274         [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13),
 275         [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12),
 276         [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
 277         [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
 278         [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9),
 279         [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8),
 280         [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7),
 281         [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
 282         [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
 283         [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4),
 284         [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3),
 285         [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2),
 286         [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1),
 287         [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0),
 288         [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18),
 289         [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11),
 290         [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9),
 291         [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20),
 292         [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19),
 293         [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7),
 294         [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3),
 295         [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0),
 296         [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2),
 297         [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1),
 298         [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0),
 299 };
 300
 301 static const struct ocelot_stat_layout ocelot_stats_layout[] = {
 302         { .name = "rx_octets", .offset = 0x00, },
 303         { .name = "rx_unicast", .offset = 0x01, },
 304         { .name = "rx_multicast", .offset = 0x02, },
 305         { .name = "rx_broadcast", .offset = 0x03, },
 306         { .name = "rx_shorts", .offset = 0x04, },
 307         { .name = "rx_fragments", .offset = 0x05, },
 308         { .name = "rx_jabbers", .offset = 0x06, },
 309         { .name = "rx_crc_align_errs", .offset = 0x07, },
 310         { .name = "rx_sym_errs", .offset = 0x08, },
 311         { .name = "rx_frames_below_65_octets", .offset = 0x09, },
 312         { .name = "rx_frames_65_to_127_octets", .offset = 0x0A, },
 313         { .name = "rx_frames_128_to_255_octets", .offset = 0x0B, },
 314         { .name = "rx_frames_256_to_511_octets", .offset = 0x0C, },
 315         { .name = "rx_frames_512_to_1023_octets", .offset = 0x0D, },
 316         { .name = "rx_frames_1024_to_1526_octets", .offset = 0x0E, },
 317         { .name = "rx_frames_over_1526_octets", .offset = 0x0F, },
 318         { .name = "rx_pause", .offset = 0x10, },
 319         { .name = "rx_control", .offset = 0x11, },
 320         { .name = "rx_longs", .offset = 0x12, },
 321         { .name = "rx_classified_drops", .offset = 0x13, },
 322         { .name = "rx_red_prio_0", .offset = 0x14, },
 323         { .name = "rx_red_prio_1", .offset = 0x15, },
 324         { .name = "rx_red_prio_2", .offset = 0x16, },
 325         { .name = "rx_red_prio_3", .offset = 0x17, },
 326         { .name = "rx_red_prio_4", .offset = 0x18, },
 327         { .name = "rx_red_prio_5", .offset = 0x19, },
 328         { .name = "rx_red_prio_6", .offset = 0x1A, },
 329         { .name = "rx_red_prio_7", .offset = 0x1B, },
 330         { .name = "rx_yellow_prio_0", .offset = 0x1C, },
 331         { .name = "rx_yellow_prio_1", .offset = 0x1D, },
 332         { .name = "rx_yellow_prio_2", .offset = 0x1E, },
 333         { .name = "rx_yellow_prio_3", .offset = 0x1F, },
 334         { .name = "rx_yellow_prio_4", .offset = 0x20, },
 335         { .name = "rx_yellow_prio_5", .offset = 0x21, },
 336         { .name = "rx_yellow_prio_6", .offset = 0x22, },
 337         { .name = "rx_yellow_prio_7", .offset = 0x23, },
 338         { .name = "rx_green_prio_0", .offset = 0x24, },
 339         { .name = "rx_green_prio_1", .offset = 0x25, },
 340         { .name = "rx_green_prio_2", .offset = 0x26, },
 341         { .name = "rx_green_prio_3", .offset = 0x27, },
 342         { .name = "rx_green_prio_4", .offset = 0x28, },
 343         { .name = "rx_green_prio_5", .offset = 0x29, },
 344         { .name = "rx_green_prio_6", .offset = 0x2A, },
 345         { .name = "rx_green_prio_7", .offset = 0x2B, },
 346         { .name = "tx_octets", .offset = 0x40, },
 347         { .name = "tx_unicast", .offset = 0x41, },
 348         { .name = "tx_multicast", .offset = 0x42, },
 349         { .name = "tx_broadcast", .offset = 0x43, },
 350         { .name = "tx_collision", .offset = 0x44, },
 351         { .name = "tx_drops", .offset = 0x45, },
 352         { .name = "tx_pause", .offset = 0x46, },
 353         { .name = "tx_frames_below_65_octets", .offset = 0x47, },
 354         { .name = "tx_frames_65_to_127_octets", .offset = 0x48, },
 355         { .name = "tx_frames_128_255_octets", .offset = 0x49, },
 356         { .name = "tx_frames_256_511_octets", .offset = 0x4A, },
 357         { .name = "tx_frames_512_1023_octets", .offset = 0x4B, },
 358         { .name = "tx_frames_1024_1526_octets", .offset = 0x4C, },
 359         { .name = "tx_frames_over_1526_octets", .offset = 0x4D, },
 360         { .name = "tx_yellow_prio_0", .offset = 0x4E, },
 361         { .name = "tx_yellow_prio_1", .offset = 0x4F, },
 362         { .name = "tx_yellow_prio_2", .offset = 0x50, },
 363         { .name = "tx_yellow_prio_3", .offset = 0x51, },
 364         { .name = "tx_yellow_prio_4", .offset = 0x52, },
 365         { .name = "tx_yellow_prio_5", .offset = 0x53, },
 366         { .name = "tx_yellow_prio_6", .offset = 0x54, },
 367         { .name = "tx_yellow_prio_7", .offset = 0x55, },
 368         { .name = "tx_green_prio_0", .offset = 0x56, },
 369         { .name = "tx_green_prio_1", .offset = 0x57, },
 370         { .name = "tx_green_prio_2", .offset = 0x58, },
 371         { .name = "tx_green_prio_3", .offset = 0x59, },
 372         { .name = "tx_green_prio_4", .offset = 0x5A, },
 373         { .name = "tx_green_prio_5", .offset = 0x5B, },
 374         { .name = "tx_green_prio_6", .offset = 0x5C, },
 375         { .name = "tx_green_prio_7", .offset = 0x5D, },
 376         { .name = "tx_aged", .offset = 0x5E, },
 377         { .name = "drop_local", .offset = 0x80, },
 378         { .name = "drop_tail", .offset = 0x81, },
 379         { .name = "drop_yellow_prio_0", .offset = 0x82, },
 380         { .name = "drop_yellow_prio_1", .offset = 0x83, },
 381         { .name = "drop_yellow_prio_2", .offset = 0x84, },
 382         { .name = "drop_yellow_prio_3", .offset = 0x85, },
 383         { .name = "drop_yellow_prio_4", .offset = 0x86, },
 384         { .name = "drop_yellow_prio_5", .offset = 0x87, },
 385         { .name = "drop_yellow_prio_6", .offset = 0x88, },
 386         { .name = "drop_yellow_prio_7", .offset = 0x89, },
 387         { .name = "drop_green_prio_0", .offset = 0x8A, },
 388         { .name = "drop_green_prio_1", .offset = 0x8B, },
 389         { .name = "drop_green_prio_2", .offset = 0x8C, },
 390         { .name = "drop_green_prio_3", .offset = 0x8D, },
 391         { .name = "drop_green_prio_4", .offset = 0x8E, },
 392         { .name = "drop_green_prio_5", .offset = 0x8F, },
 393         { .name = "drop_green_prio_6", .offset = 0x90, },
 394         { .name = "drop_green_prio_7", .offset = 0x91, },
 395 };
 396
 397 static void ocelot_pll5_init(struct ocelot *ocelot)
 398 {
 399         /* Configure PLL5. This will need a proper CCF driver
 400          * The values are coming from the VTSS API for Ocelot
 401          */
 402         regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
 403                      HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
 404                      HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8));
 405         regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
 406                      HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
 407                      HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
 408                      HSIO_PLL5G_CFG0_ENA_BIAS |
 409                      HSIO_PLL5G_CFG0_ENA_VCO_BUF |
 410                      HSIO_PLL5G_CFG0_ENA_CP1 |
 411                      HSIO_PLL5G_CFG0_SELCPI(2) |
 412                      HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
 413                      HSIO_PLL5G_CFG0_SELBGV820(4) |
 414                      HSIO_PLL5G_CFG0_DIV4 |
 415                      HSIO_PLL5G_CFG0_ENA_CLKTREE |
 416                      HSIO_PLL5G_CFG0_ENA_LANE);
 417         regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
 418                      HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
 419                      HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
 420                      HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
 421                      HSIO_PLL5G_CFG2_ENA_AMPCTRL |
 422                      HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
 423                      HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
 424 }
 425
 426 int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops)
 427 {
 428         int ret;
 429
 430         ocelot->map = ocelot_regmap;
 431         ocelot->stats_layout = ocelot_stats_layout;
 432         ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout);
 433         ocelot->shared_queue_sz = 224 * 1024;
 434         ocelot->num_mact_rows = 1024;
 435         ocelot->ops = ops;
 436
 437         ret = ocelot_regfields_init(ocelot, ocelot_regfields);
 438         if (ret)
 439                 return ret;
 440
 441         ocelot_pll5_init(ocelot);
 442
 443         eth_random_addr(ocelot->base_mac);
 444         ocelot->base_mac[5] &= 0xf0;
 445
 446         return 0;
 447 }
 448 EXPORT_SYMBOL(ocelot_chip_init);