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[thirdparty/linux.git] / drivers / net / ethernet / realtek / r8169_main.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
23 #include <linux/in.h>
24 #include <linux/io.h>
25 #include <linux/ip.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/prefetch.h>
31 #include <linux/ipv6.h>
32 #include <net/ip6_checksum.h>
33
34 #include "r8169.h"
35 #include "r8169_firmware.h"
36
37 #define MODULENAME "r8169"
38
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
56 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
59 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
60
61 #define R8169_MSG_DEFAULT \
62 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
63
64 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
65 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
66 #define MC_FILTER_LIMIT 32
67
68 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
69 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
70
71 #define R8169_REGS_SIZE 256
72 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
73 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
74 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77
78 #define RTL_CFG_NO_GBIT 1
79
80 /* write/read MMIO register */
81 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
84 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
85 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
86 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
87
88 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
89 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
90 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
91 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
92
93 static const struct {
94 const char *name;
95 const char *fw_name;
96 } rtl_chip_infos[] = {
97 /* PCI devices. */
98 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
99 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
100 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
101 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
102 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
103 /* PCI-E devices. */
104 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
105 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
106 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
107 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
108 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
109 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
110 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
111 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
112 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
113 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
114 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
115 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
116 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
117 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
118 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
119 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
120 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
121 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
122 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
123 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
124 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
125 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
126 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
127 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
128 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
129 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
130 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
131 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
132 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
133 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
134 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
135 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
136 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
137 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
138 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
139 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
140 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
141 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
142 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
143 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
144 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
145 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
146 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
147 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
148 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
149 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
150 [RTL_GIGA_MAC_VER_60] = {"RTL8125" },
151 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3},
152 };
153
154 static const struct pci_device_id rtl8169_pci_tbl[] = {
155 { PCI_VDEVICE(REALTEK, 0x2502) },
156 { PCI_VDEVICE(REALTEK, 0x2600) },
157 { PCI_VDEVICE(REALTEK, 0x8129) },
158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
159 { PCI_VDEVICE(REALTEK, 0x8161) },
160 { PCI_VDEVICE(REALTEK, 0x8167) },
161 { PCI_VDEVICE(REALTEK, 0x8168) },
162 { PCI_VDEVICE(NCUBE, 0x8168) },
163 { PCI_VDEVICE(REALTEK, 0x8169) },
164 { PCI_VENDOR_ID_DLINK, 0x4300,
165 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
166 { PCI_VDEVICE(DLINK, 0x4300) },
167 { PCI_VDEVICE(DLINK, 0x4302) },
168 { PCI_VDEVICE(AT, 0xc107) },
169 { PCI_VDEVICE(USR, 0x0116) },
170 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
171 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
172 { PCI_VDEVICE(REALTEK, 0x8125) },
173 { PCI_VDEVICE(REALTEK, 0x3000) },
174 {}
175 };
176
177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
178
179 static struct {
180 u32 msg_enable;
181 } debug = { -1 };
182
183 enum rtl_registers {
184 MAC0 = 0, /* Ethernet hardware address. */
185 MAC4 = 4,
186 MAR0 = 8, /* Multicast filter. */
187 CounterAddrLow = 0x10,
188 CounterAddrHigh = 0x14,
189 TxDescStartAddrLow = 0x20,
190 TxDescStartAddrHigh = 0x24,
191 TxHDescStartAddrLow = 0x28,
192 TxHDescStartAddrHigh = 0x2c,
193 FLASH = 0x30,
194 ERSR = 0x36,
195 ChipCmd = 0x37,
196 TxPoll = 0x38,
197 IntrMask = 0x3c,
198 IntrStatus = 0x3e,
199
200 TxConfig = 0x40,
201 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
202 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
203
204 RxConfig = 0x44,
205 #define RX128_INT_EN (1 << 15) /* 8111c and later */
206 #define RX_MULTI_EN (1 << 14) /* 8111c only */
207 #define RXCFG_FIFO_SHIFT 13
208 /* No threshold before first PCI xfer */
209 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
210 #define RX_EARLY_OFF (1 << 11)
211 #define RXCFG_DMA_SHIFT 8
212 /* Unlimited maximum PCI burst. */
213 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
214
215 Cfg9346 = 0x50,
216 Config0 = 0x51,
217 Config1 = 0x52,
218 Config2 = 0x53,
219 #define PME_SIGNAL (1 << 5) /* 8168c and later */
220
221 Config3 = 0x54,
222 Config4 = 0x55,
223 Config5 = 0x56,
224 PHYAR = 0x60,
225 PHYstatus = 0x6c,
226 RxMaxSize = 0xda,
227 CPlusCmd = 0xe0,
228 IntrMitigate = 0xe2,
229
230 #define RTL_COALESCE_MASK 0x0f
231 #define RTL_COALESCE_SHIFT 4
232 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
233 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
234
235 RxDescAddrLow = 0xe4,
236 RxDescAddrHigh = 0xe8,
237 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
238
239 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
240
241 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
242
243 #define TxPacketMax (8064 >> 7)
244 #define EarlySize 0x27
245
246 FuncEvent = 0xf0,
247 FuncEventMask = 0xf4,
248 FuncPresetState = 0xf8,
249 IBCR0 = 0xf8,
250 IBCR2 = 0xf9,
251 IBIMR0 = 0xfa,
252 IBISR0 = 0xfb,
253 FuncForceEvent = 0xfc,
254 };
255
256 enum rtl8168_8101_registers {
257 CSIDR = 0x64,
258 CSIAR = 0x68,
259 #define CSIAR_FLAG 0x80000000
260 #define CSIAR_WRITE_CMD 0x80000000
261 #define CSIAR_BYTE_ENABLE 0x0000f000
262 #define CSIAR_ADDR_MASK 0x00000fff
263 PMCH = 0x6f,
264 EPHYAR = 0x80,
265 #define EPHYAR_FLAG 0x80000000
266 #define EPHYAR_WRITE_CMD 0x80000000
267 #define EPHYAR_REG_MASK 0x1f
268 #define EPHYAR_REG_SHIFT 16
269 #define EPHYAR_DATA_MASK 0xffff
270 DLLPR = 0xd0,
271 #define PFM_EN (1 << 6)
272 #define TX_10M_PS_EN (1 << 7)
273 DBG_REG = 0xd1,
274 #define FIX_NAK_1 (1 << 4)
275 #define FIX_NAK_2 (1 << 3)
276 TWSI = 0xd2,
277 MCU = 0xd3,
278 #define NOW_IS_OOB (1 << 7)
279 #define TX_EMPTY (1 << 5)
280 #define RX_EMPTY (1 << 4)
281 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
282 #define EN_NDP (1 << 3)
283 #define EN_OOB_RESET (1 << 2)
284 #define LINK_LIST_RDY (1 << 1)
285 EFUSEAR = 0xdc,
286 #define EFUSEAR_FLAG 0x80000000
287 #define EFUSEAR_WRITE_CMD 0x80000000
288 #define EFUSEAR_READ_CMD 0x00000000
289 #define EFUSEAR_REG_MASK 0x03ff
290 #define EFUSEAR_REG_SHIFT 8
291 #define EFUSEAR_DATA_MASK 0xff
292 MISC_1 = 0xf2,
293 #define PFM_D3COLD_EN (1 << 6)
294 };
295
296 enum rtl8168_registers {
297 LED_FREQ = 0x1a,
298 EEE_LED = 0x1b,
299 ERIDR = 0x70,
300 ERIAR = 0x74,
301 #define ERIAR_FLAG 0x80000000
302 #define ERIAR_WRITE_CMD 0x80000000
303 #define ERIAR_READ_CMD 0x00000000
304 #define ERIAR_ADDR_BYTE_ALIGN 4
305 #define ERIAR_TYPE_SHIFT 16
306 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
307 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
308 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
309 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
310 #define ERIAR_MASK_SHIFT 12
311 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
312 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
313 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
314 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
315 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
316 EPHY_RXER_NUM = 0x7c,
317 OCPDR = 0xb0, /* OCP GPHY access */
318 #define OCPDR_WRITE_CMD 0x80000000
319 #define OCPDR_READ_CMD 0x00000000
320 #define OCPDR_REG_MASK 0x7f
321 #define OCPDR_GPHY_REG_SHIFT 16
322 #define OCPDR_DATA_MASK 0xffff
323 OCPAR = 0xb4,
324 #define OCPAR_FLAG 0x80000000
325 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
326 #define OCPAR_GPHY_READ_CMD 0x0000f060
327 GPHY_OCP = 0xb8,
328 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
329 MISC = 0xf0, /* 8168e only. */
330 #define TXPLA_RST (1 << 29)
331 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
332 #define PWM_EN (1 << 22)
333 #define RXDV_GATED_EN (1 << 19)
334 #define EARLY_TALLY_EN (1 << 16)
335 };
336
337 enum rtl8125_registers {
338 IntrMask_8125 = 0x38,
339 IntrStatus_8125 = 0x3c,
340 TxPoll_8125 = 0x90,
341 MAC0_BKP = 0x19e0,
342 };
343
344 #define RX_VLAN_INNER_8125 BIT(22)
345 #define RX_VLAN_OUTER_8125 BIT(23)
346 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
347
348 #define RX_FETCH_DFLT_8125 (8 << 27)
349
350 enum rtl_register_content {
351 /* InterruptStatusBits */
352 SYSErr = 0x8000,
353 PCSTimeout = 0x4000,
354 SWInt = 0x0100,
355 TxDescUnavail = 0x0080,
356 RxFIFOOver = 0x0040,
357 LinkChg = 0x0020,
358 RxOverflow = 0x0010,
359 TxErr = 0x0008,
360 TxOK = 0x0004,
361 RxErr = 0x0002,
362 RxOK = 0x0001,
363
364 /* RxStatusDesc */
365 RxRWT = (1 << 22),
366 RxRES = (1 << 21),
367 RxRUNT = (1 << 20),
368 RxCRC = (1 << 19),
369
370 /* ChipCmdBits */
371 StopReq = 0x80,
372 CmdReset = 0x10,
373 CmdRxEnb = 0x08,
374 CmdTxEnb = 0x04,
375 RxBufEmpty = 0x01,
376
377 /* TXPoll register p.5 */
378 HPQ = 0x80, /* Poll cmd on the high prio queue */
379 NPQ = 0x40, /* Poll cmd on the low prio queue */
380 FSWInt = 0x01, /* Forced software interrupt */
381
382 /* Cfg9346Bits */
383 Cfg9346_Lock = 0x00,
384 Cfg9346_Unlock = 0xc0,
385
386 /* rx_mode_bits */
387 AcceptErr = 0x20,
388 AcceptRunt = 0x10,
389 AcceptBroadcast = 0x08,
390 AcceptMulticast = 0x04,
391 AcceptMyPhys = 0x02,
392 AcceptAllPhys = 0x01,
393 #define RX_CONFIG_ACCEPT_MASK 0x3f
394
395 /* TxConfigBits */
396 TxInterFrameGapShift = 24,
397 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
398
399 /* Config1 register p.24 */
400 LEDS1 = (1 << 7),
401 LEDS0 = (1 << 6),
402 Speed_down = (1 << 4),
403 MEMMAP = (1 << 3),
404 IOMAP = (1 << 2),
405 VPD = (1 << 1),
406 PMEnable = (1 << 0), /* Power Management Enable */
407
408 /* Config2 register p. 25 */
409 ClkReqEn = (1 << 7), /* Clock Request Enable */
410 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
411 PCI_Clock_66MHz = 0x01,
412 PCI_Clock_33MHz = 0x00,
413
414 /* Config3 register p.25 */
415 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
416 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
417 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
418 Rdy_to_L23 = (1 << 1), /* L23 Enable */
419 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
420
421 /* Config4 register */
422 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
423
424 /* Config5 register p.27 */
425 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
426 MWF = (1 << 5), /* Accept Multicast wakeup frame */
427 UWF = (1 << 4), /* Accept Unicast wakeup frame */
428 Spi_en = (1 << 3),
429 LanWake = (1 << 1), /* LanWake enable/disable */
430 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
431 ASPM_en = (1 << 0), /* ASPM enable */
432
433 /* CPlusCmd p.31 */
434 EnableBist = (1 << 15), // 8168 8101
435 Mac_dbgo_oe = (1 << 14), // 8168 8101
436 EnAnaPLL = (1 << 14), // 8169
437 Normal_mode = (1 << 13), // unused
438 Force_half_dup = (1 << 12), // 8168 8101
439 Force_rxflow_en = (1 << 11), // 8168 8101
440 Force_txflow_en = (1 << 10), // 8168 8101
441 Cxpl_dbg_sel = (1 << 9), // 8168 8101
442 ASF = (1 << 8), // 8168 8101
443 PktCntrDisable = (1 << 7), // 8168 8101
444 Mac_dbgo_sel = 0x001c, // 8168
445 RxVlan = (1 << 6),
446 RxChkSum = (1 << 5),
447 PCIDAC = (1 << 4),
448 PCIMulRW = (1 << 3),
449 #define INTT_MASK GENMASK(1, 0)
450 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
451
452 /* rtl8169_PHYstatus */
453 TBI_Enable = 0x80,
454 TxFlowCtrl = 0x40,
455 RxFlowCtrl = 0x20,
456 _1000bpsF = 0x10,
457 _100bps = 0x08,
458 _10bps = 0x04,
459 LinkStatus = 0x02,
460 FullDup = 0x01,
461
462 /* ResetCounterCommand */
463 CounterReset = 0x1,
464
465 /* DumpCounterCommand */
466 CounterDump = 0x8,
467
468 /* magic enable v2 */
469 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
470 };
471
472 enum rtl_desc_bit {
473 /* First doubleword. */
474 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
475 RingEnd = (1 << 30), /* End of descriptor ring */
476 FirstFrag = (1 << 29), /* First segment of a packet */
477 LastFrag = (1 << 28), /* Final segment of a packet */
478 };
479
480 /* Generic case. */
481 enum rtl_tx_desc_bit {
482 /* First doubleword. */
483 TD_LSO = (1 << 27), /* Large Send Offload */
484 #define TD_MSS_MAX 0x07ffu /* MSS value */
485
486 /* Second doubleword. */
487 TxVlanTag = (1 << 17), /* Add VLAN tag */
488 };
489
490 /* 8169, 8168b and 810x except 8102e. */
491 enum rtl_tx_desc_bit_0 {
492 /* First doubleword. */
493 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
494 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
495 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
496 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
497 };
498
499 /* 8102e, 8168c and beyond. */
500 enum rtl_tx_desc_bit_1 {
501 /* First doubleword. */
502 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
503 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
504 #define GTTCPHO_SHIFT 18
505 #define GTTCPHO_MAX 0x7f
506
507 /* Second doubleword. */
508 #define TCPHO_SHIFT 18
509 #define TCPHO_MAX 0x3ff
510 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
511 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
512 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
513 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
514 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
515 };
516
517 enum rtl_rx_desc_bit {
518 /* Rx private */
519 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
520 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
521
522 #define RxProtoUDP (PID1)
523 #define RxProtoTCP (PID0)
524 #define RxProtoIP (PID1 | PID0)
525 #define RxProtoMask RxProtoIP
526
527 IPFail = (1 << 16), /* IP checksum failed */
528 UDPFail = (1 << 15), /* UDP/IP checksum failed */
529 TCPFail = (1 << 14), /* TCP/IP checksum failed */
530 RxVlanTag = (1 << 16), /* VLAN tag available */
531 };
532
533 #define RsvdMask 0x3fffc000
534
535 #define RTL_GSO_MAX_SIZE_V1 32000
536 #define RTL_GSO_MAX_SEGS_V1 24
537 #define RTL_GSO_MAX_SIZE_V2 64000
538 #define RTL_GSO_MAX_SEGS_V2 64
539
540 struct TxDesc {
541 __le32 opts1;
542 __le32 opts2;
543 __le64 addr;
544 };
545
546 struct RxDesc {
547 __le32 opts1;
548 __le32 opts2;
549 __le64 addr;
550 };
551
552 struct ring_info {
553 struct sk_buff *skb;
554 u32 len;
555 };
556
557 struct rtl8169_counters {
558 __le64 tx_packets;
559 __le64 rx_packets;
560 __le64 tx_errors;
561 __le32 rx_errors;
562 __le16 rx_missed;
563 __le16 align_errors;
564 __le32 tx_one_collision;
565 __le32 tx_multi_collision;
566 __le64 rx_unicast;
567 __le64 rx_broadcast;
568 __le32 rx_multicast;
569 __le16 tx_aborted;
570 __le16 tx_underun;
571 };
572
573 struct rtl8169_tc_offsets {
574 bool inited;
575 __le64 tx_errors;
576 __le32 tx_multi_collision;
577 __le16 tx_aborted;
578 __le16 rx_missed;
579 };
580
581 enum rtl_flag {
582 RTL_FLAG_TASK_ENABLED = 0,
583 RTL_FLAG_TASK_RESET_PENDING,
584 RTL_FLAG_MAX
585 };
586
587 struct rtl8169_stats {
588 u64 packets;
589 u64 bytes;
590 struct u64_stats_sync syncp;
591 };
592
593 struct rtl8169_private {
594 void __iomem *mmio_addr; /* memory map physical address */
595 struct pci_dev *pci_dev;
596 struct net_device *dev;
597 struct phy_device *phydev;
598 struct napi_struct napi;
599 u32 msg_enable;
600 enum mac_version mac_version;
601 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
602 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
603 u32 dirty_tx;
604 struct rtl8169_stats rx_stats;
605 struct rtl8169_stats tx_stats;
606 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
607 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
608 dma_addr_t TxPhyAddr;
609 dma_addr_t RxPhyAddr;
610 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
611 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
612 u16 cp_cmd;
613 u32 irq_mask;
614 struct clk *clk;
615
616 struct {
617 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
618 struct mutex mutex;
619 struct work_struct work;
620 } wk;
621
622 unsigned irq_enabled:1;
623 unsigned supports_gmii:1;
624 unsigned aspm_manageable:1;
625 dma_addr_t counters_phys_addr;
626 struct rtl8169_counters *counters;
627 struct rtl8169_tc_offsets tc_offset;
628 u32 saved_wolopts;
629 int eee_adv;
630
631 const char *fw_name;
632 struct rtl_fw *rtl_fw;
633
634 u32 ocp_base;
635 };
636
637 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
638
639 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
640 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
641 module_param_named(debug, debug.msg_enable, int, 0);
642 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
643 MODULE_SOFTDEP("pre: realtek");
644 MODULE_LICENSE("GPL");
645 MODULE_FIRMWARE(FIRMWARE_8168D_1);
646 MODULE_FIRMWARE(FIRMWARE_8168D_2);
647 MODULE_FIRMWARE(FIRMWARE_8168E_1);
648 MODULE_FIRMWARE(FIRMWARE_8168E_2);
649 MODULE_FIRMWARE(FIRMWARE_8168E_3);
650 MODULE_FIRMWARE(FIRMWARE_8105E_1);
651 MODULE_FIRMWARE(FIRMWARE_8168F_1);
652 MODULE_FIRMWARE(FIRMWARE_8168F_2);
653 MODULE_FIRMWARE(FIRMWARE_8402_1);
654 MODULE_FIRMWARE(FIRMWARE_8411_1);
655 MODULE_FIRMWARE(FIRMWARE_8411_2);
656 MODULE_FIRMWARE(FIRMWARE_8106E_1);
657 MODULE_FIRMWARE(FIRMWARE_8106E_2);
658 MODULE_FIRMWARE(FIRMWARE_8168G_2);
659 MODULE_FIRMWARE(FIRMWARE_8168G_3);
660 MODULE_FIRMWARE(FIRMWARE_8168H_1);
661 MODULE_FIRMWARE(FIRMWARE_8168H_2);
662 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
663 MODULE_FIRMWARE(FIRMWARE_8107E_1);
664 MODULE_FIRMWARE(FIRMWARE_8107E_2);
665 MODULE_FIRMWARE(FIRMWARE_8125A_3);
666
667 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
668 {
669 return &tp->pci_dev->dev;
670 }
671
672 static void rtl_lock_work(struct rtl8169_private *tp)
673 {
674 mutex_lock(&tp->wk.mutex);
675 }
676
677 static void rtl_unlock_work(struct rtl8169_private *tp)
678 {
679 mutex_unlock(&tp->wk.mutex);
680 }
681
682 static void rtl_lock_config_regs(struct rtl8169_private *tp)
683 {
684 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
685 }
686
687 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
688 {
689 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
690 }
691
692 static void rtl_pci_commit(struct rtl8169_private *tp)
693 {
694 /* Read an arbitrary register to commit a preceding PCI write */
695 RTL_R8(tp, ChipCmd);
696 }
697
698 static bool rtl_is_8125(struct rtl8169_private *tp)
699 {
700 return tp->mac_version >= RTL_GIGA_MAC_VER_60;
701 }
702
703 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
704 {
705 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
706 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
707 tp->mac_version <= RTL_GIGA_MAC_VER_52;
708 }
709
710 static bool rtl_supports_eee(struct rtl8169_private *tp)
711 {
712 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
713 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
714 tp->mac_version != RTL_GIGA_MAC_VER_39;
715 }
716
717 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
718 {
719 int i;
720
721 for (i = 0; i < ETH_ALEN; i++)
722 mac[i] = RTL_R8(tp, reg + i);
723 }
724
725 struct rtl_cond {
726 bool (*check)(struct rtl8169_private *);
727 const char *msg;
728 };
729
730 static void rtl_udelay(unsigned int d)
731 {
732 udelay(d);
733 }
734
735 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
736 void (*delay)(unsigned int), unsigned int d, int n,
737 bool high)
738 {
739 int i;
740
741 for (i = 0; i < n; i++) {
742 if (c->check(tp) == high)
743 return true;
744 delay(d);
745 }
746 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
747 c->msg, !high, n, d);
748 return false;
749 }
750
751 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
752 const struct rtl_cond *c,
753 unsigned int d, int n)
754 {
755 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
756 }
757
758 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
759 const struct rtl_cond *c,
760 unsigned int d, int n)
761 {
762 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
763 }
764
765 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
766 const struct rtl_cond *c,
767 unsigned int d, int n)
768 {
769 return rtl_loop_wait(tp, c, msleep, d, n, true);
770 }
771
772 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
773 const struct rtl_cond *c,
774 unsigned int d, int n)
775 {
776 return rtl_loop_wait(tp, c, msleep, d, n, false);
777 }
778
779 #define DECLARE_RTL_COND(name) \
780 static bool name ## _check(struct rtl8169_private *); \
781 \
782 static const struct rtl_cond name = { \
783 .check = name ## _check, \
784 .msg = #name \
785 }; \
786 \
787 static bool name ## _check(struct rtl8169_private *tp)
788
789 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
790 {
791 if (reg & 0xffff0001) {
792 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
793 return true;
794 }
795 return false;
796 }
797
798 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
799 {
800 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
801 }
802
803 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
804 {
805 if (rtl_ocp_reg_failure(tp, reg))
806 return;
807
808 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
809
810 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
811 }
812
813 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
814 {
815 if (rtl_ocp_reg_failure(tp, reg))
816 return 0;
817
818 RTL_W32(tp, GPHY_OCP, reg << 15);
819
820 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
821 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
822 }
823
824 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
825 {
826 if (rtl_ocp_reg_failure(tp, reg))
827 return;
828
829 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
830 }
831
832 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
833 {
834 if (rtl_ocp_reg_failure(tp, reg))
835 return 0;
836
837 RTL_W32(tp, OCPDR, reg << 15);
838
839 return RTL_R32(tp, OCPDR);
840 }
841
842 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
843 u16 set)
844 {
845 u16 data = r8168_mac_ocp_read(tp, reg);
846
847 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
848 }
849
850 #define OCP_STD_PHY_BASE 0xa400
851
852 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
853 {
854 if (reg == 0x1f) {
855 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
856 return;
857 }
858
859 if (tp->ocp_base != OCP_STD_PHY_BASE)
860 reg -= 0x10;
861
862 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
863 }
864
865 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
866 {
867 if (reg == 0x1f)
868 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
869
870 if (tp->ocp_base != OCP_STD_PHY_BASE)
871 reg -= 0x10;
872
873 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
874 }
875
876 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
877 {
878 if (reg == 0x1f) {
879 tp->ocp_base = value << 4;
880 return;
881 }
882
883 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
884 }
885
886 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
887 {
888 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
889 }
890
891 DECLARE_RTL_COND(rtl_phyar_cond)
892 {
893 return RTL_R32(tp, PHYAR) & 0x80000000;
894 }
895
896 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
897 {
898 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
899
900 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
901 /*
902 * According to hardware specs a 20us delay is required after write
903 * complete indication, but before sending next command.
904 */
905 udelay(20);
906 }
907
908 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
909 {
910 int value;
911
912 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
913
914 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
915 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
916
917 /*
918 * According to hardware specs a 20us delay is required after read
919 * complete indication, but before sending next command.
920 */
921 udelay(20);
922
923 return value;
924 }
925
926 DECLARE_RTL_COND(rtl_ocpar_cond)
927 {
928 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
929 }
930
931 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
932 {
933 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
934 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
935 RTL_W32(tp, EPHY_RXER_NUM, 0);
936
937 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
938 }
939
940 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
941 {
942 r8168dp_1_mdio_access(tp, reg,
943 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
944 }
945
946 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
947 {
948 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
949
950 mdelay(1);
951 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
952 RTL_W32(tp, EPHY_RXER_NUM, 0);
953
954 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
955 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
956 }
957
958 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
959
960 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
961 {
962 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
963 }
964
965 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
966 {
967 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
968 }
969
970 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
971 {
972 r8168dp_2_mdio_start(tp);
973
974 r8169_mdio_write(tp, reg, value);
975
976 r8168dp_2_mdio_stop(tp);
977 }
978
979 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
980 {
981 int value;
982
983 /* Work around issue with chip reporting wrong PHY ID */
984 if (reg == MII_PHYSID2)
985 return 0xc912;
986
987 r8168dp_2_mdio_start(tp);
988
989 value = r8169_mdio_read(tp, reg);
990
991 r8168dp_2_mdio_stop(tp);
992
993 return value;
994 }
995
996 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
997 {
998 switch (tp->mac_version) {
999 case RTL_GIGA_MAC_VER_27:
1000 r8168dp_1_mdio_write(tp, location, val);
1001 break;
1002 case RTL_GIGA_MAC_VER_28:
1003 case RTL_GIGA_MAC_VER_31:
1004 r8168dp_2_mdio_write(tp, location, val);
1005 break;
1006 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1007 r8168g_mdio_write(tp, location, val);
1008 break;
1009 default:
1010 r8169_mdio_write(tp, location, val);
1011 break;
1012 }
1013 }
1014
1015 static int rtl_readphy(struct rtl8169_private *tp, int location)
1016 {
1017 switch (tp->mac_version) {
1018 case RTL_GIGA_MAC_VER_27:
1019 return r8168dp_1_mdio_read(tp, location);
1020 case RTL_GIGA_MAC_VER_28:
1021 case RTL_GIGA_MAC_VER_31:
1022 return r8168dp_2_mdio_read(tp, location);
1023 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1024 return r8168g_mdio_read(tp, location);
1025 default:
1026 return r8169_mdio_read(tp, location);
1027 }
1028 }
1029
1030 DECLARE_RTL_COND(rtl_ephyar_cond)
1031 {
1032 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1033 }
1034
1035 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1036 {
1037 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1038 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1039
1040 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1041
1042 udelay(10);
1043 }
1044
1045 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1046 {
1047 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1048
1049 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1050 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1051 }
1052
1053 DECLARE_RTL_COND(rtl_eriar_cond)
1054 {
1055 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1056 }
1057
1058 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1059 u32 val, int type)
1060 {
1061 BUG_ON((addr & 3) || (mask == 0));
1062 RTL_W32(tp, ERIDR, val);
1063 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1064
1065 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1066 }
1067
1068 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1069 u32 val)
1070 {
1071 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1072 }
1073
1074 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1075 {
1076 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1077
1078 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1079 RTL_R32(tp, ERIDR) : ~0;
1080 }
1081
1082 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1083 {
1084 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1085 }
1086
1087 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1088 u32 m)
1089 {
1090 u32 val;
1091
1092 val = rtl_eri_read(tp, addr);
1093 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1094 }
1095
1096 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1097 u32 p)
1098 {
1099 rtl_w0w1_eri(tp, addr, mask, p, 0);
1100 }
1101
1102 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1103 u32 m)
1104 {
1105 rtl_w0w1_eri(tp, addr, mask, 0, m);
1106 }
1107
1108 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1109 {
1110 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1111 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1112 RTL_R32(tp, OCPDR) : ~0;
1113 }
1114
1115 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1116 {
1117 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1118 }
1119
1120 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1121 u32 data)
1122 {
1123 RTL_W32(tp, OCPDR, data);
1124 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1125 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1126 }
1127
1128 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1129 u32 data)
1130 {
1131 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1132 data, ERIAR_OOB);
1133 }
1134
1135 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1136 {
1137 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1138
1139 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1140 }
1141
1142 #define OOB_CMD_RESET 0x00
1143 #define OOB_CMD_DRIVER_START 0x05
1144 #define OOB_CMD_DRIVER_STOP 0x06
1145
1146 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1147 {
1148 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1149 }
1150
1151 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1152 {
1153 u16 reg;
1154
1155 reg = rtl8168_get_ocp_reg(tp);
1156
1157 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1158 }
1159
1160 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1161 {
1162 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1163 }
1164
1165 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1166 {
1167 return RTL_R8(tp, IBISR0) & 0x20;
1168 }
1169
1170 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1171 {
1172 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1173 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1174 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1175 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1176 }
1177
1178 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1179 {
1180 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1181 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1182 }
1183
1184 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1185 {
1186 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1187 r8168ep_ocp_write(tp, 0x01, 0x30,
1188 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1189 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1190 }
1191
1192 static void rtl8168_driver_start(struct rtl8169_private *tp)
1193 {
1194 switch (tp->mac_version) {
1195 case RTL_GIGA_MAC_VER_27:
1196 case RTL_GIGA_MAC_VER_28:
1197 case RTL_GIGA_MAC_VER_31:
1198 rtl8168dp_driver_start(tp);
1199 break;
1200 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1201 rtl8168ep_driver_start(tp);
1202 break;
1203 default:
1204 BUG();
1205 break;
1206 }
1207 }
1208
1209 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1210 {
1211 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1212 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1213 }
1214
1215 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1216 {
1217 rtl8168ep_stop_cmac(tp);
1218 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1219 r8168ep_ocp_write(tp, 0x01, 0x30,
1220 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1221 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1222 }
1223
1224 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1225 {
1226 switch (tp->mac_version) {
1227 case RTL_GIGA_MAC_VER_27:
1228 case RTL_GIGA_MAC_VER_28:
1229 case RTL_GIGA_MAC_VER_31:
1230 rtl8168dp_driver_stop(tp);
1231 break;
1232 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1233 rtl8168ep_driver_stop(tp);
1234 break;
1235 default:
1236 BUG();
1237 break;
1238 }
1239 }
1240
1241 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1242 {
1243 u16 reg = rtl8168_get_ocp_reg(tp);
1244
1245 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1246 }
1247
1248 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1249 {
1250 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1251 }
1252
1253 static bool r8168_check_dash(struct rtl8169_private *tp)
1254 {
1255 switch (tp->mac_version) {
1256 case RTL_GIGA_MAC_VER_27:
1257 case RTL_GIGA_MAC_VER_28:
1258 case RTL_GIGA_MAC_VER_31:
1259 return r8168dp_check_dash(tp);
1260 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1261 return r8168ep_check_dash(tp);
1262 default:
1263 return false;
1264 }
1265 }
1266
1267 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1268 {
1269 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1270 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1271 }
1272
1273 DECLARE_RTL_COND(rtl_efusear_cond)
1274 {
1275 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1276 }
1277
1278 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1279 {
1280 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1281
1282 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1283 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1284 }
1285
1286 static u32 rtl_get_events(struct rtl8169_private *tp)
1287 {
1288 if (rtl_is_8125(tp))
1289 return RTL_R32(tp, IntrStatus_8125);
1290 else
1291 return RTL_R16(tp, IntrStatus);
1292 }
1293
1294 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1295 {
1296 if (rtl_is_8125(tp))
1297 RTL_W32(tp, IntrStatus_8125, bits);
1298 else
1299 RTL_W16(tp, IntrStatus, bits);
1300 }
1301
1302 static void rtl_irq_disable(struct rtl8169_private *tp)
1303 {
1304 if (rtl_is_8125(tp))
1305 RTL_W32(tp, IntrMask_8125, 0);
1306 else
1307 RTL_W16(tp, IntrMask, 0);
1308 tp->irq_enabled = 0;
1309 }
1310
1311 static void rtl_irq_enable(struct rtl8169_private *tp)
1312 {
1313 tp->irq_enabled = 1;
1314 if (rtl_is_8125(tp))
1315 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1316 else
1317 RTL_W16(tp, IntrMask, tp->irq_mask);
1318 }
1319
1320 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1321 {
1322 rtl_irq_disable(tp);
1323 rtl_ack_events(tp, 0xffffffff);
1324 rtl_pci_commit(tp);
1325 }
1326
1327 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1328 {
1329 struct phy_device *phydev = tp->phydev;
1330
1331 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1332 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1333 if (phydev->speed == SPEED_1000) {
1334 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1335 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1336 } else if (phydev->speed == SPEED_100) {
1337 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1338 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1339 } else {
1340 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1341 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1342 }
1343 rtl_reset_packet_filter(tp);
1344 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1345 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1346 if (phydev->speed == SPEED_1000) {
1347 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1348 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1349 } else {
1350 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1351 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1352 }
1353 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1354 if (phydev->speed == SPEED_10) {
1355 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1356 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1357 } else {
1358 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1359 }
1360 }
1361 }
1362
1363 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1364
1365 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1366 {
1367 struct rtl8169_private *tp = netdev_priv(dev);
1368
1369 rtl_lock_work(tp);
1370 wol->supported = WAKE_ANY;
1371 wol->wolopts = tp->saved_wolopts;
1372 rtl_unlock_work(tp);
1373 }
1374
1375 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1376 {
1377 static const struct {
1378 u32 opt;
1379 u16 reg;
1380 u8 mask;
1381 } cfg[] = {
1382 { WAKE_PHY, Config3, LinkUp },
1383 { WAKE_UCAST, Config5, UWF },
1384 { WAKE_BCAST, Config5, BWF },
1385 { WAKE_MCAST, Config5, MWF },
1386 { WAKE_ANY, Config5, LanWake },
1387 { WAKE_MAGIC, Config3, MagicPacket }
1388 };
1389 unsigned int i, tmp = ARRAY_SIZE(cfg);
1390 u8 options;
1391
1392 rtl_unlock_config_regs(tp);
1393
1394 if (rtl_is_8168evl_up(tp)) {
1395 tmp--;
1396 if (wolopts & WAKE_MAGIC)
1397 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1398 MagicPacket_v2);
1399 else
1400 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1401 MagicPacket_v2);
1402 } else if (rtl_is_8125(tp)) {
1403 tmp--;
1404 if (wolopts & WAKE_MAGIC)
1405 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1406 else
1407 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1408 }
1409
1410 for (i = 0; i < tmp; i++) {
1411 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1412 if (wolopts & cfg[i].opt)
1413 options |= cfg[i].mask;
1414 RTL_W8(tp, cfg[i].reg, options);
1415 }
1416
1417 switch (tp->mac_version) {
1418 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1419 options = RTL_R8(tp, Config1) & ~PMEnable;
1420 if (wolopts)
1421 options |= PMEnable;
1422 RTL_W8(tp, Config1, options);
1423 break;
1424 case RTL_GIGA_MAC_VER_34:
1425 case RTL_GIGA_MAC_VER_37:
1426 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_52:
1427 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1428 if (wolopts)
1429 options |= PME_SIGNAL;
1430 RTL_W8(tp, Config2, options);
1431 break;
1432 default:
1433 break;
1434 }
1435
1436 rtl_lock_config_regs(tp);
1437
1438 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1439 tp->dev->wol_enabled = wolopts ? 1 : 0;
1440 }
1441
1442 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1443 {
1444 struct rtl8169_private *tp = netdev_priv(dev);
1445 struct device *d = tp_to_dev(tp);
1446
1447 if (wol->wolopts & ~WAKE_ANY)
1448 return -EINVAL;
1449
1450 pm_runtime_get_noresume(d);
1451
1452 rtl_lock_work(tp);
1453
1454 tp->saved_wolopts = wol->wolopts;
1455
1456 if (pm_runtime_active(d))
1457 __rtl8169_set_wol(tp, tp->saved_wolopts);
1458
1459 rtl_unlock_work(tp);
1460
1461 pm_runtime_put_noidle(d);
1462
1463 return 0;
1464 }
1465
1466 static void rtl8169_get_drvinfo(struct net_device *dev,
1467 struct ethtool_drvinfo *info)
1468 {
1469 struct rtl8169_private *tp = netdev_priv(dev);
1470 struct rtl_fw *rtl_fw = tp->rtl_fw;
1471
1472 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1473 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1474 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1475 if (rtl_fw)
1476 strlcpy(info->fw_version, rtl_fw->version,
1477 sizeof(info->fw_version));
1478 }
1479
1480 static int rtl8169_get_regs_len(struct net_device *dev)
1481 {
1482 return R8169_REGS_SIZE;
1483 }
1484
1485 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1486 netdev_features_t features)
1487 {
1488 struct rtl8169_private *tp = netdev_priv(dev);
1489
1490 if (dev->mtu > TD_MSS_MAX)
1491 features &= ~NETIF_F_ALL_TSO;
1492
1493 if (dev->mtu > ETH_DATA_LEN &&
1494 tp->mac_version > RTL_GIGA_MAC_VER_06)
1495 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1496
1497 return features;
1498 }
1499
1500 static int rtl8169_set_features(struct net_device *dev,
1501 netdev_features_t features)
1502 {
1503 struct rtl8169_private *tp = netdev_priv(dev);
1504 u32 rx_config;
1505
1506 rtl_lock_work(tp);
1507
1508 rx_config = RTL_R32(tp, RxConfig);
1509 if (features & NETIF_F_RXALL)
1510 rx_config |= (AcceptErr | AcceptRunt);
1511 else
1512 rx_config &= ~(AcceptErr | AcceptRunt);
1513
1514 if (rtl_is_8125(tp)) {
1515 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1516 rx_config |= RX_VLAN_8125;
1517 else
1518 rx_config &= ~RX_VLAN_8125;
1519 }
1520
1521 RTL_W32(tp, RxConfig, rx_config);
1522
1523 if (features & NETIF_F_RXCSUM)
1524 tp->cp_cmd |= RxChkSum;
1525 else
1526 tp->cp_cmd &= ~RxChkSum;
1527
1528 if (!rtl_is_8125(tp)) {
1529 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1530 tp->cp_cmd |= RxVlan;
1531 else
1532 tp->cp_cmd &= ~RxVlan;
1533 }
1534
1535 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1536 rtl_pci_commit(tp);
1537
1538 rtl_unlock_work(tp);
1539
1540 return 0;
1541 }
1542
1543 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1544 {
1545 return (skb_vlan_tag_present(skb)) ?
1546 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1547 }
1548
1549 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1550 {
1551 u32 opts2 = le32_to_cpu(desc->opts2);
1552
1553 if (opts2 & RxVlanTag)
1554 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1555 }
1556
1557 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1558 void *p)
1559 {
1560 struct rtl8169_private *tp = netdev_priv(dev);
1561 u32 __iomem *data = tp->mmio_addr;
1562 u32 *dw = p;
1563 int i;
1564
1565 rtl_lock_work(tp);
1566 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1567 memcpy_fromio(dw++, data++, 4);
1568 rtl_unlock_work(tp);
1569 }
1570
1571 static u32 rtl8169_get_msglevel(struct net_device *dev)
1572 {
1573 struct rtl8169_private *tp = netdev_priv(dev);
1574
1575 return tp->msg_enable;
1576 }
1577
1578 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1579 {
1580 struct rtl8169_private *tp = netdev_priv(dev);
1581
1582 tp->msg_enable = value;
1583 }
1584
1585 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1586 "tx_packets",
1587 "rx_packets",
1588 "tx_errors",
1589 "rx_errors",
1590 "rx_missed",
1591 "align_errors",
1592 "tx_single_collisions",
1593 "tx_multi_collisions",
1594 "unicast",
1595 "broadcast",
1596 "multicast",
1597 "tx_aborted",
1598 "tx_underrun",
1599 };
1600
1601 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1602 {
1603 switch (sset) {
1604 case ETH_SS_STATS:
1605 return ARRAY_SIZE(rtl8169_gstrings);
1606 default:
1607 return -EOPNOTSUPP;
1608 }
1609 }
1610
1611 DECLARE_RTL_COND(rtl_counters_cond)
1612 {
1613 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1614 }
1615
1616 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1617 {
1618 dma_addr_t paddr = tp->counters_phys_addr;
1619 u32 cmd;
1620
1621 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1622 rtl_pci_commit(tp);
1623 cmd = (u64)paddr & DMA_BIT_MASK(32);
1624 RTL_W32(tp, CounterAddrLow, cmd);
1625 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1626
1627 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1628 }
1629
1630 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1631 {
1632 /*
1633 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1634 * tally counters.
1635 */
1636 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1637 return true;
1638
1639 return rtl8169_do_counters(tp, CounterReset);
1640 }
1641
1642 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1643 {
1644 u8 val = RTL_R8(tp, ChipCmd);
1645
1646 /*
1647 * Some chips are unable to dump tally counters when the receiver
1648 * is disabled. If 0xff chip may be in a PCI power-save state.
1649 */
1650 if (!(val & CmdRxEnb) || val == 0xff)
1651 return true;
1652
1653 return rtl8169_do_counters(tp, CounterDump);
1654 }
1655
1656 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1657 {
1658 struct rtl8169_counters *counters = tp->counters;
1659 bool ret = false;
1660
1661 /*
1662 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1663 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1664 * reset by a power cycle, while the counter values collected by the
1665 * driver are reset at every driver unload/load cycle.
1666 *
1667 * To make sure the HW values returned by @get_stats64 match the SW
1668 * values, we collect the initial values at first open(*) and use them
1669 * as offsets to normalize the values returned by @get_stats64.
1670 *
1671 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1672 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1673 * set at open time by rtl_hw_start.
1674 */
1675
1676 if (tp->tc_offset.inited)
1677 return true;
1678
1679 /* If both, reset and update fail, propagate to caller. */
1680 if (rtl8169_reset_counters(tp))
1681 ret = true;
1682
1683 if (rtl8169_update_counters(tp))
1684 ret = true;
1685
1686 tp->tc_offset.tx_errors = counters->tx_errors;
1687 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1688 tp->tc_offset.tx_aborted = counters->tx_aborted;
1689 tp->tc_offset.rx_missed = counters->rx_missed;
1690 tp->tc_offset.inited = true;
1691
1692 return ret;
1693 }
1694
1695 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1696 struct ethtool_stats *stats, u64 *data)
1697 {
1698 struct rtl8169_private *tp = netdev_priv(dev);
1699 struct device *d = tp_to_dev(tp);
1700 struct rtl8169_counters *counters = tp->counters;
1701
1702 ASSERT_RTNL();
1703
1704 pm_runtime_get_noresume(d);
1705
1706 if (pm_runtime_active(d))
1707 rtl8169_update_counters(tp);
1708
1709 pm_runtime_put_noidle(d);
1710
1711 data[0] = le64_to_cpu(counters->tx_packets);
1712 data[1] = le64_to_cpu(counters->rx_packets);
1713 data[2] = le64_to_cpu(counters->tx_errors);
1714 data[3] = le32_to_cpu(counters->rx_errors);
1715 data[4] = le16_to_cpu(counters->rx_missed);
1716 data[5] = le16_to_cpu(counters->align_errors);
1717 data[6] = le32_to_cpu(counters->tx_one_collision);
1718 data[7] = le32_to_cpu(counters->tx_multi_collision);
1719 data[8] = le64_to_cpu(counters->rx_unicast);
1720 data[9] = le64_to_cpu(counters->rx_broadcast);
1721 data[10] = le32_to_cpu(counters->rx_multicast);
1722 data[11] = le16_to_cpu(counters->tx_aborted);
1723 data[12] = le16_to_cpu(counters->tx_underun);
1724 }
1725
1726 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1727 {
1728 switch(stringset) {
1729 case ETH_SS_STATS:
1730 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1731 break;
1732 }
1733 }
1734
1735 /*
1736 * Interrupt coalescing
1737 *
1738 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1739 * > 8169, 8168 and 810x line of chipsets
1740 *
1741 * 8169, 8168, and 8136(810x) serial chipsets support it.
1742 *
1743 * > 2 - the Tx timer unit at gigabit speed
1744 *
1745 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1746 * (0xe0) bit 1 and bit 0.
1747 *
1748 * For 8169
1749 * bit[1:0] \ speed 1000M 100M 10M
1750 * 0 0 320ns 2.56us 40.96us
1751 * 0 1 2.56us 20.48us 327.7us
1752 * 1 0 5.12us 40.96us 655.4us
1753 * 1 1 10.24us 81.92us 1.31ms
1754 *
1755 * For the other
1756 * bit[1:0] \ speed 1000M 100M 10M
1757 * 0 0 5us 2.56us 40.96us
1758 * 0 1 40us 20.48us 327.7us
1759 * 1 0 80us 40.96us 655.4us
1760 * 1 1 160us 81.92us 1.31ms
1761 */
1762
1763 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1764 struct rtl_coalesce_scale {
1765 /* Rx / Tx */
1766 u32 nsecs[2];
1767 };
1768
1769 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1770 struct rtl_coalesce_info {
1771 u32 speed;
1772 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1773 };
1774
1775 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1776 #define rxtx_x1822(r, t) { \
1777 {{(r), (t)}}, \
1778 {{(r)*8, (t)*8}}, \
1779 {{(r)*8*2, (t)*8*2}}, \
1780 {{(r)*8*2*2, (t)*8*2*2}}, \
1781 }
1782 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1783 /* speed delays: rx00 tx00 */
1784 { SPEED_10, rxtx_x1822(40960, 40960) },
1785 { SPEED_100, rxtx_x1822( 2560, 2560) },
1786 { SPEED_1000, rxtx_x1822( 320, 320) },
1787 { 0 },
1788 };
1789
1790 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1791 /* speed delays: rx00 tx00 */
1792 { SPEED_10, rxtx_x1822(40960, 40960) },
1793 { SPEED_100, rxtx_x1822( 2560, 2560) },
1794 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1795 { 0 },
1796 };
1797 #undef rxtx_x1822
1798
1799 /* get rx/tx scale vector corresponding to current speed */
1800 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1801 {
1802 struct rtl8169_private *tp = netdev_priv(dev);
1803 const struct rtl_coalesce_info *ci;
1804
1805 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1806 ci = rtl_coalesce_info_8169;
1807 else
1808 ci = rtl_coalesce_info_8168_8136;
1809
1810 for (; ci->speed; ci++) {
1811 if (tp->phydev->speed == ci->speed)
1812 return ci;
1813 }
1814
1815 return ERR_PTR(-ELNRNG);
1816 }
1817
1818 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1819 {
1820 struct rtl8169_private *tp = netdev_priv(dev);
1821 const struct rtl_coalesce_info *ci;
1822 const struct rtl_coalesce_scale *scale;
1823 struct {
1824 u32 *max_frames;
1825 u32 *usecs;
1826 } coal_settings [] = {
1827 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1828 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1829 }, *p = coal_settings;
1830 int i;
1831 u16 w;
1832
1833 if (rtl_is_8125(tp))
1834 return -EOPNOTSUPP;
1835
1836 memset(ec, 0, sizeof(*ec));
1837
1838 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1839 ci = rtl_coalesce_info(dev);
1840 if (IS_ERR(ci))
1841 return PTR_ERR(ci);
1842
1843 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1844
1845 /* read IntrMitigate and adjust according to scale */
1846 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1847 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1848 w >>= RTL_COALESCE_SHIFT;
1849 *p->usecs = w & RTL_COALESCE_MASK;
1850 }
1851
1852 for (i = 0; i < 2; i++) {
1853 p = coal_settings + i;
1854 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1855
1856 /*
1857 * ethtool_coalesce says it is illegal to set both usecs and
1858 * max_frames to 0.
1859 */
1860 if (!*p->usecs && !*p->max_frames)
1861 *p->max_frames = 1;
1862 }
1863
1864 return 0;
1865 }
1866
1867 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1868 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1869 struct net_device *dev, u32 nsec, u16 *cp01)
1870 {
1871 const struct rtl_coalesce_info *ci;
1872 u16 i;
1873
1874 ci = rtl_coalesce_info(dev);
1875 if (IS_ERR(ci))
1876 return ERR_CAST(ci);
1877
1878 for (i = 0; i < 4; i++) {
1879 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1880 ci->scalev[i].nsecs[1]);
1881 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1882 *cp01 = i;
1883 return &ci->scalev[i];
1884 }
1885 }
1886
1887 return ERR_PTR(-EINVAL);
1888 }
1889
1890 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1891 {
1892 struct rtl8169_private *tp = netdev_priv(dev);
1893 const struct rtl_coalesce_scale *scale;
1894 struct {
1895 u32 frames;
1896 u32 usecs;
1897 } coal_settings [] = {
1898 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1899 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1900 }, *p = coal_settings;
1901 u16 w = 0, cp01;
1902 int i;
1903
1904 if (rtl_is_8125(tp))
1905 return -EOPNOTSUPP;
1906
1907 scale = rtl_coalesce_choose_scale(dev,
1908 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1909 if (IS_ERR(scale))
1910 return PTR_ERR(scale);
1911
1912 for (i = 0; i < 2; i++, p++) {
1913 u32 units;
1914
1915 /*
1916 * accept max_frames=1 we returned in rtl_get_coalesce.
1917 * accept it not only when usecs=0 because of e.g. the following scenario:
1918 *
1919 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1920 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1921 * - then user does `ethtool -C eth0 rx-usecs 100`
1922 *
1923 * since ethtool sends to kernel whole ethtool_coalesce
1924 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1925 * we'll reject it below in `frames % 4 != 0`.
1926 */
1927 if (p->frames == 1) {
1928 p->frames = 0;
1929 }
1930
1931 units = p->usecs * 1000 / scale->nsecs[i];
1932 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1933 return -EINVAL;
1934
1935 w <<= RTL_COALESCE_SHIFT;
1936 w |= units;
1937 w <<= RTL_COALESCE_SHIFT;
1938 w |= p->frames >> 2;
1939 }
1940
1941 rtl_lock_work(tp);
1942
1943 RTL_W16(tp, IntrMitigate, swab16(w));
1944
1945 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1946 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1947 rtl_pci_commit(tp);
1948
1949 rtl_unlock_work(tp);
1950
1951 return 0;
1952 }
1953
1954 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1955 {
1956 struct rtl8169_private *tp = netdev_priv(dev);
1957 struct device *d = tp_to_dev(tp);
1958 int ret;
1959
1960 if (!rtl_supports_eee(tp))
1961 return -EOPNOTSUPP;
1962
1963 pm_runtime_get_noresume(d);
1964
1965 if (!pm_runtime_active(d)) {
1966 ret = -EOPNOTSUPP;
1967 } else {
1968 ret = phy_ethtool_get_eee(tp->phydev, data);
1969 }
1970
1971 pm_runtime_put_noidle(d);
1972
1973 return ret;
1974 }
1975
1976 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1977 {
1978 struct rtl8169_private *tp = netdev_priv(dev);
1979 struct device *d = tp_to_dev(tp);
1980 int ret;
1981
1982 if (!rtl_supports_eee(tp))
1983 return -EOPNOTSUPP;
1984
1985 pm_runtime_get_noresume(d);
1986
1987 if (!pm_runtime_active(d)) {
1988 ret = -EOPNOTSUPP;
1989 goto out;
1990 }
1991
1992 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
1993 dev->phydev->duplex != DUPLEX_FULL) {
1994 ret = -EPROTONOSUPPORT;
1995 goto out;
1996 }
1997
1998 ret = phy_ethtool_set_eee(tp->phydev, data);
1999
2000 if (!ret)
2001 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
2002 MDIO_AN_EEE_ADV);
2003 out:
2004 pm_runtime_put_noidle(d);
2005 return ret;
2006 }
2007
2008 static const struct ethtool_ops rtl8169_ethtool_ops = {
2009 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2010 ETHTOOL_COALESCE_MAX_FRAMES,
2011 .get_drvinfo = rtl8169_get_drvinfo,
2012 .get_regs_len = rtl8169_get_regs_len,
2013 .get_link = ethtool_op_get_link,
2014 .get_coalesce = rtl_get_coalesce,
2015 .set_coalesce = rtl_set_coalesce,
2016 .get_msglevel = rtl8169_get_msglevel,
2017 .set_msglevel = rtl8169_set_msglevel,
2018 .get_regs = rtl8169_get_regs,
2019 .get_wol = rtl8169_get_wol,
2020 .set_wol = rtl8169_set_wol,
2021 .get_strings = rtl8169_get_strings,
2022 .get_sset_count = rtl8169_get_sset_count,
2023 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2024 .get_ts_info = ethtool_op_get_ts_info,
2025 .nway_reset = phy_ethtool_nway_reset,
2026 .get_eee = rtl8169_get_eee,
2027 .set_eee = rtl8169_set_eee,
2028 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2029 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2030 };
2031
2032 static void rtl_enable_eee(struct rtl8169_private *tp)
2033 {
2034 struct phy_device *phydev = tp->phydev;
2035 int adv;
2036
2037 /* respect EEE advertisement the user may have set */
2038 if (tp->eee_adv >= 0)
2039 adv = tp->eee_adv;
2040 else
2041 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2042
2043 if (adv >= 0)
2044 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
2045 }
2046
2047 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
2048 {
2049 /*
2050 * The driver currently handles the 8168Bf and the 8168Be identically
2051 * but they can be identified more specifically through the test below
2052 * if needed:
2053 *
2054 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2055 *
2056 * Same thing for the 8101Eb and the 8101Ec:
2057 *
2058 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2059 */
2060 static const struct rtl_mac_info {
2061 u16 mask;
2062 u16 val;
2063 enum mac_version ver;
2064 } mac_info[] = {
2065 /* 8125 family. */
2066 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2067 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2068
2069 /* RTL8117 */
2070 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2071
2072 /* 8168EP family. */
2073 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2074 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2075 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2076
2077 /* 8168H family. */
2078 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2079 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2080
2081 /* 8168G family. */
2082 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2083 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2084 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2085 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2086
2087 /* 8168F family. */
2088 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2089 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2090 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2091
2092 /* 8168E family. */
2093 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2094 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2095 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2096
2097 /* 8168D family. */
2098 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2099 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2100
2101 /* 8168DP family. */
2102 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2103 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2104 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2105
2106 /* 8168C family. */
2107 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2108 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2109 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2110 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2111 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2112 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2113 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2114
2115 /* 8168B family. */
2116 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2117 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2118 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2119
2120 /* 8101 family. */
2121 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2122 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2123 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2124 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2125 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2126 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2127 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2128 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2129 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2130 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2131 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2132 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2133 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2134 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2135 /* FIXME: where did these entries come from ? -- FR */
2136 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2137 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2138
2139 /* 8110 family. */
2140 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2141 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2142 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2143 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2144 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2145
2146 /* Catch-all */
2147 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2148 };
2149 const struct rtl_mac_info *p = mac_info;
2150 enum mac_version ver;
2151
2152 while ((xid & p->mask) != p->val)
2153 p++;
2154 ver = p->ver;
2155
2156 if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2157 if (ver == RTL_GIGA_MAC_VER_42)
2158 ver = RTL_GIGA_MAC_VER_43;
2159 else if (ver == RTL_GIGA_MAC_VER_45)
2160 ver = RTL_GIGA_MAC_VER_47;
2161 else if (ver == RTL_GIGA_MAC_VER_46)
2162 ver = RTL_GIGA_MAC_VER_48;
2163 }
2164
2165 return ver;
2166 }
2167
2168 static void rtl_release_firmware(struct rtl8169_private *tp)
2169 {
2170 if (tp->rtl_fw) {
2171 rtl_fw_release_firmware(tp->rtl_fw);
2172 kfree(tp->rtl_fw);
2173 tp->rtl_fw = NULL;
2174 }
2175 }
2176
2177 void r8169_apply_firmware(struct rtl8169_private *tp)
2178 {
2179 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2180 if (tp->rtl_fw)
2181 rtl_fw_write_firmware(tp, tp->rtl_fw);
2182 }
2183
2184 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2185 {
2186 /* Adjust EEE LED frequency */
2187 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2188 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2189
2190 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2191 }
2192
2193 static void rtl8125_config_eee_mac(struct rtl8169_private *tp)
2194 {
2195 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2196 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2197 }
2198
2199 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2200 {
2201 const u16 w[] = {
2202 addr[0] | (addr[1] << 8),
2203 addr[2] | (addr[3] << 8),
2204 addr[4] | (addr[5] << 8)
2205 };
2206
2207 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2208 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2209 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2210 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2211 }
2212
2213 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2214 {
2215 u16 data1, data2, ioffset;
2216
2217 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2218 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2219 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2220
2221 ioffset = (data2 >> 1) & 0x7ff8;
2222 ioffset |= data2 & 0x0007;
2223 if (data1 & BIT(7))
2224 ioffset |= BIT(15);
2225
2226 return ioffset;
2227 }
2228
2229 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2230 {
2231 set_bit(flag, tp->wk.flags);
2232 schedule_work(&tp->wk.work);
2233 }
2234
2235 static void rtl8169_init_phy(struct rtl8169_private *tp)
2236 {
2237 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2238
2239 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2240 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2241 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2242 /* set undocumented MAC Reg C+CR Offset 0x82h */
2243 RTL_W8(tp, 0x82, 0x01);
2244 }
2245
2246 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2247 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2248 tp->pci_dev->subsystem_device == 0xe000)
2249 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2250
2251 /* We may have called phy_speed_down before */
2252 phy_speed_up(tp->phydev);
2253
2254 if (rtl_supports_eee(tp))
2255 rtl_enable_eee(tp);
2256
2257 genphy_soft_reset(tp->phydev);
2258 }
2259
2260 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2261 {
2262 rtl_lock_work(tp);
2263
2264 rtl_unlock_config_regs(tp);
2265
2266 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
2267 rtl_pci_commit(tp);
2268
2269 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
2270 rtl_pci_commit(tp);
2271
2272 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2273 rtl_rar_exgmac_set(tp, addr);
2274
2275 rtl_lock_config_regs(tp);
2276
2277 rtl_unlock_work(tp);
2278 }
2279
2280 static int rtl_set_mac_address(struct net_device *dev, void *p)
2281 {
2282 struct rtl8169_private *tp = netdev_priv(dev);
2283 struct device *d = tp_to_dev(tp);
2284 int ret;
2285
2286 ret = eth_mac_addr(dev, p);
2287 if (ret)
2288 return ret;
2289
2290 pm_runtime_get_noresume(d);
2291
2292 if (pm_runtime_active(d))
2293 rtl_rar_set(tp, dev->dev_addr);
2294
2295 pm_runtime_put_noidle(d);
2296
2297 return 0;
2298 }
2299
2300 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
2301 {
2302 switch (tp->mac_version) {
2303 case RTL_GIGA_MAC_VER_25:
2304 case RTL_GIGA_MAC_VER_26:
2305 case RTL_GIGA_MAC_VER_29:
2306 case RTL_GIGA_MAC_VER_30:
2307 case RTL_GIGA_MAC_VER_32:
2308 case RTL_GIGA_MAC_VER_33:
2309 case RTL_GIGA_MAC_VER_34:
2310 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61:
2311 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2312 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2313 break;
2314 default:
2315 break;
2316 }
2317 }
2318
2319 static void rtl_pll_power_down(struct rtl8169_private *tp)
2320 {
2321 if (r8168_check_dash(tp))
2322 return;
2323
2324 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2325 tp->mac_version == RTL_GIGA_MAC_VER_33)
2326 rtl_ephy_write(tp, 0x19, 0xff64);
2327
2328 if (device_may_wakeup(tp_to_dev(tp))) {
2329 phy_speed_down(tp->phydev, false);
2330 rtl_wol_suspend_quirk(tp);
2331 return;
2332 }
2333
2334 switch (tp->mac_version) {
2335 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2336 case RTL_GIGA_MAC_VER_37:
2337 case RTL_GIGA_MAC_VER_39:
2338 case RTL_GIGA_MAC_VER_43:
2339 case RTL_GIGA_MAC_VER_44:
2340 case RTL_GIGA_MAC_VER_45:
2341 case RTL_GIGA_MAC_VER_46:
2342 case RTL_GIGA_MAC_VER_47:
2343 case RTL_GIGA_MAC_VER_48:
2344 case RTL_GIGA_MAC_VER_50:
2345 case RTL_GIGA_MAC_VER_51:
2346 case RTL_GIGA_MAC_VER_52:
2347 case RTL_GIGA_MAC_VER_60:
2348 case RTL_GIGA_MAC_VER_61:
2349 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2350 break;
2351 case RTL_GIGA_MAC_VER_40:
2352 case RTL_GIGA_MAC_VER_41:
2353 case RTL_GIGA_MAC_VER_49:
2354 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
2355 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2356 break;
2357 default:
2358 break;
2359 }
2360 }
2361
2362 static void rtl_pll_power_up(struct rtl8169_private *tp)
2363 {
2364 switch (tp->mac_version) {
2365 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2366 case RTL_GIGA_MAC_VER_37:
2367 case RTL_GIGA_MAC_VER_39:
2368 case RTL_GIGA_MAC_VER_43:
2369 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
2370 break;
2371 case RTL_GIGA_MAC_VER_44:
2372 case RTL_GIGA_MAC_VER_45:
2373 case RTL_GIGA_MAC_VER_46:
2374 case RTL_GIGA_MAC_VER_47:
2375 case RTL_GIGA_MAC_VER_48:
2376 case RTL_GIGA_MAC_VER_50:
2377 case RTL_GIGA_MAC_VER_51:
2378 case RTL_GIGA_MAC_VER_52:
2379 case RTL_GIGA_MAC_VER_60:
2380 case RTL_GIGA_MAC_VER_61:
2381 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2382 break;
2383 case RTL_GIGA_MAC_VER_40:
2384 case RTL_GIGA_MAC_VER_41:
2385 case RTL_GIGA_MAC_VER_49:
2386 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2387 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
2388 break;
2389 default:
2390 break;
2391 }
2392
2393 phy_resume(tp->phydev);
2394 /* give MAC/PHY some time to resume */
2395 msleep(20);
2396 }
2397
2398 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2399 {
2400 switch (tp->mac_version) {
2401 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2402 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2403 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2404 break;
2405 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2406 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2407 case RTL_GIGA_MAC_VER_38:
2408 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2409 break;
2410 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2411 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2412 break;
2413 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2414 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 |
2415 RX_DMA_BURST);
2416 break;
2417 default:
2418 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2419 break;
2420 }
2421 }
2422
2423 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2424 {
2425 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2426 }
2427
2428 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2429 {
2430 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2431 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2432 }
2433
2434 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2435 {
2436 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2437 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2438 }
2439
2440 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2441 {
2442 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2443 }
2444
2445 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2446 {
2447 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2448 }
2449
2450 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2451 {
2452 RTL_W8(tp, MaxTxPacketSize, 0x3f);
2453 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2454 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2455 }
2456
2457 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2458 {
2459 RTL_W8(tp, MaxTxPacketSize, 0x0c);
2460 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2461 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2462 }
2463
2464 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2465 {
2466 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2467 }
2468
2469 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2470 {
2471 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2472 }
2473
2474 static void rtl_jumbo_config(struct rtl8169_private *tp)
2475 {
2476 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2477
2478 rtl_unlock_config_regs(tp);
2479 switch (tp->mac_version) {
2480 case RTL_GIGA_MAC_VER_12:
2481 case RTL_GIGA_MAC_VER_17:
2482 if (jumbo) {
2483 pcie_set_readrq(tp->pci_dev, 512);
2484 r8168b_1_hw_jumbo_enable(tp);
2485 } else {
2486 r8168b_1_hw_jumbo_disable(tp);
2487 }
2488 break;
2489 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2490 if (jumbo) {
2491 pcie_set_readrq(tp->pci_dev, 512);
2492 r8168c_hw_jumbo_enable(tp);
2493 } else {
2494 r8168c_hw_jumbo_disable(tp);
2495 }
2496 break;
2497 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2498 if (jumbo)
2499 r8168dp_hw_jumbo_enable(tp);
2500 else
2501 r8168dp_hw_jumbo_disable(tp);
2502 break;
2503 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2504 if (jumbo) {
2505 pcie_set_readrq(tp->pci_dev, 512);
2506 r8168e_hw_jumbo_enable(tp);
2507 } else {
2508 r8168e_hw_jumbo_disable(tp);
2509 }
2510 break;
2511 default:
2512 break;
2513 }
2514 rtl_lock_config_regs(tp);
2515
2516 if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2517 pcie_set_readrq(tp->pci_dev, 4096);
2518 }
2519
2520 DECLARE_RTL_COND(rtl_chipcmd_cond)
2521 {
2522 return RTL_R8(tp, ChipCmd) & CmdReset;
2523 }
2524
2525 static void rtl_hw_reset(struct rtl8169_private *tp)
2526 {
2527 RTL_W8(tp, ChipCmd, CmdReset);
2528
2529 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2530 }
2531
2532 static void rtl_request_firmware(struct rtl8169_private *tp)
2533 {
2534 struct rtl_fw *rtl_fw;
2535
2536 /* firmware loaded already or no firmware available */
2537 if (tp->rtl_fw || !tp->fw_name)
2538 return;
2539
2540 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2541 if (!rtl_fw) {
2542 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
2543 return;
2544 }
2545
2546 rtl_fw->phy_write = rtl_writephy;
2547 rtl_fw->phy_read = rtl_readphy;
2548 rtl_fw->mac_mcu_write = mac_mcu_write;
2549 rtl_fw->mac_mcu_read = mac_mcu_read;
2550 rtl_fw->fw_name = tp->fw_name;
2551 rtl_fw->dev = tp_to_dev(tp);
2552
2553 if (rtl_fw_request_firmware(rtl_fw))
2554 kfree(rtl_fw);
2555 else
2556 tp->rtl_fw = rtl_fw;
2557 }
2558
2559 static void rtl_rx_close(struct rtl8169_private *tp)
2560 {
2561 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2562 }
2563
2564 DECLARE_RTL_COND(rtl_npq_cond)
2565 {
2566 return RTL_R8(tp, TxPoll) & NPQ;
2567 }
2568
2569 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2570 {
2571 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2572 }
2573
2574 static void rtl8169_hw_reset(struct rtl8169_private *tp)
2575 {
2576 /* Disable interrupts */
2577 rtl8169_irq_mask_and_ack(tp);
2578
2579 rtl_rx_close(tp);
2580
2581 switch (tp->mac_version) {
2582 case RTL_GIGA_MAC_VER_27:
2583 case RTL_GIGA_MAC_VER_28:
2584 case RTL_GIGA_MAC_VER_31:
2585 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
2586 break;
2587 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2588 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2589 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2590 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
2591 break;
2592 default:
2593 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2594 udelay(100);
2595 break;
2596 }
2597
2598 rtl_hw_reset(tp);
2599 }
2600
2601 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2602 {
2603 u32 val = TX_DMA_BURST << TxDMAShift |
2604 InterFrameGap << TxInterFrameGapShift;
2605
2606 if (rtl_is_8168evl_up(tp))
2607 val |= TXCFG_AUTO_FIFO;
2608
2609 RTL_W32(tp, TxConfig, val);
2610 }
2611
2612 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2613 {
2614 /* Low hurts. Let's disable the filtering. */
2615 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2616 }
2617
2618 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2619 {
2620 /*
2621 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2622 * register to be written before TxDescAddrLow to work.
2623 * Switching from MMIO to I/O access fixes the issue as well.
2624 */
2625 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2626 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2627 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2628 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2629 }
2630
2631 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
2632 {
2633 u32 val;
2634
2635 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2636 val = 0x000fff00;
2637 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2638 val = 0x00ffff00;
2639 else
2640 return;
2641
2642 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2643 val |= 0xff;
2644
2645 RTL_W32(tp, 0x7c, val);
2646 }
2647
2648 static void rtl_set_rx_mode(struct net_device *dev)
2649 {
2650 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2651 /* Multicast hash filter */
2652 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2653 struct rtl8169_private *tp = netdev_priv(dev);
2654 u32 tmp;
2655
2656 if (dev->flags & IFF_PROMISC) {
2657 /* Unconditionally log net taps. */
2658 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
2659 rx_mode |= AcceptAllPhys;
2660 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2661 dev->flags & IFF_ALLMULTI ||
2662 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2663 /* accept all multicasts */
2664 } else if (netdev_mc_empty(dev)) {
2665 rx_mode &= ~AcceptMulticast;
2666 } else {
2667 struct netdev_hw_addr *ha;
2668
2669 mc_filter[1] = mc_filter[0] = 0;
2670 netdev_for_each_mc_addr(ha, dev) {
2671 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2672 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2673 }
2674
2675 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2676 tmp = mc_filter[0];
2677 mc_filter[0] = swab32(mc_filter[1]);
2678 mc_filter[1] = swab32(tmp);
2679 }
2680 }
2681
2682 if (dev->features & NETIF_F_RXALL)
2683 rx_mode |= (AcceptErr | AcceptRunt);
2684
2685 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2686 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2687
2688 tmp = RTL_R32(tp, RxConfig);
2689 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
2690 }
2691
2692 DECLARE_RTL_COND(rtl_csiar_cond)
2693 {
2694 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2695 }
2696
2697 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2698 {
2699 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2700
2701 RTL_W32(tp, CSIDR, value);
2702 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2703 CSIAR_BYTE_ENABLE | func << 16);
2704
2705 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2706 }
2707
2708 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2709 {
2710 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2711
2712 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2713 CSIAR_BYTE_ENABLE);
2714
2715 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2716 RTL_R32(tp, CSIDR) : ~0;
2717 }
2718
2719 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
2720 {
2721 struct pci_dev *pdev = tp->pci_dev;
2722 u32 csi;
2723
2724 /* According to Realtek the value at config space address 0x070f
2725 * controls the L0s/L1 entrance latency. We try standard ECAM access
2726 * first and if it fails fall back to CSI.
2727 */
2728 if (pdev->cfg_size > 0x070f &&
2729 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2730 return;
2731
2732 netdev_notice_once(tp->dev,
2733 "No native access to PCI extended config space, falling back to CSI\n");
2734 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2735 rtl_csi_write(tp, 0x070c, csi | val << 24);
2736 }
2737
2738 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2739 {
2740 rtl_csi_access_enable(tp, 0x27);
2741 }
2742
2743 struct ephy_info {
2744 unsigned int offset;
2745 u16 mask;
2746 u16 bits;
2747 };
2748
2749 static void __rtl_ephy_init(struct rtl8169_private *tp,
2750 const struct ephy_info *e, int len)
2751 {
2752 u16 w;
2753
2754 while (len-- > 0) {
2755 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2756 rtl_ephy_write(tp, e->offset, w);
2757 e++;
2758 }
2759 }
2760
2761 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2762
2763 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2764 {
2765 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2766 PCI_EXP_LNKCTL_CLKREQ_EN);
2767 }
2768
2769 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2770 {
2771 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2772 PCI_EXP_LNKCTL_CLKREQ_EN);
2773 }
2774
2775 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2776 {
2777 /* work around an issue when PCI reset occurs during L2/L3 state */
2778 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2779 }
2780
2781 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2782 {
2783 /* Don't enable ASPM in the chip if OS can't control ASPM */
2784 if (enable && tp->aspm_manageable) {
2785 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2786 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2787 } else {
2788 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2789 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2790 }
2791
2792 udelay(10);
2793 }
2794
2795 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2796 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2797 {
2798 /* Usage of dynamic vs. static FIFO is controlled by bit
2799 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2800 */
2801 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2802 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2803 }
2804
2805 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2806 u8 low, u8 high)
2807 {
2808 /* FIFO thresholds for pause flow control */
2809 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2810 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2811 }
2812
2813 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2814 {
2815 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2816 }
2817
2818 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2819 {
2820 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2821
2822 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2823
2824 rtl_disable_clock_request(tp);
2825 }
2826
2827 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2828 {
2829 static const struct ephy_info e_info_8168cp[] = {
2830 { 0x01, 0, 0x0001 },
2831 { 0x02, 0x0800, 0x1000 },
2832 { 0x03, 0, 0x0042 },
2833 { 0x06, 0x0080, 0x0000 },
2834 { 0x07, 0, 0x2000 }
2835 };
2836
2837 rtl_set_def_aspm_entry_latency(tp);
2838
2839 rtl_ephy_init(tp, e_info_8168cp);
2840
2841 __rtl_hw_start_8168cp(tp);
2842 }
2843
2844 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2845 {
2846 rtl_set_def_aspm_entry_latency(tp);
2847
2848 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2849 }
2850
2851 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2852 {
2853 rtl_set_def_aspm_entry_latency(tp);
2854
2855 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2856
2857 /* Magic. */
2858 RTL_W8(tp, DBG_REG, 0x20);
2859 }
2860
2861 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2862 {
2863 static const struct ephy_info e_info_8168c_1[] = {
2864 { 0x02, 0x0800, 0x1000 },
2865 { 0x03, 0, 0x0002 },
2866 { 0x06, 0x0080, 0x0000 }
2867 };
2868
2869 rtl_set_def_aspm_entry_latency(tp);
2870
2871 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2872
2873 rtl_ephy_init(tp, e_info_8168c_1);
2874
2875 __rtl_hw_start_8168cp(tp);
2876 }
2877
2878 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2879 {
2880 static const struct ephy_info e_info_8168c_2[] = {
2881 { 0x01, 0, 0x0001 },
2882 { 0x03, 0x0400, 0x0020 }
2883 };
2884
2885 rtl_set_def_aspm_entry_latency(tp);
2886
2887 rtl_ephy_init(tp, e_info_8168c_2);
2888
2889 __rtl_hw_start_8168cp(tp);
2890 }
2891
2892 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
2893 {
2894 rtl_hw_start_8168c_2(tp);
2895 }
2896
2897 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2898 {
2899 rtl_set_def_aspm_entry_latency(tp);
2900
2901 __rtl_hw_start_8168cp(tp);
2902 }
2903
2904 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2905 {
2906 rtl_set_def_aspm_entry_latency(tp);
2907
2908 rtl_disable_clock_request(tp);
2909 }
2910
2911 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2912 {
2913 static const struct ephy_info e_info_8168d_4[] = {
2914 { 0x0b, 0x0000, 0x0048 },
2915 { 0x19, 0x0020, 0x0050 },
2916 { 0x0c, 0x0100, 0x0020 },
2917 { 0x10, 0x0004, 0x0000 },
2918 };
2919
2920 rtl_set_def_aspm_entry_latency(tp);
2921
2922 rtl_ephy_init(tp, e_info_8168d_4);
2923
2924 rtl_enable_clock_request(tp);
2925 }
2926
2927 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2928 {
2929 static const struct ephy_info e_info_8168e_1[] = {
2930 { 0x00, 0x0200, 0x0100 },
2931 { 0x00, 0x0000, 0x0004 },
2932 { 0x06, 0x0002, 0x0001 },
2933 { 0x06, 0x0000, 0x0030 },
2934 { 0x07, 0x0000, 0x2000 },
2935 { 0x00, 0x0000, 0x0020 },
2936 { 0x03, 0x5800, 0x2000 },
2937 { 0x03, 0x0000, 0x0001 },
2938 { 0x01, 0x0800, 0x1000 },
2939 { 0x07, 0x0000, 0x4000 },
2940 { 0x1e, 0x0000, 0x2000 },
2941 { 0x19, 0xffff, 0xfe6c },
2942 { 0x0a, 0x0000, 0x0040 }
2943 };
2944
2945 rtl_set_def_aspm_entry_latency(tp);
2946
2947 rtl_ephy_init(tp, e_info_8168e_1);
2948
2949 rtl_disable_clock_request(tp);
2950
2951 /* Reset tx FIFO pointer */
2952 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2953 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2954
2955 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2956 }
2957
2958 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2959 {
2960 static const struct ephy_info e_info_8168e_2[] = {
2961 { 0x09, 0x0000, 0x0080 },
2962 { 0x19, 0x0000, 0x0224 },
2963 { 0x00, 0x0000, 0x0004 },
2964 { 0x0c, 0x3df0, 0x0200 },
2965 };
2966
2967 rtl_set_def_aspm_entry_latency(tp);
2968
2969 rtl_ephy_init(tp, e_info_8168e_2);
2970
2971 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2972 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2973 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2974 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2975 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2976 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
2977 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
2978
2979 rtl_disable_clock_request(tp);
2980
2981 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2982
2983 rtl8168_config_eee_mac(tp);
2984
2985 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2986 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2987 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2988
2989 rtl_hw_aspm_clkreq_enable(tp, true);
2990 }
2991
2992 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2993 {
2994 rtl_set_def_aspm_entry_latency(tp);
2995
2996 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2997 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2998 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2999 rtl_reset_packet_filter(tp);
3000 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
3001 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
3002 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3003 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
3004
3005 rtl_disable_clock_request(tp);
3006
3007 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3008 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3009 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3010 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
3011
3012 rtl8168_config_eee_mac(tp);
3013 }
3014
3015 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3016 {
3017 static const struct ephy_info e_info_8168f_1[] = {
3018 { 0x06, 0x00c0, 0x0020 },
3019 { 0x08, 0x0001, 0x0002 },
3020 { 0x09, 0x0000, 0x0080 },
3021 { 0x19, 0x0000, 0x0224 },
3022 { 0x00, 0x0000, 0x0004 },
3023 { 0x0c, 0x3df0, 0x0200 },
3024 };
3025
3026 rtl_hw_start_8168f(tp);
3027
3028 rtl_ephy_init(tp, e_info_8168f_1);
3029
3030 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
3031 }
3032
3033 static void rtl_hw_start_8411(struct rtl8169_private *tp)
3034 {
3035 static const struct ephy_info e_info_8168f_1[] = {
3036 { 0x06, 0x00c0, 0x0020 },
3037 { 0x0f, 0xffff, 0x5200 },
3038 { 0x19, 0x0000, 0x0224 },
3039 { 0x00, 0x0000, 0x0004 },
3040 { 0x0c, 0x3df0, 0x0200 },
3041 };
3042
3043 rtl_hw_start_8168f(tp);
3044 rtl_pcie_state_l2l3_disable(tp);
3045
3046 rtl_ephy_init(tp, e_info_8168f_1);
3047
3048 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
3049 }
3050
3051 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3052 {
3053 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3054 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3055
3056 rtl_set_def_aspm_entry_latency(tp);
3057
3058 rtl_reset_packet_filter(tp);
3059 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
3060
3061 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3062
3063 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3064 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3065
3066 rtl8168_config_eee_mac(tp);
3067
3068 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
3069 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
3070
3071 rtl_pcie_state_l2l3_disable(tp);
3072 }
3073
3074 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3075 {
3076 static const struct ephy_info e_info_8168g_1[] = {
3077 { 0x00, 0x0008, 0x0000 },
3078 { 0x0c, 0x3ff0, 0x0820 },
3079 { 0x1e, 0x0000, 0x0001 },
3080 { 0x19, 0x8000, 0x0000 }
3081 };
3082
3083 rtl_hw_start_8168g(tp);
3084
3085 /* disable aspm and clock request before access ephy */
3086 rtl_hw_aspm_clkreq_enable(tp, false);
3087 rtl_ephy_init(tp, e_info_8168g_1);
3088 rtl_hw_aspm_clkreq_enable(tp, true);
3089 }
3090
3091 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3092 {
3093 static const struct ephy_info e_info_8168g_2[] = {
3094 { 0x00, 0x0008, 0x0000 },
3095 { 0x0c, 0x3ff0, 0x0820 },
3096 { 0x19, 0xffff, 0x7c00 },
3097 { 0x1e, 0xffff, 0x20eb },
3098 { 0x0d, 0xffff, 0x1666 },
3099 { 0x00, 0xffff, 0x10a3 },
3100 { 0x06, 0xffff, 0xf050 },
3101 { 0x04, 0x0000, 0x0010 },
3102 { 0x1d, 0x4000, 0x0000 },
3103 };
3104
3105 rtl_hw_start_8168g(tp);
3106
3107 /* disable aspm and clock request before access ephy */
3108 rtl_hw_aspm_clkreq_enable(tp, false);
3109 rtl_ephy_init(tp, e_info_8168g_2);
3110 }
3111
3112 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3113 {
3114 static const struct ephy_info e_info_8411_2[] = {
3115 { 0x00, 0x0008, 0x0000 },
3116 { 0x0c, 0x37d0, 0x0820 },
3117 { 0x1e, 0x0000, 0x0001 },
3118 { 0x19, 0x8021, 0x0000 },
3119 { 0x1e, 0x0000, 0x2000 },
3120 { 0x0d, 0x0100, 0x0200 },
3121 { 0x00, 0x0000, 0x0080 },
3122 { 0x06, 0x0000, 0x0010 },
3123 { 0x04, 0x0000, 0x0010 },
3124 { 0x1d, 0x0000, 0x4000 },
3125 };
3126
3127 rtl_hw_start_8168g(tp);
3128
3129 /* disable aspm and clock request before access ephy */
3130 rtl_hw_aspm_clkreq_enable(tp, false);
3131 rtl_ephy_init(tp, e_info_8411_2);
3132
3133 /* The following Realtek-provided magic fixes an issue with the RX unit
3134 * getting confused after the PHY having been powered-down.
3135 */
3136 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3137 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3138 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3139 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3140 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3141 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3142 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3143 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3144 mdelay(3);
3145 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3146
3147 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3148 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3149 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3150 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3151 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3152 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3153 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3154 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3155 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3156 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3157 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3158 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3159 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3160 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3161 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3162 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3163 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3164 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3165 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3166 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3167 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3168 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3169 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3170 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3171 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3172 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3173 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3174 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3175 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3176 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3177 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3178 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3179 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3180 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3181 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3182 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3183 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3184 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3185 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3186 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3187 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3188 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3189 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3190 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3191 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3192 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3193 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3194 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3195 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3196 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3197 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3198 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3199 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3200 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3201 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3202 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3203 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3204 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3205 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3206 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3207 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3208 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3209 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3210 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3211 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3212 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3213 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3214 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3215 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3216 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3217 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3218 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3219 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3220 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3221 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3222 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3223 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3224 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3225 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3226 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3227 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3228 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3229 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3230 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3231 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3232 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3233 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3234 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3235 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3236 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3237 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3238 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3239 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3240 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3241 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3242 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3243 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3244 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3245 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3246 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3247 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3248 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3249 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3250 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3251 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3252 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3253 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3254 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3255 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3256 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3257 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3258
3259 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3260
3261 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3262 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3263 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3264 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3265 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3266 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3267 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3268
3269 rtl_hw_aspm_clkreq_enable(tp, true);
3270 }
3271
3272 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3273 {
3274 static const struct ephy_info e_info_8168h_1[] = {
3275 { 0x1e, 0x0800, 0x0001 },
3276 { 0x1d, 0x0000, 0x0800 },
3277 { 0x05, 0xffff, 0x2089 },
3278 { 0x06, 0xffff, 0x5881 },
3279 { 0x04, 0xffff, 0x854a },
3280 { 0x01, 0xffff, 0x068b }
3281 };
3282 int rg_saw_cnt;
3283
3284 /* disable aspm and clock request before access ephy */
3285 rtl_hw_aspm_clkreq_enable(tp, false);
3286 rtl_ephy_init(tp, e_info_8168h_1);
3287
3288 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3289 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3290
3291 rtl_set_def_aspm_entry_latency(tp);
3292
3293 rtl_reset_packet_filter(tp);
3294
3295 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
3296
3297 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
3298
3299 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3300
3301 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3302
3303 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3304 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3305
3306 rtl8168_config_eee_mac(tp);
3307
3308 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3309 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3310
3311 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3312
3313 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
3314
3315 rtl_pcie_state_l2l3_disable(tp);
3316
3317 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3318 if (rg_saw_cnt > 0) {
3319 u16 sw_cnt_1ms_ini;
3320
3321 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3322 sw_cnt_1ms_ini &= 0x0fff;
3323 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3324 }
3325
3326 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3327 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3328 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3329 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3330
3331 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3332 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3333 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3334 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3335
3336 rtl_hw_aspm_clkreq_enable(tp, true);
3337 }
3338
3339 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3340 {
3341 rtl8168ep_stop_cmac(tp);
3342
3343 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3344 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3345
3346 rtl_set_def_aspm_entry_latency(tp);
3347
3348 rtl_reset_packet_filter(tp);
3349
3350 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
3351
3352 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3353
3354 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3355
3356 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3357 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3358
3359 rtl8168_config_eee_mac(tp);
3360
3361 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
3362
3363 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3364
3365 rtl_pcie_state_l2l3_disable(tp);
3366 }
3367
3368 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3369 {
3370 static const struct ephy_info e_info_8168ep_1[] = {
3371 { 0x00, 0xffff, 0x10ab },
3372 { 0x06, 0xffff, 0xf030 },
3373 { 0x08, 0xffff, 0x2006 },
3374 { 0x0d, 0xffff, 0x1666 },
3375 { 0x0c, 0x3ff0, 0x0000 }
3376 };
3377
3378 /* disable aspm and clock request before access ephy */
3379 rtl_hw_aspm_clkreq_enable(tp, false);
3380 rtl_ephy_init(tp, e_info_8168ep_1);
3381
3382 rtl_hw_start_8168ep(tp);
3383
3384 rtl_hw_aspm_clkreq_enable(tp, true);
3385 }
3386
3387 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3388 {
3389 static const struct ephy_info e_info_8168ep_2[] = {
3390 { 0x00, 0xffff, 0x10a3 },
3391 { 0x19, 0xffff, 0xfc00 },
3392 { 0x1e, 0xffff, 0x20ea }
3393 };
3394
3395 /* disable aspm and clock request before access ephy */
3396 rtl_hw_aspm_clkreq_enable(tp, false);
3397 rtl_ephy_init(tp, e_info_8168ep_2);
3398
3399 rtl_hw_start_8168ep(tp);
3400
3401 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3402 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3403
3404 rtl_hw_aspm_clkreq_enable(tp, true);
3405 }
3406
3407 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3408 {
3409 static const struct ephy_info e_info_8168ep_3[] = {
3410 { 0x00, 0x0000, 0x0080 },
3411 { 0x0d, 0x0100, 0x0200 },
3412 { 0x19, 0x8021, 0x0000 },
3413 { 0x1e, 0x0000, 0x2000 },
3414 };
3415
3416 /* disable aspm and clock request before access ephy */
3417 rtl_hw_aspm_clkreq_enable(tp, false);
3418 rtl_ephy_init(tp, e_info_8168ep_3);
3419
3420 rtl_hw_start_8168ep(tp);
3421
3422 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3423 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3424
3425 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3426 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3427 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3428
3429 rtl_hw_aspm_clkreq_enable(tp, true);
3430 }
3431
3432 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3433 {
3434 static const struct ephy_info e_info_8117[] = {
3435 { 0x19, 0x0040, 0x1100 },
3436 { 0x59, 0x0040, 0x1100 },
3437 };
3438 int rg_saw_cnt;
3439
3440 rtl8168ep_stop_cmac(tp);
3441
3442 /* disable aspm and clock request before access ephy */
3443 rtl_hw_aspm_clkreq_enable(tp, false);
3444 rtl_ephy_init(tp, e_info_8117);
3445
3446 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3447 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3448
3449 rtl_set_def_aspm_entry_latency(tp);
3450
3451 rtl_reset_packet_filter(tp);
3452
3453 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f90);
3454
3455 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3456
3457 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3458
3459 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3460 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3461
3462 rtl8168_config_eee_mac(tp);
3463
3464 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3465 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3466
3467 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3468
3469 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
3470
3471 rtl_pcie_state_l2l3_disable(tp);
3472
3473 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3474 if (rg_saw_cnt > 0) {
3475 u16 sw_cnt_1ms_ini;
3476
3477 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3478 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3479 }
3480
3481 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3482 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3483 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3484 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3485
3486 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3487 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3488 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3489 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3490
3491 /* firmware is for MAC only */
3492 r8169_apply_firmware(tp);
3493
3494 rtl_hw_aspm_clkreq_enable(tp, true);
3495 }
3496
3497 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3498 {
3499 static const struct ephy_info e_info_8102e_1[] = {
3500 { 0x01, 0, 0x6e65 },
3501 { 0x02, 0, 0x091f },
3502 { 0x03, 0, 0xc2f9 },
3503 { 0x06, 0, 0xafb5 },
3504 { 0x07, 0, 0x0e00 },
3505 { 0x19, 0, 0xec80 },
3506 { 0x01, 0, 0x2e65 },
3507 { 0x01, 0, 0x6e65 }
3508 };
3509 u8 cfg1;
3510
3511 rtl_set_def_aspm_entry_latency(tp);
3512
3513 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3514
3515 RTL_W8(tp, Config1,
3516 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3517 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3518
3519 cfg1 = RTL_R8(tp, Config1);
3520 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3521 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3522
3523 rtl_ephy_init(tp, e_info_8102e_1);
3524 }
3525
3526 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3527 {
3528 rtl_set_def_aspm_entry_latency(tp);
3529
3530 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3531 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3532 }
3533
3534 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3535 {
3536 rtl_hw_start_8102e_2(tp);
3537
3538 rtl_ephy_write(tp, 0x03, 0xc2f9);
3539 }
3540
3541 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3542 {
3543 static const struct ephy_info e_info_8105e_1[] = {
3544 { 0x07, 0, 0x4000 },
3545 { 0x19, 0, 0x0200 },
3546 { 0x19, 0, 0x0020 },
3547 { 0x1e, 0, 0x2000 },
3548 { 0x03, 0, 0x0001 },
3549 { 0x19, 0, 0x0100 },
3550 { 0x19, 0, 0x0004 },
3551 { 0x0a, 0, 0x0020 }
3552 };
3553
3554 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3555 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3556
3557 /* Disable Early Tally Counter */
3558 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3559
3560 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3561 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3562
3563 rtl_ephy_init(tp, e_info_8105e_1);
3564
3565 rtl_pcie_state_l2l3_disable(tp);
3566 }
3567
3568 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3569 {
3570 rtl_hw_start_8105e_1(tp);
3571 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3572 }
3573
3574 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3575 {
3576 static const struct ephy_info e_info_8402[] = {
3577 { 0x19, 0xffff, 0xff64 },
3578 { 0x1e, 0, 0x4000 }
3579 };
3580
3581 rtl_set_def_aspm_entry_latency(tp);
3582
3583 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3584 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3585
3586 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3587
3588 rtl_ephy_init(tp, e_info_8402);
3589
3590 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3591 rtl_reset_packet_filter(tp);
3592 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3593 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3594 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
3595
3596 /* disable EEE */
3597 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3598
3599 rtl_pcie_state_l2l3_disable(tp);
3600 }
3601
3602 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3603 {
3604 rtl_hw_aspm_clkreq_enable(tp, false);
3605
3606 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3607 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3608
3609 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3610 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3611 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3612
3613 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3614
3615 /* disable EEE */
3616 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3617
3618 rtl_pcie_state_l2l3_disable(tp);
3619 rtl_hw_aspm_clkreq_enable(tp, true);
3620 }
3621
3622 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3623 {
3624 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3625 }
3626
3627 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3628 {
3629 rtl_pcie_state_l2l3_disable(tp);
3630
3631 RTL_W16(tp, 0x382, 0x221b);
3632 RTL_W8(tp, 0x4500, 0);
3633 RTL_W16(tp, 0x4800, 0);
3634
3635 /* disable UPS */
3636 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3637
3638 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3639
3640 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3641 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3642
3643 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3644 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3645 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3646
3647 /* disable new tx descriptor format */
3648 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3649
3650 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3651 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3652 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3653 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3654 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3655 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3656 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3657 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3658 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067);
3659 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
3660 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3661 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0);
3662 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3663 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3664 udelay(1);
3665 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3666 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3667
3668 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3669
3670 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3671
3672 rtl8125_config_eee_mac(tp);
3673
3674 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3675 udelay(10);
3676 }
3677
3678 static void rtl_hw_start_8125_1(struct rtl8169_private *tp)
3679 {
3680 static const struct ephy_info e_info_8125_1[] = {
3681 { 0x01, 0xffff, 0xa812 },
3682 { 0x09, 0xffff, 0x520c },
3683 { 0x04, 0xffff, 0xd000 },
3684 { 0x0d, 0xffff, 0xf702 },
3685 { 0x0a, 0xffff, 0x8653 },
3686 { 0x06, 0xffff, 0x001e },
3687 { 0x08, 0xffff, 0x3595 },
3688 { 0x20, 0xffff, 0x9455 },
3689 { 0x21, 0xffff, 0x99ff },
3690 { 0x02, 0xffff, 0x6046 },
3691 { 0x29, 0xffff, 0xfe00 },
3692 { 0x23, 0xffff, 0xab62 },
3693
3694 { 0x41, 0xffff, 0xa80c },
3695 { 0x49, 0xffff, 0x520c },
3696 { 0x44, 0xffff, 0xd000 },
3697 { 0x4d, 0xffff, 0xf702 },
3698 { 0x4a, 0xffff, 0x8653 },
3699 { 0x46, 0xffff, 0x001e },
3700 { 0x48, 0xffff, 0x3595 },
3701 { 0x60, 0xffff, 0x9455 },
3702 { 0x61, 0xffff, 0x99ff },
3703 { 0x42, 0xffff, 0x6046 },
3704 { 0x69, 0xffff, 0xfe00 },
3705 { 0x63, 0xffff, 0xab62 },
3706 };
3707
3708 rtl_set_def_aspm_entry_latency(tp);
3709
3710 /* disable aspm and clock request before access ephy */
3711 rtl_hw_aspm_clkreq_enable(tp, false);
3712 rtl_ephy_init(tp, e_info_8125_1);
3713
3714 rtl_hw_start_8125_common(tp);
3715 }
3716
3717 static void rtl_hw_start_8125_2(struct rtl8169_private *tp)
3718 {
3719 static const struct ephy_info e_info_8125_2[] = {
3720 { 0x04, 0xffff, 0xd000 },
3721 { 0x0a, 0xffff, 0x8653 },
3722 { 0x23, 0xffff, 0xab66 },
3723 { 0x20, 0xffff, 0x9455 },
3724 { 0x21, 0xffff, 0x99ff },
3725 { 0x29, 0xffff, 0xfe04 },
3726
3727 { 0x44, 0xffff, 0xd000 },
3728 { 0x4a, 0xffff, 0x8653 },
3729 { 0x63, 0xffff, 0xab66 },
3730 { 0x60, 0xffff, 0x9455 },
3731 { 0x61, 0xffff, 0x99ff },
3732 { 0x69, 0xffff, 0xfe04 },
3733 };
3734
3735 rtl_set_def_aspm_entry_latency(tp);
3736
3737 /* disable aspm and clock request before access ephy */
3738 rtl_hw_aspm_clkreq_enable(tp, false);
3739 rtl_ephy_init(tp, e_info_8125_2);
3740
3741 rtl_hw_start_8125_common(tp);
3742 }
3743
3744 static void rtl_hw_config(struct rtl8169_private *tp)
3745 {
3746 static const rtl_generic_fct hw_configs[] = {
3747 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3748 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3749 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3750 [RTL_GIGA_MAC_VER_10] = NULL,
3751 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3752 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3753 [RTL_GIGA_MAC_VER_13] = NULL,
3754 [RTL_GIGA_MAC_VER_14] = NULL,
3755 [RTL_GIGA_MAC_VER_15] = NULL,
3756 [RTL_GIGA_MAC_VER_16] = NULL,
3757 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3758 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3759 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3760 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3761 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
3762 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3763 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3764 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3765 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3766 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3767 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
3768 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3769 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3770 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3771 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3772 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3773 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3774 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3775 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3776 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3777 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3778 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3779 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3780 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3781 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3782 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3783 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3784 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3785 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3786 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3787 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3788 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3789 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3790 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3791 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3792 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3793 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1,
3794 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2,
3795 };
3796
3797 if (hw_configs[tp->mac_version])
3798 hw_configs[tp->mac_version](tp);
3799 }
3800
3801 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3802 {
3803 int i;
3804
3805 /* disable interrupt coalescing */
3806 for (i = 0xa00; i < 0xb00; i += 4)
3807 RTL_W32(tp, i, 0);
3808
3809 rtl_hw_config(tp);
3810 }
3811
3812 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3813 {
3814 if (rtl_is_8168evl_up(tp))
3815 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3816 else
3817 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3818
3819 rtl_hw_config(tp);
3820
3821 /* disable interrupt coalescing */
3822 RTL_W16(tp, IntrMitigate, 0x0000);
3823 }
3824
3825 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3826 {
3827 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3828
3829 tp->cp_cmd |= PCIMulRW;
3830
3831 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3832 tp->mac_version == RTL_GIGA_MAC_VER_03)
3833 tp->cp_cmd |= EnAnaPLL;
3834
3835 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3836
3837 rtl8169_set_magic_reg(tp, tp->mac_version);
3838
3839 /* disable interrupt coalescing */
3840 RTL_W16(tp, IntrMitigate, 0x0000);
3841 }
3842
3843 static void rtl_hw_start(struct rtl8169_private *tp)
3844 {
3845 rtl_unlock_config_regs(tp);
3846
3847 tp->cp_cmd &= CPCMD_MASK;
3848 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3849
3850 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3851 rtl_hw_start_8169(tp);
3852 else if (rtl_is_8125(tp))
3853 rtl_hw_start_8125(tp);
3854 else
3855 rtl_hw_start_8168(tp);
3856
3857 rtl_set_rx_max_size(tp);
3858 rtl_set_rx_tx_desc_registers(tp);
3859 rtl_lock_config_regs(tp);
3860
3861 rtl_jumbo_config(tp);
3862
3863 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3864 rtl_pci_commit(tp);
3865
3866 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3867 rtl_init_rxcfg(tp);
3868 rtl_set_tx_config_registers(tp);
3869 rtl_set_rx_mode(tp->dev);
3870 rtl_irq_enable(tp);
3871 }
3872
3873 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3874 {
3875 struct rtl8169_private *tp = netdev_priv(dev);
3876
3877 dev->mtu = new_mtu;
3878 netdev_update_features(dev);
3879 rtl_jumbo_config(tp);
3880
3881 return 0;
3882 }
3883
3884 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3885 {
3886 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3887 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3888 }
3889
3890 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
3891 {
3892 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3893
3894 desc->opts2 = 0;
3895 /* Force memory writes to complete before releasing descriptor */
3896 dma_wmb();
3897
3898 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
3899 }
3900
3901 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3902 struct RxDesc *desc)
3903 {
3904 struct device *d = tp_to_dev(tp);
3905 int node = dev_to_node(d);
3906 dma_addr_t mapping;
3907 struct page *data;
3908
3909 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3910 if (!data)
3911 return NULL;
3912
3913 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3914 if (unlikely(dma_mapping_error(d, mapping))) {
3915 if (net_ratelimit())
3916 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3917 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3918 return NULL;
3919 }
3920
3921 desc->addr = cpu_to_le64(mapping);
3922 rtl8169_mark_to_asic(desc);
3923
3924 return data;
3925 }
3926
3927 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3928 {
3929 unsigned int i;
3930
3931 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3932 dma_unmap_page(tp_to_dev(tp),
3933 le64_to_cpu(tp->RxDescArray[i].addr),
3934 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3935 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3936 tp->Rx_databuff[i] = NULL;
3937 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
3938 }
3939 }
3940
3941 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3942 {
3943 desc->opts1 |= cpu_to_le32(RingEnd);
3944 }
3945
3946 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3947 {
3948 unsigned int i;
3949
3950 for (i = 0; i < NUM_RX_DESC; i++) {
3951 struct page *data;
3952
3953 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3954 if (!data) {
3955 rtl8169_rx_clear(tp);
3956 return -ENOMEM;
3957 }
3958 tp->Rx_databuff[i] = data;
3959 }
3960
3961 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3962
3963 return 0;
3964 }
3965
3966 static int rtl8169_init_ring(struct rtl8169_private *tp)
3967 {
3968 rtl8169_init_ring_indexes(tp);
3969
3970 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3971 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3972
3973 return rtl8169_rx_fill(tp);
3974 }
3975
3976 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3977 {
3978 struct ring_info *tx_skb = tp->tx_skb + entry;
3979 struct TxDesc *desc = tp->TxDescArray + entry;
3980
3981 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3982 DMA_TO_DEVICE);
3983 memset(desc, 0, sizeof(*desc));
3984 memset(tx_skb, 0, sizeof(*tx_skb));
3985 }
3986
3987 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3988 unsigned int n)
3989 {
3990 unsigned int i;
3991
3992 for (i = 0; i < n; i++) {
3993 unsigned int entry = (start + i) % NUM_TX_DESC;
3994 struct ring_info *tx_skb = tp->tx_skb + entry;
3995 unsigned int len = tx_skb->len;
3996
3997 if (len) {
3998 struct sk_buff *skb = tx_skb->skb;
3999
4000 rtl8169_unmap_tx_skb(tp, entry);
4001 if (skb)
4002 dev_consume_skb_any(skb);
4003 }
4004 }
4005 }
4006
4007 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4008 {
4009 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4010 tp->cur_tx = tp->dirty_tx = 0;
4011 netdev_reset_queue(tp->dev);
4012 }
4013
4014 static void rtl_reset_work(struct rtl8169_private *tp)
4015 {
4016 struct net_device *dev = tp->dev;
4017 int i;
4018
4019 napi_disable(&tp->napi);
4020 netif_stop_queue(dev);
4021 synchronize_rcu();
4022
4023 rtl8169_hw_reset(tp);
4024
4025 for (i = 0; i < NUM_RX_DESC; i++)
4026 rtl8169_mark_to_asic(tp->RxDescArray + i);
4027
4028 rtl8169_tx_clear(tp);
4029 rtl8169_init_ring_indexes(tp);
4030
4031 napi_enable(&tp->napi);
4032 rtl_hw_start(tp);
4033 netif_wake_queue(dev);
4034 }
4035
4036 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4037 {
4038 struct rtl8169_private *tp = netdev_priv(dev);
4039
4040 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4041 }
4042
4043 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4044 void *addr, unsigned int entry, bool desc_own)
4045 {
4046 struct TxDesc *txd = tp->TxDescArray + entry;
4047 struct device *d = tp_to_dev(tp);
4048 dma_addr_t mapping;
4049 u32 opts1;
4050 int ret;
4051
4052 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4053 ret = dma_mapping_error(d, mapping);
4054 if (unlikely(ret)) {
4055 if (net_ratelimit())
4056 netif_err(tp, drv, tp->dev, "Failed to map TX data!\n");
4057 return ret;
4058 }
4059
4060 txd->addr = cpu_to_le64(mapping);
4061 txd->opts2 = cpu_to_le32(opts[1]);
4062
4063 opts1 = opts[0] | len;
4064 if (entry == NUM_TX_DESC - 1)
4065 opts1 |= RingEnd;
4066 if (desc_own)
4067 opts1 |= DescOwn;
4068 txd->opts1 = cpu_to_le32(opts1);
4069
4070 tp->tx_skb[entry].len = len;
4071
4072 return 0;
4073 }
4074
4075 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4076 const u32 *opts, unsigned int entry)
4077 {
4078 struct skb_shared_info *info = skb_shinfo(skb);
4079 unsigned int cur_frag;
4080
4081 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4082 const skb_frag_t *frag = info->frags + cur_frag;
4083 void *addr = skb_frag_address(frag);
4084 u32 len = skb_frag_size(frag);
4085
4086 entry = (entry + 1) % NUM_TX_DESC;
4087
4088 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4089 goto err_out;
4090 }
4091
4092 return 0;
4093
4094 err_out:
4095 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4096 return -EIO;
4097 }
4098
4099 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
4100 {
4101 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
4102 }
4103
4104 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4105 {
4106 u32 mss = skb_shinfo(skb)->gso_size;
4107
4108 if (mss) {
4109 opts[0] |= TD_LSO;
4110 opts[0] |= mss << TD0_MSS_SHIFT;
4111 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4112 const struct iphdr *ip = ip_hdr(skb);
4113
4114 if (ip->protocol == IPPROTO_TCP)
4115 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4116 else if (ip->protocol == IPPROTO_UDP)
4117 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4118 else
4119 WARN_ON_ONCE(1);
4120 }
4121 }
4122
4123 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4124 struct sk_buff *skb, u32 *opts)
4125 {
4126 u32 transport_offset = (u32)skb_transport_offset(skb);
4127 u32 mss = skb_shinfo(skb)->gso_size;
4128
4129 if (mss) {
4130 switch (vlan_get_protocol(skb)) {
4131 case htons(ETH_P_IP):
4132 opts[0] |= TD1_GTSENV4;
4133 break;
4134
4135 case htons(ETH_P_IPV6):
4136 if (skb_cow_head(skb, 0))
4137 return false;
4138
4139 tcp_v6_gso_csum_prep(skb);
4140 opts[0] |= TD1_GTSENV6;
4141 break;
4142
4143 default:
4144 WARN_ON_ONCE(1);
4145 break;
4146 }
4147
4148 opts[0] |= transport_offset << GTTCPHO_SHIFT;
4149 opts[1] |= mss << TD1_MSS_SHIFT;
4150 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4151 u8 ip_protocol;
4152
4153 switch (vlan_get_protocol(skb)) {
4154 case htons(ETH_P_IP):
4155 opts[1] |= TD1_IPv4_CS;
4156 ip_protocol = ip_hdr(skb)->protocol;
4157 break;
4158
4159 case htons(ETH_P_IPV6):
4160 opts[1] |= TD1_IPv6_CS;
4161 ip_protocol = ipv6_hdr(skb)->nexthdr;
4162 break;
4163
4164 default:
4165 ip_protocol = IPPROTO_RAW;
4166 break;
4167 }
4168
4169 if (ip_protocol == IPPROTO_TCP)
4170 opts[1] |= TD1_TCP_CS;
4171 else if (ip_protocol == IPPROTO_UDP)
4172 opts[1] |= TD1_UDP_CS;
4173 else
4174 WARN_ON_ONCE(1);
4175
4176 opts[1] |= transport_offset << TCPHO_SHIFT;
4177 } else {
4178 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
4179 return !eth_skb_pad(skb);
4180 }
4181
4182 return true;
4183 }
4184
4185 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
4186 unsigned int nr_frags)
4187 {
4188 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
4189
4190 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4191 return slots_avail > nr_frags;
4192 }
4193
4194 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4195 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4196 {
4197 switch (tp->mac_version) {
4198 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4199 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4200 return false;
4201 default:
4202 return true;
4203 }
4204 }
4205
4206 static void rtl8169_doorbell(struct rtl8169_private *tp)
4207 {
4208 if (rtl_is_8125(tp))
4209 RTL_W16(tp, TxPoll_8125, BIT(0));
4210 else
4211 RTL_W8(tp, TxPoll, NPQ);
4212 }
4213
4214 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4215 struct net_device *dev)
4216 {
4217 unsigned int frags = skb_shinfo(skb)->nr_frags;
4218 struct rtl8169_private *tp = netdev_priv(dev);
4219 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4220 struct TxDesc *txd_first, *txd_last;
4221 bool stop_queue, door_bell;
4222 u32 opts[2];
4223
4224 txd_first = tp->TxDescArray + entry;
4225
4226 if (unlikely(!rtl_tx_slots_avail(tp, frags))) {
4227 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4228 goto err_stop_0;
4229 }
4230
4231 if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn))
4232 goto err_stop_0;
4233
4234 opts[1] = rtl8169_tx_vlan_tag(skb);
4235 opts[0] = 0;
4236
4237 if (!rtl_chip_supports_csum_v2(tp))
4238 rtl8169_tso_csum_v1(skb, opts);
4239 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4240 goto err_dma_0;
4241
4242 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4243 entry, false)))
4244 goto err_dma_0;
4245
4246 if (frags) {
4247 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4248 goto err_dma_1;
4249 entry = (entry + frags) % NUM_TX_DESC;
4250 }
4251
4252 txd_last = tp->TxDescArray + entry;
4253 txd_last->opts1 |= cpu_to_le32(LastFrag);
4254 tp->tx_skb[entry].skb = skb;
4255
4256 skb_tx_timestamp(skb);
4257
4258 /* Force memory writes to complete before releasing descriptor */
4259 dma_wmb();
4260
4261 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4262
4263 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4264
4265 /* Force all memory writes to complete before notifying device */
4266 wmb();
4267
4268 tp->cur_tx += frags + 1;
4269
4270 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
4271 if (unlikely(stop_queue)) {
4272 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4273 * not miss a ring update when it notices a stopped queue.
4274 */
4275 smp_wmb();
4276 netif_stop_queue(dev);
4277 door_bell = true;
4278 }
4279
4280 if (door_bell)
4281 rtl8169_doorbell(tp);
4282
4283 if (unlikely(stop_queue)) {
4284 /* Sync with rtl_tx:
4285 * - publish queue status and cur_tx ring index (write barrier)
4286 * - refresh dirty_tx ring index (read barrier).
4287 * May the current thread have a pessimistic view of the ring
4288 * status and forget to wake up queue, a racing rtl_tx thread
4289 * can't.
4290 */
4291 smp_mb();
4292 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
4293 netif_start_queue(dev);
4294 }
4295
4296 return NETDEV_TX_OK;
4297
4298 err_dma_1:
4299 rtl8169_unmap_tx_skb(tp, entry);
4300 err_dma_0:
4301 dev_kfree_skb_any(skb);
4302 dev->stats.tx_dropped++;
4303 return NETDEV_TX_OK;
4304
4305 err_stop_0:
4306 netif_stop_queue(dev);
4307 dev->stats.tx_dropped++;
4308 return NETDEV_TX_BUSY;
4309 }
4310
4311 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4312 struct net_device *dev,
4313 netdev_features_t features)
4314 {
4315 int transport_offset = skb_transport_offset(skb);
4316 struct rtl8169_private *tp = netdev_priv(dev);
4317
4318 if (skb_is_gso(skb)) {
4319 if (transport_offset > GTTCPHO_MAX &&
4320 rtl_chip_supports_csum_v2(tp))
4321 features &= ~NETIF_F_ALL_TSO;
4322 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4323 if (skb->len < ETH_ZLEN) {
4324 switch (tp->mac_version) {
4325 case RTL_GIGA_MAC_VER_11:
4326 case RTL_GIGA_MAC_VER_12:
4327 case RTL_GIGA_MAC_VER_17:
4328 case RTL_GIGA_MAC_VER_34:
4329 features &= ~NETIF_F_CSUM_MASK;
4330 break;
4331 default:
4332 break;
4333 }
4334 }
4335
4336 if (transport_offset > TCPHO_MAX &&
4337 rtl_chip_supports_csum_v2(tp))
4338 features &= ~NETIF_F_CSUM_MASK;
4339 }
4340
4341 return vlan_features_check(skb, features);
4342 }
4343
4344 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4345 {
4346 struct rtl8169_private *tp = netdev_priv(dev);
4347 struct pci_dev *pdev = tp->pci_dev;
4348 int pci_status_errs;
4349 u16 pci_cmd;
4350
4351 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4352
4353 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4354
4355 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4356 pci_cmd, pci_status_errs);
4357
4358 /*
4359 * The recovery sequence below admits a very elaborated explanation:
4360 * - it seems to work;
4361 * - I did not see what else could be done;
4362 * - it makes iop3xx happy.
4363 *
4364 * Feel free to adjust to your needs.
4365 */
4366 if (pdev->broken_parity_status)
4367 pci_cmd &= ~PCI_COMMAND_PARITY;
4368 else
4369 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4370
4371 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4372
4373 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4374 }
4375
4376 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4377 int budget)
4378 {
4379 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
4380
4381 dirty_tx = tp->dirty_tx;
4382 smp_rmb();
4383
4384 for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) {
4385 unsigned int entry = dirty_tx % NUM_TX_DESC;
4386 struct sk_buff *skb = tp->tx_skb[entry].skb;
4387 u32 status;
4388
4389 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4390 if (status & DescOwn)
4391 break;
4392
4393 rtl8169_unmap_tx_skb(tp, entry);
4394
4395 if (skb) {
4396 pkts_compl++;
4397 bytes_compl += skb->len;
4398 napi_consume_skb(skb, budget);
4399 }
4400 dirty_tx++;
4401 }
4402
4403 if (tp->dirty_tx != dirty_tx) {
4404 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4405
4406 u64_stats_update_begin(&tp->tx_stats.syncp);
4407 tp->tx_stats.packets += pkts_compl;
4408 tp->tx_stats.bytes += bytes_compl;
4409 u64_stats_update_end(&tp->tx_stats.syncp);
4410
4411 tp->dirty_tx = dirty_tx;
4412 /* Sync with rtl8169_start_xmit:
4413 * - publish dirty_tx ring index (write barrier)
4414 * - refresh cur_tx ring index and queue status (read barrier)
4415 * May the current thread miss the stopped queue condition,
4416 * a racing xmit thread can only have a right view of the
4417 * ring status.
4418 */
4419 smp_mb();
4420 if (netif_queue_stopped(dev) &&
4421 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
4422 netif_wake_queue(dev);
4423 }
4424 /*
4425 * 8168 hack: TxPoll requests are lost when the Tx packets are
4426 * too close. Let's kick an extra TxPoll request when a burst
4427 * of start_xmit activity is detected (if it is not detected,
4428 * it is slow enough). -- FR
4429 */
4430 if (tp->cur_tx != dirty_tx)
4431 rtl8169_doorbell(tp);
4432 }
4433 }
4434
4435 static inline int rtl8169_fragmented_frame(u32 status)
4436 {
4437 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4438 }
4439
4440 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4441 {
4442 u32 status = opts1 & RxProtoMask;
4443
4444 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4445 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4446 skb->ip_summed = CHECKSUM_UNNECESSARY;
4447 else
4448 skb_checksum_none_assert(skb);
4449 }
4450
4451 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
4452 {
4453 unsigned int cur_rx, rx_left;
4454 unsigned int count;
4455
4456 cur_rx = tp->cur_rx;
4457
4458 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
4459 unsigned int entry = cur_rx % NUM_RX_DESC;
4460 const void *rx_buf = page_address(tp->Rx_databuff[entry]);
4461 struct RxDesc *desc = tp->RxDescArray + entry;
4462 u32 status;
4463
4464 status = le32_to_cpu(desc->opts1);
4465 if (status & DescOwn)
4466 break;
4467
4468 /* This barrier is needed to keep us from reading
4469 * any other fields out of the Rx descriptor until
4470 * we know the status of DescOwn
4471 */
4472 dma_rmb();
4473
4474 if (unlikely(status & RxRES)) {
4475 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4476 status);
4477 dev->stats.rx_errors++;
4478 if (status & (RxRWT | RxRUNT))
4479 dev->stats.rx_length_errors++;
4480 if (status & RxCRC)
4481 dev->stats.rx_crc_errors++;
4482 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
4483 dev->features & NETIF_F_RXALL) {
4484 goto process_pkt;
4485 }
4486 } else {
4487 unsigned int pkt_size;
4488 struct sk_buff *skb;
4489
4490 process_pkt:
4491 pkt_size = status & GENMASK(13, 0);
4492 if (likely(!(dev->features & NETIF_F_RXFCS)))
4493 pkt_size -= ETH_FCS_LEN;
4494 /*
4495 * The driver does not support incoming fragmented
4496 * frames. They are seen as a symptom of over-mtu
4497 * sized frames.
4498 */
4499 if (unlikely(rtl8169_fragmented_frame(status))) {
4500 dev->stats.rx_dropped++;
4501 dev->stats.rx_length_errors++;
4502 goto release_descriptor;
4503 }
4504
4505 skb = napi_alloc_skb(&tp->napi, pkt_size);
4506 if (unlikely(!skb)) {
4507 dev->stats.rx_dropped++;
4508 goto release_descriptor;
4509 }
4510
4511 dma_sync_single_for_cpu(tp_to_dev(tp),
4512 le64_to_cpu(desc->addr),
4513 pkt_size, DMA_FROM_DEVICE);
4514 prefetch(rx_buf);
4515 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4516 skb->tail += pkt_size;
4517 skb->len = pkt_size;
4518
4519 dma_sync_single_for_device(tp_to_dev(tp),
4520 le64_to_cpu(desc->addr),
4521 pkt_size, DMA_FROM_DEVICE);
4522
4523 rtl8169_rx_csum(skb, status);
4524 skb->protocol = eth_type_trans(skb, dev);
4525
4526 rtl8169_rx_vlan_tag(desc, skb);
4527
4528 if (skb->pkt_type == PACKET_MULTICAST)
4529 dev->stats.multicast++;
4530
4531 napi_gro_receive(&tp->napi, skb);
4532
4533 u64_stats_update_begin(&tp->rx_stats.syncp);
4534 tp->rx_stats.packets++;
4535 tp->rx_stats.bytes += pkt_size;
4536 u64_stats_update_end(&tp->rx_stats.syncp);
4537 }
4538 release_descriptor:
4539 rtl8169_mark_to_asic(desc);
4540 }
4541
4542 count = cur_rx - tp->cur_rx;
4543 tp->cur_rx = cur_rx;
4544
4545 return count;
4546 }
4547
4548 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4549 {
4550 struct rtl8169_private *tp = dev_instance;
4551 u32 status = rtl_get_events(tp);
4552
4553 if (!tp->irq_enabled || (status & 0xffff) == 0xffff ||
4554 !(status & tp->irq_mask))
4555 return IRQ_NONE;
4556
4557 if (unlikely(status & SYSErr)) {
4558 rtl8169_pcierr_interrupt(tp->dev);
4559 goto out;
4560 }
4561
4562 if (status & LinkChg)
4563 phy_mac_interrupt(tp->phydev);
4564
4565 if (unlikely(status & RxFIFOOver &&
4566 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4567 netif_stop_queue(tp->dev);
4568 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4569 }
4570
4571 rtl_irq_disable(tp);
4572 napi_schedule_irqoff(&tp->napi);
4573 out:
4574 rtl_ack_events(tp, status);
4575
4576 return IRQ_HANDLED;
4577 }
4578
4579 static void rtl_task(struct work_struct *work)
4580 {
4581 struct rtl8169_private *tp =
4582 container_of(work, struct rtl8169_private, wk.work);
4583
4584 rtl_lock_work(tp);
4585
4586 if (!netif_running(tp->dev) ||
4587 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4588 goto out_unlock;
4589
4590 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags))
4591 rtl_reset_work(tp);
4592 out_unlock:
4593 rtl_unlock_work(tp);
4594 }
4595
4596 static int rtl8169_poll(struct napi_struct *napi, int budget)
4597 {
4598 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4599 struct net_device *dev = tp->dev;
4600 int work_done;
4601
4602 work_done = rtl_rx(dev, tp, (u32) budget);
4603
4604 rtl_tx(dev, tp, budget);
4605
4606 if (work_done < budget) {
4607 napi_complete_done(napi, work_done);
4608 rtl_irq_enable(tp);
4609 }
4610
4611 return work_done;
4612 }
4613
4614 static void r8169_phylink_handler(struct net_device *ndev)
4615 {
4616 struct rtl8169_private *tp = netdev_priv(ndev);
4617
4618 if (netif_carrier_ok(ndev)) {
4619 rtl_link_chg_patch(tp);
4620 pm_request_resume(&tp->pci_dev->dev);
4621 } else {
4622 pm_runtime_idle(&tp->pci_dev->dev);
4623 }
4624
4625 if (net_ratelimit())
4626 phy_print_status(tp->phydev);
4627 }
4628
4629 static int r8169_phy_connect(struct rtl8169_private *tp)
4630 {
4631 struct phy_device *phydev = tp->phydev;
4632 phy_interface_t phy_mode;
4633 int ret;
4634
4635 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4636 PHY_INTERFACE_MODE_MII;
4637
4638 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4639 phy_mode);
4640 if (ret)
4641 return ret;
4642
4643 if (!tp->supports_gmii)
4644 phy_set_max_speed(phydev, SPEED_100);
4645
4646 phy_support_asym_pause(phydev);
4647
4648 phy_attached_info(phydev);
4649
4650 return 0;
4651 }
4652
4653 static void rtl8169_down(struct net_device *dev)
4654 {
4655 struct rtl8169_private *tp = netdev_priv(dev);
4656
4657 phy_stop(tp->phydev);
4658
4659 napi_disable(&tp->napi);
4660 netif_stop_queue(dev);
4661
4662 rtl8169_hw_reset(tp);
4663
4664 /* Give a racing hard_start_xmit a few cycles to complete. */
4665 synchronize_rcu();
4666
4667 rtl8169_tx_clear(tp);
4668
4669 rtl8169_rx_clear(tp);
4670
4671 rtl_pll_power_down(tp);
4672 }
4673
4674 static int rtl8169_close(struct net_device *dev)
4675 {
4676 struct rtl8169_private *tp = netdev_priv(dev);
4677 struct pci_dev *pdev = tp->pci_dev;
4678
4679 pm_runtime_get_sync(&pdev->dev);
4680
4681 /* Update counters before going down */
4682 rtl8169_update_counters(tp);
4683
4684 rtl_lock_work(tp);
4685 /* Clear all task flags */
4686 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4687
4688 rtl8169_down(dev);
4689 rtl_unlock_work(tp);
4690
4691 cancel_work_sync(&tp->wk.work);
4692
4693 phy_disconnect(tp->phydev);
4694
4695 pci_free_irq(pdev, 0, tp);
4696
4697 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4698 tp->RxPhyAddr);
4699 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4700 tp->TxPhyAddr);
4701 tp->TxDescArray = NULL;
4702 tp->RxDescArray = NULL;
4703
4704 pm_runtime_put_sync(&pdev->dev);
4705
4706 return 0;
4707 }
4708
4709 #ifdef CONFIG_NET_POLL_CONTROLLER
4710 static void rtl8169_netpoll(struct net_device *dev)
4711 {
4712 struct rtl8169_private *tp = netdev_priv(dev);
4713
4714 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4715 }
4716 #endif
4717
4718 static int rtl_open(struct net_device *dev)
4719 {
4720 struct rtl8169_private *tp = netdev_priv(dev);
4721 struct pci_dev *pdev = tp->pci_dev;
4722 int retval = -ENOMEM;
4723
4724 pm_runtime_get_sync(&pdev->dev);
4725
4726 /*
4727 * Rx and Tx descriptors needs 256 bytes alignment.
4728 * dma_alloc_coherent provides more.
4729 */
4730 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4731 &tp->TxPhyAddr, GFP_KERNEL);
4732 if (!tp->TxDescArray)
4733 goto err_pm_runtime_put;
4734
4735 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4736 &tp->RxPhyAddr, GFP_KERNEL);
4737 if (!tp->RxDescArray)
4738 goto err_free_tx_0;
4739
4740 retval = rtl8169_init_ring(tp);
4741 if (retval < 0)
4742 goto err_free_rx_1;
4743
4744 rtl_request_firmware(tp);
4745
4746 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
4747 dev->name);
4748 if (retval < 0)
4749 goto err_release_fw_2;
4750
4751 retval = r8169_phy_connect(tp);
4752 if (retval)
4753 goto err_free_irq;
4754
4755 rtl_lock_work(tp);
4756
4757 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4758
4759 napi_enable(&tp->napi);
4760
4761 rtl8169_init_phy(tp);
4762
4763 rtl_pll_power_up(tp);
4764
4765 rtl_hw_start(tp);
4766
4767 if (!rtl8169_init_counter_offsets(tp))
4768 netif_warn(tp, hw, dev, "counter reset/update failed\n");
4769
4770 phy_start(tp->phydev);
4771 netif_start_queue(dev);
4772
4773 rtl_unlock_work(tp);
4774
4775 pm_runtime_put_sync(&pdev->dev);
4776 out:
4777 return retval;
4778
4779 err_free_irq:
4780 pci_free_irq(pdev, 0, tp);
4781 err_release_fw_2:
4782 rtl_release_firmware(tp);
4783 rtl8169_rx_clear(tp);
4784 err_free_rx_1:
4785 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4786 tp->RxPhyAddr);
4787 tp->RxDescArray = NULL;
4788 err_free_tx_0:
4789 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4790 tp->TxPhyAddr);
4791 tp->TxDescArray = NULL;
4792 err_pm_runtime_put:
4793 pm_runtime_put_noidle(&pdev->dev);
4794 goto out;
4795 }
4796
4797 static void
4798 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4799 {
4800 struct rtl8169_private *tp = netdev_priv(dev);
4801 struct pci_dev *pdev = tp->pci_dev;
4802 struct rtl8169_counters *counters = tp->counters;
4803 unsigned int start;
4804
4805 pm_runtime_get_noresume(&pdev->dev);
4806
4807 netdev_stats_to_stats64(stats, &dev->stats);
4808
4809 do {
4810 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
4811 stats->rx_packets = tp->rx_stats.packets;
4812 stats->rx_bytes = tp->rx_stats.bytes;
4813 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
4814
4815 do {
4816 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
4817 stats->tx_packets = tp->tx_stats.packets;
4818 stats->tx_bytes = tp->tx_stats.bytes;
4819 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
4820
4821 /*
4822 * Fetch additional counter values missing in stats collected by driver
4823 * from tally counters.
4824 */
4825 if (pm_runtime_active(&pdev->dev))
4826 rtl8169_update_counters(tp);
4827
4828 /*
4829 * Subtract values fetched during initalization.
4830 * See rtl8169_init_counter_offsets for a description why we do that.
4831 */
4832 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4833 le64_to_cpu(tp->tc_offset.tx_errors);
4834 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4835 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4836 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4837 le16_to_cpu(tp->tc_offset.tx_aborted);
4838 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4839 le16_to_cpu(tp->tc_offset.rx_missed);
4840
4841 pm_runtime_put_noidle(&pdev->dev);
4842 }
4843
4844 static void rtl8169_net_suspend(struct net_device *dev)
4845 {
4846 struct rtl8169_private *tp = netdev_priv(dev);
4847
4848 if (!netif_running(dev))
4849 return;
4850
4851 phy_stop(tp->phydev);
4852 netif_device_detach(dev);
4853
4854 rtl_lock_work(tp);
4855 napi_disable(&tp->napi);
4856 /* Clear all task flags */
4857 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4858
4859 rtl_unlock_work(tp);
4860
4861 rtl_pll_power_down(tp);
4862 }
4863
4864 #ifdef CONFIG_PM
4865
4866 static int rtl8169_suspend(struct device *device)
4867 {
4868 struct net_device *dev = dev_get_drvdata(device);
4869 struct rtl8169_private *tp = netdev_priv(dev);
4870
4871 rtl8169_net_suspend(dev);
4872 clk_disable_unprepare(tp->clk);
4873
4874 return 0;
4875 }
4876
4877 static void __rtl8169_resume(struct net_device *dev)
4878 {
4879 struct rtl8169_private *tp = netdev_priv(dev);
4880
4881 netif_device_attach(dev);
4882
4883 rtl_pll_power_up(tp);
4884 rtl8169_init_phy(tp);
4885
4886 phy_start(tp->phydev);
4887
4888 rtl_lock_work(tp);
4889 napi_enable(&tp->napi);
4890 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4891 rtl_reset_work(tp);
4892 rtl_unlock_work(tp);
4893 }
4894
4895 static int rtl8169_resume(struct device *device)
4896 {
4897 struct net_device *dev = dev_get_drvdata(device);
4898 struct rtl8169_private *tp = netdev_priv(dev);
4899
4900 rtl_rar_set(tp, dev->dev_addr);
4901
4902 clk_prepare_enable(tp->clk);
4903
4904 if (netif_running(dev))
4905 __rtl8169_resume(dev);
4906
4907 return 0;
4908 }
4909
4910 static int rtl8169_runtime_suspend(struct device *device)
4911 {
4912 struct net_device *dev = dev_get_drvdata(device);
4913 struct rtl8169_private *tp = netdev_priv(dev);
4914
4915 if (!tp->TxDescArray)
4916 return 0;
4917
4918 rtl_lock_work(tp);
4919 __rtl8169_set_wol(tp, WAKE_ANY);
4920 rtl_unlock_work(tp);
4921
4922 rtl8169_net_suspend(dev);
4923
4924 /* Update counters before going runtime suspend */
4925 rtl8169_update_counters(tp);
4926
4927 return 0;
4928 }
4929
4930 static int rtl8169_runtime_resume(struct device *device)
4931 {
4932 struct net_device *dev = dev_get_drvdata(device);
4933 struct rtl8169_private *tp = netdev_priv(dev);
4934
4935 rtl_rar_set(tp, dev->dev_addr);
4936
4937 if (!tp->TxDescArray)
4938 return 0;
4939
4940 rtl_lock_work(tp);
4941 __rtl8169_set_wol(tp, tp->saved_wolopts);
4942 rtl_unlock_work(tp);
4943
4944 __rtl8169_resume(dev);
4945
4946 return 0;
4947 }
4948
4949 static int rtl8169_runtime_idle(struct device *device)
4950 {
4951 struct net_device *dev = dev_get_drvdata(device);
4952
4953 if (!netif_running(dev) || !netif_carrier_ok(dev))
4954 pm_schedule_suspend(device, 10000);
4955
4956 return -EBUSY;
4957 }
4958
4959 static const struct dev_pm_ops rtl8169_pm_ops = {
4960 .suspend = rtl8169_suspend,
4961 .resume = rtl8169_resume,
4962 .freeze = rtl8169_suspend,
4963 .thaw = rtl8169_resume,
4964 .poweroff = rtl8169_suspend,
4965 .restore = rtl8169_resume,
4966 .runtime_suspend = rtl8169_runtime_suspend,
4967 .runtime_resume = rtl8169_runtime_resume,
4968 .runtime_idle = rtl8169_runtime_idle,
4969 };
4970
4971 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4972
4973 #else /* !CONFIG_PM */
4974
4975 #define RTL8169_PM_OPS NULL
4976
4977 #endif /* !CONFIG_PM */
4978
4979 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
4980 {
4981 /* WoL fails with 8168b when the receiver is disabled. */
4982 switch (tp->mac_version) {
4983 case RTL_GIGA_MAC_VER_11:
4984 case RTL_GIGA_MAC_VER_12:
4985 case RTL_GIGA_MAC_VER_17:
4986 pci_clear_master(tp->pci_dev);
4987
4988 RTL_W8(tp, ChipCmd, CmdRxEnb);
4989 rtl_pci_commit(tp);
4990 break;
4991 default:
4992 break;
4993 }
4994 }
4995
4996 static void rtl_shutdown(struct pci_dev *pdev)
4997 {
4998 struct net_device *dev = pci_get_drvdata(pdev);
4999 struct rtl8169_private *tp = netdev_priv(dev);
5000
5001 rtl8169_net_suspend(dev);
5002
5003 /* Restore original MAC address */
5004 rtl_rar_set(tp, dev->perm_addr);
5005
5006 rtl8169_hw_reset(tp);
5007
5008 if (system_state == SYSTEM_POWER_OFF) {
5009 if (tp->saved_wolopts) {
5010 rtl_wol_suspend_quirk(tp);
5011 rtl_wol_shutdown_quirk(tp);
5012 }
5013
5014 pci_wake_from_d3(pdev, true);
5015 pci_set_power_state(pdev, PCI_D3hot);
5016 }
5017 }
5018
5019 static void rtl_remove_one(struct pci_dev *pdev)
5020 {
5021 struct net_device *dev = pci_get_drvdata(pdev);
5022 struct rtl8169_private *tp = netdev_priv(dev);
5023
5024 if (r8168_check_dash(tp))
5025 rtl8168_driver_stop(tp);
5026
5027 netif_napi_del(&tp->napi);
5028
5029 unregister_netdev(dev);
5030 mdiobus_unregister(tp->phydev->mdio.bus);
5031
5032 rtl_release_firmware(tp);
5033
5034 if (pci_dev_run_wake(pdev))
5035 pm_runtime_get_noresume(&pdev->dev);
5036
5037 /* restore original MAC address */
5038 rtl_rar_set(tp, dev->perm_addr);
5039 }
5040
5041 static const struct net_device_ops rtl_netdev_ops = {
5042 .ndo_open = rtl_open,
5043 .ndo_stop = rtl8169_close,
5044 .ndo_get_stats64 = rtl8169_get_stats64,
5045 .ndo_start_xmit = rtl8169_start_xmit,
5046 .ndo_features_check = rtl8169_features_check,
5047 .ndo_tx_timeout = rtl8169_tx_timeout,
5048 .ndo_validate_addr = eth_validate_addr,
5049 .ndo_change_mtu = rtl8169_change_mtu,
5050 .ndo_fix_features = rtl8169_fix_features,
5051 .ndo_set_features = rtl8169_set_features,
5052 .ndo_set_mac_address = rtl_set_mac_address,
5053 .ndo_do_ioctl = phy_do_ioctl_running,
5054 .ndo_set_rx_mode = rtl_set_rx_mode,
5055 #ifdef CONFIG_NET_POLL_CONTROLLER
5056 .ndo_poll_controller = rtl8169_netpoll,
5057 #endif
5058
5059 };
5060
5061 static void rtl_set_irq_mask(struct rtl8169_private *tp)
5062 {
5063 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5064
5065 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5066 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
5067 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
5068 /* special workaround needed */
5069 tp->irq_mask |= RxFIFOOver;
5070 else
5071 tp->irq_mask |= RxOverflow;
5072 }
5073
5074 static int rtl_alloc_irq(struct rtl8169_private *tp)
5075 {
5076 unsigned int flags;
5077
5078 switch (tp->mac_version) {
5079 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5080 rtl_unlock_config_regs(tp);
5081 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5082 rtl_lock_config_regs(tp);
5083 /* fall through */
5084 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5085 flags = PCI_IRQ_LEGACY;
5086 break;
5087 default:
5088 flags = PCI_IRQ_ALL_TYPES;
5089 break;
5090 }
5091
5092 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5093 }
5094
5095 static void rtl_read_mac_address(struct rtl8169_private *tp,
5096 u8 mac_addr[ETH_ALEN])
5097 {
5098 /* Get MAC address */
5099 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5100 u32 value = rtl_eri_read(tp, 0xe0);
5101
5102 mac_addr[0] = (value >> 0) & 0xff;
5103 mac_addr[1] = (value >> 8) & 0xff;
5104 mac_addr[2] = (value >> 16) & 0xff;
5105 mac_addr[3] = (value >> 24) & 0xff;
5106
5107 value = rtl_eri_read(tp, 0xe4);
5108 mac_addr[4] = (value >> 0) & 0xff;
5109 mac_addr[5] = (value >> 8) & 0xff;
5110 } else if (rtl_is_8125(tp)) {
5111 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5112 }
5113 }
5114
5115 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5116 {
5117 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5118 }
5119
5120 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
5121 {
5122 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
5123 }
5124
5125 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5126 {
5127 struct rtl8169_private *tp = mii_bus->priv;
5128
5129 if (phyaddr > 0)
5130 return -ENODEV;
5131
5132 return rtl_readphy(tp, phyreg);
5133 }
5134
5135 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5136 int phyreg, u16 val)
5137 {
5138 struct rtl8169_private *tp = mii_bus->priv;
5139
5140 if (phyaddr > 0)
5141 return -ENODEV;
5142
5143 rtl_writephy(tp, phyreg, val);
5144
5145 return 0;
5146 }
5147
5148 static int r8169_mdio_register(struct rtl8169_private *tp)
5149 {
5150 struct pci_dev *pdev = tp->pci_dev;
5151 struct mii_bus *new_bus;
5152 int ret;
5153
5154 new_bus = devm_mdiobus_alloc(&pdev->dev);
5155 if (!new_bus)
5156 return -ENOMEM;
5157
5158 new_bus->name = "r8169";
5159 new_bus->priv = tp;
5160 new_bus->parent = &pdev->dev;
5161 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
5162 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
5163
5164 new_bus->read = r8169_mdio_read_reg;
5165 new_bus->write = r8169_mdio_write_reg;
5166
5167 ret = mdiobus_register(new_bus);
5168 if (ret)
5169 return ret;
5170
5171 tp->phydev = mdiobus_get_phy(new_bus, 0);
5172 if (!tp->phydev) {
5173 mdiobus_unregister(new_bus);
5174 return -ENODEV;
5175 } else if (!tp->phydev->drv) {
5176 /* Most chip versions fail with the genphy driver.
5177 * Therefore ensure that the dedicated PHY driver is loaded.
5178 */
5179 dev_err(&pdev->dev, "realtek.ko not loaded, maybe it needs to be added to initramfs?\n");
5180 mdiobus_unregister(new_bus);
5181 return -EUNATCH;
5182 }
5183
5184 /* PHY will be woken up in rtl_open() */
5185 phy_suspend(tp->phydev);
5186
5187 return 0;
5188 }
5189
5190 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5191 {
5192 tp->ocp_base = OCP_STD_PHY_BASE;
5193
5194 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
5195
5196 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
5197 return;
5198
5199 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
5200 return;
5201
5202 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5203 msleep(1);
5204 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5205
5206 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5207
5208 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
5209 return;
5210
5211 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5212
5213 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5214 }
5215
5216 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5217 {
5218 tp->ocp_base = OCP_STD_PHY_BASE;
5219
5220 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
5221
5222 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
5223 return;
5224
5225 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5226 msleep(1);
5227 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5228
5229 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5230
5231 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
5232 return;
5233
5234 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5235 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5236 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5237
5238 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5239 }
5240
5241 static void rtl_hw_initialize(struct rtl8169_private *tp)
5242 {
5243 switch (tp->mac_version) {
5244 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
5245 rtl8168ep_stop_cmac(tp);
5246 /* fall through */
5247 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5248 rtl_hw_init_8168g(tp);
5249 break;
5250 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
5251 rtl_hw_init_8125(tp);
5252 break;
5253 default:
5254 break;
5255 }
5256 }
5257
5258 static int rtl_jumbo_max(struct rtl8169_private *tp)
5259 {
5260 /* Non-GBit versions don't support jumbo frames */
5261 if (!tp->supports_gmii)
5262 return 0;
5263
5264 switch (tp->mac_version) {
5265 /* RTL8169 */
5266 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5267 return JUMBO_7K;
5268 /* RTL8168b */
5269 case RTL_GIGA_MAC_VER_11:
5270 case RTL_GIGA_MAC_VER_12:
5271 case RTL_GIGA_MAC_VER_17:
5272 return JUMBO_4K;
5273 /* RTL8168c */
5274 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5275 return JUMBO_6K;
5276 default:
5277 return JUMBO_9K;
5278 }
5279 }
5280
5281 static void rtl_disable_clk(void *data)
5282 {
5283 clk_disable_unprepare(data);
5284 }
5285
5286 static int rtl_get_ether_clk(struct rtl8169_private *tp)
5287 {
5288 struct device *d = tp_to_dev(tp);
5289 struct clk *clk;
5290 int rc;
5291
5292 clk = devm_clk_get(d, "ether_clk");
5293 if (IS_ERR(clk)) {
5294 rc = PTR_ERR(clk);
5295 if (rc == -ENOENT)
5296 /* clk-core allows NULL (for suspend / resume) */
5297 rc = 0;
5298 else if (rc != -EPROBE_DEFER)
5299 dev_err(d, "failed to get clk: %d\n", rc);
5300 } else {
5301 tp->clk = clk;
5302 rc = clk_prepare_enable(clk);
5303 if (rc)
5304 dev_err(d, "failed to enable clk: %d\n", rc);
5305 else
5306 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5307 }
5308
5309 return rc;
5310 }
5311
5312 static void rtl_init_mac_address(struct rtl8169_private *tp)
5313 {
5314 struct net_device *dev = tp->dev;
5315 u8 *mac_addr = dev->dev_addr;
5316 int rc;
5317
5318 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5319 if (!rc)
5320 goto done;
5321
5322 rtl_read_mac_address(tp, mac_addr);
5323 if (is_valid_ether_addr(mac_addr))
5324 goto done;
5325
5326 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5327 if (is_valid_ether_addr(mac_addr))
5328 goto done;
5329
5330 eth_hw_addr_random(dev);
5331 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5332 done:
5333 rtl_rar_set(tp, mac_addr);
5334 }
5335
5336 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5337 {
5338 struct rtl8169_private *tp;
5339 int jumbo_max, region, rc;
5340 enum mac_version chipset;
5341 struct net_device *dev;
5342 u16 xid;
5343
5344 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5345 if (!dev)
5346 return -ENOMEM;
5347
5348 SET_NETDEV_DEV(dev, &pdev->dev);
5349 dev->netdev_ops = &rtl_netdev_ops;
5350 tp = netdev_priv(dev);
5351 tp->dev = dev;
5352 tp->pci_dev = pdev;
5353 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
5354 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5355 tp->eee_adv = -1;
5356
5357 /* Get the *optional* external "ether_clk" used on some boards */
5358 rc = rtl_get_ether_clk(tp);
5359 if (rc)
5360 return rc;
5361
5362 /* Disable ASPM completely as that cause random device stop working
5363 * problems as well as full system hangs for some PCIe devices users.
5364 */
5365 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
5366 PCIE_LINK_STATE_L1);
5367 tp->aspm_manageable = !rc;
5368
5369 /* enable device (incl. PCI PM wakeup and hotplug setup) */
5370 rc = pcim_enable_device(pdev);
5371 if (rc < 0) {
5372 dev_err(&pdev->dev, "enable failure\n");
5373 return rc;
5374 }
5375
5376 if (pcim_set_mwi(pdev) < 0)
5377 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5378
5379 /* use first MMIO region */
5380 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5381 if (region < 0) {
5382 dev_err(&pdev->dev, "no MMIO resource found\n");
5383 return -ENODEV;
5384 }
5385
5386 /* check for weird/broken PCI region reporting */
5387 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5388 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5389 return -ENODEV;
5390 }
5391
5392 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
5393 if (rc < 0) {
5394 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5395 return rc;
5396 }
5397
5398 tp->mmio_addr = pcim_iomap_table(pdev)[region];
5399
5400 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5401
5402 /* Identify chip attached to board */
5403 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5404 if (chipset == RTL_GIGA_MAC_NONE) {
5405 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid);
5406 return -ENODEV;
5407 }
5408
5409 tp->mac_version = chipset;
5410
5411 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
5412
5413 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5414 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5415 dev->features |= NETIF_F_HIGHDMA;
5416
5417 rtl_init_rxcfg(tp);
5418
5419 rtl8169_irq_mask_and_ack(tp);
5420
5421 rtl_hw_initialize(tp);
5422
5423 rtl_hw_reset(tp);
5424
5425 pci_set_master(pdev);
5426
5427 rc = rtl_alloc_irq(tp);
5428 if (rc < 0) {
5429 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5430 return rc;
5431 }
5432
5433 mutex_init(&tp->wk.mutex);
5434 INIT_WORK(&tp->wk.work, rtl_task);
5435 u64_stats_init(&tp->rx_stats.syncp);
5436 u64_stats_init(&tp->tx_stats.syncp);
5437
5438 rtl_init_mac_address(tp);
5439
5440 dev->ethtool_ops = &rtl8169_ethtool_ops;
5441
5442 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5443
5444 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5445 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5446 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5447 NETIF_F_HIGHDMA;
5448 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5449
5450 tp->cp_cmd |= RxChkSum;
5451 /* RTL8125 uses register RxConfig for VLAN offloading config */
5452 if (!rtl_is_8125(tp))
5453 tp->cp_cmd |= RxVlan;
5454 /*
5455 * Pretend we are using VLANs; This bypasses a nasty bug where
5456 * Interrupts stop flowing on high load on 8110SCd controllers.
5457 */
5458 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5459 /* Disallow toggling */
5460 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5461
5462 if (rtl_chip_supports_csum_v2(tp))
5463 dev->hw_features |= NETIF_F_IPV6_CSUM;
5464
5465 dev->features |= dev->hw_features;
5466
5467 /* There has been a number of reports that using SG/TSO results in
5468 * tx timeouts. However for a lot of people SG/TSO works fine.
5469 * Therefore disable both features by default, but allow users to
5470 * enable them. Use at own risk!
5471 */
5472 if (rtl_chip_supports_csum_v2(tp)) {
5473 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5474 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5475 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5476 } else {
5477 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5478 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5479 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5480 }
5481
5482 dev->hw_features |= NETIF_F_RXALL;
5483 dev->hw_features |= NETIF_F_RXFCS;
5484
5485 jumbo_max = rtl_jumbo_max(tp);
5486 if (jumbo_max)
5487 dev->max_mtu = jumbo_max;
5488
5489 rtl_set_irq_mask(tp);
5490
5491 tp->fw_name = rtl_chip_infos[chipset].fw_name;
5492
5493 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5494 &tp->counters_phys_addr,
5495 GFP_KERNEL);
5496 if (!tp->counters)
5497 return -ENOMEM;
5498
5499 pci_set_drvdata(pdev, dev);
5500
5501 rc = r8169_mdio_register(tp);
5502 if (rc)
5503 return rc;
5504
5505 /* chip gets powered up in rtl_open() */
5506 rtl_pll_power_down(tp);
5507
5508 rc = register_netdev(dev);
5509 if (rc)
5510 goto err_mdio_unregister;
5511
5512 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
5513 rtl_chip_infos[chipset].name, dev->dev_addr, xid,
5514 pci_irq_vector(pdev, 0));
5515
5516 if (jumbo_max)
5517 netif_info(tp, probe, dev,
5518 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5519 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5520 "ok" : "ko");
5521
5522 if (r8168_check_dash(tp))
5523 rtl8168_driver_start(tp);
5524
5525 if (pci_dev_run_wake(pdev))
5526 pm_runtime_put_sync(&pdev->dev);
5527
5528 return 0;
5529
5530 err_mdio_unregister:
5531 mdiobus_unregister(tp->phydev->mdio.bus);
5532 return rc;
5533 }
5534
5535 static struct pci_driver rtl8169_pci_driver = {
5536 .name = MODULENAME,
5537 .id_table = rtl8169_pci_tbl,
5538 .probe = rtl_init_one,
5539 .remove = rtl_remove_one,
5540 .shutdown = rtl_shutdown,
5541 .driver.pm = RTL8169_PM_OPS,
5542 };
5543
5544 module_pci_driver(rtl8169_pci_driver);
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