drivers/net/ethernet/stmicro/stmmac/common.h

   1 /*******************************************************************************
   2   STMMAC Common Header File
   3
   4   Copyright (C) 2007-2009  STMicroelectronics Ltd
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   The full GNU General Public License is included in this distribution in
  16   the file called "COPYING".
  17
  18   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  19 *******************************************************************************/
  20
  21 #ifndef __COMMON_H__
  22 #define __COMMON_H__
  23
  24 #include <linux/etherdevice.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/stmmac.h>
  27 #include <linux/phy.h>
  28 #include <linux/module.h>
  29 #if IS_ENABLED(CONFIG_VLAN_8021Q)
  30 #define STMMAC_VLAN_TAG_USED
  31 #include <linux/if_vlan.h>
  32 #endif
  33
  34 #include "descs.h"
  35 #include "hwif.h"
  36 #include "mmc.h"
  37
  38 /* Synopsys Core versions */
  39 #define DWMAC_CORE_3_40 0x34
  40 #define DWMAC_CORE_3_50 0x35
  41 #define DWMAC_CORE_4_00 0x40
  42 #define DWMAC_CORE_4_10 0x41
  43 #define DWMAC_CORE_5_00 0x50
  44 #define DWMAC_CORE_5_10 0x51
  45 #define STMMAC_CHAN0    0       /* Always supported and default for all chips */
  46
  47 /* These need to be power of two, and >= 4 */
  48 #define DMA_TX_SIZE 512
  49 #define DMA_RX_SIZE 512
  50 #define STMMAC_GET_ENTRY(x, size)       ((x + 1) & (size - 1))
  51
  52 #undef FRAME_FILTER_DEBUG
  53 /* #define FRAME_FILTER_DEBUG */
  54
  55 /* Extra statistic and debug information exposed by ethtool */
  56 struct stmmac_extra_stats {
  57         /* Transmit errors */
  58         unsigned long tx_underflow ____cacheline_aligned;
  59         unsigned long tx_carrier;
  60         unsigned long tx_losscarrier;
  61         unsigned long vlan_tag;
  62         unsigned long tx_deferred;
  63         unsigned long tx_vlan;
  64         unsigned long tx_jabber;
  65         unsigned long tx_frame_flushed;
  66         unsigned long tx_payload_error;
  67         unsigned long tx_ip_header_error;
  68         /* Receive errors */
  69         unsigned long rx_desc;
  70         unsigned long sa_filter_fail;
  71         unsigned long overflow_error;
  72         unsigned long ipc_csum_error;
  73         unsigned long rx_collision;
  74         unsigned long rx_crc_errors;
  75         unsigned long dribbling_bit;
  76         unsigned long rx_length;
  77         unsigned long rx_mii;
  78         unsigned long rx_multicast;
  79         unsigned long rx_gmac_overflow;
  80         unsigned long rx_watchdog;
  81         unsigned long da_rx_filter_fail;
  82         unsigned long sa_rx_filter_fail;
  83         unsigned long rx_missed_cntr;
  84         unsigned long rx_overflow_cntr;
  85         unsigned long rx_vlan;
  86         /* Tx/Rx IRQ error info */
  87         unsigned long tx_undeflow_irq;
  88         unsigned long tx_process_stopped_irq;
  89         unsigned long tx_jabber_irq;
  90         unsigned long rx_overflow_irq;
  91         unsigned long rx_buf_unav_irq;
  92         unsigned long rx_process_stopped_irq;
  93         unsigned long rx_watchdog_irq;
  94         unsigned long tx_early_irq;
  95         unsigned long fatal_bus_error_irq;
  96         /* Tx/Rx IRQ Events */
  97         unsigned long rx_early_irq;
  98         unsigned long threshold;
  99         unsigned long tx_pkt_n;
 100         unsigned long rx_pkt_n;
 101         unsigned long normal_irq_n;
 102         unsigned long rx_normal_irq_n;
 103         unsigned long napi_poll;
 104         unsigned long tx_normal_irq_n;
 105         unsigned long tx_clean;
 106         unsigned long tx_set_ic_bit;
 107         unsigned long irq_receive_pmt_irq_n;
 108         /* MMC info */
 109         unsigned long mmc_tx_irq_n;
 110         unsigned long mmc_rx_irq_n;
 111         unsigned long mmc_rx_csum_offload_irq_n;
 112         /* EEE */
 113         unsigned long irq_tx_path_in_lpi_mode_n;
 114         unsigned long irq_tx_path_exit_lpi_mode_n;
 115         unsigned long irq_rx_path_in_lpi_mode_n;
 116         unsigned long irq_rx_path_exit_lpi_mode_n;
 117         unsigned long phy_eee_wakeup_error_n;
 118         /* Extended RDES status */
 119         unsigned long ip_hdr_err;
 120         unsigned long ip_payload_err;
 121         unsigned long ip_csum_bypassed;
 122         unsigned long ipv4_pkt_rcvd;
 123         unsigned long ipv6_pkt_rcvd;
 124         unsigned long no_ptp_rx_msg_type_ext;
 125         unsigned long ptp_rx_msg_type_sync;
 126         unsigned long ptp_rx_msg_type_follow_up;
 127         unsigned long ptp_rx_msg_type_delay_req;
 128         unsigned long ptp_rx_msg_type_delay_resp;
 129         unsigned long ptp_rx_msg_type_pdelay_req;
 130         unsigned long ptp_rx_msg_type_pdelay_resp;
 131         unsigned long ptp_rx_msg_type_pdelay_follow_up;
 132         unsigned long ptp_rx_msg_type_announce;
 133         unsigned long ptp_rx_msg_type_management;
 134         unsigned long ptp_rx_msg_pkt_reserved_type;
 135         unsigned long ptp_frame_type;
 136         unsigned long ptp_ver;
 137         unsigned long timestamp_dropped;
 138         unsigned long av_pkt_rcvd;
 139         unsigned long av_tagged_pkt_rcvd;
 140         unsigned long vlan_tag_priority_val;
 141         unsigned long l3_filter_match;
 142         unsigned long l4_filter_match;
 143         unsigned long l3_l4_filter_no_match;
 144         /* PCS */
 145         unsigned long irq_pcs_ane_n;
 146         unsigned long irq_pcs_link_n;
 147         unsigned long irq_rgmii_n;
 148         unsigned long pcs_link;
 149         unsigned long pcs_duplex;
 150         unsigned long pcs_speed;
 151         /* debug register */
 152         unsigned long mtl_tx_status_fifo_full;
 153         unsigned long mtl_tx_fifo_not_empty;
 154         unsigned long mmtl_fifo_ctrl;
 155         unsigned long mtl_tx_fifo_read_ctrl_write;
 156         unsigned long mtl_tx_fifo_read_ctrl_wait;
 157         unsigned long mtl_tx_fifo_read_ctrl_read;
 158         unsigned long mtl_tx_fifo_read_ctrl_idle;
 159         unsigned long mac_tx_in_pause;
 160         unsigned long mac_tx_frame_ctrl_xfer;
 161         unsigned long mac_tx_frame_ctrl_idle;
 162         unsigned long mac_tx_frame_ctrl_wait;
 163         unsigned long mac_tx_frame_ctrl_pause;
 164         unsigned long mac_gmii_tx_proto_engine;
 165         unsigned long mtl_rx_fifo_fill_level_full;
 166         unsigned long mtl_rx_fifo_fill_above_thresh;
 167         unsigned long mtl_rx_fifo_fill_below_thresh;
 168         unsigned long mtl_rx_fifo_fill_level_empty;
 169         unsigned long mtl_rx_fifo_read_ctrl_flush;
 170         unsigned long mtl_rx_fifo_read_ctrl_read_data;
 171         unsigned long mtl_rx_fifo_read_ctrl_status;
 172         unsigned long mtl_rx_fifo_read_ctrl_idle;
 173         unsigned long mtl_rx_fifo_ctrl_active;
 174         unsigned long mac_rx_frame_ctrl_fifo;
 175         unsigned long mac_gmii_rx_proto_engine;
 176         /* TSO */
 177         unsigned long tx_tso_frames;
 178         unsigned long tx_tso_nfrags;
 179 };
 180
 181 /* Safety Feature statistics exposed by ethtool */
 182 struct stmmac_safety_stats {
 183         unsigned long mac_errors[32];
 184         unsigned long mtl_errors[32];
 185         unsigned long dma_errors[32];
 186 };
 187
 188 /* Number of fields in Safety Stats */
 189 #define STMMAC_SAFETY_FEAT_SIZE \
 190         (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
 191
 192 /* CSR Frequency Access Defines*/
 193 #define CSR_F_35M       35000000
 194 #define CSR_F_60M       60000000
 195 #define CSR_F_100M      100000000
 196 #define CSR_F_150M      150000000
 197 #define CSR_F_250M      250000000
 198 #define CSR_F_300M      300000000
 199
 200 #define MAC_CSR_H_FRQ_MASK      0x20
 201
 202 #define HASH_TABLE_SIZE 64
 203 #define PAUSE_TIME 0xffff
 204
 205 /* Flow Control defines */
 206 #define FLOW_OFF        0
 207 #define FLOW_RX         1
 208 #define FLOW_TX         2
 209 #define FLOW_AUTO       (FLOW_TX | FLOW_RX)
 210
 211 /* PCS defines */
 212 #define STMMAC_PCS_RGMII        (1 << 0)
 213 #define STMMAC_PCS_SGMII        (1 << 1)
 214 #define STMMAC_PCS_TBI          (1 << 2)
 215 #define STMMAC_PCS_RTBI         (1 << 3)
 216
 217 #define SF_DMA_MODE 1           /* DMA STORE-AND-FORWARD Operation Mode */
 218
 219 /* DAM HW feature register fields */
 220 #define DMA_HW_FEAT_MIISEL      0x00000001      /* 10/100 Mbps Support */
 221 #define DMA_HW_FEAT_GMIISEL     0x00000002      /* 1000 Mbps Support */
 222 #define DMA_HW_FEAT_HDSEL       0x00000004      /* Half-Duplex Support */
 223 #define DMA_HW_FEAT_EXTHASHEN   0x00000008      /* Expanded DA Hash Filter */
 224 #define DMA_HW_FEAT_HASHSEL     0x00000010      /* HASH Filter */
 225 #define DMA_HW_FEAT_ADDMAC      0x00000020      /* Multiple MAC Addr Reg */
 226 #define DMA_HW_FEAT_PCSSEL      0x00000040      /* PCS registers */
 227 #define DMA_HW_FEAT_L3L4FLTREN  0x00000080      /* Layer 3 & Layer 4 Feature */
 228 #define DMA_HW_FEAT_SMASEL      0x00000100      /* SMA(MDIO) Interface */
 229 #define DMA_HW_FEAT_RWKSEL      0x00000200      /* PMT Remote Wakeup */
 230 #define DMA_HW_FEAT_MGKSEL      0x00000400      /* PMT Magic Packet */
 231 #define DMA_HW_FEAT_MMCSEL      0x00000800      /* RMON Module */
 232 #define DMA_HW_FEAT_TSVER1SEL   0x00001000      /* Only IEEE 1588-2002 */
 233 #define DMA_HW_FEAT_TSVER2SEL   0x00002000      /* IEEE 1588-2008 PTPv2 */
 234 #define DMA_HW_FEAT_EEESEL      0x00004000      /* Energy Efficient Ethernet */
 235 #define DMA_HW_FEAT_AVSEL       0x00008000      /* AV Feature */
 236 #define DMA_HW_FEAT_TXCOESEL    0x00010000      /* Checksum Offload in Tx */
 237 #define DMA_HW_FEAT_RXTYP1COE   0x00020000      /* IP COE (Type 1) in Rx */
 238 #define DMA_HW_FEAT_RXTYP2COE   0x00040000      /* IP COE (Type 2) in Rx */
 239 #define DMA_HW_FEAT_RXFIFOSIZE  0x00080000      /* Rx FIFO > 2048 Bytes */
 240 #define DMA_HW_FEAT_RXCHCNT     0x00300000      /* No. additional Rx Channels */
 241 #define DMA_HW_FEAT_TXCHCNT     0x00c00000      /* No. additional Tx Channels */
 242 #define DMA_HW_FEAT_ENHDESSEL   0x01000000      /* Alternate Descriptor */
 243 /* Timestamping with Internal System Time */
 244 #define DMA_HW_FEAT_INTTSEN     0x02000000
 245 #define DMA_HW_FEAT_FLEXIPPSEN  0x04000000      /* Flexible PPS Output */
 246 #define DMA_HW_FEAT_SAVLANINS   0x08000000      /* Source Addr or VLAN */
 247 #define DMA_HW_FEAT_ACTPHYIF    0x70000000      /* Active/selected PHY iface */
 248 #define DEFAULT_DMA_PBL         8
 249
 250 /* PCS status and mask defines */
 251 #define PCS_ANE_IRQ             BIT(2)  /* PCS Auto-Negotiation */
 252 #define PCS_LINK_IRQ            BIT(1)  /* PCS Link */
 253 #define PCS_RGSMIIIS_IRQ        BIT(0)  /* RGMII or SMII Interrupt */
 254
 255 /* Max/Min RI Watchdog Timer count value */
 256 #define MAX_DMA_RIWT            0xff
 257 #define MIN_DMA_RIWT            0x20
 258 /* Tx coalesce parameters */
 259 #define STMMAC_COAL_TX_TIMER    40000
 260 #define STMMAC_MAX_COAL_TX_TICK 100000
 261 #define STMMAC_TX_MAX_FRAMES    256
 262 #define STMMAC_TX_FRAMES        64
 263
 264 /* Packets types */
 265 enum packets_types {
 266         PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
 267         PACKET_PTPQ = 0x2, /* PTP Packets */
 268         PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
 269         PACKET_UPQ = 0x4, /* Untagged Packets */
 270         PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
 271 };
 272
 273 /* Rx IPC status */
 274 enum rx_frame_status {
 275         good_frame = 0x0,
 276         discard_frame = 0x1,
 277         csum_none = 0x2,
 278         llc_snap = 0x4,
 279         dma_own = 0x8,
 280         rx_not_ls = 0x10,
 281 };
 282
 283 /* Tx status */
 284 enum tx_frame_status {
 285         tx_done = 0x0,
 286         tx_not_ls = 0x1,
 287         tx_err = 0x2,
 288         tx_dma_own = 0x4,
 289 };
 290
 291 enum dma_irq_status {
 292         tx_hard_error = 0x1,
 293         tx_hard_error_bump_tc = 0x2,
 294         handle_rx = 0x4,
 295         handle_tx = 0x8,
 296 };
 297
 298 /* EEE and LPI defines */
 299 #define CORE_IRQ_TX_PATH_IN_LPI_MODE    (1 << 0)
 300 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE  (1 << 1)
 301 #define CORE_IRQ_RX_PATH_IN_LPI_MODE    (1 << 2)
 302 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE  (1 << 3)
 303
 304 #define CORE_IRQ_MTL_RX_OVERFLOW        BIT(8)
 305
 306 /* Physical Coding Sublayer */
 307 struct rgmii_adv {
 308         unsigned int pause;
 309         unsigned int duplex;
 310         unsigned int lp_pause;
 311         unsigned int lp_duplex;
 312 };
 313
 314 #define STMMAC_PCS_PAUSE        1
 315 #define STMMAC_PCS_ASYM_PAUSE   2
 316
 317 /* DMA HW capabilities */
 318 struct dma_features {
 319         unsigned int mbps_10_100;
 320         unsigned int mbps_1000;
 321         unsigned int half_duplex;
 322         unsigned int hash_filter;
 323         unsigned int multi_addr;
 324         unsigned int pcs;
 325         unsigned int sma_mdio;
 326         unsigned int pmt_remote_wake_up;
 327         unsigned int pmt_magic_frame;
 328         unsigned int rmon;
 329         /* IEEE 1588-2002 */
 330         unsigned int time_stamp;
 331         /* IEEE 1588-2008 */
 332         unsigned int atime_stamp;
 333         /* 802.3az - Energy-Efficient Ethernet (EEE) */
 334         unsigned int eee;
 335         unsigned int av;
 336         unsigned int tsoen;
 337         /* TX and RX csum */
 338         unsigned int tx_coe;
 339         unsigned int rx_coe;
 340         unsigned int rx_coe_type1;
 341         unsigned int rx_coe_type2;
 342         unsigned int rxfifo_over_2048;
 343         /* TX and RX number of channels */
 344         unsigned int number_rx_channel;
 345         unsigned int number_tx_channel;
 346         /* TX and RX number of queues */
 347         unsigned int number_rx_queues;
 348         unsigned int number_tx_queues;
 349         /* Alternate (enhanced) DESC mode */
 350         unsigned int enh_desc;
 351         /* TX and RX FIFO sizes */
 352         unsigned int tx_fifo_size;
 353         unsigned int rx_fifo_size;
 354         /* Automotive Safety Package */
 355         unsigned int asp;
 356         /* RX Parser */
 357         unsigned int frpsel;
 358         unsigned int frpbs;
 359         unsigned int frpes;
 360 };
 361
 362 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
 363 #define BUF_SIZE_16KiB 16384
 364 #define BUF_SIZE_8KiB 8192
 365 #define BUF_SIZE_4KiB 4096
 366 #define BUF_SIZE_2KiB 2048
 367
 368 /* Power Down and WOL */
 369 #define PMT_NOT_SUPPORTED 0
 370 #define PMT_SUPPORTED 1
 371
 372 /* Common MAC defines */
 373 #define MAC_CTRL_REG            0x00000000      /* MAC Control */
 374 #define MAC_ENABLE_TX           0x00000008      /* Transmitter Enable */
 375 #define MAC_ENABLE_RX           0x00000004      /* Receiver Enable */
 376
 377 /* Default LPI timers */
 378 #define STMMAC_DEFAULT_LIT_LS   0x3E8
 379 #define STMMAC_DEFAULT_TWT_LS   0x1E
 380
 381 #define STMMAC_CHAIN_MODE       0x1
 382 #define STMMAC_RING_MODE        0x2
 383
 384 #define JUMBO_LEN               9000
 385
 386 extern const struct stmmac_desc_ops enh_desc_ops;
 387 extern const struct stmmac_desc_ops ndesc_ops;
 388
 389 struct mac_device_info;
 390
 391 extern const struct stmmac_hwtimestamp stmmac_ptp;
 392 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
 393
 394 struct mac_link {
 395         u32 speed_mask;
 396         u32 speed10;
 397         u32 speed100;
 398         u32 speed1000;
 399         u32 duplex;
 400 };
 401
 402 struct mii_regs {
 403         unsigned int addr;      /* MII Address */
 404         unsigned int data;      /* MII Data */
 405         unsigned int addr_shift;        /* MII address shift */
 406         unsigned int reg_shift;         /* MII reg shift */
 407         unsigned int addr_mask;         /* MII address mask */
 408         unsigned int reg_mask;          /* MII reg mask */
 409         unsigned int clk_csr_shift;
 410         unsigned int clk_csr_mask;
 411 };
 412
 413 struct mac_device_info {
 414         const struct stmmac_ops *mac;
 415         const struct stmmac_desc_ops *desc;
 416         const struct stmmac_dma_ops *dma;
 417         const struct stmmac_mode_ops *mode;
 418         const struct stmmac_hwtimestamp *ptp;
 419         const struct stmmac_tc_ops *tc;
 420         struct mii_regs mii;    /* MII register Addresses */
 421         struct mac_link link;
 422         void __iomem *pcsr;     /* vpointer to device CSRs */
 423         int multicast_filter_bins;
 424         int unicast_filter_entries;
 425         int mcast_bits_log2;
 426         unsigned int rx_csum;
 427         unsigned int pcs;
 428         unsigned int pmt;
 429         unsigned int ps;
 430 };
 431
 432 struct stmmac_rx_routing {
 433         u32 reg_mask;
 434         u32 reg_shift;
 435 };
 436
 437 int dwmac100_setup(struct stmmac_priv *priv);
 438 int dwmac1000_setup(struct stmmac_priv *priv);
 439 int dwmac4_setup(struct stmmac_priv *priv);
 440
 441 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
 442                          unsigned int high, unsigned int low);
 443 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
 444                          unsigned int high, unsigned int low);
 445 void stmmac_set_mac(void __iomem *ioaddr, bool enable);
 446
 447 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
 448                                 unsigned int high, unsigned int low);
 449 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
 450                                 unsigned int high, unsigned int low);
 451 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
 452
 453 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
 454
 455 extern const struct stmmac_mode_ops ring_mode_ops;
 456 extern const struct stmmac_mode_ops chain_mode_ops;
 457 extern const struct stmmac_desc_ops dwmac4_desc_ops;
 458
 459 #endif /* __COMMON_H__ */