1 // SPDX-License-Identifier: GPL-2.0-only
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 * DWC Ether MAC version 4.00 has been used for developing this code.
6 * This only implements the mac core functions for this chip.
8 * Copyright (C) 2015 STMicroelectronics Ltd
10 * Author: Alexandre Torgue <alexandre.torgue@st.com>
13 #include <linux/crc32.h>
14 #include <linux/slab.h>
15 #include <linux/ethtool.h>
18 #include "stmmac_pcs.h"
22 static void dwmac4_core_init(struct mac_device_info
*hw
,
23 struct net_device
*dev
)
25 struct stmmac_priv
*priv
= netdev_priv(dev
);
26 void __iomem
*ioaddr
= hw
->pcsr
;
27 u32 value
= readl(ioaddr
+ GMAC_CONFIG
);
30 value
|= GMAC_CORE_INIT
;
33 value
|= GMAC_CONFIG_TE
;
35 value
&= hw
->link
.speed_mask
;
38 value
|= hw
->link
.speed1000
;
41 value
|= hw
->link
.speed100
;
44 value
|= hw
->link
.speed10
;
49 writel(value
, ioaddr
+ GMAC_CONFIG
);
51 /* Configure LPI 1us counter to number of CSR clock ticks in 1us - 1 */
52 clk_rate
= clk_get_rate(priv
->plat
->stmmac_clk
);
53 writel((clk_rate
/ 1000000) - 1, ioaddr
+ GMAC4_MAC_ONEUS_TIC_COUNTER
);
55 /* Enable GMAC interrupts */
56 value
= GMAC_INT_DEFAULT_ENABLE
;
59 value
|= GMAC_PCS_IRQ_DEFAULT
;
61 /* Enable FPE interrupt */
62 if ((GMAC_HW_FEAT_FPESEL
& readl(ioaddr
+ GMAC_HW_FEATURE3
)) >> 26)
63 value
|= GMAC_INT_FPE_EN
;
65 writel(value
, ioaddr
+ GMAC_INT_EN
);
67 if (GMAC_INT_DEFAULT_ENABLE
& GMAC_INT_TSIE
)
68 init_waitqueue_head(&priv
->tstamp_busy_wait
);
71 static void dwmac4_update_caps(struct stmmac_priv
*priv
)
73 if (priv
->plat
->tx_queues_to_use
> 1)
74 priv
->hw
->link
.caps
&= ~(MAC_10HD
| MAC_100HD
| MAC_1000HD
);
76 priv
->hw
->link
.caps
|= (MAC_10HD
| MAC_100HD
| MAC_1000HD
);
79 static void dwmac4_rx_queue_enable(struct mac_device_info
*hw
,
82 void __iomem
*ioaddr
= hw
->pcsr
;
83 u32 value
= readl(ioaddr
+ GMAC_RXQ_CTRL0
);
85 value
&= GMAC_RX_QUEUE_CLEAR(queue
);
86 if (mode
== MTL_QUEUE_AVB
)
87 value
|= GMAC_RX_AV_QUEUE_ENABLE(queue
);
88 else if (mode
== MTL_QUEUE_DCB
)
89 value
|= GMAC_RX_DCB_QUEUE_ENABLE(queue
);
91 writel(value
, ioaddr
+ GMAC_RXQ_CTRL0
);
94 static void dwmac4_rx_queue_priority(struct mac_device_info
*hw
,
97 void __iomem
*ioaddr
= hw
->pcsr
;
102 ctrl2
= readl(ioaddr
+ GMAC_RXQ_CTRL2
);
103 ctrl3
= readl(ioaddr
+ GMAC_RXQ_CTRL3
);
105 /* The software must ensure that the same priority
106 * is not mapped to multiple Rx queues
108 for (i
= 0; i
< 4; i
++)
109 clear_mask
|= ((prio
<< GMAC_RXQCTRL_PSRQX_SHIFT(i
)) &
110 GMAC_RXQCTRL_PSRQX_MASK(i
));
112 ctrl2
&= ~clear_mask
;
113 ctrl3
&= ~clear_mask
;
115 /* First assign new priorities to a queue, then
116 * clear them from others queues
119 ctrl2
|= (prio
<< GMAC_RXQCTRL_PSRQX_SHIFT(queue
)) &
120 GMAC_RXQCTRL_PSRQX_MASK(queue
);
122 writel(ctrl2
, ioaddr
+ GMAC_RXQ_CTRL2
);
123 writel(ctrl3
, ioaddr
+ GMAC_RXQ_CTRL3
);
127 ctrl3
|= (prio
<< GMAC_RXQCTRL_PSRQX_SHIFT(queue
)) &
128 GMAC_RXQCTRL_PSRQX_MASK(queue
);
130 writel(ctrl3
, ioaddr
+ GMAC_RXQ_CTRL3
);
131 writel(ctrl2
, ioaddr
+ GMAC_RXQ_CTRL2
);
135 static void dwmac4_tx_queue_priority(struct mac_device_info
*hw
,
138 void __iomem
*ioaddr
= hw
->pcsr
;
142 base_register
= (queue
< 4) ? GMAC_TXQ_PRTY_MAP0
: GMAC_TXQ_PRTY_MAP1
;
146 value
= readl(ioaddr
+ base_register
);
148 value
&= ~GMAC_TXQCTRL_PSTQX_MASK(queue
);
149 value
|= (prio
<< GMAC_TXQCTRL_PSTQX_SHIFT(queue
)) &
150 GMAC_TXQCTRL_PSTQX_MASK(queue
);
152 writel(value
, ioaddr
+ base_register
);
155 static void dwmac4_rx_queue_routing(struct mac_device_info
*hw
,
156 u8 packet
, u32 queue
)
158 void __iomem
*ioaddr
= hw
->pcsr
;
161 static const struct stmmac_rx_routing route_possibilities
[] = {
162 { GMAC_RXQCTRL_AVCPQ_MASK
, GMAC_RXQCTRL_AVCPQ_SHIFT
},
163 { GMAC_RXQCTRL_PTPQ_MASK
, GMAC_RXQCTRL_PTPQ_SHIFT
},
164 { GMAC_RXQCTRL_DCBCPQ_MASK
, GMAC_RXQCTRL_DCBCPQ_SHIFT
},
165 { GMAC_RXQCTRL_UPQ_MASK
, GMAC_RXQCTRL_UPQ_SHIFT
},
166 { GMAC_RXQCTRL_MCBCQ_MASK
, GMAC_RXQCTRL_MCBCQ_SHIFT
},
169 value
= readl(ioaddr
+ GMAC_RXQ_CTRL1
);
171 /* routing configuration */
172 value
&= ~route_possibilities
[packet
- 1].reg_mask
;
173 value
|= (queue
<< route_possibilities
[packet
-1].reg_shift
) &
174 route_possibilities
[packet
- 1].reg_mask
;
176 /* some packets require extra ops */
177 if (packet
== PACKET_AVCPQ
) {
178 value
&= ~GMAC_RXQCTRL_TACPQE
;
179 value
|= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT
;
180 } else if (packet
== PACKET_MCBCQ
) {
181 value
&= ~GMAC_RXQCTRL_MCBCQEN
;
182 value
|= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT
;
185 writel(value
, ioaddr
+ GMAC_RXQ_CTRL1
);
188 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info
*hw
,
191 void __iomem
*ioaddr
= hw
->pcsr
;
192 u32 value
= readl(ioaddr
+ MTL_OPERATION_MODE
);
194 value
&= ~MTL_OPERATION_RAA
;
196 case MTL_RX_ALGORITHM_SP
:
197 value
|= MTL_OPERATION_RAA_SP
;
199 case MTL_RX_ALGORITHM_WSP
:
200 value
|= MTL_OPERATION_RAA_WSP
;
206 writel(value
, ioaddr
+ MTL_OPERATION_MODE
);
209 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info
*hw
,
212 void __iomem
*ioaddr
= hw
->pcsr
;
213 u32 value
= readl(ioaddr
+ MTL_OPERATION_MODE
);
215 value
&= ~MTL_OPERATION_SCHALG_MASK
;
217 case MTL_TX_ALGORITHM_WRR
:
218 value
|= MTL_OPERATION_SCHALG_WRR
;
220 case MTL_TX_ALGORITHM_WFQ
:
221 value
|= MTL_OPERATION_SCHALG_WFQ
;
223 case MTL_TX_ALGORITHM_DWRR
:
224 value
|= MTL_OPERATION_SCHALG_DWRR
;
226 case MTL_TX_ALGORITHM_SP
:
227 value
|= MTL_OPERATION_SCHALG_SP
;
233 writel(value
, ioaddr
+ MTL_OPERATION_MODE
);
236 static void dwmac4_set_mtl_tx_queue_weight(struct stmmac_priv
*priv
,
237 struct mac_device_info
*hw
,
238 u32 weight
, u32 queue
)
240 const struct dwmac4_addrs
*dwmac4_addrs
= priv
->plat
->dwmac4_addrs
;
241 void __iomem
*ioaddr
= hw
->pcsr
;
242 u32 value
= readl(ioaddr
+ mtl_txqx_weight_base_addr(dwmac4_addrs
,
245 value
&= ~MTL_TXQ_WEIGHT_ISCQW_MASK
;
246 value
|= weight
& MTL_TXQ_WEIGHT_ISCQW_MASK
;
247 writel(value
, ioaddr
+ mtl_txqx_weight_base_addr(dwmac4_addrs
, queue
));
250 static void dwmac4_map_mtl_dma(struct mac_device_info
*hw
, u32 queue
, u32 chan
)
252 void __iomem
*ioaddr
= hw
->pcsr
;
256 value
= readl(ioaddr
+ MTL_RXQ_DMA_MAP0
);
257 value
&= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue
);
258 value
|= MTL_RXQ_DMA_QXMDMACH(chan
, queue
);
259 writel(value
, ioaddr
+ MTL_RXQ_DMA_MAP0
);
261 value
= readl(ioaddr
+ MTL_RXQ_DMA_MAP1
);
262 value
&= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue
- 4);
263 value
|= MTL_RXQ_DMA_QXMDMACH(chan
, queue
- 4);
264 writel(value
, ioaddr
+ MTL_RXQ_DMA_MAP1
);
268 static void dwmac4_config_cbs(struct stmmac_priv
*priv
,
269 struct mac_device_info
*hw
,
270 u32 send_slope
, u32 idle_slope
,
271 u32 high_credit
, u32 low_credit
, u32 queue
)
273 const struct dwmac4_addrs
*dwmac4_addrs
= priv
->plat
->dwmac4_addrs
;
274 void __iomem
*ioaddr
= hw
->pcsr
;
277 pr_debug("Queue %d configured as AVB. Parameters:\n", queue
);
278 pr_debug("\tsend_slope: 0x%08x\n", send_slope
);
279 pr_debug("\tidle_slope: 0x%08x\n", idle_slope
);
280 pr_debug("\thigh_credit: 0x%08x\n", high_credit
);
281 pr_debug("\tlow_credit: 0x%08x\n", low_credit
);
283 /* enable AV algorithm */
284 value
= readl(ioaddr
+ mtl_etsx_ctrl_base_addr(dwmac4_addrs
, queue
));
285 value
|= MTL_ETS_CTRL_AVALG
;
286 value
|= MTL_ETS_CTRL_CC
;
287 writel(value
, ioaddr
+ mtl_etsx_ctrl_base_addr(dwmac4_addrs
, queue
));
289 /* configure send slope */
290 value
= readl(ioaddr
+ mtl_send_slp_credx_base_addr(dwmac4_addrs
,
292 value
&= ~MTL_SEND_SLP_CRED_SSC_MASK
;
293 value
|= send_slope
& MTL_SEND_SLP_CRED_SSC_MASK
;
294 writel(value
, ioaddr
+ mtl_send_slp_credx_base_addr(dwmac4_addrs
,
297 /* configure idle slope (same register as tx weight) */
298 dwmac4_set_mtl_tx_queue_weight(priv
, hw
, idle_slope
, queue
);
300 /* configure high credit */
301 value
= readl(ioaddr
+ mtl_high_credx_base_addr(dwmac4_addrs
, queue
));
302 value
&= ~MTL_HIGH_CRED_HC_MASK
;
303 value
|= high_credit
& MTL_HIGH_CRED_HC_MASK
;
304 writel(value
, ioaddr
+ mtl_high_credx_base_addr(dwmac4_addrs
, queue
));
306 /* configure high credit */
307 value
= readl(ioaddr
+ mtl_low_credx_base_addr(dwmac4_addrs
, queue
));
308 value
&= ~MTL_HIGH_CRED_LC_MASK
;
309 value
|= low_credit
& MTL_HIGH_CRED_LC_MASK
;
310 writel(value
, ioaddr
+ mtl_low_credx_base_addr(dwmac4_addrs
, queue
));
313 static void dwmac4_dump_regs(struct mac_device_info
*hw
, u32
*reg_space
)
315 void __iomem
*ioaddr
= hw
->pcsr
;
318 for (i
= 0; i
< GMAC_REG_NUM
; i
++)
319 reg_space
[i
] = readl(ioaddr
+ i
* 4);
322 static int dwmac4_rx_ipc_enable(struct mac_device_info
*hw
)
324 void __iomem
*ioaddr
= hw
->pcsr
;
325 u32 value
= readl(ioaddr
+ GMAC_CONFIG
);
328 value
|= GMAC_CONFIG_IPC
;
330 value
&= ~GMAC_CONFIG_IPC
;
332 writel(value
, ioaddr
+ GMAC_CONFIG
);
334 value
= readl(ioaddr
+ GMAC_CONFIG
);
336 return !!(value
& GMAC_CONFIG_IPC
);
339 static void dwmac4_pmt(struct mac_device_info
*hw
, unsigned long mode
)
341 void __iomem
*ioaddr
= hw
->pcsr
;
342 unsigned int pmt
= 0;
345 if (mode
& WAKE_MAGIC
) {
346 pr_debug("GMAC: WOL Magic frame\n");
347 pmt
|= power_down
| magic_pkt_en
;
349 if (mode
& WAKE_UCAST
) {
350 pr_debug("GMAC: WOL on global unicast\n");
351 pmt
|= power_down
| global_unicast
| wake_up_frame_en
;
355 /* The receiver must be enabled for WOL before powering down */
356 config
= readl(ioaddr
+ GMAC_CONFIG
);
357 config
|= GMAC_CONFIG_RE
;
358 writel(config
, ioaddr
+ GMAC_CONFIG
);
360 writel(pmt
, ioaddr
+ GMAC_PMT
);
363 static void dwmac4_set_umac_addr(struct mac_device_info
*hw
,
364 const unsigned char *addr
, unsigned int reg_n
)
366 void __iomem
*ioaddr
= hw
->pcsr
;
368 stmmac_dwmac4_set_mac_addr(ioaddr
, addr
, GMAC_ADDR_HIGH(reg_n
),
369 GMAC_ADDR_LOW(reg_n
));
372 static void dwmac4_get_umac_addr(struct mac_device_info
*hw
,
373 unsigned char *addr
, unsigned int reg_n
)
375 void __iomem
*ioaddr
= hw
->pcsr
;
377 stmmac_dwmac4_get_mac_addr(ioaddr
, addr
, GMAC_ADDR_HIGH(reg_n
),
378 GMAC_ADDR_LOW(reg_n
));
381 static void dwmac4_set_eee_mode(struct mac_device_info
*hw
,
382 bool en_tx_lpi_clockgating
)
384 void __iomem
*ioaddr
= hw
->pcsr
;
387 /* Enable the link status receive on RGMII, SGMII ore SMII
388 * receive path and instruct the transmit to enter in LPI
391 value
= readl(ioaddr
+ GMAC4_LPI_CTRL_STATUS
);
392 value
|= GMAC4_LPI_CTRL_STATUS_LPIEN
| GMAC4_LPI_CTRL_STATUS_LPITXA
;
394 if (en_tx_lpi_clockgating
)
395 value
|= GMAC4_LPI_CTRL_STATUS_LPITCSE
;
397 writel(value
, ioaddr
+ GMAC4_LPI_CTRL_STATUS
);
400 static void dwmac4_reset_eee_mode(struct mac_device_info
*hw
)
402 void __iomem
*ioaddr
= hw
->pcsr
;
405 value
= readl(ioaddr
+ GMAC4_LPI_CTRL_STATUS
);
406 value
&= ~(GMAC4_LPI_CTRL_STATUS_LPIEN
| GMAC4_LPI_CTRL_STATUS_LPITXA
);
407 writel(value
, ioaddr
+ GMAC4_LPI_CTRL_STATUS
);
410 static void dwmac4_set_eee_pls(struct mac_device_info
*hw
, int link
)
412 void __iomem
*ioaddr
= hw
->pcsr
;
415 value
= readl(ioaddr
+ GMAC4_LPI_CTRL_STATUS
);
418 value
|= GMAC4_LPI_CTRL_STATUS_PLS
;
420 value
&= ~GMAC4_LPI_CTRL_STATUS_PLS
;
422 writel(value
, ioaddr
+ GMAC4_LPI_CTRL_STATUS
);
425 static void dwmac4_set_eee_lpi_entry_timer(struct mac_device_info
*hw
, int et
)
427 void __iomem
*ioaddr
= hw
->pcsr
;
428 int value
= et
& STMMAC_ET_MAX
;
431 /* Program LPI entry timer value into register */
432 writel(value
, ioaddr
+ GMAC4_LPI_ENTRY_TIMER
);
434 /* Enable/disable LPI entry timer */
435 regval
= readl(ioaddr
+ GMAC4_LPI_CTRL_STATUS
);
436 regval
|= GMAC4_LPI_CTRL_STATUS_LPIEN
| GMAC4_LPI_CTRL_STATUS_LPITXA
;
439 regval
|= GMAC4_LPI_CTRL_STATUS_LPIATE
;
441 regval
&= ~GMAC4_LPI_CTRL_STATUS_LPIATE
;
443 writel(regval
, ioaddr
+ GMAC4_LPI_CTRL_STATUS
);
446 static void dwmac4_set_eee_timer(struct mac_device_info
*hw
, int ls
, int tw
)
448 void __iomem
*ioaddr
= hw
->pcsr
;
449 int value
= ((tw
& 0xffff)) | ((ls
& 0x3ff) << 16);
451 /* Program the timers in the LPI timer control register:
452 * LS: minimum time (ms) for which the link
453 * status from PHY should be ok before transmitting
455 * TW: minimum time (us) for which the core waits
456 * after it has stopped transmitting the LPI pattern.
458 writel(value
, ioaddr
+ GMAC4_LPI_TIMER_CTRL
);
461 static void dwmac4_write_single_vlan(struct net_device
*dev
, u16 vid
)
463 void __iomem
*ioaddr
= (void __iomem
*)dev
->base_addr
;
466 val
= readl(ioaddr
+ GMAC_VLAN_TAG
);
467 val
&= ~GMAC_VLAN_TAG_VID
;
468 val
|= GMAC_VLAN_TAG_ETV
| vid
;
470 writel(val
, ioaddr
+ GMAC_VLAN_TAG
);
473 static int dwmac4_write_vlan_filter(struct net_device
*dev
,
474 struct mac_device_info
*hw
,
477 void __iomem
*ioaddr
= (void __iomem
*)dev
->base_addr
;
481 if (index
>= hw
->num_vlan
)
484 writel(data
, ioaddr
+ GMAC_VLAN_TAG_DATA
);
486 val
= readl(ioaddr
+ GMAC_VLAN_TAG
);
487 val
&= ~(GMAC_VLAN_TAG_CTRL_OFS_MASK
|
488 GMAC_VLAN_TAG_CTRL_CT
|
489 GMAC_VLAN_TAG_CTRL_OB
);
490 val
|= (index
<< GMAC_VLAN_TAG_CTRL_OFS_SHIFT
) | GMAC_VLAN_TAG_CTRL_OB
;
492 writel(val
, ioaddr
+ GMAC_VLAN_TAG
);
494 for (i
= 0; i
< timeout
; i
++) {
495 val
= readl(ioaddr
+ GMAC_VLAN_TAG
);
496 if (!(val
& GMAC_VLAN_TAG_CTRL_OB
))
501 netdev_err(dev
, "Timeout accessing MAC_VLAN_Tag_Filter\n");
506 static int dwmac4_add_hw_vlan_rx_fltr(struct net_device
*dev
,
507 struct mac_device_info
*hw
,
508 __be16 proto
, u16 vid
)
517 /* Single Rx VLAN Filter */
518 if (hw
->num_vlan
== 1) {
519 /* For single VLAN filter, VID 0 means VLAN promiscuous */
521 netdev_warn(dev
, "Adding VLAN ID 0 is not supported\n");
525 if (hw
->vlan_filter
[0] & GMAC_VLAN_TAG_VID
) {
526 netdev_err(dev
, "Only single VLAN ID supported\n");
530 hw
->vlan_filter
[0] = vid
;
531 dwmac4_write_single_vlan(dev
, vid
);
536 /* Extended Rx VLAN Filter Enable */
537 val
|= GMAC_VLAN_TAG_DATA_ETV
| GMAC_VLAN_TAG_DATA_VEN
| vid
;
539 for (i
= 0; i
< hw
->num_vlan
; i
++) {
540 if (hw
->vlan_filter
[i
] == val
)
542 else if (!(hw
->vlan_filter
[i
] & GMAC_VLAN_TAG_DATA_VEN
))
547 netdev_err(dev
, "MAC_VLAN_Tag_Filter full (size: %0u)\n",
552 ret
= dwmac4_write_vlan_filter(dev
, hw
, index
, val
);
555 hw
->vlan_filter
[index
] = val
;
560 static int dwmac4_del_hw_vlan_rx_fltr(struct net_device
*dev
,
561 struct mac_device_info
*hw
,
562 __be16 proto
, u16 vid
)
566 /* Single Rx VLAN Filter */
567 if (hw
->num_vlan
== 1) {
568 if ((hw
->vlan_filter
[0] & GMAC_VLAN_TAG_VID
) == vid
) {
569 hw
->vlan_filter
[0] = 0;
570 dwmac4_write_single_vlan(dev
, 0);
575 /* Extended Rx VLAN Filter Enable */
576 for (i
= 0; i
< hw
->num_vlan
; i
++) {
577 if ((hw
->vlan_filter
[i
] & GMAC_VLAN_TAG_DATA_VID
) == vid
) {
578 ret
= dwmac4_write_vlan_filter(dev
, hw
, i
, 0);
581 hw
->vlan_filter
[i
] = 0;
590 static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device
*dev
,
591 struct mac_device_info
*hw
)
593 void __iomem
*ioaddr
= hw
->pcsr
;
599 /* Single Rx VLAN Filter */
600 if (hw
->num_vlan
== 1) {
601 dwmac4_write_single_vlan(dev
, hw
->vlan_filter
[0]);
605 /* Extended Rx VLAN Filter Enable */
606 for (i
= 0; i
< hw
->num_vlan
; i
++) {
607 if (hw
->vlan_filter
[i
] & GMAC_VLAN_TAG_DATA_VEN
) {
608 val
= hw
->vlan_filter
[i
];
609 dwmac4_write_vlan_filter(dev
, hw
, i
, val
);
613 hash
= readl(ioaddr
+ GMAC_VLAN_HASH_TABLE
);
614 if (hash
& GMAC_VLAN_VLHT
) {
615 value
= readl(ioaddr
+ GMAC_VLAN_TAG
);
616 value
|= GMAC_VLAN_VTHM
;
617 writel(value
, ioaddr
+ GMAC_VLAN_TAG
);
621 static void dwmac4_set_filter(struct mac_device_info
*hw
,
622 struct net_device
*dev
)
624 void __iomem
*ioaddr
= (void __iomem
*)dev
->base_addr
;
625 int numhashregs
= (hw
->multicast_filter_bins
>> 5);
626 int mcbitslog2
= hw
->mcast_bits_log2
;
631 memset(mc_filter
, 0, sizeof(mc_filter
));
633 value
= readl(ioaddr
+ GMAC_PACKET_FILTER
);
634 value
&= ~GMAC_PACKET_FILTER_HMC
;
635 value
&= ~GMAC_PACKET_FILTER_HPF
;
636 value
&= ~GMAC_PACKET_FILTER_PCF
;
637 value
&= ~GMAC_PACKET_FILTER_PM
;
638 value
&= ~GMAC_PACKET_FILTER_PR
;
639 value
&= ~GMAC_PACKET_FILTER_RA
;
640 if (dev
->flags
& IFF_PROMISC
) {
641 /* VLAN Tag Filter Fail Packets Queuing */
642 if (hw
->vlan_fail_q_en
) {
643 value
= readl(ioaddr
+ GMAC_RXQ_CTRL4
);
644 value
&= ~GMAC_RXQCTRL_VFFQ_MASK
;
645 value
|= GMAC_RXQCTRL_VFFQE
|
646 (hw
->vlan_fail_q
<< GMAC_RXQCTRL_VFFQ_SHIFT
);
647 writel(value
, ioaddr
+ GMAC_RXQ_CTRL4
);
648 value
= GMAC_PACKET_FILTER_PR
| GMAC_PACKET_FILTER_RA
;
650 value
= GMAC_PACKET_FILTER_PR
| GMAC_PACKET_FILTER_PCF
;
653 } else if ((dev
->flags
& IFF_ALLMULTI
) ||
654 (netdev_mc_count(dev
) > hw
->multicast_filter_bins
)) {
656 value
|= GMAC_PACKET_FILTER_PM
;
657 /* Set all the bits of the HASH tab */
658 memset(mc_filter
, 0xff, sizeof(mc_filter
));
659 } else if (!netdev_mc_empty(dev
) && (dev
->flags
& IFF_MULTICAST
)) {
660 struct netdev_hw_addr
*ha
;
662 /* Hash filter for multicast */
663 value
|= GMAC_PACKET_FILTER_HMC
;
665 netdev_for_each_mc_addr(ha
, dev
) {
666 /* The upper n bits of the calculated CRC are used to
667 * index the contents of the hash table. The number of
668 * bits used depends on the hardware configuration
669 * selected at core configuration time.
671 u32 bit_nr
= bitrev32(~crc32_le(~0, ha
->addr
,
672 ETH_ALEN
)) >> (32 - mcbitslog2
);
673 /* The most significant bit determines the register to
674 * use (H/L) while the other 5 bits determine the bit
675 * within the register.
677 mc_filter
[bit_nr
>> 5] |= (1 << (bit_nr
& 0x1f));
681 for (i
= 0; i
< numhashregs
; i
++)
682 writel(mc_filter
[i
], ioaddr
+ GMAC_HASH_TAB(i
));
684 value
|= GMAC_PACKET_FILTER_HPF
;
686 /* Handle multiple unicast addresses */
687 if (netdev_uc_count(dev
) > hw
->unicast_filter_entries
) {
688 /* Switch to promiscuous mode if more than 128 addrs
691 value
|= GMAC_PACKET_FILTER_PR
;
693 struct netdev_hw_addr
*ha
;
696 netdev_for_each_uc_addr(ha
, dev
) {
697 dwmac4_set_umac_addr(hw
, ha
->addr
, reg
);
701 while (reg
< GMAC_MAX_PERFECT_ADDRESSES
) {
702 writel(0, ioaddr
+ GMAC_ADDR_HIGH(reg
));
703 writel(0, ioaddr
+ GMAC_ADDR_LOW(reg
));
709 if (dev
->flags
& IFF_PROMISC
&& !hw
->vlan_fail_q_en
)
710 value
&= ~GMAC_PACKET_FILTER_VTFE
;
711 else if (dev
->features
& NETIF_F_HW_VLAN_CTAG_FILTER
)
712 value
|= GMAC_PACKET_FILTER_VTFE
;
714 writel(value
, ioaddr
+ GMAC_PACKET_FILTER
);
717 static void dwmac4_flow_ctrl(struct mac_device_info
*hw
, unsigned int duplex
,
718 unsigned int fc
, unsigned int pause_time
,
721 void __iomem
*ioaddr
= hw
->pcsr
;
722 unsigned int flow
= 0;
725 pr_debug("GMAC Flow-Control:\n");
727 pr_debug("\tReceive Flow-Control ON\n");
728 flow
|= GMAC_RX_FLOW_CTRL_RFE
;
730 pr_debug("\tReceive Flow-Control OFF\n");
732 writel(flow
, ioaddr
+ GMAC_RX_FLOW_CTRL
);
735 pr_debug("\tTransmit Flow-Control ON\n");
738 pr_debug("\tduplex mode: PAUSE %d\n", pause_time
);
740 for (queue
= 0; queue
< tx_cnt
; queue
++) {
741 flow
= GMAC_TX_FLOW_CTRL_TFE
;
745 (pause_time
<< GMAC_TX_FLOW_CTRL_PT_SHIFT
);
747 writel(flow
, ioaddr
+ GMAC_QX_TX_FLOW_CTRL(queue
));
750 for (queue
= 0; queue
< tx_cnt
; queue
++)
751 writel(0, ioaddr
+ GMAC_QX_TX_FLOW_CTRL(queue
));
755 static void dwmac4_ctrl_ane(void __iomem
*ioaddr
, bool ane
, bool srgmi_ral
,
758 dwmac_ctrl_ane(ioaddr
, GMAC_PCS_BASE
, ane
, srgmi_ral
, loopback
);
761 static void dwmac4_rane(void __iomem
*ioaddr
, bool restart
)
763 dwmac_rane(ioaddr
, GMAC_PCS_BASE
, restart
);
766 static void dwmac4_get_adv_lp(void __iomem
*ioaddr
, struct rgmii_adv
*adv
)
768 dwmac_get_adv_lp(ioaddr
, GMAC_PCS_BASE
, adv
);
771 /* RGMII or SMII interface */
772 static void dwmac4_phystatus(void __iomem
*ioaddr
, struct stmmac_extra_stats
*x
)
776 status
= readl(ioaddr
+ GMAC_PHYIF_CONTROL_STATUS
);
779 /* Check the link status */
780 if (status
& GMAC_PHYIF_CTRLSTATUS_LNKSTS
) {
785 speed_value
= ((status
& GMAC_PHYIF_CTRLSTATUS_SPEED
) >>
786 GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT
);
787 if (speed_value
== GMAC_PHYIF_CTRLSTATUS_SPEED_125
)
788 x
->pcs_speed
= SPEED_1000
;
789 else if (speed_value
== GMAC_PHYIF_CTRLSTATUS_SPEED_25
)
790 x
->pcs_speed
= SPEED_100
;
792 x
->pcs_speed
= SPEED_10
;
794 x
->pcs_duplex
= (status
& GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK
);
796 pr_info("Link is Up - %d/%s\n", (int)x
->pcs_speed
,
797 x
->pcs_duplex
? "Full" : "Half");
800 pr_info("Link is Down\n");
804 static int dwmac4_irq_mtl_status(struct stmmac_priv
*priv
,
805 struct mac_device_info
*hw
, u32 chan
)
807 const struct dwmac4_addrs
*dwmac4_addrs
= priv
->plat
->dwmac4_addrs
;
808 void __iomem
*ioaddr
= hw
->pcsr
;
809 u32 mtl_int_qx_status
;
812 mtl_int_qx_status
= readl(ioaddr
+ MTL_INT_STATUS
);
814 /* Check MTL Interrupt */
815 if (mtl_int_qx_status
& MTL_INT_QX(chan
)) {
816 /* read Queue x Interrupt status */
817 u32 status
= readl(ioaddr
+ MTL_CHAN_INT_CTRL(dwmac4_addrs
,
820 if (status
& MTL_RX_OVERFLOW_INT
) {
821 /* clear Interrupt */
822 writel(status
| MTL_RX_OVERFLOW_INT
,
823 ioaddr
+ MTL_CHAN_INT_CTRL(dwmac4_addrs
, chan
));
824 ret
= CORE_IRQ_MTL_RX_OVERFLOW
;
831 static int dwmac4_irq_status(struct mac_device_info
*hw
,
832 struct stmmac_extra_stats
*x
)
834 void __iomem
*ioaddr
= hw
->pcsr
;
835 u32 intr_status
= readl(ioaddr
+ GMAC_INT_STATUS
);
836 u32 intr_enable
= readl(ioaddr
+ GMAC_INT_EN
);
839 /* Discard disabled bits */
840 intr_status
&= intr_enable
;
842 /* Not used events (e.g. MMC interrupts) are not handled. */
843 if ((intr_status
& mmc_tx_irq
))
845 if (unlikely(intr_status
& mmc_rx_irq
))
847 if (unlikely(intr_status
& mmc_rx_csum_offload_irq
))
848 x
->mmc_rx_csum_offload_irq_n
++;
849 /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
850 if (unlikely(intr_status
& pmt_irq
)) {
851 readl(ioaddr
+ GMAC_PMT
);
852 x
->irq_receive_pmt_irq_n
++;
855 /* MAC tx/rx EEE LPI entry/exit interrupts */
856 if (intr_status
& lpi_irq
) {
857 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
858 u32 status
= readl(ioaddr
+ GMAC4_LPI_CTRL_STATUS
);
860 if (status
& GMAC4_LPI_CTRL_STATUS_TLPIEN
) {
861 ret
|= CORE_IRQ_TX_PATH_IN_LPI_MODE
;
862 x
->irq_tx_path_in_lpi_mode_n
++;
864 if (status
& GMAC4_LPI_CTRL_STATUS_TLPIEX
) {
865 ret
|= CORE_IRQ_TX_PATH_EXIT_LPI_MODE
;
866 x
->irq_tx_path_exit_lpi_mode_n
++;
868 if (status
& GMAC4_LPI_CTRL_STATUS_RLPIEN
)
869 x
->irq_rx_path_in_lpi_mode_n
++;
870 if (status
& GMAC4_LPI_CTRL_STATUS_RLPIEX
)
871 x
->irq_rx_path_exit_lpi_mode_n
++;
874 dwmac_pcs_isr(ioaddr
, GMAC_PCS_BASE
, intr_status
, x
);
875 if (intr_status
& PCS_RGSMIIIS_IRQ
)
876 dwmac4_phystatus(ioaddr
, x
);
881 static void dwmac4_debug(struct stmmac_priv
*priv
, void __iomem
*ioaddr
,
882 struct stmmac_extra_stats
*x
,
883 u32 rx_queues
, u32 tx_queues
)
885 const struct dwmac4_addrs
*dwmac4_addrs
= priv
->plat
->dwmac4_addrs
;
889 for (queue
= 0; queue
< tx_queues
; queue
++) {
890 value
= readl(ioaddr
+ MTL_CHAN_TX_DEBUG(dwmac4_addrs
, queue
));
892 if (value
& MTL_DEBUG_TXSTSFSTS
)
893 x
->mtl_tx_status_fifo_full
++;
894 if (value
& MTL_DEBUG_TXFSTS
)
895 x
->mtl_tx_fifo_not_empty
++;
896 if (value
& MTL_DEBUG_TWCSTS
)
898 if (value
& MTL_DEBUG_TRCSTS_MASK
) {
899 u32 trcsts
= (value
& MTL_DEBUG_TRCSTS_MASK
)
900 >> MTL_DEBUG_TRCSTS_SHIFT
;
901 if (trcsts
== MTL_DEBUG_TRCSTS_WRITE
)
902 x
->mtl_tx_fifo_read_ctrl_write
++;
903 else if (trcsts
== MTL_DEBUG_TRCSTS_TXW
)
904 x
->mtl_tx_fifo_read_ctrl_wait
++;
905 else if (trcsts
== MTL_DEBUG_TRCSTS_READ
)
906 x
->mtl_tx_fifo_read_ctrl_read
++;
908 x
->mtl_tx_fifo_read_ctrl_idle
++;
910 if (value
& MTL_DEBUG_TXPAUSED
)
911 x
->mac_tx_in_pause
++;
914 for (queue
= 0; queue
< rx_queues
; queue
++) {
915 value
= readl(ioaddr
+ MTL_CHAN_RX_DEBUG(dwmac4_addrs
, queue
));
917 if (value
& MTL_DEBUG_RXFSTS_MASK
) {
918 u32 rxfsts
= (value
& MTL_DEBUG_RXFSTS_MASK
)
919 >> MTL_DEBUG_RRCSTS_SHIFT
;
921 if (rxfsts
== MTL_DEBUG_RXFSTS_FULL
)
922 x
->mtl_rx_fifo_fill_level_full
++;
923 else if (rxfsts
== MTL_DEBUG_RXFSTS_AT
)
924 x
->mtl_rx_fifo_fill_above_thresh
++;
925 else if (rxfsts
== MTL_DEBUG_RXFSTS_BT
)
926 x
->mtl_rx_fifo_fill_below_thresh
++;
928 x
->mtl_rx_fifo_fill_level_empty
++;
930 if (value
& MTL_DEBUG_RRCSTS_MASK
) {
931 u32 rrcsts
= (value
& MTL_DEBUG_RRCSTS_MASK
) >>
932 MTL_DEBUG_RRCSTS_SHIFT
;
934 if (rrcsts
== MTL_DEBUG_RRCSTS_FLUSH
)
935 x
->mtl_rx_fifo_read_ctrl_flush
++;
936 else if (rrcsts
== MTL_DEBUG_RRCSTS_RSTAT
)
937 x
->mtl_rx_fifo_read_ctrl_read_data
++;
938 else if (rrcsts
== MTL_DEBUG_RRCSTS_RDATA
)
939 x
->mtl_rx_fifo_read_ctrl_status
++;
941 x
->mtl_rx_fifo_read_ctrl_idle
++;
943 if (value
& MTL_DEBUG_RWCSTS
)
944 x
->mtl_rx_fifo_ctrl_active
++;
948 value
= readl(ioaddr
+ GMAC_DEBUG
);
950 if (value
& GMAC_DEBUG_TFCSTS_MASK
) {
951 u32 tfcsts
= (value
& GMAC_DEBUG_TFCSTS_MASK
)
952 >> GMAC_DEBUG_TFCSTS_SHIFT
;
954 if (tfcsts
== GMAC_DEBUG_TFCSTS_XFER
)
955 x
->mac_tx_frame_ctrl_xfer
++;
956 else if (tfcsts
== GMAC_DEBUG_TFCSTS_GEN_PAUSE
)
957 x
->mac_tx_frame_ctrl_pause
++;
958 else if (tfcsts
== GMAC_DEBUG_TFCSTS_WAIT
)
959 x
->mac_tx_frame_ctrl_wait
++;
961 x
->mac_tx_frame_ctrl_idle
++;
963 if (value
& GMAC_DEBUG_TPESTS
)
964 x
->mac_gmii_tx_proto_engine
++;
965 if (value
& GMAC_DEBUG_RFCFCSTS_MASK
)
966 x
->mac_rx_frame_ctrl_fifo
= (value
& GMAC_DEBUG_RFCFCSTS_MASK
)
967 >> GMAC_DEBUG_RFCFCSTS_SHIFT
;
968 if (value
& GMAC_DEBUG_RPESTS
)
969 x
->mac_gmii_rx_proto_engine
++;
972 static void dwmac4_set_mac_loopback(void __iomem
*ioaddr
, bool enable
)
974 u32 value
= readl(ioaddr
+ GMAC_CONFIG
);
977 value
|= GMAC_CONFIG_LM
;
979 value
&= ~GMAC_CONFIG_LM
;
981 writel(value
, ioaddr
+ GMAC_CONFIG
);
984 static void dwmac4_update_vlan_hash(struct mac_device_info
*hw
, u32 hash
,
985 __le16 perfect_match
, bool is_double
)
987 void __iomem
*ioaddr
= hw
->pcsr
;
990 writel(hash
, ioaddr
+ GMAC_VLAN_HASH_TABLE
);
992 value
= readl(ioaddr
+ GMAC_VLAN_TAG
);
995 value
|= GMAC_VLAN_VTHM
| GMAC_VLAN_ETV
;
997 value
|= GMAC_VLAN_EDVLP
;
998 value
|= GMAC_VLAN_ESVL
;
999 value
|= GMAC_VLAN_DOVLTC
;
1002 writel(value
, ioaddr
+ GMAC_VLAN_TAG
);
1003 } else if (perfect_match
) {
1004 u32 value
= GMAC_VLAN_ETV
;
1007 value
|= GMAC_VLAN_EDVLP
;
1008 value
|= GMAC_VLAN_ESVL
;
1009 value
|= GMAC_VLAN_DOVLTC
;
1012 writel(value
| perfect_match
, ioaddr
+ GMAC_VLAN_TAG
);
1014 value
&= ~(GMAC_VLAN_VTHM
| GMAC_VLAN_ETV
);
1015 value
&= ~(GMAC_VLAN_EDVLP
| GMAC_VLAN_ESVL
);
1016 value
&= ~GMAC_VLAN_DOVLTC
;
1017 value
&= ~GMAC_VLAN_VID
;
1019 writel(value
, ioaddr
+ GMAC_VLAN_TAG
);
1023 static void dwmac4_sarc_configure(void __iomem
*ioaddr
, int val
)
1025 u32 value
= readl(ioaddr
+ GMAC_CONFIG
);
1027 value
&= ~GMAC_CONFIG_SARC
;
1028 value
|= val
<< GMAC_CONFIG_SARC_SHIFT
;
1030 writel(value
, ioaddr
+ GMAC_CONFIG
);
1033 static void dwmac4_enable_vlan(struct mac_device_info
*hw
, u32 type
)
1035 void __iomem
*ioaddr
= hw
->pcsr
;
1038 value
= readl(ioaddr
+ GMAC_VLAN_INCL
);
1039 value
|= GMAC_VLAN_VLTI
;
1040 value
|= GMAC_VLAN_CSVL
; /* Only use SVLAN */
1041 value
&= ~GMAC_VLAN_VLC
;
1042 value
|= (type
<< GMAC_VLAN_VLC_SHIFT
) & GMAC_VLAN_VLC
;
1043 writel(value
, ioaddr
+ GMAC_VLAN_INCL
);
1046 static void dwmac4_set_arp_offload(struct mac_device_info
*hw
, bool en
,
1049 void __iomem
*ioaddr
= hw
->pcsr
;
1052 writel(addr
, ioaddr
+ GMAC_ARP_ADDR
);
1054 value
= readl(ioaddr
+ GMAC_CONFIG
);
1056 value
|= GMAC_CONFIG_ARPEN
;
1058 value
&= ~GMAC_CONFIG_ARPEN
;
1059 writel(value
, ioaddr
+ GMAC_CONFIG
);
1062 static int dwmac4_config_l3_filter(struct mac_device_info
*hw
, u32 filter_no
,
1063 bool en
, bool ipv6
, bool sa
, bool inv
,
1066 void __iomem
*ioaddr
= hw
->pcsr
;
1069 value
= readl(ioaddr
+ GMAC_PACKET_FILTER
);
1070 value
|= GMAC_PACKET_FILTER_IPFE
;
1071 writel(value
, ioaddr
+ GMAC_PACKET_FILTER
);
1073 value
= readl(ioaddr
+ GMAC_L3L4_CTRL(filter_no
));
1075 /* For IPv6 not both SA/DA filters can be active */
1077 value
|= GMAC_L3PEN0
;
1078 value
&= ~(GMAC_L3SAM0
| GMAC_L3SAIM0
);
1079 value
&= ~(GMAC_L3DAM0
| GMAC_L3DAIM0
);
1081 value
|= GMAC_L3SAM0
;
1083 value
|= GMAC_L3SAIM0
;
1085 value
|= GMAC_L3DAM0
;
1087 value
|= GMAC_L3DAIM0
;
1090 value
&= ~GMAC_L3PEN0
;
1092 value
|= GMAC_L3SAM0
;
1094 value
|= GMAC_L3SAIM0
;
1096 value
|= GMAC_L3DAM0
;
1098 value
|= GMAC_L3DAIM0
;
1102 writel(value
, ioaddr
+ GMAC_L3L4_CTRL(filter_no
));
1105 writel(match
, ioaddr
+ GMAC_L3_ADDR0(filter_no
));
1107 writel(match
, ioaddr
+ GMAC_L3_ADDR1(filter_no
));
1111 writel(0, ioaddr
+ GMAC_L3L4_CTRL(filter_no
));
1116 static int dwmac4_config_l4_filter(struct mac_device_info
*hw
, u32 filter_no
,
1117 bool en
, bool udp
, bool sa
, bool inv
,
1120 void __iomem
*ioaddr
= hw
->pcsr
;
1123 value
= readl(ioaddr
+ GMAC_PACKET_FILTER
);
1124 value
|= GMAC_PACKET_FILTER_IPFE
;
1125 writel(value
, ioaddr
+ GMAC_PACKET_FILTER
);
1127 value
= readl(ioaddr
+ GMAC_L3L4_CTRL(filter_no
));
1129 value
|= GMAC_L4PEN0
;
1131 value
&= ~GMAC_L4PEN0
;
1134 value
&= ~(GMAC_L4SPM0
| GMAC_L4SPIM0
);
1135 value
&= ~(GMAC_L4DPM0
| GMAC_L4DPIM0
);
1137 value
|= GMAC_L4SPM0
;
1139 value
|= GMAC_L4SPIM0
;
1141 value
|= GMAC_L4DPM0
;
1143 value
|= GMAC_L4DPIM0
;
1146 writel(value
, ioaddr
+ GMAC_L3L4_CTRL(filter_no
));
1149 value
= match
& GMAC_L4SP0
;
1151 value
= (match
<< GMAC_L4DP0_SHIFT
) & GMAC_L4DP0
;
1154 writel(value
, ioaddr
+ GMAC_L4_ADDR(filter_no
));
1157 writel(0, ioaddr
+ GMAC_L3L4_CTRL(filter_no
));
1162 static void dwmac4_rx_hw_vlan(struct mac_device_info
*hw
,
1163 struct dma_desc
*rx_desc
, struct sk_buff
*skb
)
1165 if (hw
->desc
->get_rx_vlan_valid(rx_desc
)) {
1166 u16 vid
= hw
->desc
->get_rx_vlan_tci(rx_desc
);
1168 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vid
);
1172 static void dwmac4_set_hw_vlan_mode(struct mac_device_info
*hw
)
1174 void __iomem
*ioaddr
= hw
->pcsr
;
1175 u32 value
= readl(ioaddr
+ GMAC_VLAN_TAG
);
1177 value
&= ~GMAC_VLAN_TAG_CTRL_EVLS_MASK
;
1180 /* Always strip VLAN on Receive */
1181 value
|= GMAC_VLAN_TAG_STRIP_ALL
;
1183 /* Do not strip VLAN on Receive */
1184 value
|= GMAC_VLAN_TAG_STRIP_NONE
;
1186 /* Enable outer VLAN Tag in Rx DMA descriptor */
1187 value
|= GMAC_VLAN_TAG_CTRL_EVLRXS
;
1188 writel(value
, ioaddr
+ GMAC_VLAN_TAG
);
1191 const struct stmmac_ops dwmac4_ops
= {
1192 .core_init
= dwmac4_core_init
,
1193 .update_caps
= dwmac4_update_caps
,
1194 .set_mac
= stmmac_set_mac
,
1195 .rx_ipc
= dwmac4_rx_ipc_enable
,
1196 .rx_queue_enable
= dwmac4_rx_queue_enable
,
1197 .rx_queue_prio
= dwmac4_rx_queue_priority
,
1198 .tx_queue_prio
= dwmac4_tx_queue_priority
,
1199 .rx_queue_routing
= dwmac4_rx_queue_routing
,
1200 .prog_mtl_rx_algorithms
= dwmac4_prog_mtl_rx_algorithms
,
1201 .prog_mtl_tx_algorithms
= dwmac4_prog_mtl_tx_algorithms
,
1202 .set_mtl_tx_queue_weight
= dwmac4_set_mtl_tx_queue_weight
,
1203 .map_mtl_to_dma
= dwmac4_map_mtl_dma
,
1204 .config_cbs
= dwmac4_config_cbs
,
1205 .dump_regs
= dwmac4_dump_regs
,
1206 .host_irq_status
= dwmac4_irq_status
,
1207 .host_mtl_irq_status
= dwmac4_irq_mtl_status
,
1208 .flow_ctrl
= dwmac4_flow_ctrl
,
1210 .set_umac_addr
= dwmac4_set_umac_addr
,
1211 .get_umac_addr
= dwmac4_get_umac_addr
,
1212 .set_eee_mode
= dwmac4_set_eee_mode
,
1213 .reset_eee_mode
= dwmac4_reset_eee_mode
,
1214 .set_eee_lpi_entry_timer
= dwmac4_set_eee_lpi_entry_timer
,
1215 .set_eee_timer
= dwmac4_set_eee_timer
,
1216 .set_eee_pls
= dwmac4_set_eee_pls
,
1217 .pcs_ctrl_ane
= dwmac4_ctrl_ane
,
1218 .pcs_rane
= dwmac4_rane
,
1219 .pcs_get_adv_lp
= dwmac4_get_adv_lp
,
1220 .debug
= dwmac4_debug
,
1221 .set_filter
= dwmac4_set_filter
,
1222 .set_mac_loopback
= dwmac4_set_mac_loopback
,
1223 .update_vlan_hash
= dwmac4_update_vlan_hash
,
1224 .sarc_configure
= dwmac4_sarc_configure
,
1225 .enable_vlan
= dwmac4_enable_vlan
,
1226 .set_arp_offload
= dwmac4_set_arp_offload
,
1227 .config_l3_filter
= dwmac4_config_l3_filter
,
1228 .config_l4_filter
= dwmac4_config_l4_filter
,
1229 .add_hw_vlan_rx_fltr
= dwmac4_add_hw_vlan_rx_fltr
,
1230 .del_hw_vlan_rx_fltr
= dwmac4_del_hw_vlan_rx_fltr
,
1231 .restore_hw_vlan_rx_fltr
= dwmac4_restore_hw_vlan_rx_fltr
,
1232 .rx_hw_vlan
= dwmac4_rx_hw_vlan
,
1233 .set_hw_vlan_mode
= dwmac4_set_hw_vlan_mode
,
1236 const struct stmmac_ops dwmac410_ops
= {
1237 .core_init
= dwmac4_core_init
,
1238 .update_caps
= dwmac4_update_caps
,
1239 .set_mac
= stmmac_dwmac4_set_mac
,
1240 .rx_ipc
= dwmac4_rx_ipc_enable
,
1241 .rx_queue_enable
= dwmac4_rx_queue_enable
,
1242 .rx_queue_prio
= dwmac4_rx_queue_priority
,
1243 .tx_queue_prio
= dwmac4_tx_queue_priority
,
1244 .rx_queue_routing
= dwmac4_rx_queue_routing
,
1245 .prog_mtl_rx_algorithms
= dwmac4_prog_mtl_rx_algorithms
,
1246 .prog_mtl_tx_algorithms
= dwmac4_prog_mtl_tx_algorithms
,
1247 .set_mtl_tx_queue_weight
= dwmac4_set_mtl_tx_queue_weight
,
1248 .map_mtl_to_dma
= dwmac4_map_mtl_dma
,
1249 .config_cbs
= dwmac4_config_cbs
,
1250 .dump_regs
= dwmac4_dump_regs
,
1251 .host_irq_status
= dwmac4_irq_status
,
1252 .host_mtl_irq_status
= dwmac4_irq_mtl_status
,
1253 .flow_ctrl
= dwmac4_flow_ctrl
,
1255 .set_umac_addr
= dwmac4_set_umac_addr
,
1256 .get_umac_addr
= dwmac4_get_umac_addr
,
1257 .set_eee_mode
= dwmac4_set_eee_mode
,
1258 .reset_eee_mode
= dwmac4_reset_eee_mode
,
1259 .set_eee_lpi_entry_timer
= dwmac4_set_eee_lpi_entry_timer
,
1260 .set_eee_timer
= dwmac4_set_eee_timer
,
1261 .set_eee_pls
= dwmac4_set_eee_pls
,
1262 .pcs_ctrl_ane
= dwmac4_ctrl_ane
,
1263 .pcs_rane
= dwmac4_rane
,
1264 .pcs_get_adv_lp
= dwmac4_get_adv_lp
,
1265 .debug
= dwmac4_debug
,
1266 .set_filter
= dwmac4_set_filter
,
1267 .flex_pps_config
= dwmac5_flex_pps_config
,
1268 .set_mac_loopback
= dwmac4_set_mac_loopback
,
1269 .update_vlan_hash
= dwmac4_update_vlan_hash
,
1270 .sarc_configure
= dwmac4_sarc_configure
,
1271 .enable_vlan
= dwmac4_enable_vlan
,
1272 .set_arp_offload
= dwmac4_set_arp_offload
,
1273 .config_l3_filter
= dwmac4_config_l3_filter
,
1274 .config_l4_filter
= dwmac4_config_l4_filter
,
1275 .fpe_configure
= dwmac5_fpe_configure
,
1276 .fpe_send_mpacket
= dwmac5_fpe_send_mpacket
,
1277 .fpe_irq_status
= dwmac5_fpe_irq_status
,
1278 .add_hw_vlan_rx_fltr
= dwmac4_add_hw_vlan_rx_fltr
,
1279 .del_hw_vlan_rx_fltr
= dwmac4_del_hw_vlan_rx_fltr
,
1280 .restore_hw_vlan_rx_fltr
= dwmac4_restore_hw_vlan_rx_fltr
,
1281 .rx_hw_vlan
= dwmac4_rx_hw_vlan
,
1282 .set_hw_vlan_mode
= dwmac4_set_hw_vlan_mode
,
1285 const struct stmmac_ops dwmac510_ops
= {
1286 .core_init
= dwmac4_core_init
,
1287 .update_caps
= dwmac4_update_caps
,
1288 .set_mac
= stmmac_dwmac4_set_mac
,
1289 .rx_ipc
= dwmac4_rx_ipc_enable
,
1290 .rx_queue_enable
= dwmac4_rx_queue_enable
,
1291 .rx_queue_prio
= dwmac4_rx_queue_priority
,
1292 .tx_queue_prio
= dwmac4_tx_queue_priority
,
1293 .rx_queue_routing
= dwmac4_rx_queue_routing
,
1294 .prog_mtl_rx_algorithms
= dwmac4_prog_mtl_rx_algorithms
,
1295 .prog_mtl_tx_algorithms
= dwmac4_prog_mtl_tx_algorithms
,
1296 .set_mtl_tx_queue_weight
= dwmac4_set_mtl_tx_queue_weight
,
1297 .map_mtl_to_dma
= dwmac4_map_mtl_dma
,
1298 .config_cbs
= dwmac4_config_cbs
,
1299 .dump_regs
= dwmac4_dump_regs
,
1300 .host_irq_status
= dwmac4_irq_status
,
1301 .host_mtl_irq_status
= dwmac4_irq_mtl_status
,
1302 .flow_ctrl
= dwmac4_flow_ctrl
,
1304 .set_umac_addr
= dwmac4_set_umac_addr
,
1305 .get_umac_addr
= dwmac4_get_umac_addr
,
1306 .set_eee_mode
= dwmac4_set_eee_mode
,
1307 .reset_eee_mode
= dwmac4_reset_eee_mode
,
1308 .set_eee_lpi_entry_timer
= dwmac4_set_eee_lpi_entry_timer
,
1309 .set_eee_timer
= dwmac4_set_eee_timer
,
1310 .set_eee_pls
= dwmac4_set_eee_pls
,
1311 .pcs_ctrl_ane
= dwmac4_ctrl_ane
,
1312 .pcs_rane
= dwmac4_rane
,
1313 .pcs_get_adv_lp
= dwmac4_get_adv_lp
,
1314 .debug
= dwmac4_debug
,
1315 .set_filter
= dwmac4_set_filter
,
1316 .safety_feat_config
= dwmac5_safety_feat_config
,
1317 .safety_feat_irq_status
= dwmac5_safety_feat_irq_status
,
1318 .safety_feat_dump
= dwmac5_safety_feat_dump
,
1319 .rxp_config
= dwmac5_rxp_config
,
1320 .flex_pps_config
= dwmac5_flex_pps_config
,
1321 .set_mac_loopback
= dwmac4_set_mac_loopback
,
1322 .update_vlan_hash
= dwmac4_update_vlan_hash
,
1323 .sarc_configure
= dwmac4_sarc_configure
,
1324 .enable_vlan
= dwmac4_enable_vlan
,
1325 .set_arp_offload
= dwmac4_set_arp_offload
,
1326 .config_l3_filter
= dwmac4_config_l3_filter
,
1327 .config_l4_filter
= dwmac4_config_l4_filter
,
1328 .fpe_configure
= dwmac5_fpe_configure
,
1329 .fpe_send_mpacket
= dwmac5_fpe_send_mpacket
,
1330 .fpe_irq_status
= dwmac5_fpe_irq_status
,
1331 .add_hw_vlan_rx_fltr
= dwmac4_add_hw_vlan_rx_fltr
,
1332 .del_hw_vlan_rx_fltr
= dwmac4_del_hw_vlan_rx_fltr
,
1333 .restore_hw_vlan_rx_fltr
= dwmac4_restore_hw_vlan_rx_fltr
,
1334 .rx_hw_vlan
= dwmac4_rx_hw_vlan
,
1335 .set_hw_vlan_mode
= dwmac4_set_hw_vlan_mode
,
1338 static u32
dwmac4_get_num_vlan(void __iomem
*ioaddr
)
1342 val
= readl(ioaddr
+ GMAC_HW_FEATURE3
);
1343 switch (val
& GMAC_HW_FEAT_NRVF
) {
1369 int dwmac4_setup(struct stmmac_priv
*priv
)
1371 struct mac_device_info
*mac
= priv
->hw
;
1373 dev_info(priv
->device
, "\tDWMAC4/5\n");
1375 priv
->dev
->priv_flags
|= IFF_UNICAST_FLT
;
1376 mac
->pcsr
= priv
->ioaddr
;
1377 mac
->multicast_filter_bins
= priv
->plat
->multicast_filter_bins
;
1378 mac
->unicast_filter_entries
= priv
->plat
->unicast_filter_entries
;
1379 mac
->mcast_bits_log2
= 0;
1381 if (mac
->multicast_filter_bins
)
1382 mac
->mcast_bits_log2
= ilog2(mac
->multicast_filter_bins
);
1384 mac
->link
.caps
= MAC_ASYM_PAUSE
| MAC_SYM_PAUSE
|
1385 MAC_10
| MAC_100
| MAC_1000
| MAC_2500FD
;
1386 mac
->link
.duplex
= GMAC_CONFIG_DM
;
1387 mac
->link
.speed10
= GMAC_CONFIG_PS
;
1388 mac
->link
.speed100
= GMAC_CONFIG_FES
| GMAC_CONFIG_PS
;
1389 mac
->link
.speed1000
= 0;
1390 mac
->link
.speed2500
= GMAC_CONFIG_FES
;
1391 mac
->link
.speed_mask
= GMAC_CONFIG_FES
| GMAC_CONFIG_PS
;
1392 mac
->mii
.addr
= GMAC_MDIO_ADDR
;
1393 mac
->mii
.data
= GMAC_MDIO_DATA
;
1394 mac
->mii
.addr_shift
= 21;
1395 mac
->mii
.addr_mask
= GENMASK(25, 21);
1396 mac
->mii
.reg_shift
= 16;
1397 mac
->mii
.reg_mask
= GENMASK(20, 16);
1398 mac
->mii
.clk_csr_shift
= 8;
1399 mac
->mii
.clk_csr_mask
= GENMASK(11, 8);
1400 mac
->num_vlan
= dwmac4_get_num_vlan(priv
->ioaddr
);