1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 The full GNU General Public License is included in this distribution in
17 the file called "COPYING".
19 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21 Documentation available at:
22 http://www.stlinux.com
24 https://bugzilla.stlinux.com/
25 *******************************************************************************/
27 #include <linux/clk.h>
28 #include <linux/kernel.h>
29 #include <linux/interrupt.h>
31 #include <linux/tcp.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/if_ether.h>
35 #include <linux/crc32.h>
36 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/prefetch.h>
42 #include <linux/pinctrl/consumer.h>
43 #ifdef CONFIG_DEBUG_FS
44 #include <linux/debugfs.h>
45 #include <linux/seq_file.h>
46 #endif /* CONFIG_DEBUG_FS */
47 #include <linux/net_tstamp.h>
48 #include "stmmac_ptp.h"
50 #include <linux/reset.h>
51 #include <linux/of_mdio.h>
52 #include "dwmac1000.h"
54 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
55 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
57 /* Module parameters */
59 static int watchdog
= TX_TIMEO
;
60 module_param(watchdog
, int, 0644);
61 MODULE_PARM_DESC(watchdog
, "Transmit timeout in milliseconds (default 5s)");
63 static int debug
= -1;
64 module_param(debug
, int, 0644);
65 MODULE_PARM_DESC(debug
, "Message Level (-1: default, 0: no output, 16: all)");
67 static int phyaddr
= -1;
68 module_param(phyaddr
, int, 0444);
69 MODULE_PARM_DESC(phyaddr
, "Physical device address");
71 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
72 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
74 static int flow_ctrl
= FLOW_OFF
;
75 module_param(flow_ctrl
, int, 0644);
76 MODULE_PARM_DESC(flow_ctrl
, "Flow control ability [on/off]");
78 static int pause
= PAUSE_TIME
;
79 module_param(pause
, int, 0644);
80 MODULE_PARM_DESC(pause
, "Flow Control Pause Time");
83 static int tc
= TC_DEFAULT
;
84 module_param(tc
, int, 0644);
85 MODULE_PARM_DESC(tc
, "DMA threshold control value");
87 #define DEFAULT_BUFSIZE 1536
88 static int buf_sz
= DEFAULT_BUFSIZE
;
89 module_param(buf_sz
, int, 0644);
90 MODULE_PARM_DESC(buf_sz
, "DMA buffer size");
92 #define STMMAC_RX_COPYBREAK 256
94 static const u32 default_msg_level
= (NETIF_MSG_DRV
| NETIF_MSG_PROBE
|
95 NETIF_MSG_LINK
| NETIF_MSG_IFUP
|
96 NETIF_MSG_IFDOWN
| NETIF_MSG_TIMER
);
98 #define STMMAC_DEFAULT_LPI_TIMER 1000
99 static int eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
100 module_param(eee_timer
, int, 0644);
101 MODULE_PARM_DESC(eee_timer
, "LPI tx expiration time in msec");
102 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
104 /* By default the driver will use the ring mode to manage tx and rx descriptors,
105 * but allow user to force to use the chain instead of the ring
107 static unsigned int chain_mode
;
108 module_param(chain_mode
, int, 0444);
109 MODULE_PARM_DESC(chain_mode
, "To use chain instead of ring mode");
111 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
);
113 #ifdef CONFIG_DEBUG_FS
114 static int stmmac_init_fs(struct net_device
*dev
);
115 static void stmmac_exit_fs(struct net_device
*dev
);
118 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
121 * stmmac_verify_args - verify the driver parameters.
122 * Description: it checks the driver parameters and set a default in case of
125 static void stmmac_verify_args(void)
127 if (unlikely(watchdog
< 0))
129 if (unlikely((buf_sz
< DEFAULT_BUFSIZE
) || (buf_sz
> BUF_SIZE_16KiB
)))
130 buf_sz
= DEFAULT_BUFSIZE
;
131 if (unlikely(flow_ctrl
> 1))
132 flow_ctrl
= FLOW_AUTO
;
133 else if (likely(flow_ctrl
< 0))
134 flow_ctrl
= FLOW_OFF
;
135 if (unlikely((pause
< 0) || (pause
> 0xffff)))
138 eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
142 * stmmac_disable_all_queues - Disable all queues
143 * @priv: driver private structure
145 static void stmmac_disable_all_queues(struct stmmac_priv
*priv
)
147 u32 rx_queues_cnt
= priv
->plat
->rx_queues_to_use
;
150 for (queue
= 0; queue
< rx_queues_cnt
; queue
++) {
151 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
153 napi_disable(&rx_q
->napi
);
158 * stmmac_enable_all_queues - Enable all queues
159 * @priv: driver private structure
161 static void stmmac_enable_all_queues(struct stmmac_priv
*priv
)
163 u32 rx_queues_cnt
= priv
->plat
->rx_queues_to_use
;
166 for (queue
= 0; queue
< rx_queues_cnt
; queue
++) {
167 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
169 napi_enable(&rx_q
->napi
);
174 * stmmac_stop_all_queues - Stop all queues
175 * @priv: driver private structure
177 static void stmmac_stop_all_queues(struct stmmac_priv
*priv
)
179 u32 tx_queues_cnt
= priv
->plat
->tx_queues_to_use
;
182 for (queue
= 0; queue
< tx_queues_cnt
; queue
++)
183 netif_tx_stop_queue(netdev_get_tx_queue(priv
->dev
, queue
));
187 * stmmac_start_all_queues - Start all queues
188 * @priv: driver private structure
190 static void stmmac_start_all_queues(struct stmmac_priv
*priv
)
192 u32 tx_queues_cnt
= priv
->plat
->tx_queues_to_use
;
195 for (queue
= 0; queue
< tx_queues_cnt
; queue
++)
196 netif_tx_start_queue(netdev_get_tx_queue(priv
->dev
, queue
));
199 static void stmmac_service_event_schedule(struct stmmac_priv
*priv
)
201 if (!test_bit(STMMAC_DOWN
, &priv
->state
) &&
202 !test_and_set_bit(STMMAC_SERVICE_SCHED
, &priv
->state
))
203 queue_work(priv
->wq
, &priv
->service_task
);
206 static void stmmac_global_err(struct stmmac_priv
*priv
)
208 netif_carrier_off(priv
->dev
);
209 set_bit(STMMAC_RESET_REQUESTED
, &priv
->state
);
210 stmmac_service_event_schedule(priv
);
214 * stmmac_clk_csr_set - dynamically set the MDC clock
215 * @priv: driver private structure
216 * Description: this is to dynamically set the MDC clock according to the csr
219 * If a specific clk_csr value is passed from the platform
220 * this means that the CSR Clock Range selection cannot be
221 * changed at run-time and it is fixed (as reported in the driver
222 * documentation). Viceversa the driver will try to set the MDC
223 * clock dynamically according to the actual clock input.
225 static void stmmac_clk_csr_set(struct stmmac_priv
*priv
)
229 clk_rate
= clk_get_rate(priv
->plat
->stmmac_clk
);
231 /* Platform provided default clk_csr would be assumed valid
232 * for all other cases except for the below mentioned ones.
233 * For values higher than the IEEE 802.3 specified frequency
234 * we can not estimate the proper divider as it is not known
235 * the frequency of clk_csr_i. So we do not change the default
238 if (!(priv
->clk_csr
& MAC_CSR_H_FRQ_MASK
)) {
239 if (clk_rate
< CSR_F_35M
)
240 priv
->clk_csr
= STMMAC_CSR_20_35M
;
241 else if ((clk_rate
>= CSR_F_35M
) && (clk_rate
< CSR_F_60M
))
242 priv
->clk_csr
= STMMAC_CSR_35_60M
;
243 else if ((clk_rate
>= CSR_F_60M
) && (clk_rate
< CSR_F_100M
))
244 priv
->clk_csr
= STMMAC_CSR_60_100M
;
245 else if ((clk_rate
>= CSR_F_100M
) && (clk_rate
< CSR_F_150M
))
246 priv
->clk_csr
= STMMAC_CSR_100_150M
;
247 else if ((clk_rate
>= CSR_F_150M
) && (clk_rate
< CSR_F_250M
))
248 priv
->clk_csr
= STMMAC_CSR_150_250M
;
249 else if ((clk_rate
>= CSR_F_250M
) && (clk_rate
< CSR_F_300M
))
250 priv
->clk_csr
= STMMAC_CSR_250_300M
;
253 if (priv
->plat
->has_sun8i
) {
254 if (clk_rate
> 160000000)
255 priv
->clk_csr
= 0x03;
256 else if (clk_rate
> 80000000)
257 priv
->clk_csr
= 0x02;
258 else if (clk_rate
> 40000000)
259 priv
->clk_csr
= 0x01;
265 static void print_pkt(unsigned char *buf
, int len
)
267 pr_debug("len = %d byte, buf addr: 0x%p\n", len
, buf
);
268 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
, buf
, len
);
271 static inline u32
stmmac_tx_avail(struct stmmac_priv
*priv
, u32 queue
)
273 struct stmmac_tx_queue
*tx_q
= &priv
->tx_queue
[queue
];
276 if (tx_q
->dirty_tx
> tx_q
->cur_tx
)
277 avail
= tx_q
->dirty_tx
- tx_q
->cur_tx
- 1;
279 avail
= DMA_TX_SIZE
- tx_q
->cur_tx
+ tx_q
->dirty_tx
- 1;
285 * stmmac_rx_dirty - Get RX queue dirty
286 * @priv: driver private structure
287 * @queue: RX queue index
289 static inline u32
stmmac_rx_dirty(struct stmmac_priv
*priv
, u32 queue
)
291 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
294 if (rx_q
->dirty_rx
<= rx_q
->cur_rx
)
295 dirty
= rx_q
->cur_rx
- rx_q
->dirty_rx
;
297 dirty
= DMA_RX_SIZE
- rx_q
->dirty_rx
+ rx_q
->cur_rx
;
303 * stmmac_hw_fix_mac_speed - callback for speed selection
304 * @priv: driver private structure
305 * Description: on some platforms (e.g. ST), some HW system configuration
306 * registers have to be set according to the link speed negotiated.
308 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv
*priv
)
310 struct net_device
*ndev
= priv
->dev
;
311 struct phy_device
*phydev
= ndev
->phydev
;
313 if (likely(priv
->plat
->fix_mac_speed
))
314 priv
->plat
->fix_mac_speed(priv
->plat
->bsp_priv
, phydev
->speed
);
318 * stmmac_enable_eee_mode - check and enter in LPI mode
319 * @priv: driver private structure
320 * Description: this function is to verify and enter in LPI mode in case of
323 static void stmmac_enable_eee_mode(struct stmmac_priv
*priv
)
325 u32 tx_cnt
= priv
->plat
->tx_queues_to_use
;
328 /* check if all TX queues have the work finished */
329 for (queue
= 0; queue
< tx_cnt
; queue
++) {
330 struct stmmac_tx_queue
*tx_q
= &priv
->tx_queue
[queue
];
332 if (tx_q
->dirty_tx
!= tx_q
->cur_tx
)
333 return; /* still unfinished work */
336 /* Check and enter in LPI mode */
337 if (!priv
->tx_path_in_lpi_mode
)
338 priv
->hw
->mac
->set_eee_mode(priv
->hw
,
339 priv
->plat
->en_tx_lpi_clockgating
);
343 * stmmac_disable_eee_mode - disable and exit from LPI mode
344 * @priv: driver private structure
345 * Description: this function is to exit and disable EEE in case of
346 * LPI state is true. This is called by the xmit.
348 void stmmac_disable_eee_mode(struct stmmac_priv
*priv
)
350 priv
->hw
->mac
->reset_eee_mode(priv
->hw
);
351 del_timer_sync(&priv
->eee_ctrl_timer
);
352 priv
->tx_path_in_lpi_mode
= false;
356 * stmmac_eee_ctrl_timer - EEE TX SW timer.
359 * if there is no data transfer and if we are not in LPI state,
360 * then MAC Transmitter can be moved to LPI state.
362 static void stmmac_eee_ctrl_timer(struct timer_list
*t
)
364 struct stmmac_priv
*priv
= from_timer(priv
, t
, eee_ctrl_timer
);
366 stmmac_enable_eee_mode(priv
);
367 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
371 * stmmac_eee_init - init EEE
372 * @priv: driver private structure
374 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
375 * can also manage EEE, this function enable the LPI state and start related
378 bool stmmac_eee_init(struct stmmac_priv
*priv
)
380 struct net_device
*ndev
= priv
->dev
;
381 int interface
= priv
->plat
->interface
;
385 if ((interface
!= PHY_INTERFACE_MODE_MII
) &&
386 (interface
!= PHY_INTERFACE_MODE_GMII
) &&
387 !phy_interface_mode_is_rgmii(interface
))
390 /* Using PCS we cannot dial with the phy registers at this stage
391 * so we do not support extra feature like EEE.
393 if ((priv
->hw
->pcs
== STMMAC_PCS_RGMII
) ||
394 (priv
->hw
->pcs
== STMMAC_PCS_TBI
) ||
395 (priv
->hw
->pcs
== STMMAC_PCS_RTBI
))
398 /* MAC core supports the EEE feature. */
399 if (priv
->dma_cap
.eee
) {
400 int tx_lpi_timer
= priv
->tx_lpi_timer
;
402 /* Check if the PHY supports EEE */
403 if (phy_init_eee(ndev
->phydev
, 1)) {
404 /* To manage at run-time if the EEE cannot be supported
405 * anymore (for example because the lp caps have been
407 * In that case the driver disable own timers.
409 spin_lock_irqsave(&priv
->lock
, flags
);
410 if (priv
->eee_active
) {
411 netdev_dbg(priv
->dev
, "disable EEE\n");
412 del_timer_sync(&priv
->eee_ctrl_timer
);
413 priv
->hw
->mac
->set_eee_timer(priv
->hw
, 0,
416 priv
->eee_active
= 0;
417 spin_unlock_irqrestore(&priv
->lock
, flags
);
420 /* Activate the EEE and start timers */
421 spin_lock_irqsave(&priv
->lock
, flags
);
422 if (!priv
->eee_active
) {
423 priv
->eee_active
= 1;
424 timer_setup(&priv
->eee_ctrl_timer
,
425 stmmac_eee_ctrl_timer
, 0);
426 mod_timer(&priv
->eee_ctrl_timer
,
427 STMMAC_LPI_T(eee_timer
));
429 priv
->hw
->mac
->set_eee_timer(priv
->hw
,
430 STMMAC_DEFAULT_LIT_LS
,
433 /* Set HW EEE according to the speed */
434 priv
->hw
->mac
->set_eee_pls(priv
->hw
, ndev
->phydev
->link
);
437 spin_unlock_irqrestore(&priv
->lock
, flags
);
439 netdev_dbg(priv
->dev
, "Energy-Efficient Ethernet initialized\n");
445 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
446 * @priv: driver private structure
447 * @p : descriptor pointer
448 * @skb : the socket buffer
450 * This function will read timestamp from the descriptor & pass it to stack.
451 * and also perform some sanity checks.
453 static void stmmac_get_tx_hwtstamp(struct stmmac_priv
*priv
,
454 struct dma_desc
*p
, struct sk_buff
*skb
)
456 struct skb_shared_hwtstamps shhwtstamp
;
459 if (!priv
->hwts_tx_en
)
462 /* exit if skb doesn't support hw tstamp */
463 if (likely(!skb
|| !(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)))
466 /* check tx tstamp status */
467 if (priv
->hw
->desc
->get_tx_timestamp_status(p
)) {
468 /* get the valid tstamp */
469 ns
= priv
->hw
->desc
->get_timestamp(p
, priv
->adv_ts
);
471 memset(&shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
472 shhwtstamp
.hwtstamp
= ns_to_ktime(ns
);
474 netdev_dbg(priv
->dev
, "get valid TX hw timestamp %llu\n", ns
);
475 /* pass tstamp to stack */
476 skb_tstamp_tx(skb
, &shhwtstamp
);
482 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
483 * @priv: driver private structure
484 * @p : descriptor pointer
485 * @np : next descriptor pointer
486 * @skb : the socket buffer
488 * This function will read received packet's timestamp from the descriptor
489 * and pass it to stack. It also perform some sanity checks.
491 static void stmmac_get_rx_hwtstamp(struct stmmac_priv
*priv
, struct dma_desc
*p
,
492 struct dma_desc
*np
, struct sk_buff
*skb
)
494 struct skb_shared_hwtstamps
*shhwtstamp
= NULL
;
495 struct dma_desc
*desc
= p
;
498 if (!priv
->hwts_rx_en
)
500 /* For GMAC4, the valid timestamp is from CTX next desc. */
501 if (priv
->plat
->has_gmac4
)
504 /* Check if timestamp is available */
505 if (priv
->hw
->desc
->get_rx_timestamp_status(p
, np
, priv
->adv_ts
)) {
506 ns
= priv
->hw
->desc
->get_timestamp(desc
, priv
->adv_ts
);
507 netdev_dbg(priv
->dev
, "get valid RX hw timestamp %llu\n", ns
);
508 shhwtstamp
= skb_hwtstamps(skb
);
509 memset(shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
510 shhwtstamp
->hwtstamp
= ns_to_ktime(ns
);
512 netdev_dbg(priv
->dev
, "cannot get RX hw timestamp\n");
517 * stmmac_hwtstamp_ioctl - control hardware timestamping.
518 * @dev: device pointer.
519 * @ifr: An IOCTL specific structure, that can contain a pointer to
520 * a proprietary structure used to pass information to the driver.
522 * This function configures the MAC to enable/disable both outgoing(TX)
523 * and incoming(RX) packets time stamping based on user input.
525 * 0 on success and an appropriate -ve integer on failure.
527 static int stmmac_hwtstamp_ioctl(struct net_device
*dev
, struct ifreq
*ifr
)
529 struct stmmac_priv
*priv
= netdev_priv(dev
);
530 struct hwtstamp_config config
;
531 struct timespec64 now
;
535 u32 ptp_over_ipv4_udp
= 0;
536 u32 ptp_over_ipv6_udp
= 0;
537 u32 ptp_over_ethernet
= 0;
538 u32 snap_type_sel
= 0;
539 u32 ts_master_en
= 0;
544 if (!(priv
->dma_cap
.time_stamp
|| priv
->adv_ts
)) {
545 netdev_alert(priv
->dev
, "No support for HW time stamping\n");
546 priv
->hwts_tx_en
= 0;
547 priv
->hwts_rx_en
= 0;
552 if (copy_from_user(&config
, ifr
->ifr_data
,
553 sizeof(struct hwtstamp_config
)))
556 netdev_dbg(priv
->dev
, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
557 __func__
, config
.flags
, config
.tx_type
, config
.rx_filter
);
559 /* reserved for future extensions */
563 if (config
.tx_type
!= HWTSTAMP_TX_OFF
&&
564 config
.tx_type
!= HWTSTAMP_TX_ON
)
568 switch (config
.rx_filter
) {
569 case HWTSTAMP_FILTER_NONE
:
570 /* time stamp no incoming packet at all */
571 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
574 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
575 /* PTP v1, UDP, any kind of event packet */
576 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
577 /* take time stamp for all event messages */
578 if (priv
->plat
->has_gmac4
)
579 snap_type_sel
= PTP_GMAC4_TCR_SNAPTYPSEL_1
;
581 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
583 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
584 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
587 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
588 /* PTP v1, UDP, Sync packet */
589 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_SYNC
;
590 /* take time stamp for SYNC messages only */
591 ts_event_en
= PTP_TCR_TSEVNTENA
;
593 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
594 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
597 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
598 /* PTP v1, UDP, Delay_req packet */
599 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
;
600 /* take time stamp for Delay_Req messages only */
601 ts_master_en
= PTP_TCR_TSMSTRENA
;
602 ts_event_en
= PTP_TCR_TSEVNTENA
;
604 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
605 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
608 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
609 /* PTP v2, UDP, any kind of event packet */
610 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_EVENT
;
611 ptp_v2
= PTP_TCR_TSVER2ENA
;
612 /* take time stamp for all event messages */
613 if (priv
->plat
->has_gmac4
)
614 snap_type_sel
= PTP_GMAC4_TCR_SNAPTYPSEL_1
;
616 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
618 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
619 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
622 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
623 /* PTP v2, UDP, Sync packet */
624 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_SYNC
;
625 ptp_v2
= PTP_TCR_TSVER2ENA
;
626 /* take time stamp for SYNC messages only */
627 ts_event_en
= PTP_TCR_TSEVNTENA
;
629 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
630 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
633 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
634 /* PTP v2, UDP, Delay_req packet */
635 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
;
636 ptp_v2
= PTP_TCR_TSVER2ENA
;
637 /* take time stamp for Delay_Req messages only */
638 ts_master_en
= PTP_TCR_TSMSTRENA
;
639 ts_event_en
= PTP_TCR_TSEVNTENA
;
641 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
642 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
645 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
646 /* PTP v2/802.AS1 any layer, any kind of event packet */
647 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
648 ptp_v2
= PTP_TCR_TSVER2ENA
;
649 /* take time stamp for all event messages */
650 if (priv
->plat
->has_gmac4
)
651 snap_type_sel
= PTP_GMAC4_TCR_SNAPTYPSEL_1
;
653 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
655 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
656 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
657 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
660 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
661 /* PTP v2/802.AS1, any layer, Sync packet */
662 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_SYNC
;
663 ptp_v2
= PTP_TCR_TSVER2ENA
;
664 /* take time stamp for SYNC messages only */
665 ts_event_en
= PTP_TCR_TSEVNTENA
;
667 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
668 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
669 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
672 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
673 /* PTP v2/802.AS1, any layer, Delay_req packet */
674 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
;
675 ptp_v2
= PTP_TCR_TSVER2ENA
;
676 /* take time stamp for Delay_Req messages only */
677 ts_master_en
= PTP_TCR_TSMSTRENA
;
678 ts_event_en
= PTP_TCR_TSEVNTENA
;
680 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
681 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
682 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
685 case HWTSTAMP_FILTER_NTP_ALL
:
686 case HWTSTAMP_FILTER_ALL
:
687 /* time stamp any incoming packet */
688 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
689 tstamp_all
= PTP_TCR_TSENALL
;
696 switch (config
.rx_filter
) {
697 case HWTSTAMP_FILTER_NONE
:
698 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
701 /* PTP v1, UDP, any kind of event packet */
702 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
706 priv
->hwts_rx_en
= ((config
.rx_filter
== HWTSTAMP_FILTER_NONE
) ? 0 : 1);
707 priv
->hwts_tx_en
= config
.tx_type
== HWTSTAMP_TX_ON
;
709 if (!priv
->hwts_tx_en
&& !priv
->hwts_rx_en
)
710 priv
->hw
->ptp
->config_hw_tstamping(priv
->ptpaddr
, 0);
712 value
= (PTP_TCR_TSENA
| PTP_TCR_TSCFUPDT
| PTP_TCR_TSCTRLSSR
|
713 tstamp_all
| ptp_v2
| ptp_over_ethernet
|
714 ptp_over_ipv6_udp
| ptp_over_ipv4_udp
| ts_event_en
|
715 ts_master_en
| snap_type_sel
);
716 priv
->hw
->ptp
->config_hw_tstamping(priv
->ptpaddr
, value
);
718 /* program Sub Second Increment reg */
719 sec_inc
= priv
->hw
->ptp
->config_sub_second_increment(
720 priv
->ptpaddr
, priv
->plat
->clk_ptp_rate
,
721 priv
->plat
->has_gmac4
);
722 temp
= div_u64(1000000000ULL, sec_inc
);
724 /* calculate default added value:
726 * addend = (2^32)/freq_div_ratio;
727 * where, freq_div_ratio = 1e9ns/sec_inc
729 temp
= (u64
)(temp
<< 32);
730 priv
->default_addend
= div_u64(temp
, priv
->plat
->clk_ptp_rate
);
731 priv
->hw
->ptp
->config_addend(priv
->ptpaddr
,
732 priv
->default_addend
);
734 /* initialize system time */
735 ktime_get_real_ts64(&now
);
737 /* lower 32 bits of tv_sec are safe until y2106 */
738 priv
->hw
->ptp
->init_systime(priv
->ptpaddr
, (u32
)now
.tv_sec
,
742 return copy_to_user(ifr
->ifr_data
, &config
,
743 sizeof(struct hwtstamp_config
)) ? -EFAULT
: 0;
747 * stmmac_init_ptp - init PTP
748 * @priv: driver private structure
749 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
750 * This is done by looking at the HW cap. register.
751 * This function also registers the ptp driver.
753 static int stmmac_init_ptp(struct stmmac_priv
*priv
)
755 if (!(priv
->dma_cap
.time_stamp
|| priv
->dma_cap
.atime_stamp
))
759 /* Check if adv_ts can be enabled for dwmac 4.x core */
760 if (priv
->plat
->has_gmac4
&& priv
->dma_cap
.atime_stamp
)
762 /* Dwmac 3.x core with extend_desc can support adv_ts */
763 else if (priv
->extend_desc
&& priv
->dma_cap
.atime_stamp
)
766 if (priv
->dma_cap
.time_stamp
)
767 netdev_info(priv
->dev
, "IEEE 1588-2002 Timestamp supported\n");
770 netdev_info(priv
->dev
,
771 "IEEE 1588-2008 Advanced Timestamp supported\n");
773 priv
->hw
->ptp
= &stmmac_ptp
;
774 priv
->hwts_tx_en
= 0;
775 priv
->hwts_rx_en
= 0;
777 stmmac_ptp_register(priv
);
782 static void stmmac_release_ptp(struct stmmac_priv
*priv
)
784 if (priv
->plat
->clk_ptp_ref
)
785 clk_disable_unprepare(priv
->plat
->clk_ptp_ref
);
786 stmmac_ptp_unregister(priv
);
790 * stmmac_mac_flow_ctrl - Configure flow control in all queues
791 * @priv: driver private structure
792 * Description: It is used for configuring the flow control in all queues
794 static void stmmac_mac_flow_ctrl(struct stmmac_priv
*priv
, u32 duplex
)
796 u32 tx_cnt
= priv
->plat
->tx_queues_to_use
;
798 priv
->hw
->mac
->flow_ctrl(priv
->hw
, duplex
, priv
->flow_ctrl
,
799 priv
->pause
, tx_cnt
);
803 * stmmac_adjust_link - adjusts the link parameters
804 * @dev: net device structure
805 * Description: this is the helper called by the physical abstraction layer
806 * drivers to communicate the phy link status. According the speed and duplex
807 * this driver can invoke registered glue-logic as well.
808 * It also invoke the eee initialization because it could happen when switch
809 * on different networks (that are eee capable).
811 static void stmmac_adjust_link(struct net_device
*dev
)
813 struct stmmac_priv
*priv
= netdev_priv(dev
);
814 struct phy_device
*phydev
= dev
->phydev
;
816 bool new_state
= false;
821 spin_lock_irqsave(&priv
->lock
, flags
);
824 u32 ctrl
= readl(priv
->ioaddr
+ MAC_CTRL_REG
);
826 /* Now we make sure that we can be in full duplex mode.
827 * If not, we operate in half-duplex mode. */
828 if (phydev
->duplex
!= priv
->oldduplex
) {
831 ctrl
&= ~priv
->hw
->link
.duplex
;
833 ctrl
|= priv
->hw
->link
.duplex
;
834 priv
->oldduplex
= phydev
->duplex
;
836 /* Flow Control operation */
838 stmmac_mac_flow_ctrl(priv
, phydev
->duplex
);
840 if (phydev
->speed
!= priv
->speed
) {
842 ctrl
&= ~priv
->hw
->link
.speed_mask
;
843 switch (phydev
->speed
) {
845 ctrl
|= priv
->hw
->link
.speed1000
;
848 ctrl
|= priv
->hw
->link
.speed100
;
851 ctrl
|= priv
->hw
->link
.speed10
;
854 netif_warn(priv
, link
, priv
->dev
,
855 "broken speed: %d\n", phydev
->speed
);
856 phydev
->speed
= SPEED_UNKNOWN
;
859 if (phydev
->speed
!= SPEED_UNKNOWN
)
860 stmmac_hw_fix_mac_speed(priv
);
861 priv
->speed
= phydev
->speed
;
864 writel(ctrl
, priv
->ioaddr
+ MAC_CTRL_REG
);
866 if (!priv
->oldlink
) {
868 priv
->oldlink
= true;
870 } else if (priv
->oldlink
) {
872 priv
->oldlink
= false;
873 priv
->speed
= SPEED_UNKNOWN
;
874 priv
->oldduplex
= DUPLEX_UNKNOWN
;
877 if (new_state
&& netif_msg_link(priv
))
878 phy_print_status(phydev
);
880 spin_unlock_irqrestore(&priv
->lock
, flags
);
882 if (phydev
->is_pseudo_fixed_link
)
883 /* Stop PHY layer to call the hook to adjust the link in case
884 * of a switch is attached to the stmmac driver.
886 phydev
->irq
= PHY_IGNORE_INTERRUPT
;
888 /* At this stage, init the EEE if supported.
889 * Never called in case of fixed_link.
891 priv
->eee_enabled
= stmmac_eee_init(priv
);
895 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
896 * @priv: driver private structure
897 * Description: this is to verify if the HW supports the PCS.
898 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
899 * configured for the TBI, RTBI, or SGMII PHY interface.
901 static void stmmac_check_pcs_mode(struct stmmac_priv
*priv
)
903 int interface
= priv
->plat
->interface
;
905 if (priv
->dma_cap
.pcs
) {
906 if ((interface
== PHY_INTERFACE_MODE_RGMII
) ||
907 (interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
908 (interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
909 (interface
== PHY_INTERFACE_MODE_RGMII_TXID
)) {
910 netdev_dbg(priv
->dev
, "PCS RGMII support enabled\n");
911 priv
->hw
->pcs
= STMMAC_PCS_RGMII
;
912 } else if (interface
== PHY_INTERFACE_MODE_SGMII
) {
913 netdev_dbg(priv
->dev
, "PCS SGMII support enabled\n");
914 priv
->hw
->pcs
= STMMAC_PCS_SGMII
;
920 * stmmac_init_phy - PHY initialization
921 * @dev: net device structure
922 * Description: it initializes the driver's PHY state, and attaches the PHY
927 static int stmmac_init_phy(struct net_device
*dev
)
929 struct stmmac_priv
*priv
= netdev_priv(dev
);
930 struct phy_device
*phydev
;
931 char phy_id_fmt
[MII_BUS_ID_SIZE
+ 3];
932 char bus_id
[MII_BUS_ID_SIZE
];
933 int interface
= priv
->plat
->interface
;
934 int max_speed
= priv
->plat
->max_speed
;
935 priv
->oldlink
= false;
936 priv
->speed
= SPEED_UNKNOWN
;
937 priv
->oldduplex
= DUPLEX_UNKNOWN
;
939 if (priv
->plat
->phy_node
) {
940 phydev
= of_phy_connect(dev
, priv
->plat
->phy_node
,
941 &stmmac_adjust_link
, 0, interface
);
943 snprintf(bus_id
, MII_BUS_ID_SIZE
, "stmmac-%x",
946 snprintf(phy_id_fmt
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, bus_id
,
947 priv
->plat
->phy_addr
);
948 netdev_dbg(priv
->dev
, "%s: trying to attach to %s\n", __func__
,
951 phydev
= phy_connect(dev
, phy_id_fmt
, &stmmac_adjust_link
,
955 if (IS_ERR_OR_NULL(phydev
)) {
956 netdev_err(priv
->dev
, "Could not attach to PHY\n");
960 return PTR_ERR(phydev
);
963 /* Stop Advertising 1000BASE Capability if interface is not GMII */
964 if ((interface
== PHY_INTERFACE_MODE_MII
) ||
965 (interface
== PHY_INTERFACE_MODE_RMII
) ||
966 (max_speed
< 1000 && max_speed
> 0))
967 phydev
->advertising
&= ~(SUPPORTED_1000baseT_Half
|
968 SUPPORTED_1000baseT_Full
);
971 * Broken HW is sometimes missing the pull-up resistor on the
972 * MDIO line, which results in reads to non-existent devices returning
973 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
975 * Note: phydev->phy_id is the result of reading the UID PHY registers.
977 if (!priv
->plat
->phy_node
&& phydev
->phy_id
== 0) {
978 phy_disconnect(phydev
);
982 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
983 * subsequent PHY polling, make sure we force a link transition if
984 * we have a UP/DOWN/UP transition
986 if (phydev
->is_pseudo_fixed_link
)
987 phydev
->irq
= PHY_POLL
;
989 phy_attached_info(phydev
);
993 static void stmmac_display_rx_rings(struct stmmac_priv
*priv
)
995 u32 rx_cnt
= priv
->plat
->rx_queues_to_use
;
999 /* Display RX rings */
1000 for (queue
= 0; queue
< rx_cnt
; queue
++) {
1001 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
1003 pr_info("\tRX Queue %u rings\n", queue
);
1005 if (priv
->extend_desc
)
1006 head_rx
= (void *)rx_q
->dma_erx
;
1008 head_rx
= (void *)rx_q
->dma_rx
;
1010 /* Display RX ring */
1011 priv
->hw
->desc
->display_ring(head_rx
, DMA_RX_SIZE
, true);
1015 static void stmmac_display_tx_rings(struct stmmac_priv
*priv
)
1017 u32 tx_cnt
= priv
->plat
->tx_queues_to_use
;
1021 /* Display TX rings */
1022 for (queue
= 0; queue
< tx_cnt
; queue
++) {
1023 struct stmmac_tx_queue
*tx_q
= &priv
->tx_queue
[queue
];
1025 pr_info("\tTX Queue %d rings\n", queue
);
1027 if (priv
->extend_desc
)
1028 head_tx
= (void *)tx_q
->dma_etx
;
1030 head_tx
= (void *)tx_q
->dma_tx
;
1032 priv
->hw
->desc
->display_ring(head_tx
, DMA_TX_SIZE
, false);
1036 static void stmmac_display_rings(struct stmmac_priv
*priv
)
1038 /* Display RX ring */
1039 stmmac_display_rx_rings(priv
);
1041 /* Display TX ring */
1042 stmmac_display_tx_rings(priv
);
1045 static int stmmac_set_bfsize(int mtu
, int bufsize
)
1049 if (mtu
>= BUF_SIZE_4KiB
)
1050 ret
= BUF_SIZE_8KiB
;
1051 else if (mtu
>= BUF_SIZE_2KiB
)
1052 ret
= BUF_SIZE_4KiB
;
1053 else if (mtu
> DEFAULT_BUFSIZE
)
1054 ret
= BUF_SIZE_2KiB
;
1056 ret
= DEFAULT_BUFSIZE
;
1062 * stmmac_clear_rx_descriptors - clear RX descriptors
1063 * @priv: driver private structure
1064 * @queue: RX queue index
1065 * Description: this function is called to clear the RX descriptors
1066 * in case of both basic and extended descriptors are used.
1068 static void stmmac_clear_rx_descriptors(struct stmmac_priv
*priv
, u32 queue
)
1070 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
1073 /* Clear the RX descriptors */
1074 for (i
= 0; i
< DMA_RX_SIZE
; i
++)
1075 if (priv
->extend_desc
)
1076 priv
->hw
->desc
->init_rx_desc(&rx_q
->dma_erx
[i
].basic
,
1077 priv
->use_riwt
, priv
->mode
,
1078 (i
== DMA_RX_SIZE
- 1));
1080 priv
->hw
->desc
->init_rx_desc(&rx_q
->dma_rx
[i
],
1081 priv
->use_riwt
, priv
->mode
,
1082 (i
== DMA_RX_SIZE
- 1));
1086 * stmmac_clear_tx_descriptors - clear tx descriptors
1087 * @priv: driver private structure
1088 * @queue: TX queue index.
1089 * Description: this function is called to clear the TX descriptors
1090 * in case of both basic and extended descriptors are used.
1092 static void stmmac_clear_tx_descriptors(struct stmmac_priv
*priv
, u32 queue
)
1094 struct stmmac_tx_queue
*tx_q
= &priv
->tx_queue
[queue
];
1097 /* Clear the TX descriptors */
1098 for (i
= 0; i
< DMA_TX_SIZE
; i
++)
1099 if (priv
->extend_desc
)
1100 priv
->hw
->desc
->init_tx_desc(&tx_q
->dma_etx
[i
].basic
,
1102 (i
== DMA_TX_SIZE
- 1));
1104 priv
->hw
->desc
->init_tx_desc(&tx_q
->dma_tx
[i
],
1106 (i
== DMA_TX_SIZE
- 1));
1110 * stmmac_clear_descriptors - clear descriptors
1111 * @priv: driver private structure
1112 * Description: this function is called to clear the TX and RX descriptors
1113 * in case of both basic and extended descriptors are used.
1115 static void stmmac_clear_descriptors(struct stmmac_priv
*priv
)
1117 u32 rx_queue_cnt
= priv
->plat
->rx_queues_to_use
;
1118 u32 tx_queue_cnt
= priv
->plat
->tx_queues_to_use
;
1121 /* Clear the RX descriptors */
1122 for (queue
= 0; queue
< rx_queue_cnt
; queue
++)
1123 stmmac_clear_rx_descriptors(priv
, queue
);
1125 /* Clear the TX descriptors */
1126 for (queue
= 0; queue
< tx_queue_cnt
; queue
++)
1127 stmmac_clear_tx_descriptors(priv
, queue
);
1131 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1132 * @priv: driver private structure
1133 * @p: descriptor pointer
1134 * @i: descriptor index
1136 * @queue: RX queue index
1137 * Description: this function is called to allocate a receive buffer, perform
1138 * the DMA mapping and init the descriptor.
1140 static int stmmac_init_rx_buffers(struct stmmac_priv
*priv
, struct dma_desc
*p
,
1141 int i
, gfp_t flags
, u32 queue
)
1143 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
1144 struct sk_buff
*skb
;
1146 skb
= __netdev_alloc_skb_ip_align(priv
->dev
, priv
->dma_buf_sz
, flags
);
1148 netdev_err(priv
->dev
,
1149 "%s: Rx init fails; skb is NULL\n", __func__
);
1152 rx_q
->rx_skbuff
[i
] = skb
;
1153 rx_q
->rx_skbuff_dma
[i
] = dma_map_single(priv
->device
, skb
->data
,
1156 if (dma_mapping_error(priv
->device
, rx_q
->rx_skbuff_dma
[i
])) {
1157 netdev_err(priv
->dev
, "%s: DMA mapping error\n", __func__
);
1158 dev_kfree_skb_any(skb
);
1162 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
)
1163 p
->des0
= cpu_to_le32(rx_q
->rx_skbuff_dma
[i
]);
1165 p
->des2
= cpu_to_le32(rx_q
->rx_skbuff_dma
[i
]);
1167 if ((priv
->hw
->mode
->init_desc3
) &&
1168 (priv
->dma_buf_sz
== BUF_SIZE_16KiB
))
1169 priv
->hw
->mode
->init_desc3(p
);
1175 * stmmac_free_rx_buffer - free RX dma buffers
1176 * @priv: private structure
1177 * @queue: RX queue index
1180 static void stmmac_free_rx_buffer(struct stmmac_priv
*priv
, u32 queue
, int i
)
1182 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
1184 if (rx_q
->rx_skbuff
[i
]) {
1185 dma_unmap_single(priv
->device
, rx_q
->rx_skbuff_dma
[i
],
1186 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
1187 dev_kfree_skb_any(rx_q
->rx_skbuff
[i
]);
1189 rx_q
->rx_skbuff
[i
] = NULL
;
1193 * stmmac_free_tx_buffer - free RX dma buffers
1194 * @priv: private structure
1195 * @queue: RX queue index
1198 static void stmmac_free_tx_buffer(struct stmmac_priv
*priv
, u32 queue
, int i
)
1200 struct stmmac_tx_queue
*tx_q
= &priv
->tx_queue
[queue
];
1202 if (tx_q
->tx_skbuff_dma
[i
].buf
) {
1203 if (tx_q
->tx_skbuff_dma
[i
].map_as_page
)
1204 dma_unmap_page(priv
->device
,
1205 tx_q
->tx_skbuff_dma
[i
].buf
,
1206 tx_q
->tx_skbuff_dma
[i
].len
,
1209 dma_unmap_single(priv
->device
,
1210 tx_q
->tx_skbuff_dma
[i
].buf
,
1211 tx_q
->tx_skbuff_dma
[i
].len
,
1215 if (tx_q
->tx_skbuff
[i
]) {
1216 dev_kfree_skb_any(tx_q
->tx_skbuff
[i
]);
1217 tx_q
->tx_skbuff
[i
] = NULL
;
1218 tx_q
->tx_skbuff_dma
[i
].buf
= 0;
1219 tx_q
->tx_skbuff_dma
[i
].map_as_page
= false;
1224 * init_dma_rx_desc_rings - init the RX descriptor rings
1225 * @dev: net device structure
1227 * Description: this function initializes the DMA RX descriptors
1228 * and allocates the socket buffers. It supports the chained and ring
1231 static int init_dma_rx_desc_rings(struct net_device
*dev
, gfp_t flags
)
1233 struct stmmac_priv
*priv
= netdev_priv(dev
);
1234 u32 rx_count
= priv
->plat
->rx_queues_to_use
;
1235 unsigned int bfsize
= 0;
1240 if (priv
->hw
->mode
->set_16kib_bfsize
)
1241 bfsize
= priv
->hw
->mode
->set_16kib_bfsize(dev
->mtu
);
1243 if (bfsize
< BUF_SIZE_16KiB
)
1244 bfsize
= stmmac_set_bfsize(dev
->mtu
, priv
->dma_buf_sz
);
1246 priv
->dma_buf_sz
= bfsize
;
1248 /* RX INITIALIZATION */
1249 netif_dbg(priv
, probe
, priv
->dev
,
1250 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1252 for (queue
= 0; queue
< rx_count
; queue
++) {
1253 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
1255 netif_dbg(priv
, probe
, priv
->dev
,
1256 "(%s) dma_rx_phy=0x%08x\n", __func__
,
1257 (u32
)rx_q
->dma_rx_phy
);
1259 for (i
= 0; i
< DMA_RX_SIZE
; i
++) {
1262 if (priv
->extend_desc
)
1263 p
= &((rx_q
->dma_erx
+ i
)->basic
);
1265 p
= rx_q
->dma_rx
+ i
;
1267 ret
= stmmac_init_rx_buffers(priv
, p
, i
, flags
,
1270 goto err_init_rx_buffers
;
1272 netif_dbg(priv
, probe
, priv
->dev
, "[%p]\t[%p]\t[%x]\n",
1273 rx_q
->rx_skbuff
[i
], rx_q
->rx_skbuff
[i
]->data
,
1274 (unsigned int)rx_q
->rx_skbuff_dma
[i
]);
1278 rx_q
->dirty_rx
= (unsigned int)(i
- DMA_RX_SIZE
);
1280 stmmac_clear_rx_descriptors(priv
, queue
);
1282 /* Setup the chained descriptor addresses */
1283 if (priv
->mode
== STMMAC_CHAIN_MODE
) {
1284 if (priv
->extend_desc
)
1285 priv
->hw
->mode
->init(rx_q
->dma_erx
,
1289 priv
->hw
->mode
->init(rx_q
->dma_rx
,
1299 err_init_rx_buffers
:
1300 while (queue
>= 0) {
1302 stmmac_free_rx_buffer(priv
, queue
, i
);
1315 * init_dma_tx_desc_rings - init the TX descriptor rings
1316 * @dev: net device structure.
1317 * Description: this function initializes the DMA TX descriptors
1318 * and allocates the socket buffers. It supports the chained and ring
1321 static int init_dma_tx_desc_rings(struct net_device
*dev
)
1323 struct stmmac_priv
*priv
= netdev_priv(dev
);
1324 u32 tx_queue_cnt
= priv
->plat
->tx_queues_to_use
;
1328 for (queue
= 0; queue
< tx_queue_cnt
; queue
++) {
1329 struct stmmac_tx_queue
*tx_q
= &priv
->tx_queue
[queue
];
1331 netif_dbg(priv
, probe
, priv
->dev
,
1332 "(%s) dma_tx_phy=0x%08x\n", __func__
,
1333 (u32
)tx_q
->dma_tx_phy
);
1335 /* Setup the chained descriptor addresses */
1336 if (priv
->mode
== STMMAC_CHAIN_MODE
) {
1337 if (priv
->extend_desc
)
1338 priv
->hw
->mode
->init(tx_q
->dma_etx
,
1342 priv
->hw
->mode
->init(tx_q
->dma_tx
,
1347 for (i
= 0; i
< DMA_TX_SIZE
; i
++) {
1349 if (priv
->extend_desc
)
1350 p
= &((tx_q
->dma_etx
+ i
)->basic
);
1352 p
= tx_q
->dma_tx
+ i
;
1354 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
1363 tx_q
->tx_skbuff_dma
[i
].buf
= 0;
1364 tx_q
->tx_skbuff_dma
[i
].map_as_page
= false;
1365 tx_q
->tx_skbuff_dma
[i
].len
= 0;
1366 tx_q
->tx_skbuff_dma
[i
].last_segment
= false;
1367 tx_q
->tx_skbuff
[i
] = NULL
;
1374 netdev_tx_reset_queue(netdev_get_tx_queue(priv
->dev
, queue
));
1381 * init_dma_desc_rings - init the RX/TX descriptor rings
1382 * @dev: net device structure
1384 * Description: this function initializes the DMA RX/TX descriptors
1385 * and allocates the socket buffers. It supports the chained and ring
1388 static int init_dma_desc_rings(struct net_device
*dev
, gfp_t flags
)
1390 struct stmmac_priv
*priv
= netdev_priv(dev
);
1393 ret
= init_dma_rx_desc_rings(dev
, flags
);
1397 ret
= init_dma_tx_desc_rings(dev
);
1399 stmmac_clear_descriptors(priv
);
1401 if (netif_msg_hw(priv
))
1402 stmmac_display_rings(priv
);
1408 * dma_free_rx_skbufs - free RX dma buffers
1409 * @priv: private structure
1410 * @queue: RX queue index
1412 static void dma_free_rx_skbufs(struct stmmac_priv
*priv
, u32 queue
)
1416 for (i
= 0; i
< DMA_RX_SIZE
; i
++)
1417 stmmac_free_rx_buffer(priv
, queue
, i
);
1421 * dma_free_tx_skbufs - free TX dma buffers
1422 * @priv: private structure
1423 * @queue: TX queue index
1425 static void dma_free_tx_skbufs(struct stmmac_priv
*priv
, u32 queue
)
1429 for (i
= 0; i
< DMA_TX_SIZE
; i
++)
1430 stmmac_free_tx_buffer(priv
, queue
, i
);
1434 * free_dma_rx_desc_resources - free RX dma desc resources
1435 * @priv: private structure
1437 static void free_dma_rx_desc_resources(struct stmmac_priv
*priv
)
1439 u32 rx_count
= priv
->plat
->rx_queues_to_use
;
1442 /* Free RX queue resources */
1443 for (queue
= 0; queue
< rx_count
; queue
++) {
1444 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
1446 /* Release the DMA RX socket buffers */
1447 dma_free_rx_skbufs(priv
, queue
);
1449 /* Free DMA regions of consistent memory previously allocated */
1450 if (!priv
->extend_desc
)
1451 dma_free_coherent(priv
->device
,
1452 DMA_RX_SIZE
* sizeof(struct dma_desc
),
1453 rx_q
->dma_rx
, rx_q
->dma_rx_phy
);
1455 dma_free_coherent(priv
->device
, DMA_RX_SIZE
*
1456 sizeof(struct dma_extended_desc
),
1457 rx_q
->dma_erx
, rx_q
->dma_rx_phy
);
1459 kfree(rx_q
->rx_skbuff_dma
);
1460 kfree(rx_q
->rx_skbuff
);
1465 * free_dma_tx_desc_resources - free TX dma desc resources
1466 * @priv: private structure
1468 static void free_dma_tx_desc_resources(struct stmmac_priv
*priv
)
1470 u32 tx_count
= priv
->plat
->tx_queues_to_use
;
1473 /* Free TX queue resources */
1474 for (queue
= 0; queue
< tx_count
; queue
++) {
1475 struct stmmac_tx_queue
*tx_q
= &priv
->tx_queue
[queue
];
1477 /* Release the DMA TX socket buffers */
1478 dma_free_tx_skbufs(priv
, queue
);
1480 /* Free DMA regions of consistent memory previously allocated */
1481 if (!priv
->extend_desc
)
1482 dma_free_coherent(priv
->device
,
1483 DMA_TX_SIZE
* sizeof(struct dma_desc
),
1484 tx_q
->dma_tx
, tx_q
->dma_tx_phy
);
1486 dma_free_coherent(priv
->device
, DMA_TX_SIZE
*
1487 sizeof(struct dma_extended_desc
),
1488 tx_q
->dma_etx
, tx_q
->dma_tx_phy
);
1490 kfree(tx_q
->tx_skbuff_dma
);
1491 kfree(tx_q
->tx_skbuff
);
1496 * alloc_dma_rx_desc_resources - alloc RX resources.
1497 * @priv: private structure
1498 * Description: according to which descriptor can be used (extend or basic)
1499 * this function allocates the resources for TX and RX paths. In case of
1500 * reception, for example, it pre-allocated the RX socket buffer in order to
1501 * allow zero-copy mechanism.
1503 static int alloc_dma_rx_desc_resources(struct stmmac_priv
*priv
)
1505 u32 rx_count
= priv
->plat
->rx_queues_to_use
;
1509 /* RX queues buffers and DMA */
1510 for (queue
= 0; queue
< rx_count
; queue
++) {
1511 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
1513 rx_q
->queue_index
= queue
;
1514 rx_q
->priv_data
= priv
;
1516 rx_q
->rx_skbuff_dma
= kmalloc_array(DMA_RX_SIZE
,
1519 if (!rx_q
->rx_skbuff_dma
)
1522 rx_q
->rx_skbuff
= kmalloc_array(DMA_RX_SIZE
,
1523 sizeof(struct sk_buff
*),
1525 if (!rx_q
->rx_skbuff
)
1528 if (priv
->extend_desc
) {
1529 rx_q
->dma_erx
= dma_zalloc_coherent(priv
->device
,
1539 rx_q
->dma_rx
= dma_zalloc_coherent(priv
->device
,
1553 free_dma_rx_desc_resources(priv
);
1559 * alloc_dma_tx_desc_resources - alloc TX resources.
1560 * @priv: private structure
1561 * Description: according to which descriptor can be used (extend or basic)
1562 * this function allocates the resources for TX and RX paths. In case of
1563 * reception, for example, it pre-allocated the RX socket buffer in order to
1564 * allow zero-copy mechanism.
1566 static int alloc_dma_tx_desc_resources(struct stmmac_priv
*priv
)
1568 u32 tx_count
= priv
->plat
->tx_queues_to_use
;
1572 /* TX queues buffers and DMA */
1573 for (queue
= 0; queue
< tx_count
; queue
++) {
1574 struct stmmac_tx_queue
*tx_q
= &priv
->tx_queue
[queue
];
1576 tx_q
->queue_index
= queue
;
1577 tx_q
->priv_data
= priv
;
1579 tx_q
->tx_skbuff_dma
= kmalloc_array(DMA_TX_SIZE
,
1580 sizeof(*tx_q
->tx_skbuff_dma
),
1582 if (!tx_q
->tx_skbuff_dma
)
1585 tx_q
->tx_skbuff
= kmalloc_array(DMA_TX_SIZE
,
1586 sizeof(struct sk_buff
*),
1588 if (!tx_q
->tx_skbuff
)
1591 if (priv
->extend_desc
) {
1592 tx_q
->dma_etx
= dma_zalloc_coherent(priv
->device
,
1601 tx_q
->dma_tx
= dma_zalloc_coherent(priv
->device
,
1615 free_dma_tx_desc_resources(priv
);
1621 * alloc_dma_desc_resources - alloc TX/RX resources.
1622 * @priv: private structure
1623 * Description: according to which descriptor can be used (extend or basic)
1624 * this function allocates the resources for TX and RX paths. In case of
1625 * reception, for example, it pre-allocated the RX socket buffer in order to
1626 * allow zero-copy mechanism.
1628 static int alloc_dma_desc_resources(struct stmmac_priv
*priv
)
1631 int ret
= alloc_dma_rx_desc_resources(priv
);
1636 ret
= alloc_dma_tx_desc_resources(priv
);
1642 * free_dma_desc_resources - free dma desc resources
1643 * @priv: private structure
1645 static void free_dma_desc_resources(struct stmmac_priv
*priv
)
1647 /* Release the DMA RX socket buffers */
1648 free_dma_rx_desc_resources(priv
);
1650 /* Release the DMA TX socket buffers */
1651 free_dma_tx_desc_resources(priv
);
1655 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1656 * @priv: driver private structure
1657 * Description: It is used for enabling the rx queues in the MAC
1659 static void stmmac_mac_enable_rx_queues(struct stmmac_priv
*priv
)
1661 u32 rx_queues_count
= priv
->plat
->rx_queues_to_use
;
1665 for (queue
= 0; queue
< rx_queues_count
; queue
++) {
1666 mode
= priv
->plat
->rx_queues_cfg
[queue
].mode_to_use
;
1667 priv
->hw
->mac
->rx_queue_enable(priv
->hw
, mode
, queue
);
1672 * stmmac_start_rx_dma - start RX DMA channel
1673 * @priv: driver private structure
1674 * @chan: RX channel index
1676 * This starts a RX DMA channel
1678 static void stmmac_start_rx_dma(struct stmmac_priv
*priv
, u32 chan
)
1680 netdev_dbg(priv
->dev
, "DMA RX processes started in channel %d\n", chan
);
1681 priv
->hw
->dma
->start_rx(priv
->ioaddr
, chan
);
1685 * stmmac_start_tx_dma - start TX DMA channel
1686 * @priv: driver private structure
1687 * @chan: TX channel index
1689 * This starts a TX DMA channel
1691 static void stmmac_start_tx_dma(struct stmmac_priv
*priv
, u32 chan
)
1693 netdev_dbg(priv
->dev
, "DMA TX processes started in channel %d\n", chan
);
1694 priv
->hw
->dma
->start_tx(priv
->ioaddr
, chan
);
1698 * stmmac_stop_rx_dma - stop RX DMA channel
1699 * @priv: driver private structure
1700 * @chan: RX channel index
1702 * This stops a RX DMA channel
1704 static void stmmac_stop_rx_dma(struct stmmac_priv
*priv
, u32 chan
)
1706 netdev_dbg(priv
->dev
, "DMA RX processes stopped in channel %d\n", chan
);
1707 priv
->hw
->dma
->stop_rx(priv
->ioaddr
, chan
);
1711 * stmmac_stop_tx_dma - stop TX DMA channel
1712 * @priv: driver private structure
1713 * @chan: TX channel index
1715 * This stops a TX DMA channel
1717 static void stmmac_stop_tx_dma(struct stmmac_priv
*priv
, u32 chan
)
1719 netdev_dbg(priv
->dev
, "DMA TX processes stopped in channel %d\n", chan
);
1720 priv
->hw
->dma
->stop_tx(priv
->ioaddr
, chan
);
1724 * stmmac_start_all_dma - start all RX and TX DMA channels
1725 * @priv: driver private structure
1727 * This starts all the RX and TX DMA channels
1729 static void stmmac_start_all_dma(struct stmmac_priv
*priv
)
1731 u32 rx_channels_count
= priv
->plat
->rx_queues_to_use
;
1732 u32 tx_channels_count
= priv
->plat
->tx_queues_to_use
;
1735 for (chan
= 0; chan
< rx_channels_count
; chan
++)
1736 stmmac_start_rx_dma(priv
, chan
);
1738 for (chan
= 0; chan
< tx_channels_count
; chan
++)
1739 stmmac_start_tx_dma(priv
, chan
);
1743 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1744 * @priv: driver private structure
1746 * This stops the RX and TX DMA channels
1748 static void stmmac_stop_all_dma(struct stmmac_priv
*priv
)
1750 u32 rx_channels_count
= priv
->plat
->rx_queues_to_use
;
1751 u32 tx_channels_count
= priv
->plat
->tx_queues_to_use
;
1754 for (chan
= 0; chan
< rx_channels_count
; chan
++)
1755 stmmac_stop_rx_dma(priv
, chan
);
1757 for (chan
= 0; chan
< tx_channels_count
; chan
++)
1758 stmmac_stop_tx_dma(priv
, chan
);
1762 * stmmac_dma_operation_mode - HW DMA operation mode
1763 * @priv: driver private structure
1764 * Description: it is used for configuring the DMA operation mode register in
1765 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1767 static void stmmac_dma_operation_mode(struct stmmac_priv
*priv
)
1769 u32 rx_channels_count
= priv
->plat
->rx_queues_to_use
;
1770 u32 tx_channels_count
= priv
->plat
->tx_queues_to_use
;
1771 int rxfifosz
= priv
->plat
->rx_fifo_size
;
1772 int txfifosz
= priv
->plat
->tx_fifo_size
;
1779 rxfifosz
= priv
->dma_cap
.rx_fifo_size
;
1781 txfifosz
= priv
->dma_cap
.tx_fifo_size
;
1783 /* Adjust for real per queue fifo size */
1784 rxfifosz
/= rx_channels_count
;
1785 txfifosz
/= tx_channels_count
;
1787 if (priv
->plat
->force_thresh_dma_mode
) {
1790 } else if (priv
->plat
->force_sf_dma_mode
|| priv
->plat
->tx_coe
) {
1792 * In case of GMAC, SF mode can be enabled
1793 * to perform the TX COE in HW. This depends on:
1794 * 1) TX COE if actually supported
1795 * 2) There is no bugged Jumbo frame support
1796 * that needs to not insert csum in the TDES.
1798 txmode
= SF_DMA_MODE
;
1799 rxmode
= SF_DMA_MODE
;
1800 priv
->xstats
.threshold
= SF_DMA_MODE
;
1803 rxmode
= SF_DMA_MODE
;
1806 /* configure all channels */
1807 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
1808 for (chan
= 0; chan
< rx_channels_count
; chan
++) {
1809 qmode
= priv
->plat
->rx_queues_cfg
[chan
].mode_to_use
;
1811 priv
->hw
->dma
->dma_rx_mode(priv
->ioaddr
, rxmode
, chan
,
1815 for (chan
= 0; chan
< tx_channels_count
; chan
++) {
1816 qmode
= priv
->plat
->tx_queues_cfg
[chan
].mode_to_use
;
1818 priv
->hw
->dma
->dma_tx_mode(priv
->ioaddr
, txmode
, chan
,
1822 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, txmode
, rxmode
,
1828 * stmmac_tx_clean - to manage the transmission completion
1829 * @priv: driver private structure
1830 * @queue: TX queue index
1831 * Description: it reclaims the transmit resources after transmission completes.
1833 static void stmmac_tx_clean(struct stmmac_priv
*priv
, u32 queue
)
1835 struct stmmac_tx_queue
*tx_q
= &priv
->tx_queue
[queue
];
1836 unsigned int bytes_compl
= 0, pkts_compl
= 0;
1839 netif_tx_lock(priv
->dev
);
1841 priv
->xstats
.tx_clean
++;
1843 entry
= tx_q
->dirty_tx
;
1844 while (entry
!= tx_q
->cur_tx
) {
1845 struct sk_buff
*skb
= tx_q
->tx_skbuff
[entry
];
1849 if (priv
->extend_desc
)
1850 p
= (struct dma_desc
*)(tx_q
->dma_etx
+ entry
);
1852 p
= tx_q
->dma_tx
+ entry
;
1854 status
= priv
->hw
->desc
->tx_status(&priv
->dev
->stats
,
1857 /* Check if the descriptor is owned by the DMA */
1858 if (unlikely(status
& tx_dma_own
))
1861 /* Make sure descriptor fields are read after reading
1866 /* Just consider the last segment and ...*/
1867 if (likely(!(status
& tx_not_ls
))) {
1868 /* ... verify the status error condition */
1869 if (unlikely(status
& tx_err
)) {
1870 priv
->dev
->stats
.tx_errors
++;
1872 priv
->dev
->stats
.tx_packets
++;
1873 priv
->xstats
.tx_pkt_n
++;
1875 stmmac_get_tx_hwtstamp(priv
, p
, skb
);
1878 if (likely(tx_q
->tx_skbuff_dma
[entry
].buf
)) {
1879 if (tx_q
->tx_skbuff_dma
[entry
].map_as_page
)
1880 dma_unmap_page(priv
->device
,
1881 tx_q
->tx_skbuff_dma
[entry
].buf
,
1882 tx_q
->tx_skbuff_dma
[entry
].len
,
1885 dma_unmap_single(priv
->device
,
1886 tx_q
->tx_skbuff_dma
[entry
].buf
,
1887 tx_q
->tx_skbuff_dma
[entry
].len
,
1889 tx_q
->tx_skbuff_dma
[entry
].buf
= 0;
1890 tx_q
->tx_skbuff_dma
[entry
].len
= 0;
1891 tx_q
->tx_skbuff_dma
[entry
].map_as_page
= false;
1894 if (priv
->hw
->mode
->clean_desc3
)
1895 priv
->hw
->mode
->clean_desc3(tx_q
, p
);
1897 tx_q
->tx_skbuff_dma
[entry
].last_segment
= false;
1898 tx_q
->tx_skbuff_dma
[entry
].is_jumbo
= false;
1900 if (likely(skb
!= NULL
)) {
1902 bytes_compl
+= skb
->len
;
1903 dev_consume_skb_any(skb
);
1904 tx_q
->tx_skbuff
[entry
] = NULL
;
1907 priv
->hw
->desc
->release_tx_desc(p
, priv
->mode
);
1909 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
1911 tx_q
->dirty_tx
= entry
;
1913 netdev_tx_completed_queue(netdev_get_tx_queue(priv
->dev
, queue
),
1914 pkts_compl
, bytes_compl
);
1916 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv
->dev
,
1918 stmmac_tx_avail(priv
, queue
) > STMMAC_TX_THRESH
) {
1920 netif_dbg(priv
, tx_done
, priv
->dev
,
1921 "%s: restart transmit\n", __func__
);
1922 netif_tx_wake_queue(netdev_get_tx_queue(priv
->dev
, queue
));
1925 if ((priv
->eee_enabled
) && (!priv
->tx_path_in_lpi_mode
)) {
1926 stmmac_enable_eee_mode(priv
);
1927 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
1929 netif_tx_unlock(priv
->dev
);
1932 static inline void stmmac_enable_dma_irq(struct stmmac_priv
*priv
, u32 chan
)
1934 priv
->hw
->dma
->enable_dma_irq(priv
->ioaddr
, chan
);
1937 static inline void stmmac_disable_dma_irq(struct stmmac_priv
*priv
, u32 chan
)
1939 priv
->hw
->dma
->disable_dma_irq(priv
->ioaddr
, chan
);
1943 * stmmac_tx_err - to manage the tx error
1944 * @priv: driver private structure
1945 * @chan: channel index
1946 * Description: it cleans the descriptors and restarts the transmission
1947 * in case of transmission errors.
1949 static void stmmac_tx_err(struct stmmac_priv
*priv
, u32 chan
)
1951 struct stmmac_tx_queue
*tx_q
= &priv
->tx_queue
[chan
];
1954 netif_tx_stop_queue(netdev_get_tx_queue(priv
->dev
, chan
));
1956 stmmac_stop_tx_dma(priv
, chan
);
1957 dma_free_tx_skbufs(priv
, chan
);
1958 for (i
= 0; i
< DMA_TX_SIZE
; i
++)
1959 if (priv
->extend_desc
)
1960 priv
->hw
->desc
->init_tx_desc(&tx_q
->dma_etx
[i
].basic
,
1962 (i
== DMA_TX_SIZE
- 1));
1964 priv
->hw
->desc
->init_tx_desc(&tx_q
->dma_tx
[i
],
1966 (i
== DMA_TX_SIZE
- 1));
1970 netdev_tx_reset_queue(netdev_get_tx_queue(priv
->dev
, chan
));
1971 stmmac_start_tx_dma(priv
, chan
);
1973 priv
->dev
->stats
.tx_errors
++;
1974 netif_tx_wake_queue(netdev_get_tx_queue(priv
->dev
, chan
));
1978 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
1979 * @priv: driver private structure
1980 * @txmode: TX operating mode
1981 * @rxmode: RX operating mode
1982 * @chan: channel index
1983 * Description: it is used for configuring of the DMA operation mode in
1984 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
1987 static void stmmac_set_dma_operation_mode(struct stmmac_priv
*priv
, u32 txmode
,
1988 u32 rxmode
, u32 chan
)
1990 u8 rxqmode
= priv
->plat
->rx_queues_cfg
[chan
].mode_to_use
;
1991 u8 txqmode
= priv
->plat
->tx_queues_cfg
[chan
].mode_to_use
;
1992 u32 rx_channels_count
= priv
->plat
->rx_queues_to_use
;
1993 u32 tx_channels_count
= priv
->plat
->tx_queues_to_use
;
1994 int rxfifosz
= priv
->plat
->rx_fifo_size
;
1995 int txfifosz
= priv
->plat
->tx_fifo_size
;
1998 rxfifosz
= priv
->dma_cap
.rx_fifo_size
;
2000 txfifosz
= priv
->dma_cap
.tx_fifo_size
;
2002 /* Adjust for real per queue fifo size */
2003 rxfifosz
/= rx_channels_count
;
2004 txfifosz
/= tx_channels_count
;
2006 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
2007 priv
->hw
->dma
->dma_rx_mode(priv
->ioaddr
, rxmode
, chan
,
2009 priv
->hw
->dma
->dma_tx_mode(priv
->ioaddr
, txmode
, chan
,
2012 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, txmode
, rxmode
,
2017 static bool stmmac_safety_feat_interrupt(struct stmmac_priv
*priv
)
2021 /* Safety features are only available in cores >= 5.10 */
2022 if (priv
->synopsys_id
< DWMAC_CORE_5_10
)
2024 if (priv
->hw
->mac
->safety_feat_irq_status
)
2025 ret
= priv
->hw
->mac
->safety_feat_irq_status(priv
->dev
,
2026 priv
->ioaddr
, priv
->dma_cap
.asp
, &priv
->sstats
);
2029 stmmac_global_err(priv
);
2034 * stmmac_dma_interrupt - DMA ISR
2035 * @priv: driver private structure
2036 * Description: this is the DMA ISR. It is called by the main ISR.
2037 * It calls the dwmac dma routine and schedule poll method in case of some
2040 static void stmmac_dma_interrupt(struct stmmac_priv
*priv
)
2042 u32 tx_channel_count
= priv
->plat
->tx_queues_to_use
;
2043 u32 rx_channel_count
= priv
->plat
->rx_queues_to_use
;
2044 u32 channels_to_check
= tx_channel_count
> rx_channel_count
?
2045 tx_channel_count
: rx_channel_count
;
2047 bool poll_scheduled
= false;
2048 int status
[channels_to_check
];
2050 /* Each DMA channel can be used for rx and tx simultaneously, yet
2051 * napi_struct is embedded in struct stmmac_rx_queue rather than in a
2052 * stmmac_channel struct.
2053 * Because of this, stmmac_poll currently checks (and possibly wakes)
2054 * all tx queues rather than just a single tx queue.
2056 for (chan
= 0; chan
< channels_to_check
; chan
++)
2057 status
[chan
] = priv
->hw
->dma
->dma_interrupt(priv
->ioaddr
,
2061 for (chan
= 0; chan
< rx_channel_count
; chan
++) {
2062 if (likely(status
[chan
] & handle_rx
)) {
2063 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[chan
];
2065 if (likely(napi_schedule_prep(&rx_q
->napi
))) {
2066 stmmac_disable_dma_irq(priv
, chan
);
2067 __napi_schedule(&rx_q
->napi
);
2068 poll_scheduled
= true;
2073 /* If we scheduled poll, we already know that tx queues will be checked.
2074 * If we didn't schedule poll, see if any DMA channel (used by tx) has a
2075 * completed transmission, if so, call stmmac_poll (once).
2077 if (!poll_scheduled
) {
2078 for (chan
= 0; chan
< tx_channel_count
; chan
++) {
2079 if (status
[chan
] & handle_tx
) {
2080 /* It doesn't matter what rx queue we choose
2081 * here. We use 0 since it always exists.
2083 struct stmmac_rx_queue
*rx_q
=
2086 if (likely(napi_schedule_prep(&rx_q
->napi
))) {
2087 stmmac_disable_dma_irq(priv
, chan
);
2088 __napi_schedule(&rx_q
->napi
);
2095 for (chan
= 0; chan
< tx_channel_count
; chan
++) {
2096 if (unlikely(status
[chan
] & tx_hard_error_bump_tc
)) {
2097 /* Try to bump up the dma threshold on this failure */
2098 if (unlikely(priv
->xstats
.threshold
!= SF_DMA_MODE
) &&
2101 if (priv
->plat
->force_thresh_dma_mode
)
2102 stmmac_set_dma_operation_mode(priv
,
2107 stmmac_set_dma_operation_mode(priv
,
2111 priv
->xstats
.threshold
= tc
;
2113 } else if (unlikely(status
[chan
] == tx_hard_error
)) {
2114 stmmac_tx_err(priv
, chan
);
2120 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2121 * @priv: driver private structure
2122 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2124 static void stmmac_mmc_setup(struct stmmac_priv
*priv
)
2126 unsigned int mode
= MMC_CNTRL_RESET_ON_READ
| MMC_CNTRL_COUNTER_RESET
|
2127 MMC_CNTRL_PRESET
| MMC_CNTRL_FULL_HALF_PRESET
;
2129 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
2130 priv
->ptpaddr
= priv
->ioaddr
+ PTP_GMAC4_OFFSET
;
2131 priv
->mmcaddr
= priv
->ioaddr
+ MMC_GMAC4_OFFSET
;
2133 priv
->ptpaddr
= priv
->ioaddr
+ PTP_GMAC3_X_OFFSET
;
2134 priv
->mmcaddr
= priv
->ioaddr
+ MMC_GMAC3_X_OFFSET
;
2137 dwmac_mmc_intr_all_mask(priv
->mmcaddr
);
2139 if (priv
->dma_cap
.rmon
) {
2140 dwmac_mmc_ctrl(priv
->mmcaddr
, mode
);
2141 memset(&priv
->mmc
, 0, sizeof(struct stmmac_counters
));
2143 netdev_info(priv
->dev
, "No MAC Management Counters available\n");
2147 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
2148 * @priv: driver private structure
2149 * Description: select the Enhanced/Alternate or Normal descriptors.
2150 * In case of Enhanced/Alternate, it checks if the extended descriptors are
2151 * supported by the HW capability register.
2153 static void stmmac_selec_desc_mode(struct stmmac_priv
*priv
)
2155 if (priv
->plat
->enh_desc
) {
2156 dev_info(priv
->device
, "Enhanced/Alternate descriptors\n");
2158 /* GMAC older than 3.50 has no extended descriptors */
2159 if (priv
->synopsys_id
>= DWMAC_CORE_3_50
) {
2160 dev_info(priv
->device
, "Enabled extended descriptors\n");
2161 priv
->extend_desc
= 1;
2163 dev_warn(priv
->device
, "Extended descriptors not supported\n");
2165 priv
->hw
->desc
= &enh_desc_ops
;
2167 dev_info(priv
->device
, "Normal descriptors\n");
2168 priv
->hw
->desc
= &ndesc_ops
;
2173 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2174 * @priv: driver private structure
2176 * new GMAC chip generations have a new register to indicate the
2177 * presence of the optional feature/functions.
2178 * This can be also used to override the value passed through the
2179 * platform and necessary for old MAC10/100 and GMAC chips.
2181 static int stmmac_get_hw_features(struct stmmac_priv
*priv
)
2185 if (priv
->hw
->dma
->get_hw_feature
) {
2186 priv
->hw
->dma
->get_hw_feature(priv
->ioaddr
,
2195 * stmmac_check_ether_addr - check if the MAC addr is valid
2196 * @priv: driver private structure
2198 * it is to verify if the MAC address is valid, in case of failures it
2199 * generates a random MAC address
2201 static void stmmac_check_ether_addr(struct stmmac_priv
*priv
)
2203 if (!is_valid_ether_addr(priv
->dev
->dev_addr
)) {
2204 priv
->hw
->mac
->get_umac_addr(priv
->hw
,
2205 priv
->dev
->dev_addr
, 0);
2206 if (!is_valid_ether_addr(priv
->dev
->dev_addr
))
2207 eth_hw_addr_random(priv
->dev
);
2208 netdev_info(priv
->dev
, "device MAC address %pM\n",
2209 priv
->dev
->dev_addr
);
2214 * stmmac_init_dma_engine - DMA init.
2215 * @priv: driver private structure
2217 * It inits the DMA invoking the specific MAC/GMAC callback.
2218 * Some DMA parameters can be passed from the platform;
2219 * in case of these are not passed a default is kept for the MAC or GMAC.
2221 static int stmmac_init_dma_engine(struct stmmac_priv
*priv
)
2223 u32 rx_channels_count
= priv
->plat
->rx_queues_to_use
;
2224 u32 tx_channels_count
= priv
->plat
->tx_queues_to_use
;
2225 struct stmmac_rx_queue
*rx_q
;
2226 struct stmmac_tx_queue
*tx_q
;
2227 u32 dummy_dma_rx_phy
= 0;
2228 u32 dummy_dma_tx_phy
= 0;
2233 if (!priv
->plat
->dma_cfg
|| !priv
->plat
->dma_cfg
->pbl
) {
2234 dev_err(priv
->device
, "Invalid DMA configuration\n");
2238 if (priv
->extend_desc
&& (priv
->mode
== STMMAC_RING_MODE
))
2241 ret
= priv
->hw
->dma
->reset(priv
->ioaddr
);
2243 dev_err(priv
->device
, "Failed to reset the dma\n");
2247 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
2248 /* DMA Configuration */
2249 priv
->hw
->dma
->init(priv
->ioaddr
, priv
->plat
->dma_cfg
,
2250 dummy_dma_tx_phy
, dummy_dma_rx_phy
, atds
);
2252 /* DMA RX Channel Configuration */
2253 for (chan
= 0; chan
< rx_channels_count
; chan
++) {
2254 rx_q
= &priv
->rx_queue
[chan
];
2256 priv
->hw
->dma
->init_rx_chan(priv
->ioaddr
,
2257 priv
->plat
->dma_cfg
,
2258 rx_q
->dma_rx_phy
, chan
);
2260 rx_q
->rx_tail_addr
= rx_q
->dma_rx_phy
+
2261 (DMA_RX_SIZE
* sizeof(struct dma_desc
));
2262 priv
->hw
->dma
->set_rx_tail_ptr(priv
->ioaddr
,
2267 /* DMA TX Channel Configuration */
2268 for (chan
= 0; chan
< tx_channels_count
; chan
++) {
2269 tx_q
= &priv
->tx_queue
[chan
];
2271 priv
->hw
->dma
->init_chan(priv
->ioaddr
,
2272 priv
->plat
->dma_cfg
,
2275 priv
->hw
->dma
->init_tx_chan(priv
->ioaddr
,
2276 priv
->plat
->dma_cfg
,
2277 tx_q
->dma_tx_phy
, chan
);
2279 tx_q
->tx_tail_addr
= tx_q
->dma_tx_phy
+
2280 (DMA_TX_SIZE
* sizeof(struct dma_desc
));
2281 priv
->hw
->dma
->set_tx_tail_ptr(priv
->ioaddr
,
2286 rx_q
= &priv
->rx_queue
[chan
];
2287 tx_q
= &priv
->tx_queue
[chan
];
2288 priv
->hw
->dma
->init(priv
->ioaddr
, priv
->plat
->dma_cfg
,
2289 tx_q
->dma_tx_phy
, rx_q
->dma_rx_phy
, atds
);
2292 if (priv
->plat
->axi
&& priv
->hw
->dma
->axi
)
2293 priv
->hw
->dma
->axi(priv
->ioaddr
, priv
->plat
->axi
);
2299 * stmmac_tx_timer - mitigation sw timer for tx.
2300 * @data: data pointer
2302 * This is the timer handler to directly invoke the stmmac_tx_clean.
2304 static void stmmac_tx_timer(struct timer_list
*t
)
2306 struct stmmac_priv
*priv
= from_timer(priv
, t
, txtimer
);
2307 u32 tx_queues_count
= priv
->plat
->tx_queues_to_use
;
2310 /* let's scan all the tx queues */
2311 for (queue
= 0; queue
< tx_queues_count
; queue
++)
2312 stmmac_tx_clean(priv
, queue
);
2316 * stmmac_init_tx_coalesce - init tx mitigation options.
2317 * @priv: driver private structure
2319 * This inits the transmit coalesce parameters: i.e. timer rate,
2320 * timer handler and default threshold used for enabling the
2321 * interrupt on completion bit.
2323 static void stmmac_init_tx_coalesce(struct stmmac_priv
*priv
)
2325 priv
->tx_coal_frames
= STMMAC_TX_FRAMES
;
2326 priv
->tx_coal_timer
= STMMAC_COAL_TX_TIMER
;
2327 timer_setup(&priv
->txtimer
, stmmac_tx_timer
, 0);
2328 priv
->txtimer
.expires
= STMMAC_COAL_TIMER(priv
->tx_coal_timer
);
2329 add_timer(&priv
->txtimer
);
2332 static void stmmac_set_rings_length(struct stmmac_priv
*priv
)
2334 u32 rx_channels_count
= priv
->plat
->rx_queues_to_use
;
2335 u32 tx_channels_count
= priv
->plat
->tx_queues_to_use
;
2338 /* set TX ring length */
2339 if (priv
->hw
->dma
->set_tx_ring_len
) {
2340 for (chan
= 0; chan
< tx_channels_count
; chan
++)
2341 priv
->hw
->dma
->set_tx_ring_len(priv
->ioaddr
,
2342 (DMA_TX_SIZE
- 1), chan
);
2345 /* set RX ring length */
2346 if (priv
->hw
->dma
->set_rx_ring_len
) {
2347 for (chan
= 0; chan
< rx_channels_count
; chan
++)
2348 priv
->hw
->dma
->set_rx_ring_len(priv
->ioaddr
,
2349 (DMA_RX_SIZE
- 1), chan
);
2354 * stmmac_set_tx_queue_weight - Set TX queue weight
2355 * @priv: driver private structure
2356 * Description: It is used for setting TX queues weight
2358 static void stmmac_set_tx_queue_weight(struct stmmac_priv
*priv
)
2360 u32 tx_queues_count
= priv
->plat
->tx_queues_to_use
;
2364 for (queue
= 0; queue
< tx_queues_count
; queue
++) {
2365 weight
= priv
->plat
->tx_queues_cfg
[queue
].weight
;
2366 priv
->hw
->mac
->set_mtl_tx_queue_weight(priv
->hw
, weight
, queue
);
2371 * stmmac_configure_cbs - Configure CBS in TX queue
2372 * @priv: driver private structure
2373 * Description: It is used for configuring CBS in AVB TX queues
2375 static void stmmac_configure_cbs(struct stmmac_priv
*priv
)
2377 u32 tx_queues_count
= priv
->plat
->tx_queues_to_use
;
2381 /* queue 0 is reserved for legacy traffic */
2382 for (queue
= 1; queue
< tx_queues_count
; queue
++) {
2383 mode_to_use
= priv
->plat
->tx_queues_cfg
[queue
].mode_to_use
;
2384 if (mode_to_use
== MTL_QUEUE_DCB
)
2387 priv
->hw
->mac
->config_cbs(priv
->hw
,
2388 priv
->plat
->tx_queues_cfg
[queue
].send_slope
,
2389 priv
->plat
->tx_queues_cfg
[queue
].idle_slope
,
2390 priv
->plat
->tx_queues_cfg
[queue
].high_credit
,
2391 priv
->plat
->tx_queues_cfg
[queue
].low_credit
,
2397 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2398 * @priv: driver private structure
2399 * Description: It is used for mapping RX queues to RX dma channels
2401 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv
*priv
)
2403 u32 rx_queues_count
= priv
->plat
->rx_queues_to_use
;
2407 for (queue
= 0; queue
< rx_queues_count
; queue
++) {
2408 chan
= priv
->plat
->rx_queues_cfg
[queue
].chan
;
2409 priv
->hw
->mac
->map_mtl_to_dma(priv
->hw
, queue
, chan
);
2414 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2415 * @priv: driver private structure
2416 * Description: It is used for configuring the RX Queue Priority
2418 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv
*priv
)
2420 u32 rx_queues_count
= priv
->plat
->rx_queues_to_use
;
2424 for (queue
= 0; queue
< rx_queues_count
; queue
++) {
2425 if (!priv
->plat
->rx_queues_cfg
[queue
].use_prio
)
2428 prio
= priv
->plat
->rx_queues_cfg
[queue
].prio
;
2429 priv
->hw
->mac
->rx_queue_prio(priv
->hw
, prio
, queue
);
2434 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2435 * @priv: driver private structure
2436 * Description: It is used for configuring the TX Queue Priority
2438 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv
*priv
)
2440 u32 tx_queues_count
= priv
->plat
->tx_queues_to_use
;
2444 for (queue
= 0; queue
< tx_queues_count
; queue
++) {
2445 if (!priv
->plat
->tx_queues_cfg
[queue
].use_prio
)
2448 prio
= priv
->plat
->tx_queues_cfg
[queue
].prio
;
2449 priv
->hw
->mac
->tx_queue_prio(priv
->hw
, prio
, queue
);
2454 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2455 * @priv: driver private structure
2456 * Description: It is used for configuring the RX queue routing
2458 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv
*priv
)
2460 u32 rx_queues_count
= priv
->plat
->rx_queues_to_use
;
2464 for (queue
= 0; queue
< rx_queues_count
; queue
++) {
2465 /* no specific packet type routing specified for the queue */
2466 if (priv
->plat
->rx_queues_cfg
[queue
].pkt_route
== 0x0)
2469 packet
= priv
->plat
->rx_queues_cfg
[queue
].pkt_route
;
2470 priv
->hw
->mac
->rx_queue_routing(priv
->hw
, packet
, queue
);
2475 * stmmac_mtl_configuration - Configure MTL
2476 * @priv: driver private structure
2477 * Description: It is used for configurring MTL
2479 static void stmmac_mtl_configuration(struct stmmac_priv
*priv
)
2481 u32 rx_queues_count
= priv
->plat
->rx_queues_to_use
;
2482 u32 tx_queues_count
= priv
->plat
->tx_queues_to_use
;
2484 if (tx_queues_count
> 1 && priv
->hw
->mac
->set_mtl_tx_queue_weight
)
2485 stmmac_set_tx_queue_weight(priv
);
2487 /* Configure MTL RX algorithms */
2488 if (rx_queues_count
> 1 && priv
->hw
->mac
->prog_mtl_rx_algorithms
)
2489 priv
->hw
->mac
->prog_mtl_rx_algorithms(priv
->hw
,
2490 priv
->plat
->rx_sched_algorithm
);
2492 /* Configure MTL TX algorithms */
2493 if (tx_queues_count
> 1 && priv
->hw
->mac
->prog_mtl_tx_algorithms
)
2494 priv
->hw
->mac
->prog_mtl_tx_algorithms(priv
->hw
,
2495 priv
->plat
->tx_sched_algorithm
);
2497 /* Configure CBS in AVB TX queues */
2498 if (tx_queues_count
> 1 && priv
->hw
->mac
->config_cbs
)
2499 stmmac_configure_cbs(priv
);
2501 /* Map RX MTL to DMA channels */
2502 if (priv
->hw
->mac
->map_mtl_to_dma
)
2503 stmmac_rx_queue_dma_chan_map(priv
);
2505 /* Enable MAC RX Queues */
2506 if (priv
->hw
->mac
->rx_queue_enable
)
2507 stmmac_mac_enable_rx_queues(priv
);
2509 /* Set RX priorities */
2510 if (rx_queues_count
> 1 && priv
->hw
->mac
->rx_queue_prio
)
2511 stmmac_mac_config_rx_queues_prio(priv
);
2513 /* Set TX priorities */
2514 if (tx_queues_count
> 1 && priv
->hw
->mac
->tx_queue_prio
)
2515 stmmac_mac_config_tx_queues_prio(priv
);
2517 /* Set RX routing */
2518 if (rx_queues_count
> 1 && priv
->hw
->mac
->rx_queue_routing
)
2519 stmmac_mac_config_rx_queues_routing(priv
);
2522 static void stmmac_safety_feat_configuration(struct stmmac_priv
*priv
)
2524 if (priv
->hw
->mac
->safety_feat_config
&& priv
->dma_cap
.asp
) {
2525 netdev_info(priv
->dev
, "Enabling Safety Features\n");
2526 priv
->hw
->mac
->safety_feat_config(priv
->ioaddr
,
2529 netdev_info(priv
->dev
, "No Safety Features support found\n");
2534 * stmmac_hw_setup - setup mac in a usable state.
2535 * @dev : pointer to the device structure.
2537 * this is the main function to setup the HW in a usable state because the
2538 * dma engine is reset, the core registers are configured (e.g. AXI,
2539 * Checksum features, timers). The DMA is ready to start receiving and
2542 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2545 static int stmmac_hw_setup(struct net_device
*dev
, bool init_ptp
)
2547 struct stmmac_priv
*priv
= netdev_priv(dev
);
2548 u32 rx_cnt
= priv
->plat
->rx_queues_to_use
;
2549 u32 tx_cnt
= priv
->plat
->tx_queues_to_use
;
2553 /* DMA initialization and SW reset */
2554 ret
= stmmac_init_dma_engine(priv
);
2556 netdev_err(priv
->dev
, "%s: DMA engine initialization failed\n",
2561 /* Copy the MAC addr into the HW */
2562 priv
->hw
->mac
->set_umac_addr(priv
->hw
, dev
->dev_addr
, 0);
2564 /* PS and related bits will be programmed according to the speed */
2565 if (priv
->hw
->pcs
) {
2566 int speed
= priv
->plat
->mac_port_sel_speed
;
2568 if ((speed
== SPEED_10
) || (speed
== SPEED_100
) ||
2569 (speed
== SPEED_1000
)) {
2570 priv
->hw
->ps
= speed
;
2572 dev_warn(priv
->device
, "invalid port speed\n");
2577 /* Initialize the MAC Core */
2578 priv
->hw
->mac
->core_init(priv
->hw
, dev
);
2581 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
)
2582 stmmac_mtl_configuration(priv
);
2584 /* Initialize Safety Features */
2585 if (priv
->synopsys_id
>= DWMAC_CORE_5_10
)
2586 stmmac_safety_feat_configuration(priv
);
2588 ret
= priv
->hw
->mac
->rx_ipc(priv
->hw
);
2590 netdev_warn(priv
->dev
, "RX IPC Checksum Offload disabled\n");
2591 priv
->plat
->rx_coe
= STMMAC_RX_COE_NONE
;
2592 priv
->hw
->rx_csum
= 0;
2595 /* Enable the MAC Rx/Tx */
2596 priv
->hw
->mac
->set_mac(priv
->ioaddr
, true);
2598 /* Set the HW DMA mode and the COE */
2599 stmmac_dma_operation_mode(priv
);
2601 stmmac_mmc_setup(priv
);
2604 ret
= clk_prepare_enable(priv
->plat
->clk_ptp_ref
);
2606 netdev_warn(priv
->dev
, "failed to enable PTP reference clock: %d\n", ret
);
2608 ret
= stmmac_init_ptp(priv
);
2609 if (ret
== -EOPNOTSUPP
)
2610 netdev_warn(priv
->dev
, "PTP not supported by HW\n");
2612 netdev_warn(priv
->dev
, "PTP init failed\n");
2615 #ifdef CONFIG_DEBUG_FS
2616 ret
= stmmac_init_fs(dev
);
2618 netdev_warn(priv
->dev
, "%s: failed debugFS registration\n",
2621 /* Start the ball rolling... */
2622 stmmac_start_all_dma(priv
);
2624 priv
->tx_lpi_timer
= STMMAC_DEFAULT_TWT_LS
;
2626 if ((priv
->use_riwt
) && (priv
->hw
->dma
->rx_watchdog
)) {
2627 priv
->rx_riwt
= MAX_DMA_RIWT
;
2628 priv
->hw
->dma
->rx_watchdog(priv
->ioaddr
, MAX_DMA_RIWT
, rx_cnt
);
2631 if (priv
->hw
->pcs
&& priv
->hw
->mac
->pcs_ctrl_ane
)
2632 priv
->hw
->mac
->pcs_ctrl_ane(priv
->hw
, 1, priv
->hw
->ps
, 0);
2634 /* set TX and RX rings length */
2635 stmmac_set_rings_length(priv
);
2639 for (chan
= 0; chan
< tx_cnt
; chan
++)
2640 priv
->hw
->dma
->enable_tso(priv
->ioaddr
, 1, chan
);
2646 static void stmmac_hw_teardown(struct net_device
*dev
)
2648 struct stmmac_priv
*priv
= netdev_priv(dev
);
2650 clk_disable_unprepare(priv
->plat
->clk_ptp_ref
);
2654 * stmmac_open - open entry point of the driver
2655 * @dev : pointer to the device structure.
2657 * This function is the open entry point of the driver.
2659 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2662 static int stmmac_open(struct net_device
*dev
)
2664 struct stmmac_priv
*priv
= netdev_priv(dev
);
2667 stmmac_check_ether_addr(priv
);
2669 if (priv
->hw
->pcs
!= STMMAC_PCS_RGMII
&&
2670 priv
->hw
->pcs
!= STMMAC_PCS_TBI
&&
2671 priv
->hw
->pcs
!= STMMAC_PCS_RTBI
) {
2672 ret
= stmmac_init_phy(dev
);
2674 netdev_err(priv
->dev
,
2675 "%s: Cannot attach to PHY (error: %d)\n",
2681 /* Extra statistics */
2682 memset(&priv
->xstats
, 0, sizeof(struct stmmac_extra_stats
));
2683 priv
->xstats
.threshold
= tc
;
2685 priv
->dma_buf_sz
= STMMAC_ALIGN(buf_sz
);
2686 priv
->rx_copybreak
= STMMAC_RX_COPYBREAK
;
2688 ret
= alloc_dma_desc_resources(priv
);
2690 netdev_err(priv
->dev
, "%s: DMA descriptors allocation failed\n",
2692 goto dma_desc_error
;
2695 ret
= init_dma_desc_rings(dev
, GFP_KERNEL
);
2697 netdev_err(priv
->dev
, "%s: DMA descriptors initialization failed\n",
2702 ret
= stmmac_hw_setup(dev
, true);
2704 netdev_err(priv
->dev
, "%s: Hw setup failed\n", __func__
);
2708 stmmac_init_tx_coalesce(priv
);
2711 phy_start(dev
->phydev
);
2713 /* Request the IRQ lines */
2714 ret
= request_irq(dev
->irq
, stmmac_interrupt
,
2715 IRQF_SHARED
, dev
->name
, dev
);
2716 if (unlikely(ret
< 0)) {
2717 netdev_err(priv
->dev
,
2718 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2719 __func__
, dev
->irq
, ret
);
2723 /* Request the Wake IRQ in case of another line is used for WoL */
2724 if (priv
->wol_irq
!= dev
->irq
) {
2725 ret
= request_irq(priv
->wol_irq
, stmmac_interrupt
,
2726 IRQF_SHARED
, dev
->name
, dev
);
2727 if (unlikely(ret
< 0)) {
2728 netdev_err(priv
->dev
,
2729 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2730 __func__
, priv
->wol_irq
, ret
);
2735 /* Request the IRQ lines */
2736 if (priv
->lpi_irq
> 0) {
2737 ret
= request_irq(priv
->lpi_irq
, stmmac_interrupt
, IRQF_SHARED
,
2739 if (unlikely(ret
< 0)) {
2740 netdev_err(priv
->dev
,
2741 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2742 __func__
, priv
->lpi_irq
, ret
);
2747 stmmac_enable_all_queues(priv
);
2748 stmmac_start_all_queues(priv
);
2753 if (priv
->wol_irq
!= dev
->irq
)
2754 free_irq(priv
->wol_irq
, dev
);
2756 free_irq(dev
->irq
, dev
);
2759 phy_stop(dev
->phydev
);
2761 del_timer_sync(&priv
->txtimer
);
2762 stmmac_hw_teardown(dev
);
2764 free_dma_desc_resources(priv
);
2767 phy_disconnect(dev
->phydev
);
2773 * stmmac_release - close entry point of the driver
2774 * @dev : device pointer.
2776 * This is the stop entry point of the driver.
2778 static int stmmac_release(struct net_device
*dev
)
2780 struct stmmac_priv
*priv
= netdev_priv(dev
);
2782 if (priv
->eee_enabled
)
2783 del_timer_sync(&priv
->eee_ctrl_timer
);
2785 /* Stop and disconnect the PHY */
2787 phy_stop(dev
->phydev
);
2788 phy_disconnect(dev
->phydev
);
2791 stmmac_stop_all_queues(priv
);
2793 stmmac_disable_all_queues(priv
);
2795 del_timer_sync(&priv
->txtimer
);
2797 /* Free the IRQ lines */
2798 free_irq(dev
->irq
, dev
);
2799 if (priv
->wol_irq
!= dev
->irq
)
2800 free_irq(priv
->wol_irq
, dev
);
2801 if (priv
->lpi_irq
> 0)
2802 free_irq(priv
->lpi_irq
, dev
);
2804 /* Stop TX/RX DMA and clear the descriptors */
2805 stmmac_stop_all_dma(priv
);
2807 /* Release and free the Rx/Tx resources */
2808 free_dma_desc_resources(priv
);
2810 /* Disable the MAC Rx/Tx */
2811 priv
->hw
->mac
->set_mac(priv
->ioaddr
, false);
2813 netif_carrier_off(dev
);
2815 #ifdef CONFIG_DEBUG_FS
2816 stmmac_exit_fs(dev
);
2819 stmmac_release_ptp(priv
);
2825 * stmmac_tso_allocator - close entry point of the driver
2826 * @priv: driver private structure
2827 * @des: buffer start address
2828 * @total_len: total length to fill in descriptors
2829 * @last_segmant: condition for the last descriptor
2830 * @queue: TX queue index
2832 * This function fills descriptor and request new descriptors according to
2833 * buffer length to fill
2835 static void stmmac_tso_allocator(struct stmmac_priv
*priv
, unsigned int des
,
2836 int total_len
, bool last_segment
, u32 queue
)
2838 struct stmmac_tx_queue
*tx_q
= &priv
->tx_queue
[queue
];
2839 struct dma_desc
*desc
;
2843 tmp_len
= total_len
;
2845 while (tmp_len
> 0) {
2846 tx_q
->cur_tx
= STMMAC_GET_ENTRY(tx_q
->cur_tx
, DMA_TX_SIZE
);
2847 WARN_ON(tx_q
->tx_skbuff
[tx_q
->cur_tx
]);
2848 desc
= tx_q
->dma_tx
+ tx_q
->cur_tx
;
2850 desc
->des0
= cpu_to_le32(des
+ (total_len
- tmp_len
));
2851 buff_size
= tmp_len
>= TSO_MAX_BUFF_SIZE
?
2852 TSO_MAX_BUFF_SIZE
: tmp_len
;
2854 priv
->hw
->desc
->prepare_tso_tx_desc(desc
, 0, buff_size
,
2856 (last_segment
) && (tmp_len
<= TSO_MAX_BUFF_SIZE
),
2859 tmp_len
-= TSO_MAX_BUFF_SIZE
;
2864 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2865 * @skb : the socket buffer
2866 * @dev : device pointer
2867 * Description: this is the transmit function that is called on TSO frames
2868 * (support available on GMAC4 and newer chips).
2869 * Diagram below show the ring programming in case of TSO frames:
2873 * | DES0 |---> buffer1 = L2/L3/L4 header
2874 * | DES1 |---> TCP Payload (can continue on next descr...)
2875 * | DES2 |---> buffer 1 and 2 len
2876 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2882 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2884 * | DES2 | --> buffer 1 and 2 len
2888 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2890 static netdev_tx_t
stmmac_tso_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2892 struct dma_desc
*desc
, *first
, *mss_desc
= NULL
;
2893 struct stmmac_priv
*priv
= netdev_priv(dev
);
2894 int nfrags
= skb_shinfo(skb
)->nr_frags
;
2895 u32 queue
= skb_get_queue_mapping(skb
);
2896 unsigned int first_entry
, des
;
2897 struct stmmac_tx_queue
*tx_q
;
2898 int tmp_pay_len
= 0;
2903 tx_q
= &priv
->tx_queue
[queue
];
2905 /* Compute header lengths */
2906 proto_hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
2908 /* Desc availability based on threshold should be enough safe */
2909 if (unlikely(stmmac_tx_avail(priv
, queue
) <
2910 (((skb
->len
- proto_hdr_len
) / TSO_MAX_BUFF_SIZE
+ 1)))) {
2911 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev
, queue
))) {
2912 netif_tx_stop_queue(netdev_get_tx_queue(priv
->dev
,
2914 /* This is a hard error, log it. */
2915 netdev_err(priv
->dev
,
2916 "%s: Tx Ring full when queue awake\n",
2919 return NETDEV_TX_BUSY
;
2922 pay_len
= skb_headlen(skb
) - proto_hdr_len
; /* no frags */
2924 mss
= skb_shinfo(skb
)->gso_size
;
2926 /* set new MSS value if needed */
2927 if (mss
!= tx_q
->mss
) {
2928 mss_desc
= tx_q
->dma_tx
+ tx_q
->cur_tx
;
2929 priv
->hw
->desc
->set_mss(mss_desc
, mss
);
2931 tx_q
->cur_tx
= STMMAC_GET_ENTRY(tx_q
->cur_tx
, DMA_TX_SIZE
);
2932 WARN_ON(tx_q
->tx_skbuff
[tx_q
->cur_tx
]);
2935 if (netif_msg_tx_queued(priv
)) {
2936 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2937 __func__
, tcp_hdrlen(skb
), proto_hdr_len
, pay_len
, mss
);
2938 pr_info("\tskb->len %d, skb->data_len %d\n", skb
->len
,
2942 first_entry
= tx_q
->cur_tx
;
2943 WARN_ON(tx_q
->tx_skbuff
[first_entry
]);
2945 desc
= tx_q
->dma_tx
+ first_entry
;
2948 /* first descriptor: fill Headers on Buf1 */
2949 des
= dma_map_single(priv
->device
, skb
->data
, skb_headlen(skb
),
2951 if (dma_mapping_error(priv
->device
, des
))
2954 tx_q
->tx_skbuff_dma
[first_entry
].buf
= des
;
2955 tx_q
->tx_skbuff_dma
[first_entry
].len
= skb_headlen(skb
);
2957 first
->des0
= cpu_to_le32(des
);
2959 /* Fill start of payload in buff2 of first descriptor */
2961 first
->des1
= cpu_to_le32(des
+ proto_hdr_len
);
2963 /* If needed take extra descriptors to fill the remaining payload */
2964 tmp_pay_len
= pay_len
- TSO_MAX_BUFF_SIZE
;
2966 stmmac_tso_allocator(priv
, des
, tmp_pay_len
, (nfrags
== 0), queue
);
2968 /* Prepare fragments */
2969 for (i
= 0; i
< nfrags
; i
++) {
2970 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2972 des
= skb_frag_dma_map(priv
->device
, frag
, 0,
2973 skb_frag_size(frag
),
2975 if (dma_mapping_error(priv
->device
, des
))
2978 stmmac_tso_allocator(priv
, des
, skb_frag_size(frag
),
2979 (i
== nfrags
- 1), queue
);
2981 tx_q
->tx_skbuff_dma
[tx_q
->cur_tx
].buf
= des
;
2982 tx_q
->tx_skbuff_dma
[tx_q
->cur_tx
].len
= skb_frag_size(frag
);
2983 tx_q
->tx_skbuff_dma
[tx_q
->cur_tx
].map_as_page
= true;
2986 tx_q
->tx_skbuff_dma
[tx_q
->cur_tx
].last_segment
= true;
2988 /* Only the last descriptor gets to point to the skb. */
2989 tx_q
->tx_skbuff
[tx_q
->cur_tx
] = skb
;
2991 /* We've used all descriptors we need for this skb, however,
2992 * advance cur_tx so that it references a fresh descriptor.
2993 * ndo_start_xmit will fill this descriptor the next time it's
2994 * called and stmmac_tx_clean may clean up to this descriptor.
2996 tx_q
->cur_tx
= STMMAC_GET_ENTRY(tx_q
->cur_tx
, DMA_TX_SIZE
);
2998 if (unlikely(stmmac_tx_avail(priv
, queue
) <= (MAX_SKB_FRAGS
+ 1))) {
2999 netif_dbg(priv
, hw
, priv
->dev
, "%s: stop transmitted packets\n",
3001 netif_tx_stop_queue(netdev_get_tx_queue(priv
->dev
, queue
));
3004 dev
->stats
.tx_bytes
+= skb
->len
;
3005 priv
->xstats
.tx_tso_frames
++;
3006 priv
->xstats
.tx_tso_nfrags
+= nfrags
;
3008 /* Manage tx mitigation */
3009 priv
->tx_count_frames
+= nfrags
+ 1;
3010 if (likely(priv
->tx_coal_frames
> priv
->tx_count_frames
)) {
3011 mod_timer(&priv
->txtimer
,
3012 STMMAC_COAL_TIMER(priv
->tx_coal_timer
));
3014 priv
->tx_count_frames
= 0;
3015 priv
->hw
->desc
->set_tx_ic(desc
);
3016 priv
->xstats
.tx_set_ic_bit
++;
3019 skb_tx_timestamp(skb
);
3021 if (unlikely((skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) &&
3022 priv
->hwts_tx_en
)) {
3023 /* declare that device is doing timestamping */
3024 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
3025 priv
->hw
->desc
->enable_tx_timestamp(first
);
3028 /* Complete the first descriptor before granting the DMA */
3029 priv
->hw
->desc
->prepare_tso_tx_desc(first
, 1,
3032 1, tx_q
->tx_skbuff_dma
[first_entry
].last_segment
,
3033 tcp_hdrlen(skb
) / 4, (skb
->len
- proto_hdr_len
));
3035 /* If context desc is used to change MSS */
3037 /* Make sure that first descriptor has been completely
3038 * written, including its own bit. This is because MSS is
3039 * actually before first descriptor, so we need to make
3040 * sure that MSS's own bit is the last thing written.
3043 priv
->hw
->desc
->set_tx_owner(mss_desc
);
3046 /* The own bit must be the latest setting done when prepare the
3047 * descriptor and then barrier is needed to make sure that
3048 * all is coherent before granting the DMA engine.
3052 if (netif_msg_pktdata(priv
)) {
3053 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
3054 __func__
, tx_q
->cur_tx
, tx_q
->dirty_tx
, first_entry
,
3055 tx_q
->cur_tx
, first
, nfrags
);
3057 priv
->hw
->desc
->display_ring((void *)tx_q
->dma_tx
, DMA_TX_SIZE
,
3060 pr_info(">>> frame to be transmitted: ");
3061 print_pkt(skb
->data
, skb_headlen(skb
));
3064 netdev_tx_sent_queue(netdev_get_tx_queue(dev
, queue
), skb
->len
);
3066 priv
->hw
->dma
->set_tx_tail_ptr(priv
->ioaddr
, tx_q
->tx_tail_addr
,
3069 return NETDEV_TX_OK
;
3072 dev_err(priv
->device
, "Tx dma map failed\n");
3074 priv
->dev
->stats
.tx_dropped
++;
3075 return NETDEV_TX_OK
;
3079 * stmmac_xmit - Tx entry point of the driver
3080 * @skb : the socket buffer
3081 * @dev : device pointer
3082 * Description : this is the tx entry point of the driver.
3083 * It programs the chain or the ring and supports oversized frames
3086 static netdev_tx_t
stmmac_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3088 struct stmmac_priv
*priv
= netdev_priv(dev
);
3089 unsigned int nopaged_len
= skb_headlen(skb
);
3090 int i
, csum_insertion
= 0, is_jumbo
= 0;
3091 u32 queue
= skb_get_queue_mapping(skb
);
3092 int nfrags
= skb_shinfo(skb
)->nr_frags
;
3094 unsigned int first_entry
;
3095 struct dma_desc
*desc
, *first
;
3096 struct stmmac_tx_queue
*tx_q
;
3097 unsigned int enh_desc
;
3100 tx_q
= &priv
->tx_queue
[queue
];
3102 /* Manage oversized TCP frames for GMAC4 device */
3103 if (skb_is_gso(skb
) && priv
->tso
) {
3104 if (skb_shinfo(skb
)->gso_type
& (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
))
3105 return stmmac_tso_xmit(skb
, dev
);
3108 if (unlikely(stmmac_tx_avail(priv
, queue
) < nfrags
+ 1)) {
3109 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev
, queue
))) {
3110 netif_tx_stop_queue(netdev_get_tx_queue(priv
->dev
,
3112 /* This is a hard error, log it. */
3113 netdev_err(priv
->dev
,
3114 "%s: Tx Ring full when queue awake\n",
3117 return NETDEV_TX_BUSY
;
3120 if (priv
->tx_path_in_lpi_mode
)
3121 stmmac_disable_eee_mode(priv
);
3123 entry
= tx_q
->cur_tx
;
3124 first_entry
= entry
;
3125 WARN_ON(tx_q
->tx_skbuff
[first_entry
]);
3127 csum_insertion
= (skb
->ip_summed
== CHECKSUM_PARTIAL
);
3129 if (likely(priv
->extend_desc
))
3130 desc
= (struct dma_desc
*)(tx_q
->dma_etx
+ entry
);
3132 desc
= tx_q
->dma_tx
+ entry
;
3136 enh_desc
= priv
->plat
->enh_desc
;
3137 /* To program the descriptors according to the size of the frame */
3139 is_jumbo
= priv
->hw
->mode
->is_jumbo_frm(skb
->len
, enh_desc
);
3141 if (unlikely(is_jumbo
) && likely(priv
->synopsys_id
<
3143 entry
= priv
->hw
->mode
->jumbo_frm(tx_q
, skb
, csum_insertion
);
3144 if (unlikely(entry
< 0))
3148 for (i
= 0; i
< nfrags
; i
++) {
3149 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
3150 int len
= skb_frag_size(frag
);
3151 bool last_segment
= (i
== (nfrags
- 1));
3153 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
3154 WARN_ON(tx_q
->tx_skbuff
[entry
]);
3156 if (likely(priv
->extend_desc
))
3157 desc
= (struct dma_desc
*)(tx_q
->dma_etx
+ entry
);
3159 desc
= tx_q
->dma_tx
+ entry
;
3161 des
= skb_frag_dma_map(priv
->device
, frag
, 0, len
,
3163 if (dma_mapping_error(priv
->device
, des
))
3164 goto dma_map_err
; /* should reuse desc w/o issues */
3166 tx_q
->tx_skbuff_dma
[entry
].buf
= des
;
3167 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
))
3168 desc
->des0
= cpu_to_le32(des
);
3170 desc
->des2
= cpu_to_le32(des
);
3172 tx_q
->tx_skbuff_dma
[entry
].map_as_page
= true;
3173 tx_q
->tx_skbuff_dma
[entry
].len
= len
;
3174 tx_q
->tx_skbuff_dma
[entry
].last_segment
= last_segment
;
3176 /* Prepare the descriptor and set the own bit too */
3177 priv
->hw
->desc
->prepare_tx_desc(desc
, 0, len
, csum_insertion
,
3178 priv
->mode
, 1, last_segment
,
3182 /* Only the last descriptor gets to point to the skb. */
3183 tx_q
->tx_skbuff
[entry
] = skb
;
3185 /* We've used all descriptors we need for this skb, however,
3186 * advance cur_tx so that it references a fresh descriptor.
3187 * ndo_start_xmit will fill this descriptor the next time it's
3188 * called and stmmac_tx_clean may clean up to this descriptor.
3190 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
3191 tx_q
->cur_tx
= entry
;
3193 if (netif_msg_pktdata(priv
)) {
3196 netdev_dbg(priv
->dev
,
3197 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3198 __func__
, tx_q
->cur_tx
, tx_q
->dirty_tx
, first_entry
,
3199 entry
, first
, nfrags
);
3201 if (priv
->extend_desc
)
3202 tx_head
= (void *)tx_q
->dma_etx
;
3204 tx_head
= (void *)tx_q
->dma_tx
;
3206 priv
->hw
->desc
->display_ring(tx_head
, DMA_TX_SIZE
, false);
3208 netdev_dbg(priv
->dev
, ">>> frame to be transmitted: ");
3209 print_pkt(skb
->data
, skb
->len
);
3212 if (unlikely(stmmac_tx_avail(priv
, queue
) <= (MAX_SKB_FRAGS
+ 1))) {
3213 netif_dbg(priv
, hw
, priv
->dev
, "%s: stop transmitted packets\n",
3215 netif_tx_stop_queue(netdev_get_tx_queue(priv
->dev
, queue
));
3218 dev
->stats
.tx_bytes
+= skb
->len
;
3220 /* According to the coalesce parameter the IC bit for the latest
3221 * segment is reset and the timer re-started to clean the tx status.
3222 * This approach takes care about the fragments: desc is the first
3223 * element in case of no SG.
3225 priv
->tx_count_frames
+= nfrags
+ 1;
3226 if (likely(priv
->tx_coal_frames
> priv
->tx_count_frames
)) {
3227 mod_timer(&priv
->txtimer
,
3228 STMMAC_COAL_TIMER(priv
->tx_coal_timer
));
3230 priv
->tx_count_frames
= 0;
3231 priv
->hw
->desc
->set_tx_ic(desc
);
3232 priv
->xstats
.tx_set_ic_bit
++;
3235 skb_tx_timestamp(skb
);
3237 /* Ready to fill the first descriptor and set the OWN bit w/o any
3238 * problems because all the descriptors are actually ready to be
3239 * passed to the DMA engine.
3241 if (likely(!is_jumbo
)) {
3242 bool last_segment
= (nfrags
== 0);
3244 des
= dma_map_single(priv
->device
, skb
->data
,
3245 nopaged_len
, DMA_TO_DEVICE
);
3246 if (dma_mapping_error(priv
->device
, des
))
3249 tx_q
->tx_skbuff_dma
[first_entry
].buf
= des
;
3250 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
))
3251 first
->des0
= cpu_to_le32(des
);
3253 first
->des2
= cpu_to_le32(des
);
3255 tx_q
->tx_skbuff_dma
[first_entry
].len
= nopaged_len
;
3256 tx_q
->tx_skbuff_dma
[first_entry
].last_segment
= last_segment
;
3258 if (unlikely((skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) &&
3259 priv
->hwts_tx_en
)) {
3260 /* declare that device is doing timestamping */
3261 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
3262 priv
->hw
->desc
->enable_tx_timestamp(first
);
3265 /* Prepare the first descriptor setting the OWN bit too */
3266 priv
->hw
->desc
->prepare_tx_desc(first
, 1, nopaged_len
,
3267 csum_insertion
, priv
->mode
, 1,
3268 last_segment
, skb
->len
);
3270 /* The own bit must be the latest setting done when prepare the
3271 * descriptor and then barrier is needed to make sure that
3272 * all is coherent before granting the DMA engine.
3277 netdev_tx_sent_queue(netdev_get_tx_queue(dev
, queue
), skb
->len
);
3279 if (priv
->synopsys_id
< DWMAC_CORE_4_00
)
3280 priv
->hw
->dma
->enable_dma_transmission(priv
->ioaddr
);
3282 priv
->hw
->dma
->set_tx_tail_ptr(priv
->ioaddr
, tx_q
->tx_tail_addr
,
3285 return NETDEV_TX_OK
;
3288 netdev_err(priv
->dev
, "Tx DMA map failed\n");
3290 priv
->dev
->stats
.tx_dropped
++;
3291 return NETDEV_TX_OK
;
3294 static void stmmac_rx_vlan(struct net_device
*dev
, struct sk_buff
*skb
)
3296 struct ethhdr
*ehdr
;
3299 if ((dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) ==
3300 NETIF_F_HW_VLAN_CTAG_RX
&&
3301 !__vlan_get_tag(skb
, &vlanid
)) {
3302 /* pop the vlan tag */
3303 ehdr
= (struct ethhdr
*)skb
->data
;
3304 memmove(skb
->data
+ VLAN_HLEN
, ehdr
, ETH_ALEN
* 2);
3305 skb_pull(skb
, VLAN_HLEN
);
3306 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vlanid
);
3311 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue
*rx_q
)
3313 if (rx_q
->rx_zeroc_thresh
< STMMAC_RX_THRESH
)
3320 * stmmac_rx_refill - refill used skb preallocated buffers
3321 * @priv: driver private structure
3322 * @queue: RX queue index
3323 * Description : this is to reallocate the skb for the reception process
3324 * that is based on zero-copy.
3326 static inline void stmmac_rx_refill(struct stmmac_priv
*priv
, u32 queue
)
3328 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
3329 int dirty
= stmmac_rx_dirty(priv
, queue
);
3330 unsigned int entry
= rx_q
->dirty_rx
;
3332 int bfsize
= priv
->dma_buf_sz
;
3334 while (dirty
-- > 0) {
3337 if (priv
->extend_desc
)
3338 p
= (struct dma_desc
*)(rx_q
->dma_erx
+ entry
);
3340 p
= rx_q
->dma_rx
+ entry
;
3342 if (likely(!rx_q
->rx_skbuff
[entry
])) {
3343 struct sk_buff
*skb
;
3345 skb
= netdev_alloc_skb_ip_align(priv
->dev
, bfsize
);
3346 if (unlikely(!skb
)) {
3347 /* so for a while no zero-copy! */
3348 rx_q
->rx_zeroc_thresh
= STMMAC_RX_THRESH
;
3349 if (unlikely(net_ratelimit()))
3350 dev_err(priv
->device
,
3351 "fail to alloc skb entry %d\n",
3356 rx_q
->rx_skbuff
[entry
] = skb
;
3357 rx_q
->rx_skbuff_dma
[entry
] =
3358 dma_map_single(priv
->device
, skb
->data
, bfsize
,
3360 if (dma_mapping_error(priv
->device
,
3361 rx_q
->rx_skbuff_dma
[entry
])) {
3362 netdev_err(priv
->dev
, "Rx DMA map failed\n");
3367 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
)) {
3368 p
->des0
= cpu_to_le32(rx_q
->rx_skbuff_dma
[entry
]);
3371 p
->des2
= cpu_to_le32(rx_q
->rx_skbuff_dma
[entry
]);
3373 if (priv
->hw
->mode
->refill_desc3
)
3374 priv
->hw
->mode
->refill_desc3(rx_q
, p
);
3376 if (rx_q
->rx_zeroc_thresh
> 0)
3377 rx_q
->rx_zeroc_thresh
--;
3379 netif_dbg(priv
, rx_status
, priv
->dev
,
3380 "refill entry #%d\n", entry
);
3384 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
))
3385 priv
->hw
->desc
->init_rx_desc(p
, priv
->use_riwt
, 0, 0);
3387 priv
->hw
->desc
->set_rx_owner(p
);
3391 entry
= STMMAC_GET_ENTRY(entry
, DMA_RX_SIZE
);
3393 rx_q
->dirty_rx
= entry
;
3397 * stmmac_rx - manage the receive process
3398 * @priv: driver private structure
3399 * @limit: napi bugget
3400 * @queue: RX queue index.
3401 * Description : this the function called by the napi poll method.
3402 * It gets all the frames inside the ring.
3404 static int stmmac_rx(struct stmmac_priv
*priv
, int limit
, u32 queue
)
3406 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
3407 unsigned int entry
= rx_q
->cur_rx
;
3408 int coe
= priv
->hw
->rx_csum
;
3409 unsigned int next_entry
;
3410 unsigned int count
= 0;
3412 if (netif_msg_rx_status(priv
)) {
3415 netdev_dbg(priv
->dev
, "%s: descriptor ring:\n", __func__
);
3416 if (priv
->extend_desc
)
3417 rx_head
= (void *)rx_q
->dma_erx
;
3419 rx_head
= (void *)rx_q
->dma_rx
;
3421 priv
->hw
->desc
->display_ring(rx_head
, DMA_RX_SIZE
, true);
3423 while (count
< limit
) {
3426 struct dma_desc
*np
;
3428 if (priv
->extend_desc
)
3429 p
= (struct dma_desc
*)(rx_q
->dma_erx
+ entry
);
3431 p
= rx_q
->dma_rx
+ entry
;
3433 /* read the status of the incoming frame */
3434 status
= priv
->hw
->desc
->rx_status(&priv
->dev
->stats
,
3436 /* check if managed by the DMA otherwise go ahead */
3437 if (unlikely(status
& dma_own
))
3442 rx_q
->cur_rx
= STMMAC_GET_ENTRY(rx_q
->cur_rx
, DMA_RX_SIZE
);
3443 next_entry
= rx_q
->cur_rx
;
3445 if (priv
->extend_desc
)
3446 np
= (struct dma_desc
*)(rx_q
->dma_erx
+ next_entry
);
3448 np
= rx_q
->dma_rx
+ next_entry
;
3452 if ((priv
->extend_desc
) && (priv
->hw
->desc
->rx_extended_status
))
3453 priv
->hw
->desc
->rx_extended_status(&priv
->dev
->stats
,
3457 if (unlikely(status
== discard_frame
)) {
3458 priv
->dev
->stats
.rx_errors
++;
3459 if (priv
->hwts_rx_en
&& !priv
->extend_desc
) {
3460 /* DESC2 & DESC3 will be overwritten by device
3461 * with timestamp value, hence reinitialize
3462 * them in stmmac_rx_refill() function so that
3463 * device can reuse it.
3465 dev_kfree_skb_any(rx_q
->rx_skbuff
[entry
]);
3466 rx_q
->rx_skbuff
[entry
] = NULL
;
3467 dma_unmap_single(priv
->device
,
3468 rx_q
->rx_skbuff_dma
[entry
],
3473 struct sk_buff
*skb
;
3477 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
))
3478 des
= le32_to_cpu(p
->des0
);
3480 des
= le32_to_cpu(p
->des2
);
3482 frame_len
= priv
->hw
->desc
->get_rx_frame_len(p
, coe
);
3484 /* If frame length is greater than skb buffer size
3485 * (preallocated during init) then the packet is
3488 if (frame_len
> priv
->dma_buf_sz
) {
3489 netdev_err(priv
->dev
,
3490 "len %d larger than size (%d)\n",
3491 frame_len
, priv
->dma_buf_sz
);
3492 priv
->dev
->stats
.rx_length_errors
++;
3496 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3497 * Type frames (LLC/LLC-SNAP)
3499 * llc_snap is never checked in GMAC >= 4, so this ACS
3500 * feature is always disabled and packets need to be
3501 * stripped manually.
3503 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
) ||
3504 unlikely(status
!= llc_snap
))
3505 frame_len
-= ETH_FCS_LEN
;
3507 if (netif_msg_rx_status(priv
)) {
3508 netdev_dbg(priv
->dev
, "\tdesc: %p [entry %d] buff=0x%x\n",
3510 netdev_dbg(priv
->dev
, "frame size %d, COE: %d\n",
3514 /* The zero-copy is always used for all the sizes
3515 * in case of GMAC4 because it needs
3516 * to refill the used descriptors, always.
3518 if (unlikely(!priv
->plat
->has_gmac4
&&
3519 ((frame_len
< priv
->rx_copybreak
) ||
3520 stmmac_rx_threshold_count(rx_q
)))) {
3521 skb
= netdev_alloc_skb_ip_align(priv
->dev
,
3523 if (unlikely(!skb
)) {
3524 if (net_ratelimit())
3525 dev_warn(priv
->device
,
3526 "packet dropped\n");
3527 priv
->dev
->stats
.rx_dropped
++;
3531 dma_sync_single_for_cpu(priv
->device
,
3535 skb_copy_to_linear_data(skb
,
3537 rx_skbuff
[entry
]->data
,
3540 skb_put(skb
, frame_len
);
3541 dma_sync_single_for_device(priv
->device
,
3546 skb
= rx_q
->rx_skbuff
[entry
];
3547 if (unlikely(!skb
)) {
3548 netdev_err(priv
->dev
,
3549 "%s: Inconsistent Rx chain\n",
3551 priv
->dev
->stats
.rx_dropped
++;
3554 prefetch(skb
->data
- NET_IP_ALIGN
);
3555 rx_q
->rx_skbuff
[entry
] = NULL
;
3556 rx_q
->rx_zeroc_thresh
++;
3558 skb_put(skb
, frame_len
);
3559 dma_unmap_single(priv
->device
,
3560 rx_q
->rx_skbuff_dma
[entry
],
3565 if (netif_msg_pktdata(priv
)) {
3566 netdev_dbg(priv
->dev
, "frame received (%dbytes)",
3568 print_pkt(skb
->data
, frame_len
);
3571 stmmac_get_rx_hwtstamp(priv
, p
, np
, skb
);
3573 stmmac_rx_vlan(priv
->dev
, skb
);
3575 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
3578 skb_checksum_none_assert(skb
);
3580 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3582 napi_gro_receive(&rx_q
->napi
, skb
);
3584 priv
->dev
->stats
.rx_packets
++;
3585 priv
->dev
->stats
.rx_bytes
+= frame_len
;
3590 stmmac_rx_refill(priv
, queue
);
3592 priv
->xstats
.rx_pkt_n
+= count
;
3598 * stmmac_poll - stmmac poll method (NAPI)
3599 * @napi : pointer to the napi structure.
3600 * @budget : maximum number of packets that the current CPU can receive from
3603 * To look at the incoming frames and clear the tx resources.
3605 static int stmmac_poll(struct napi_struct
*napi
, int budget
)
3607 struct stmmac_rx_queue
*rx_q
=
3608 container_of(napi
, struct stmmac_rx_queue
, napi
);
3609 struct stmmac_priv
*priv
= rx_q
->priv_data
;
3610 u32 tx_count
= priv
->plat
->tx_queues_to_use
;
3611 u32 chan
= rx_q
->queue_index
;
3615 priv
->xstats
.napi_poll
++;
3617 /* check all the queues */
3618 for (queue
= 0; queue
< tx_count
; queue
++)
3619 stmmac_tx_clean(priv
, queue
);
3621 work_done
= stmmac_rx(priv
, budget
, rx_q
->queue_index
);
3622 if (work_done
< budget
) {
3623 napi_complete_done(napi
, work_done
);
3624 stmmac_enable_dma_irq(priv
, chan
);
3631 * @dev : Pointer to net device structure
3632 * Description: this function is called when a packet transmission fails to
3633 * complete within a reasonable time. The driver will mark the error in the
3634 * netdev structure and arrange for the device to be reset to a sane state
3635 * in order to transmit a new packet.
3637 static void stmmac_tx_timeout(struct net_device
*dev
)
3639 struct stmmac_priv
*priv
= netdev_priv(dev
);
3641 stmmac_global_err(priv
);
3645 * stmmac_set_rx_mode - entry point for multicast addressing
3646 * @dev : pointer to the device structure
3648 * This function is a driver entry point which gets called by the kernel
3649 * whenever multicast addresses must be enabled/disabled.
3653 static void stmmac_set_rx_mode(struct net_device
*dev
)
3655 struct stmmac_priv
*priv
= netdev_priv(dev
);
3657 priv
->hw
->mac
->set_filter(priv
->hw
, dev
);
3661 * stmmac_change_mtu - entry point to change MTU size for the device.
3662 * @dev : device pointer.
3663 * @new_mtu : the new MTU size for the device.
3664 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3665 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3666 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3668 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3671 static int stmmac_change_mtu(struct net_device
*dev
, int new_mtu
)
3673 struct stmmac_priv
*priv
= netdev_priv(dev
);
3675 if (netif_running(dev
)) {
3676 netdev_err(priv
->dev
, "must be stopped to change its MTU\n");
3682 netdev_update_features(dev
);
3687 static netdev_features_t
stmmac_fix_features(struct net_device
*dev
,
3688 netdev_features_t features
)
3690 struct stmmac_priv
*priv
= netdev_priv(dev
);
3692 if (priv
->plat
->rx_coe
== STMMAC_RX_COE_NONE
)
3693 features
&= ~NETIF_F_RXCSUM
;
3695 if (!priv
->plat
->tx_coe
)
3696 features
&= ~NETIF_F_CSUM_MASK
;
3698 /* Some GMAC devices have a bugged Jumbo frame support that
3699 * needs to have the Tx COE disabled for oversized frames
3700 * (due to limited buffer sizes). In this case we disable
3701 * the TX csum insertion in the TDES and not use SF.
3703 if (priv
->plat
->bugged_jumbo
&& (dev
->mtu
> ETH_DATA_LEN
))
3704 features
&= ~NETIF_F_CSUM_MASK
;
3706 /* Disable tso if asked by ethtool */
3707 if ((priv
->plat
->tso_en
) && (priv
->dma_cap
.tsoen
)) {
3708 if (features
& NETIF_F_TSO
)
3717 static int stmmac_set_features(struct net_device
*netdev
,
3718 netdev_features_t features
)
3720 struct stmmac_priv
*priv
= netdev_priv(netdev
);
3722 /* Keep the COE Type in case of csum is supporting */
3723 if (features
& NETIF_F_RXCSUM
)
3724 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
3726 priv
->hw
->rx_csum
= 0;
3727 /* No check needed because rx_coe has been set before and it will be
3728 * fixed in case of issue.
3730 priv
->hw
->mac
->rx_ipc(priv
->hw
);
3736 * stmmac_interrupt - main ISR
3737 * @irq: interrupt number.
3738 * @dev_id: to pass the net device pointer.
3739 * Description: this is the main driver interrupt service routine.
3741 * o DMA service routine (to manage incoming frame reception and transmission
3743 * o Core interrupts to manage: remote wake-up, management counter, LPI
3746 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
)
3748 struct net_device
*dev
= (struct net_device
*)dev_id
;
3749 struct stmmac_priv
*priv
= netdev_priv(dev
);
3750 u32 rx_cnt
= priv
->plat
->rx_queues_to_use
;
3751 u32 tx_cnt
= priv
->plat
->tx_queues_to_use
;
3755 queues_count
= (rx_cnt
> tx_cnt
) ? rx_cnt
: tx_cnt
;
3758 pm_wakeup_event(priv
->device
, 0);
3760 if (unlikely(!dev
)) {
3761 netdev_err(priv
->dev
, "%s: invalid dev pointer\n", __func__
);
3765 /* Check if adapter is up */
3766 if (test_bit(STMMAC_DOWN
, &priv
->state
))
3768 /* Check if a fatal error happened */
3769 if (stmmac_safety_feat_interrupt(priv
))
3772 /* To handle GMAC own interrupts */
3773 if ((priv
->plat
->has_gmac
) || (priv
->plat
->has_gmac4
)) {
3774 int status
= priv
->hw
->mac
->host_irq_status(priv
->hw
,
3777 if (unlikely(status
)) {
3778 /* For LPI we need to save the tx status */
3779 if (status
& CORE_IRQ_TX_PATH_IN_LPI_MODE
)
3780 priv
->tx_path_in_lpi_mode
= true;
3781 if (status
& CORE_IRQ_TX_PATH_EXIT_LPI_MODE
)
3782 priv
->tx_path_in_lpi_mode
= false;
3785 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
3786 for (queue
= 0; queue
< queues_count
; queue
++) {
3787 struct stmmac_rx_queue
*rx_q
=
3788 &priv
->rx_queue
[queue
];
3791 priv
->hw
->mac
->host_mtl_irq_status(priv
->hw
,
3794 if (status
& CORE_IRQ_MTL_RX_OVERFLOW
&&
3795 priv
->hw
->dma
->set_rx_tail_ptr
)
3796 priv
->hw
->dma
->set_rx_tail_ptr(priv
->ioaddr
,
3802 /* PCS link status */
3803 if (priv
->hw
->pcs
) {
3804 if (priv
->xstats
.pcs_link
)
3805 netif_carrier_on(dev
);
3807 netif_carrier_off(dev
);
3811 /* To handle DMA interrupts */
3812 stmmac_dma_interrupt(priv
);
3817 #ifdef CONFIG_NET_POLL_CONTROLLER
3818 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3819 * to allow network I/O with interrupts disabled.
3821 static void stmmac_poll_controller(struct net_device
*dev
)
3823 disable_irq(dev
->irq
);
3824 stmmac_interrupt(dev
->irq
, dev
);
3825 enable_irq(dev
->irq
);
3830 * stmmac_ioctl - Entry point for the Ioctl
3831 * @dev: Device pointer.
3832 * @rq: An IOCTL specefic structure, that can contain a pointer to
3833 * a proprietary structure used to pass information to the driver.
3834 * @cmd: IOCTL command
3836 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3838 static int stmmac_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
3840 int ret
= -EOPNOTSUPP
;
3842 if (!netif_running(dev
))
3851 ret
= phy_mii_ioctl(dev
->phydev
, rq
, cmd
);
3854 ret
= stmmac_hwtstamp_ioctl(dev
, rq
);
3863 static int stmmac_set_mac_address(struct net_device
*ndev
, void *addr
)
3865 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3868 ret
= eth_mac_addr(ndev
, addr
);
3872 priv
->hw
->mac
->set_umac_addr(priv
->hw
, ndev
->dev_addr
, 0);
3877 #ifdef CONFIG_DEBUG_FS
3878 static struct dentry
*stmmac_fs_dir
;
3880 static void sysfs_display_ring(void *head
, int size
, int extend_desc
,
3881 struct seq_file
*seq
)
3884 struct dma_extended_desc
*ep
= (struct dma_extended_desc
*)head
;
3885 struct dma_desc
*p
= (struct dma_desc
*)head
;
3887 for (i
= 0; i
< size
; i
++) {
3889 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3890 i
, (unsigned int)virt_to_phys(ep
),
3891 le32_to_cpu(ep
->basic
.des0
),
3892 le32_to_cpu(ep
->basic
.des1
),
3893 le32_to_cpu(ep
->basic
.des2
),
3894 le32_to_cpu(ep
->basic
.des3
));
3897 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3898 i
, (unsigned int)virt_to_phys(p
),
3899 le32_to_cpu(p
->des0
), le32_to_cpu(p
->des1
),
3900 le32_to_cpu(p
->des2
), le32_to_cpu(p
->des3
));
3903 seq_printf(seq
, "\n");
3907 static int stmmac_sysfs_ring_read(struct seq_file
*seq
, void *v
)
3909 struct net_device
*dev
= seq
->private;
3910 struct stmmac_priv
*priv
= netdev_priv(dev
);
3911 u32 rx_count
= priv
->plat
->rx_queues_to_use
;
3912 u32 tx_count
= priv
->plat
->tx_queues_to_use
;
3915 for (queue
= 0; queue
< rx_count
; queue
++) {
3916 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
3918 seq_printf(seq
, "RX Queue %d:\n", queue
);
3920 if (priv
->extend_desc
) {
3921 seq_printf(seq
, "Extended descriptor ring:\n");
3922 sysfs_display_ring((void *)rx_q
->dma_erx
,
3923 DMA_RX_SIZE
, 1, seq
);
3925 seq_printf(seq
, "Descriptor ring:\n");
3926 sysfs_display_ring((void *)rx_q
->dma_rx
,
3927 DMA_RX_SIZE
, 0, seq
);
3931 for (queue
= 0; queue
< tx_count
; queue
++) {
3932 struct stmmac_tx_queue
*tx_q
= &priv
->tx_queue
[queue
];
3934 seq_printf(seq
, "TX Queue %d:\n", queue
);
3936 if (priv
->extend_desc
) {
3937 seq_printf(seq
, "Extended descriptor ring:\n");
3938 sysfs_display_ring((void *)tx_q
->dma_etx
,
3939 DMA_TX_SIZE
, 1, seq
);
3941 seq_printf(seq
, "Descriptor ring:\n");
3942 sysfs_display_ring((void *)tx_q
->dma_tx
,
3943 DMA_TX_SIZE
, 0, seq
);
3950 static int stmmac_sysfs_ring_open(struct inode
*inode
, struct file
*file
)
3952 return single_open(file
, stmmac_sysfs_ring_read
, inode
->i_private
);
3955 /* Debugfs files, should appear in /sys/kernel/debug/stmmaceth/eth0 */
3957 static const struct file_operations stmmac_rings_status_fops
= {
3958 .owner
= THIS_MODULE
,
3959 .open
= stmmac_sysfs_ring_open
,
3961 .llseek
= seq_lseek
,
3962 .release
= single_release
,
3965 static int stmmac_sysfs_dma_cap_read(struct seq_file
*seq
, void *v
)
3967 struct net_device
*dev
= seq
->private;
3968 struct stmmac_priv
*priv
= netdev_priv(dev
);
3970 if (!priv
->hw_cap_support
) {
3971 seq_printf(seq
, "DMA HW features not supported\n");
3975 seq_printf(seq
, "==============================\n");
3976 seq_printf(seq
, "\tDMA HW features\n");
3977 seq_printf(seq
, "==============================\n");
3979 seq_printf(seq
, "\t10/100 Mbps: %s\n",
3980 (priv
->dma_cap
.mbps_10_100
) ? "Y" : "N");
3981 seq_printf(seq
, "\t1000 Mbps: %s\n",
3982 (priv
->dma_cap
.mbps_1000
) ? "Y" : "N");
3983 seq_printf(seq
, "\tHalf duplex: %s\n",
3984 (priv
->dma_cap
.half_duplex
) ? "Y" : "N");
3985 seq_printf(seq
, "\tHash Filter: %s\n",
3986 (priv
->dma_cap
.hash_filter
) ? "Y" : "N");
3987 seq_printf(seq
, "\tMultiple MAC address registers: %s\n",
3988 (priv
->dma_cap
.multi_addr
) ? "Y" : "N");
3989 seq_printf(seq
, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3990 (priv
->dma_cap
.pcs
) ? "Y" : "N");
3991 seq_printf(seq
, "\tSMA (MDIO) Interface: %s\n",
3992 (priv
->dma_cap
.sma_mdio
) ? "Y" : "N");
3993 seq_printf(seq
, "\tPMT Remote wake up: %s\n",
3994 (priv
->dma_cap
.pmt_remote_wake_up
) ? "Y" : "N");
3995 seq_printf(seq
, "\tPMT Magic Frame: %s\n",
3996 (priv
->dma_cap
.pmt_magic_frame
) ? "Y" : "N");
3997 seq_printf(seq
, "\tRMON module: %s\n",
3998 (priv
->dma_cap
.rmon
) ? "Y" : "N");
3999 seq_printf(seq
, "\tIEEE 1588-2002 Time Stamp: %s\n",
4000 (priv
->dma_cap
.time_stamp
) ? "Y" : "N");
4001 seq_printf(seq
, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
4002 (priv
->dma_cap
.atime_stamp
) ? "Y" : "N");
4003 seq_printf(seq
, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
4004 (priv
->dma_cap
.eee
) ? "Y" : "N");
4005 seq_printf(seq
, "\tAV features: %s\n", (priv
->dma_cap
.av
) ? "Y" : "N");
4006 seq_printf(seq
, "\tChecksum Offload in TX: %s\n",
4007 (priv
->dma_cap
.tx_coe
) ? "Y" : "N");
4008 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
4009 seq_printf(seq
, "\tIP Checksum Offload in RX: %s\n",
4010 (priv
->dma_cap
.rx_coe
) ? "Y" : "N");
4012 seq_printf(seq
, "\tIP Checksum Offload (type1) in RX: %s\n",
4013 (priv
->dma_cap
.rx_coe_type1
) ? "Y" : "N");
4014 seq_printf(seq
, "\tIP Checksum Offload (type2) in RX: %s\n",
4015 (priv
->dma_cap
.rx_coe_type2
) ? "Y" : "N");
4017 seq_printf(seq
, "\tRXFIFO > 2048bytes: %s\n",
4018 (priv
->dma_cap
.rxfifo_over_2048
) ? "Y" : "N");
4019 seq_printf(seq
, "\tNumber of Additional RX channel: %d\n",
4020 priv
->dma_cap
.number_rx_channel
);
4021 seq_printf(seq
, "\tNumber of Additional TX channel: %d\n",
4022 priv
->dma_cap
.number_tx_channel
);
4023 seq_printf(seq
, "\tEnhanced descriptors: %s\n",
4024 (priv
->dma_cap
.enh_desc
) ? "Y" : "N");
4029 static int stmmac_sysfs_dma_cap_open(struct inode
*inode
, struct file
*file
)
4031 return single_open(file
, stmmac_sysfs_dma_cap_read
, inode
->i_private
);
4034 static const struct file_operations stmmac_dma_cap_fops
= {
4035 .owner
= THIS_MODULE
,
4036 .open
= stmmac_sysfs_dma_cap_open
,
4038 .llseek
= seq_lseek
,
4039 .release
= single_release
,
4042 static int stmmac_init_fs(struct net_device
*dev
)
4044 struct stmmac_priv
*priv
= netdev_priv(dev
);
4046 /* Create per netdev entries */
4047 priv
->dbgfs_dir
= debugfs_create_dir(dev
->name
, stmmac_fs_dir
);
4049 if (!priv
->dbgfs_dir
|| IS_ERR(priv
->dbgfs_dir
)) {
4050 netdev_err(priv
->dev
, "ERROR failed to create debugfs directory\n");
4055 /* Entry to report DMA RX/TX rings */
4056 priv
->dbgfs_rings_status
=
4057 debugfs_create_file("descriptors_status", 0444,
4058 priv
->dbgfs_dir
, dev
,
4059 &stmmac_rings_status_fops
);
4061 if (!priv
->dbgfs_rings_status
|| IS_ERR(priv
->dbgfs_rings_status
)) {
4062 netdev_err(priv
->dev
, "ERROR creating stmmac ring debugfs file\n");
4063 debugfs_remove_recursive(priv
->dbgfs_dir
);
4068 /* Entry to report the DMA HW features */
4069 priv
->dbgfs_dma_cap
= debugfs_create_file("dma_cap", 0444,
4071 dev
, &stmmac_dma_cap_fops
);
4073 if (!priv
->dbgfs_dma_cap
|| IS_ERR(priv
->dbgfs_dma_cap
)) {
4074 netdev_err(priv
->dev
, "ERROR creating stmmac MMC debugfs file\n");
4075 debugfs_remove_recursive(priv
->dbgfs_dir
);
4083 static void stmmac_exit_fs(struct net_device
*dev
)
4085 struct stmmac_priv
*priv
= netdev_priv(dev
);
4087 debugfs_remove_recursive(priv
->dbgfs_dir
);
4089 #endif /* CONFIG_DEBUG_FS */
4091 static const struct net_device_ops stmmac_netdev_ops
= {
4092 .ndo_open
= stmmac_open
,
4093 .ndo_start_xmit
= stmmac_xmit
,
4094 .ndo_stop
= stmmac_release
,
4095 .ndo_change_mtu
= stmmac_change_mtu
,
4096 .ndo_fix_features
= stmmac_fix_features
,
4097 .ndo_set_features
= stmmac_set_features
,
4098 .ndo_set_rx_mode
= stmmac_set_rx_mode
,
4099 .ndo_tx_timeout
= stmmac_tx_timeout
,
4100 .ndo_do_ioctl
= stmmac_ioctl
,
4101 #ifdef CONFIG_NET_POLL_CONTROLLER
4102 .ndo_poll_controller
= stmmac_poll_controller
,
4104 .ndo_set_mac_address
= stmmac_set_mac_address
,
4107 static void stmmac_reset_subtask(struct stmmac_priv
*priv
)
4109 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED
, &priv
->state
))
4111 if (test_bit(STMMAC_DOWN
, &priv
->state
))
4114 netdev_err(priv
->dev
, "Reset adapter.\n");
4117 netif_trans_update(priv
->dev
);
4118 while (test_and_set_bit(STMMAC_RESETING
, &priv
->state
))
4119 usleep_range(1000, 2000);
4121 set_bit(STMMAC_DOWN
, &priv
->state
);
4122 dev_close(priv
->dev
);
4123 dev_open(priv
->dev
);
4124 clear_bit(STMMAC_DOWN
, &priv
->state
);
4125 clear_bit(STMMAC_RESETING
, &priv
->state
);
4129 static void stmmac_service_task(struct work_struct
*work
)
4131 struct stmmac_priv
*priv
= container_of(work
, struct stmmac_priv
,
4134 stmmac_reset_subtask(priv
);
4135 clear_bit(STMMAC_SERVICE_SCHED
, &priv
->state
);
4139 * stmmac_hw_init - Init the MAC device
4140 * @priv: driver private structure
4141 * Description: this function is to configure the MAC device according to
4142 * some platform parameters or the HW capability register. It prepares the
4143 * driver to use either ring or chain modes and to setup either enhanced or
4144 * normal descriptors.
4146 static int stmmac_hw_init(struct stmmac_priv
*priv
)
4148 struct mac_device_info
*mac
;
4150 /* Identify the MAC HW device */
4151 if (priv
->plat
->setup
) {
4152 mac
= priv
->plat
->setup(priv
);
4153 } else if (priv
->plat
->has_gmac
) {
4154 priv
->dev
->priv_flags
|= IFF_UNICAST_FLT
;
4155 mac
= dwmac1000_setup(priv
->ioaddr
,
4156 priv
->plat
->multicast_filter_bins
,
4157 priv
->plat
->unicast_filter_entries
,
4158 &priv
->synopsys_id
);
4159 } else if (priv
->plat
->has_gmac4
) {
4160 priv
->dev
->priv_flags
|= IFF_UNICAST_FLT
;
4161 mac
= dwmac4_setup(priv
->ioaddr
,
4162 priv
->plat
->multicast_filter_bins
,
4163 priv
->plat
->unicast_filter_entries
,
4164 &priv
->synopsys_id
);
4166 mac
= dwmac100_setup(priv
->ioaddr
, &priv
->synopsys_id
);
4173 /* dwmac-sun8i only work in chain mode */
4174 if (priv
->plat
->has_sun8i
)
4177 /* To use the chained or ring mode */
4178 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
4179 priv
->hw
->mode
= &dwmac4_ring_mode_ops
;
4182 priv
->hw
->mode
= &chain_mode_ops
;
4183 dev_info(priv
->device
, "Chain mode enabled\n");
4184 priv
->mode
= STMMAC_CHAIN_MODE
;
4186 priv
->hw
->mode
= &ring_mode_ops
;
4187 dev_info(priv
->device
, "Ring mode enabled\n");
4188 priv
->mode
= STMMAC_RING_MODE
;
4192 /* Get the HW capability (new GMAC newer than 3.50a) */
4193 priv
->hw_cap_support
= stmmac_get_hw_features(priv
);
4194 if (priv
->hw_cap_support
) {
4195 dev_info(priv
->device
, "DMA HW capability register supported\n");
4197 /* We can override some gmac/dma configuration fields: e.g.
4198 * enh_desc, tx_coe (e.g. that are passed through the
4199 * platform) with the values from the HW capability
4200 * register (if supported).
4202 priv
->plat
->enh_desc
= priv
->dma_cap
.enh_desc
;
4203 priv
->plat
->pmt
= priv
->dma_cap
.pmt_remote_wake_up
;
4204 priv
->hw
->pmt
= priv
->plat
->pmt
;
4206 /* TXCOE doesn't work in thresh DMA mode */
4207 if (priv
->plat
->force_thresh_dma_mode
)
4208 priv
->plat
->tx_coe
= 0;
4210 priv
->plat
->tx_coe
= priv
->dma_cap
.tx_coe
;
4212 /* In case of GMAC4 rx_coe is from HW cap register. */
4213 priv
->plat
->rx_coe
= priv
->dma_cap
.rx_coe
;
4215 if (priv
->dma_cap
.rx_coe_type2
)
4216 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE2
;
4217 else if (priv
->dma_cap
.rx_coe_type1
)
4218 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE1
;
4221 dev_info(priv
->device
, "No HW DMA feature register supported\n");
4224 /* To use alternate (extended), normal or GMAC4 descriptor structures */
4225 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
)
4226 priv
->hw
->desc
= &dwmac4_desc_ops
;
4228 stmmac_selec_desc_mode(priv
);
4230 if (priv
->plat
->rx_coe
) {
4231 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
4232 dev_info(priv
->device
, "RX Checksum Offload Engine supported\n");
4233 if (priv
->synopsys_id
< DWMAC_CORE_4_00
)
4234 dev_info(priv
->device
, "COE Type %d\n", priv
->hw
->rx_csum
);
4236 if (priv
->plat
->tx_coe
)
4237 dev_info(priv
->device
, "TX Checksum insertion supported\n");
4239 if (priv
->plat
->pmt
) {
4240 dev_info(priv
->device
, "Wake-Up On Lan supported\n");
4241 device_set_wakeup_capable(priv
->device
, 1);
4244 if (priv
->dma_cap
.tsoen
)
4245 dev_info(priv
->device
, "TSO supported\n");
4252 * @device: device pointer
4253 * @plat_dat: platform data pointer
4254 * @res: stmmac resource pointer
4255 * Description: this is the main probe function used to
4256 * call the alloc_etherdev, allocate the priv structure.
4258 * returns 0 on success, otherwise errno.
4260 int stmmac_dvr_probe(struct device
*device
,
4261 struct plat_stmmacenet_data
*plat_dat
,
4262 struct stmmac_resources
*res
)
4264 struct net_device
*ndev
= NULL
;
4265 struct stmmac_priv
*priv
;
4269 ndev
= alloc_etherdev_mqs(sizeof(struct stmmac_priv
),
4275 SET_NETDEV_DEV(ndev
, device
);
4277 priv
= netdev_priv(ndev
);
4278 priv
->device
= device
;
4281 stmmac_set_ethtool_ops(ndev
);
4282 priv
->pause
= pause
;
4283 priv
->plat
= plat_dat
;
4284 priv
->ioaddr
= res
->addr
;
4285 priv
->dev
->base_addr
= (unsigned long)res
->addr
;
4287 priv
->dev
->irq
= res
->irq
;
4288 priv
->wol_irq
= res
->wol_irq
;
4289 priv
->lpi_irq
= res
->lpi_irq
;
4292 memcpy(priv
->dev
->dev_addr
, res
->mac
, ETH_ALEN
);
4294 dev_set_drvdata(device
, priv
->dev
);
4296 /* Verify driver arguments */
4297 stmmac_verify_args();
4299 /* Allocate workqueue */
4300 priv
->wq
= create_singlethread_workqueue("stmmac_wq");
4302 dev_err(priv
->device
, "failed to create workqueue\n");
4306 INIT_WORK(&priv
->service_task
, stmmac_service_task
);
4308 /* Override with kernel parameters if supplied XXX CRS XXX
4309 * this needs to have multiple instances
4311 if ((phyaddr
>= 0) && (phyaddr
<= 31))
4312 priv
->plat
->phy_addr
= phyaddr
;
4314 if (priv
->plat
->stmmac_rst
) {
4315 ret
= reset_control_assert(priv
->plat
->stmmac_rst
);
4316 reset_control_deassert(priv
->plat
->stmmac_rst
);
4317 /* Some reset controllers have only reset callback instead of
4318 * assert + deassert callbacks pair.
4320 if (ret
== -ENOTSUPP
)
4321 reset_control_reset(priv
->plat
->stmmac_rst
);
4324 /* Init MAC and get the capabilities */
4325 ret
= stmmac_hw_init(priv
);
4329 /* Configure real RX and TX queues */
4330 netif_set_real_num_rx_queues(ndev
, priv
->plat
->rx_queues_to_use
);
4331 netif_set_real_num_tx_queues(ndev
, priv
->plat
->tx_queues_to_use
);
4333 ndev
->netdev_ops
= &stmmac_netdev_ops
;
4335 ndev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
4338 if ((priv
->plat
->tso_en
) && (priv
->dma_cap
.tsoen
)) {
4339 ndev
->hw_features
|= NETIF_F_TSO
| NETIF_F_TSO6
;
4341 dev_info(priv
->device
, "TSO feature enabled\n");
4343 ndev
->features
|= ndev
->hw_features
| NETIF_F_HIGHDMA
;
4344 ndev
->watchdog_timeo
= msecs_to_jiffies(watchdog
);
4345 #ifdef STMMAC_VLAN_TAG_USED
4346 /* Both mac100 and gmac support receive VLAN tag detection */
4347 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_RX
;
4349 priv
->msg_enable
= netif_msg_init(debug
, default_msg_level
);
4351 /* MTU range: 46 - hw-specific max */
4352 ndev
->min_mtu
= ETH_ZLEN
- ETH_HLEN
;
4353 if ((priv
->plat
->enh_desc
) || (priv
->synopsys_id
>= DWMAC_CORE_4_00
))
4354 ndev
->max_mtu
= JUMBO_LEN
;
4356 ndev
->max_mtu
= SKB_MAX_HEAD(NET_SKB_PAD
+ NET_IP_ALIGN
);
4357 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4358 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4360 if ((priv
->plat
->maxmtu
< ndev
->max_mtu
) &&
4361 (priv
->plat
->maxmtu
>= ndev
->min_mtu
))
4362 ndev
->max_mtu
= priv
->plat
->maxmtu
;
4363 else if (priv
->plat
->maxmtu
< ndev
->min_mtu
)
4364 dev_warn(priv
->device
,
4365 "%s: warning: maxmtu having invalid value (%d)\n",
4366 __func__
, priv
->plat
->maxmtu
);
4369 priv
->flow_ctrl
= FLOW_AUTO
; /* RX/TX pause on */
4371 /* Rx Watchdog is available in the COREs newer than the 3.40.
4372 * In some case, for example on bugged HW this feature
4373 * has to be disable and this can be done by passing the
4374 * riwt_off field from the platform.
4376 if ((priv
->synopsys_id
>= DWMAC_CORE_3_50
) && (!priv
->plat
->riwt_off
)) {
4378 dev_info(priv
->device
,
4379 "Enable RX Mitigation via HW Watchdog Timer\n");
4382 for (queue
= 0; queue
< priv
->plat
->rx_queues_to_use
; queue
++) {
4383 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
4385 netif_napi_add(ndev
, &rx_q
->napi
, stmmac_poll
,
4386 (8 * priv
->plat
->rx_queues_to_use
));
4389 spin_lock_init(&priv
->lock
);
4391 /* If a specific clk_csr value is passed from the platform
4392 * this means that the CSR Clock Range selection cannot be
4393 * changed at run-time and it is fixed. Viceversa the driver'll try to
4394 * set the MDC clock dynamically according to the csr actual
4397 if (!priv
->plat
->clk_csr
)
4398 stmmac_clk_csr_set(priv
);
4400 priv
->clk_csr
= priv
->plat
->clk_csr
;
4402 stmmac_check_pcs_mode(priv
);
4404 if (priv
->hw
->pcs
!= STMMAC_PCS_RGMII
&&
4405 priv
->hw
->pcs
!= STMMAC_PCS_TBI
&&
4406 priv
->hw
->pcs
!= STMMAC_PCS_RTBI
) {
4407 /* MDIO bus Registration */
4408 ret
= stmmac_mdio_register(ndev
);
4410 dev_err(priv
->device
,
4411 "%s: MDIO bus (id: %d) registration failed",
4412 __func__
, priv
->plat
->bus_id
);
4413 goto error_mdio_register
;
4417 ret
= register_netdev(ndev
);
4419 dev_err(priv
->device
, "%s: ERROR %i registering the device\n",
4421 goto error_netdev_register
;
4426 error_netdev_register
:
4427 if (priv
->hw
->pcs
!= STMMAC_PCS_RGMII
&&
4428 priv
->hw
->pcs
!= STMMAC_PCS_TBI
&&
4429 priv
->hw
->pcs
!= STMMAC_PCS_RTBI
)
4430 stmmac_mdio_unregister(ndev
);
4431 error_mdio_register
:
4432 for (queue
= 0; queue
< priv
->plat
->rx_queues_to_use
; queue
++) {
4433 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
4435 netif_napi_del(&rx_q
->napi
);
4438 destroy_workqueue(priv
->wq
);
4444 EXPORT_SYMBOL_GPL(stmmac_dvr_probe
);
4448 * @dev: device pointer
4449 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4450 * changes the link status, releases the DMA descriptor rings.
4452 int stmmac_dvr_remove(struct device
*dev
)
4454 struct net_device
*ndev
= dev_get_drvdata(dev
);
4455 struct stmmac_priv
*priv
= netdev_priv(ndev
);
4457 netdev_info(priv
->dev
, "%s: removing driver", __func__
);
4459 stmmac_stop_all_dma(priv
);
4461 priv
->hw
->mac
->set_mac(priv
->ioaddr
, false);
4462 netif_carrier_off(ndev
);
4463 unregister_netdev(ndev
);
4464 if (priv
->plat
->stmmac_rst
)
4465 reset_control_assert(priv
->plat
->stmmac_rst
);
4466 clk_disable_unprepare(priv
->plat
->pclk
);
4467 clk_disable_unprepare(priv
->plat
->stmmac_clk
);
4468 if (priv
->hw
->pcs
!= STMMAC_PCS_RGMII
&&
4469 priv
->hw
->pcs
!= STMMAC_PCS_TBI
&&
4470 priv
->hw
->pcs
!= STMMAC_PCS_RTBI
)
4471 stmmac_mdio_unregister(ndev
);
4472 destroy_workqueue(priv
->wq
);
4477 EXPORT_SYMBOL_GPL(stmmac_dvr_remove
);
4480 * stmmac_suspend - suspend callback
4481 * @dev: device pointer
4482 * Description: this is the function to suspend the device and it is called
4483 * by the platform driver to stop the network queue, release the resources,
4484 * program the PMT register (for WoL), clean and release driver resources.
4486 int stmmac_suspend(struct device
*dev
)
4488 struct net_device
*ndev
= dev_get_drvdata(dev
);
4489 struct stmmac_priv
*priv
= netdev_priv(ndev
);
4490 unsigned long flags
;
4492 if (!ndev
|| !netif_running(ndev
))
4496 phy_stop(ndev
->phydev
);
4498 spin_lock_irqsave(&priv
->lock
, flags
);
4500 netif_device_detach(ndev
);
4501 stmmac_stop_all_queues(priv
);
4503 stmmac_disable_all_queues(priv
);
4505 /* Stop TX/RX DMA */
4506 stmmac_stop_all_dma(priv
);
4508 /* Enable Power down mode by programming the PMT regs */
4509 if (device_may_wakeup(priv
->device
)) {
4510 priv
->hw
->mac
->pmt(priv
->hw
, priv
->wolopts
);
4513 priv
->hw
->mac
->set_mac(priv
->ioaddr
, false);
4514 pinctrl_pm_select_sleep_state(priv
->device
);
4515 /* Disable clock in case of PWM is off */
4516 clk_disable(priv
->plat
->pclk
);
4517 clk_disable(priv
->plat
->stmmac_clk
);
4519 spin_unlock_irqrestore(&priv
->lock
, flags
);
4521 priv
->oldlink
= false;
4522 priv
->speed
= SPEED_UNKNOWN
;
4523 priv
->oldduplex
= DUPLEX_UNKNOWN
;
4526 EXPORT_SYMBOL_GPL(stmmac_suspend
);
4529 * stmmac_reset_queues_param - reset queue parameters
4530 * @dev: device pointer
4532 static void stmmac_reset_queues_param(struct stmmac_priv
*priv
)
4534 u32 rx_cnt
= priv
->plat
->rx_queues_to_use
;
4535 u32 tx_cnt
= priv
->plat
->tx_queues_to_use
;
4538 for (queue
= 0; queue
< rx_cnt
; queue
++) {
4539 struct stmmac_rx_queue
*rx_q
= &priv
->rx_queue
[queue
];
4545 for (queue
= 0; queue
< tx_cnt
; queue
++) {
4546 struct stmmac_tx_queue
*tx_q
= &priv
->tx_queue
[queue
];
4555 * stmmac_resume - resume callback
4556 * @dev: device pointer
4557 * Description: when resume this function is invoked to setup the DMA and CORE
4558 * in a usable state.
4560 int stmmac_resume(struct device
*dev
)
4562 struct net_device
*ndev
= dev_get_drvdata(dev
);
4563 struct stmmac_priv
*priv
= netdev_priv(ndev
);
4564 unsigned long flags
;
4566 if (!netif_running(ndev
))
4569 /* Power Down bit, into the PM register, is cleared
4570 * automatically as soon as a magic packet or a Wake-up frame
4571 * is received. Anyway, it's better to manually clear
4572 * this bit because it can generate problems while resuming
4573 * from another devices (e.g. serial console).
4575 if (device_may_wakeup(priv
->device
)) {
4576 spin_lock_irqsave(&priv
->lock
, flags
);
4577 priv
->hw
->mac
->pmt(priv
->hw
, 0);
4578 spin_unlock_irqrestore(&priv
->lock
, flags
);
4581 pinctrl_pm_select_default_state(priv
->device
);
4582 /* enable the clk previously disabled */
4583 clk_enable(priv
->plat
->stmmac_clk
);
4584 clk_enable(priv
->plat
->pclk
);
4585 /* reset the phy so that it's ready */
4587 stmmac_mdio_reset(priv
->mii
);
4590 netif_device_attach(ndev
);
4592 spin_lock_irqsave(&priv
->lock
, flags
);
4594 stmmac_reset_queues_param(priv
);
4596 stmmac_clear_descriptors(priv
);
4598 stmmac_hw_setup(ndev
, false);
4599 stmmac_init_tx_coalesce(priv
);
4600 stmmac_set_rx_mode(ndev
);
4602 stmmac_enable_all_queues(priv
);
4604 stmmac_start_all_queues(priv
);
4606 spin_unlock_irqrestore(&priv
->lock
, flags
);
4609 phy_start(ndev
->phydev
);
4613 EXPORT_SYMBOL_GPL(stmmac_resume
);
4616 static int __init
stmmac_cmdline_opt(char *str
)
4622 while ((opt
= strsep(&str
, ",")) != NULL
) {
4623 if (!strncmp(opt
, "debug:", 6)) {
4624 if (kstrtoint(opt
+ 6, 0, &debug
))
4626 } else if (!strncmp(opt
, "phyaddr:", 8)) {
4627 if (kstrtoint(opt
+ 8, 0, &phyaddr
))
4629 } else if (!strncmp(opt
, "buf_sz:", 7)) {
4630 if (kstrtoint(opt
+ 7, 0, &buf_sz
))
4632 } else if (!strncmp(opt
, "tc:", 3)) {
4633 if (kstrtoint(opt
+ 3, 0, &tc
))
4635 } else if (!strncmp(opt
, "watchdog:", 9)) {
4636 if (kstrtoint(opt
+ 9, 0, &watchdog
))
4638 } else if (!strncmp(opt
, "flow_ctrl:", 10)) {
4639 if (kstrtoint(opt
+ 10, 0, &flow_ctrl
))
4641 } else if (!strncmp(opt
, "pause:", 6)) {
4642 if (kstrtoint(opt
+ 6, 0, &pause
))
4644 } else if (!strncmp(opt
, "eee_timer:", 10)) {
4645 if (kstrtoint(opt
+ 10, 0, &eee_timer
))
4647 } else if (!strncmp(opt
, "chain_mode:", 11)) {
4648 if (kstrtoint(opt
+ 11, 0, &chain_mode
))
4655 pr_err("%s: ERROR broken module parameter conversion", __func__
);
4659 __setup("stmmaceth=", stmmac_cmdline_opt
);
4662 static int __init
stmmac_init(void)
4664 #ifdef CONFIG_DEBUG_FS
4665 /* Create debugfs main directory if it doesn't exist yet */
4666 if (!stmmac_fs_dir
) {
4667 stmmac_fs_dir
= debugfs_create_dir(STMMAC_RESOURCE_NAME
, NULL
);
4669 if (!stmmac_fs_dir
|| IS_ERR(stmmac_fs_dir
)) {
4670 pr_err("ERROR %s, debugfs create directory failed\n",
4671 STMMAC_RESOURCE_NAME
);
4681 static void __exit
stmmac_exit(void)
4683 #ifdef CONFIG_DEBUG_FS
4684 debugfs_remove_recursive(stmmac_fs_dir
);
4688 module_init(stmmac_init
)
4689 module_exit(stmmac_exit
)
4691 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4692 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4693 MODULE_LICENSE("GPL");