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[thirdparty/kernel/stable.git] / drivers / net / ethernet / ti / am65-cpsw-nuss.c
1 // SPDX-License-Identifier: GPL-2.0
2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 */
7
8 #include <linux/clk.h>
9 #include <linux/etherdevice.h>
10 #include <linux/if_vlan.h>
11 #include <linux/interrupt.h>
12 #include <linux/irqdomain.h>
13 #include <linux/kernel.h>
14 #include <linux/kmemleak.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/net_tstamp.h>
18 #include <linux/of.h>
19 #include <linux/of_mdio.h>
20 #include <linux/of_net.h>
21 #include <linux/of_device.h>
22 #include <linux/of_platform.h>
23 #include <linux/phylink.h>
24 #include <linux/phy/phy.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/regmap.h>
28 #include <linux/rtnetlink.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/sys_soc.h>
31 #include <linux/dma/ti-cppi5.h>
32 #include <linux/dma/k3-udma-glue.h>
33 #include <net/switchdev.h>
34
35 #include "cpsw_ale.h"
36 #include "cpsw_sl.h"
37 #include "am65-cpsw-nuss.h"
38 #include "am65-cpsw-switchdev.h"
39 #include "k3-cppi-desc-pool.h"
40 #include "am65-cpts.h"
41
42 #define AM65_CPSW_SS_BASE 0x0
43 #define AM65_CPSW_SGMII_BASE 0x100
44 #define AM65_CPSW_XGMII_BASE 0x2100
45 #define AM65_CPSW_CPSW_NU_BASE 0x20000
46 #define AM65_CPSW_NU_PORTS_BASE 0x1000
47 #define AM65_CPSW_NU_FRAM_BASE 0x12000
48 #define AM65_CPSW_NU_STATS_BASE 0x1a000
49 #define AM65_CPSW_NU_ALE_BASE 0x1e000
50 #define AM65_CPSW_NU_CPTS_BASE 0x1d000
51
52 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000
53 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200
54 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200
55
56 #define AM65_CPSW_MAX_PORTS 8
57
58 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN
59 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
60
61 #define AM65_CPSW_REG_CTL 0x004
62 #define AM65_CPSW_REG_STAT_PORT_EN 0x014
63 #define AM65_CPSW_REG_PTYPE 0x018
64
65 #define AM65_CPSW_P0_REG_CTL 0x004
66 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008
67
68 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c
69 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020
70 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024
71
72 #define AM65_CPSW_PORTN_REG_SA_L 0x308
73 #define AM65_CPSW_PORTN_REG_SA_H 0x30c
74 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310
75 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314
76 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318
77 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C
78
79 #define AM65_CPSW_SGMII_CONTROL_REG 0x010
80 #define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018
81 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0)
82
83 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1)
84 #define AM65_CPSW_CTL_P0_ENABLE BIT(2)
85 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13)
86 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14)
87
88 /* AM65_CPSW_P0_REG_CTL */
89 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0)
90 #define AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN BIT(16)
91
92 /* AM65_CPSW_PORT_REG_PRI_CTL */
93 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8)
94
95 /* AM65_CPSW_PN_TS_CTL register fields */
96 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4)
97 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5)
98 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6)
99 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7)
100 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10)
101 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11)
102 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16
103
104 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */
105 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16
106
107 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */
108 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16)
109 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17)
110 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18)
111 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19)
112 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20)
113 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21)
114 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22)
115 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23)
116
117 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
118 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))
119
120 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e)
121
122 #define AM65_CPSW_TS_TX_ANX_ALL_EN \
123 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \
124 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \
125 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN)
126
127 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30
128 /* Number of TX/RX descriptors */
129 #define AM65_CPSW_MAX_TX_DESC 500
130 #define AM65_CPSW_MAX_RX_DESC 500
131
132 #define AM65_CPSW_NAV_PS_DATA_SIZE 16
133 #define AM65_CPSW_NAV_SW_DATA_SIZE 16
134
135 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \
136 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \
137 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
138
139 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave,
140 const u8 *dev_addr)
141 {
142 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) |
143 (dev_addr[2] << 16) | (dev_addr[3] << 24);
144 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8);
145
146 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H);
147 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L);
148 }
149
150 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port)
151 {
152 cpsw_sl_reset(port->slave.mac_sl, 100);
153 /* Max length register has to be restored after MAC SL reset */
154 writel(AM65_CPSW_MAX_PACKET_SIZE,
155 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN);
156 }
157
158 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common)
159 {
160 common->nuss_ver = readl(common->ss_base);
161 common->cpsw_ver = readl(common->cpsw_base);
162 dev_info(common->dev,
163 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n",
164 common->nuss_ver,
165 common->cpsw_ver,
166 common->port_num + 1,
167 common->pdata.quirks);
168 }
169
170 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev,
171 __be16 proto, u16 vid)
172 {
173 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
174 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
175 u32 port_mask, unreg_mcast = 0;
176 int ret;
177
178 if (!common->is_emac_mode)
179 return 0;
180
181 if (!netif_running(ndev) || !vid)
182 return 0;
183
184 ret = pm_runtime_resume_and_get(common->dev);
185 if (ret < 0)
186 return ret;
187
188 port_mask = BIT(port->port_id) | ALE_PORT_HOST;
189 if (!vid)
190 unreg_mcast = port_mask;
191 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid);
192 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask,
193 unreg_mcast, port_mask, 0);
194
195 pm_runtime_put(common->dev);
196 return ret;
197 }
198
199 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev,
200 __be16 proto, u16 vid)
201 {
202 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
203 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
204 int ret;
205
206 if (!common->is_emac_mode)
207 return 0;
208
209 if (!netif_running(ndev) || !vid)
210 return 0;
211
212 ret = pm_runtime_resume_and_get(common->dev);
213 if (ret < 0)
214 return ret;
215
216 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid);
217 ret = cpsw_ale_del_vlan(common->ale, vid,
218 BIT(port->port_id) | ALE_PORT_HOST);
219
220 pm_runtime_put(common->dev);
221 return ret;
222 }
223
224 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port,
225 bool promisc)
226 {
227 struct am65_cpsw_common *common = port->common;
228
229 if (promisc && !common->is_emac_mode) {
230 dev_dbg(common->dev, "promisc mode requested in switch mode");
231 return;
232 }
233
234 if (promisc) {
235 /* Enable promiscuous mode */
236 cpsw_ale_control_set(common->ale, port->port_id,
237 ALE_PORT_MACONLY_CAF, 1);
238 dev_dbg(common->dev, "promisc enabled\n");
239 } else {
240 /* Disable promiscuous mode */
241 cpsw_ale_control_set(common->ale, port->port_id,
242 ALE_PORT_MACONLY_CAF, 0);
243 dev_dbg(common->dev, "promisc disabled\n");
244 }
245 }
246
247 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev)
248 {
249 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
250 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
251 u32 port_mask;
252 bool promisc;
253
254 promisc = !!(ndev->flags & IFF_PROMISC);
255 am65_cpsw_slave_set_promisc(port, promisc);
256
257 if (promisc)
258 return;
259
260 /* Restore allmulti on vlans if necessary */
261 cpsw_ale_set_allmulti(common->ale,
262 ndev->flags & IFF_ALLMULTI, port->port_id);
263
264 port_mask = ALE_PORT_HOST;
265 /* Clear all mcast from ALE */
266 cpsw_ale_flush_multicast(common->ale, port_mask, -1);
267
268 if (!netdev_mc_empty(ndev)) {
269 struct netdev_hw_addr *ha;
270
271 /* program multicast address list into ALE register */
272 netdev_for_each_mc_addr(ha, ndev) {
273 cpsw_ale_add_mcast(common->ale, ha->addr,
274 port_mask, 0, 0, 0);
275 }
276 }
277 }
278
279 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev,
280 unsigned int txqueue)
281 {
282 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
283 struct am65_cpsw_tx_chn *tx_chn;
284 struct netdev_queue *netif_txq;
285 unsigned long trans_start;
286
287 netif_txq = netdev_get_tx_queue(ndev, txqueue);
288 tx_chn = &common->tx_chns[txqueue];
289 trans_start = READ_ONCE(netif_txq->trans_start);
290
291 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n",
292 txqueue,
293 netif_tx_queue_stopped(netif_txq),
294 jiffies_to_msecs(jiffies - trans_start),
295 dql_avail(&netif_txq->dql),
296 k3_cppi_desc_pool_avail(tx_chn->desc_pool));
297
298 if (netif_tx_queue_stopped(netif_txq)) {
299 /* try recover if stopped by us */
300 txq_trans_update(netif_txq);
301 netif_tx_wake_queue(netif_txq);
302 }
303 }
304
305 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common,
306 struct sk_buff *skb)
307 {
308 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;
309 struct cppi5_host_desc_t *desc_rx;
310 struct device *dev = common->dev;
311 u32 pkt_len = skb_tailroom(skb);
312 dma_addr_t desc_dma;
313 dma_addr_t buf_dma;
314 void *swdata;
315
316 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool);
317 if (!desc_rx) {
318 dev_err(dev, "Failed to allocate RXFDQ descriptor\n");
319 return -ENOMEM;
320 }
321 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx);
322
323 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len,
324 DMA_FROM_DEVICE);
325 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) {
326 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
327 dev_err(dev, "Failed to map rx skb buffer\n");
328 return -EINVAL;
329 }
330
331 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT,
332 AM65_CPSW_NAV_PS_DATA_SIZE);
333 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma);
334 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb));
335 swdata = cppi5_hdesc_get_swdata(desc_rx);
336 *((void **)swdata) = skb;
337
338 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma);
339 }
340
341 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common)
342 {
343 struct am65_cpsw_host *host_p = am65_common_get_host(common);
344 u32 val, pri_map;
345
346 /* P0 set Receive Priority Type */
347 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL);
348
349 if (common->pf_p0_rx_ptype_rrobin) {
350 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN;
351 /* Enet Ports fifos works in fixed priority mode only, so
352 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0
353 */
354 pri_map = 0x0;
355 } else {
356 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN;
357 /* restore P0_Rx_Pri_Map */
358 pri_map = 0x76543210;
359 }
360
361 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP);
362 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL);
363 }
364
365 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common);
366 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common);
367 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port);
368 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port);
369
370 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common)
371 {
372 struct am65_cpsw_host *host_p = am65_common_get_host(common);
373 int port_idx, i, ret;
374 struct sk_buff *skb;
375 u32 val, port_mask;
376
377 if (common->usage_count)
378 return 0;
379
380 /* Control register */
381 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE |
382 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD,
383 common->cpsw_base + AM65_CPSW_REG_CTL);
384 /* Max length register */
385 writel(AM65_CPSW_MAX_PACKET_SIZE,
386 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN);
387 /* set base flow_id */
388 writel(common->rx_flow_id_base,
389 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET);
390 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN | AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN,
391 host_p->port_base + AM65_CPSW_P0_REG_CTL);
392
393 am65_cpsw_nuss_set_p0_ptype(common);
394
395 /* enable statistic */
396 val = BIT(HOST_PORT_NUM);
397 for (port_idx = 0; port_idx < common->port_num; port_idx++) {
398 struct am65_cpsw_port *port = &common->ports[port_idx];
399
400 if (!port->disabled)
401 val |= BIT(port->port_id);
402 }
403 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN);
404
405 /* disable priority elevation */
406 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE);
407
408 cpsw_ale_start(common->ale);
409
410 /* limit to one RX flow only */
411 cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
412 ALE_DEFAULT_THREAD_ID, 0);
413 cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
414 ALE_DEFAULT_THREAD_ENABLE, 1);
415 /* switch to vlan unaware mode */
416 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1);
417 cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
418 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
419
420 /* default vlan cfg: create mask based on enabled ports */
421 port_mask = GENMASK(common->port_num, 0) &
422 ~common->disabled_ports_mask;
423
424 cpsw_ale_add_vlan(common->ale, 0, port_mask,
425 port_mask, port_mask,
426 port_mask & ~ALE_PORT_HOST);
427
428 if (common->is_emac_mode)
429 am65_cpsw_init_host_port_emac(common);
430 else
431 am65_cpsw_init_host_port_switch(common);
432
433 am65_cpsw_qos_tx_p0_rate_init(common);
434
435 for (i = 0; i < common->rx_chns.descs_num; i++) {
436 skb = __netdev_alloc_skb_ip_align(NULL,
437 AM65_CPSW_MAX_PACKET_SIZE,
438 GFP_KERNEL);
439 if (!skb) {
440 dev_err(common->dev, "cannot allocate skb\n");
441 return -ENOMEM;
442 }
443
444 ret = am65_cpsw_nuss_rx_push(common, skb);
445 if (ret < 0) {
446 dev_err(common->dev,
447 "cannot submit skb to channel rx, error %d\n",
448 ret);
449 kfree_skb(skb);
450 return ret;
451 }
452 kmemleak_not_leak(skb);
453 }
454 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn);
455
456 for (i = 0; i < common->tx_ch_num; i++) {
457 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn);
458 if (ret)
459 return ret;
460 napi_enable(&common->tx_chns[i].napi_tx);
461 }
462
463 napi_enable(&common->napi_rx);
464 if (common->rx_irq_disabled) {
465 common->rx_irq_disabled = false;
466 enable_irq(common->rx_chns.irq);
467 }
468
469 dev_dbg(common->dev, "cpsw_nuss started\n");
470 return 0;
471 }
472
473 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma);
474 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma);
475
476 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common)
477 {
478 int i;
479
480 if (common->usage_count != 1)
481 return 0;
482
483 cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
484 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
485
486 /* shutdown tx channels */
487 atomic_set(&common->tdown_cnt, common->tx_ch_num);
488 /* ensure new tdown_cnt value is visible */
489 smp_mb__after_atomic();
490 reinit_completion(&common->tdown_complete);
491
492 for (i = 0; i < common->tx_ch_num; i++)
493 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false);
494
495 i = wait_for_completion_timeout(&common->tdown_complete,
496 msecs_to_jiffies(1000));
497 if (!i)
498 dev_err(common->dev, "tx timeout\n");
499 for (i = 0; i < common->tx_ch_num; i++)
500 napi_disable(&common->tx_chns[i].napi_tx);
501
502 for (i = 0; i < common->tx_ch_num; i++) {
503 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn,
504 &common->tx_chns[i],
505 am65_cpsw_nuss_tx_cleanup);
506 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn);
507 }
508
509 reinit_completion(&common->tdown_complete);
510 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true);
511
512 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) {
513 i = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000));
514 if (!i)
515 dev_err(common->dev, "rx teardown timeout\n");
516 }
517
518 napi_disable(&common->napi_rx);
519
520 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++)
521 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i,
522 &common->rx_chns,
523 am65_cpsw_nuss_rx_cleanup, !!i);
524
525 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn);
526
527 cpsw_ale_stop(common->ale);
528
529 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL);
530 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN);
531
532 dev_dbg(common->dev, "cpsw_nuss stopped\n");
533 return 0;
534 }
535
536 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev)
537 {
538 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
539 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
540 int ret;
541
542 phylink_stop(port->slave.phylink);
543
544 netif_tx_stop_all_queues(ndev);
545
546 phylink_disconnect_phy(port->slave.phylink);
547
548 ret = am65_cpsw_nuss_common_stop(common);
549 if (ret)
550 return ret;
551
552 common->usage_count--;
553 pm_runtime_put(common->dev);
554 return 0;
555 }
556
557 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg)
558 {
559 struct am65_cpsw_port *port = arg;
560
561 if (!vdev)
562 return 0;
563
564 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid);
565 }
566
567 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev)
568 {
569 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
570 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
571 int ret, i;
572 u32 reg;
573
574 ret = pm_runtime_resume_and_get(common->dev);
575 if (ret < 0)
576 return ret;
577
578 /* Idle MAC port */
579 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE);
580 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100);
581 cpsw_sl_ctl_reset(port->slave.mac_sl);
582
583 /* soft reset MAC */
584 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1);
585 mdelay(1);
586 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET);
587 if (reg) {
588 dev_err(common->dev, "soft RESET didn't complete\n");
589 ret = -ETIMEDOUT;
590 goto runtime_put;
591 }
592
593 /* Notify the stack of the actual queue counts. */
594 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num);
595 if (ret) {
596 dev_err(common->dev, "cannot set real number of tx queues\n");
597 goto runtime_put;
598 }
599
600 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES);
601 if (ret) {
602 dev_err(common->dev, "cannot set real number of rx queues\n");
603 goto runtime_put;
604 }
605
606 for (i = 0; i < common->tx_ch_num; i++) {
607 struct netdev_queue *txq = netdev_get_tx_queue(ndev, i);
608
609 netdev_tx_reset_queue(txq);
610 txq->tx_maxrate = common->tx_chns[i].rate_mbps;
611 }
612
613 ret = am65_cpsw_nuss_common_open(common);
614 if (ret)
615 goto runtime_put;
616
617 common->usage_count++;
618
619 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr);
620
621 if (common->is_emac_mode)
622 am65_cpsw_init_port_emac_ale(port);
623 else
624 am65_cpsw_init_port_switch_ale(port);
625
626 /* mac_sl should be configured via phy-link interface */
627 am65_cpsw_sl_ctl_reset(port);
628
629 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0);
630 if (ret)
631 goto error_cleanup;
632
633 /* restore vlan configurations */
634 vlan_for_each(ndev, cpsw_restore_vlans, port);
635
636 phylink_start(port->slave.phylink);
637
638 return 0;
639
640 error_cleanup:
641 am65_cpsw_nuss_ndo_slave_stop(ndev);
642 return ret;
643
644 runtime_put:
645 pm_runtime_put(common->dev);
646 return ret;
647 }
648
649 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma)
650 {
651 struct am65_cpsw_rx_chn *rx_chn = data;
652 struct cppi5_host_desc_t *desc_rx;
653 struct sk_buff *skb;
654 dma_addr_t buf_dma;
655 u32 buf_dma_len;
656 void **swdata;
657
658 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma);
659 swdata = cppi5_hdesc_get_swdata(desc_rx);
660 skb = *swdata;
661 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
662 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma);
663
664 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE);
665 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
666
667 dev_kfree_skb_any(skb);
668 }
669
670 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata)
671 {
672 struct skb_shared_hwtstamps *ssh;
673 u64 ns;
674
675 ns = ((u64)psdata[1] << 32) | psdata[0];
676
677 ssh = skb_hwtstamps(skb);
678 memset(ssh, 0, sizeof(*ssh));
679 ssh->hwtstamp = ns_to_ktime(ns);
680 }
681
682 /* RX psdata[2] word format - checksum information */
683 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0)
684 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16)
685 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17)
686 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18)
687 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19)
688 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20)
689
690 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info)
691 {
692 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum
693 * csum information provides in psdata[2] word:
694 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error
695 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID
696 * bits - indicates IPv4/IPv6 packet
697 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet
698 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets
699 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR
700 */
701 skb_checksum_none_assert(skb);
702
703 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM)))
704 return;
705
706 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID |
707 AM65_CPSW_RX_PSD_IPV4_VALID)) &&
708 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) {
709 /* csum for fragmented packets is unsupported */
710 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT))
711 skb->ip_summed = CHECKSUM_UNNECESSARY;
712 }
713 }
714
715 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common,
716 u32 flow_idx)
717 {
718 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;
719 u32 buf_dma_len, pkt_len, port_id = 0, csum_info;
720 struct am65_cpsw_ndev_priv *ndev_priv;
721 struct am65_cpsw_ndev_stats *stats;
722 struct cppi5_host_desc_t *desc_rx;
723 struct device *dev = common->dev;
724 struct sk_buff *skb, *new_skb;
725 dma_addr_t desc_dma, buf_dma;
726 struct am65_cpsw_port *port;
727 struct net_device *ndev;
728 void **swdata;
729 u32 *psdata;
730 int ret = 0;
731
732 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma);
733 if (ret) {
734 if (ret != -ENODATA)
735 dev_err(dev, "RX: pop chn fail %d\n", ret);
736 return ret;
737 }
738
739 if (cppi5_desc_is_tdcm(desc_dma)) {
740 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx);
741 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ)
742 complete(&common->tdown_complete);
743 return 0;
744 }
745
746 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma);
747 dev_dbg(dev, "%s flow_idx: %u desc %pad\n",
748 __func__, flow_idx, &desc_dma);
749
750 swdata = cppi5_hdesc_get_swdata(desc_rx);
751 skb = *swdata;
752 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
753 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma);
754 pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
755 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
756 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id);
757 port = am65_common_get_port(common, port_id);
758 ndev = port->ndev;
759 skb->dev = ndev;
760
761 psdata = cppi5_hdesc_get_psdata(desc_rx);
762 /* add RX timestamp */
763 if (port->rx_ts_enabled)
764 am65_cpsw_nuss_rx_ts(skb, psdata);
765 csum_info = psdata[2];
766 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info);
767
768 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE);
769
770 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
771
772 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE);
773 if (new_skb) {
774 ndev_priv = netdev_priv(ndev);
775 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark);
776 skb_put(skb, pkt_len);
777 skb->protocol = eth_type_trans(skb, ndev);
778 am65_cpsw_nuss_rx_csum(skb, csum_info);
779 napi_gro_receive(&common->napi_rx, skb);
780
781 stats = this_cpu_ptr(ndev_priv->stats);
782
783 u64_stats_update_begin(&stats->syncp);
784 stats->rx_packets++;
785 stats->rx_bytes += pkt_len;
786 u64_stats_update_end(&stats->syncp);
787 kmemleak_not_leak(new_skb);
788 } else {
789 ndev->stats.rx_dropped++;
790 new_skb = skb;
791 }
792
793 if (netif_dormant(ndev)) {
794 dev_kfree_skb_any(new_skb);
795 ndev->stats.rx_dropped++;
796 return 0;
797 }
798
799 ret = am65_cpsw_nuss_rx_push(common, new_skb);
800 if (WARN_ON(ret < 0)) {
801 dev_kfree_skb_any(new_skb);
802 ndev->stats.rx_errors++;
803 ndev->stats.rx_dropped++;
804 }
805
806 return ret;
807 }
808
809 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget)
810 {
811 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx);
812 int flow = AM65_CPSW_MAX_RX_FLOWS;
813 int cur_budget, ret;
814 int num_rx = 0;
815
816 /* process every flow */
817 while (flow--) {
818 cur_budget = budget - num_rx;
819
820 while (cur_budget--) {
821 ret = am65_cpsw_nuss_rx_packets(common, flow);
822 if (ret)
823 break;
824 num_rx++;
825 }
826
827 if (num_rx >= budget)
828 break;
829 }
830
831 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget);
832
833 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) {
834 if (common->rx_irq_disabled) {
835 common->rx_irq_disabled = false;
836 enable_irq(common->rx_chns.irq);
837 }
838 }
839
840 return num_rx;
841 }
842
843 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn,
844 struct cppi5_host_desc_t *desc)
845 {
846 struct cppi5_host_desc_t *first_desc, *next_desc;
847 dma_addr_t buf_dma, next_desc_dma;
848 u32 buf_dma_len;
849
850 first_desc = desc;
851 next_desc = first_desc;
852
853 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len);
854 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma);
855
856 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE);
857
858 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc);
859 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma);
860 while (next_desc_dma) {
861 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
862 next_desc_dma);
863 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len);
864 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma);
865
866 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len,
867 DMA_TO_DEVICE);
868
869 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc);
870 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma);
871
872 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc);
873 }
874
875 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc);
876 }
877
878 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma)
879 {
880 struct am65_cpsw_tx_chn *tx_chn = data;
881 struct cppi5_host_desc_t *desc_tx;
882 struct sk_buff *skb;
883 void **swdata;
884
885 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma);
886 swdata = cppi5_hdesc_get_swdata(desc_tx);
887 skb = *(swdata);
888 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx);
889
890 dev_kfree_skb_any(skb);
891 }
892
893 static struct sk_buff *
894 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn,
895 dma_addr_t desc_dma)
896 {
897 struct am65_cpsw_ndev_priv *ndev_priv;
898 struct am65_cpsw_ndev_stats *stats;
899 struct cppi5_host_desc_t *desc_tx;
900 struct net_device *ndev;
901 struct sk_buff *skb;
902 void **swdata;
903
904 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
905 desc_dma);
906 swdata = cppi5_hdesc_get_swdata(desc_tx);
907 skb = *(swdata);
908 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx);
909
910 ndev = skb->dev;
911
912 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb);
913
914 ndev_priv = netdev_priv(ndev);
915 stats = this_cpu_ptr(ndev_priv->stats);
916 u64_stats_update_begin(&stats->syncp);
917 stats->tx_packets++;
918 stats->tx_bytes += skb->len;
919 u64_stats_update_end(&stats->syncp);
920
921 return skb;
922 }
923
924 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev,
925 struct netdev_queue *netif_txq)
926 {
927 if (netif_tx_queue_stopped(netif_txq)) {
928 /* Check whether the queue is stopped due to stalled
929 * tx dma, if the queue is stopped then wake the queue
930 * as we have free desc for tx
931 */
932 __netif_tx_lock(netif_txq, smp_processor_id());
933 if (netif_running(ndev) &&
934 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS))
935 netif_tx_wake_queue(netif_txq);
936
937 __netif_tx_unlock(netif_txq);
938 }
939 }
940
941 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common,
942 int chn, unsigned int budget)
943 {
944 struct device *dev = common->dev;
945 struct am65_cpsw_tx_chn *tx_chn;
946 struct netdev_queue *netif_txq;
947 unsigned int total_bytes = 0;
948 struct net_device *ndev;
949 struct sk_buff *skb;
950 dma_addr_t desc_dma;
951 int res, num_tx = 0;
952
953 tx_chn = &common->tx_chns[chn];
954
955 while (true) {
956 spin_lock(&tx_chn->lock);
957 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma);
958 spin_unlock(&tx_chn->lock);
959 if (res == -ENODATA)
960 break;
961
962 if (cppi5_desc_is_tdcm(desc_dma)) {
963 if (atomic_dec_and_test(&common->tdown_cnt))
964 complete(&common->tdown_complete);
965 break;
966 }
967
968 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma);
969 total_bytes = skb->len;
970 ndev = skb->dev;
971 napi_consume_skb(skb, budget);
972 num_tx++;
973
974 netif_txq = netdev_get_tx_queue(ndev, chn);
975
976 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes);
977
978 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq);
979 }
980
981 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx);
982
983 return num_tx;
984 }
985
986 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common,
987 int chn, unsigned int budget)
988 {
989 struct device *dev = common->dev;
990 struct am65_cpsw_tx_chn *tx_chn;
991 struct netdev_queue *netif_txq;
992 unsigned int total_bytes = 0;
993 struct net_device *ndev;
994 struct sk_buff *skb;
995 dma_addr_t desc_dma;
996 int res, num_tx = 0;
997
998 tx_chn = &common->tx_chns[chn];
999
1000 while (true) {
1001 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma);
1002 if (res == -ENODATA)
1003 break;
1004
1005 if (cppi5_desc_is_tdcm(desc_dma)) {
1006 if (atomic_dec_and_test(&common->tdown_cnt))
1007 complete(&common->tdown_complete);
1008 break;
1009 }
1010
1011 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma);
1012
1013 ndev = skb->dev;
1014 total_bytes += skb->len;
1015 napi_consume_skb(skb, budget);
1016 num_tx++;
1017 }
1018
1019 if (!num_tx)
1020 return 0;
1021
1022 netif_txq = netdev_get_tx_queue(ndev, chn);
1023
1024 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes);
1025
1026 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq);
1027
1028 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx);
1029
1030 return num_tx;
1031 }
1032
1033 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget)
1034 {
1035 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx);
1036 int num_tx;
1037
1038 if (AM65_CPSW_IS_CPSW2G(tx_chn->common))
1039 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget);
1040 else
1041 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget);
1042
1043 if (num_tx >= budget)
1044 return budget;
1045
1046 if (napi_complete_done(napi_tx, num_tx))
1047 enable_irq(tx_chn->irq);
1048
1049 return 0;
1050 }
1051
1052 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id)
1053 {
1054 struct am65_cpsw_common *common = dev_id;
1055
1056 common->rx_irq_disabled = true;
1057 disable_irq_nosync(irq);
1058 napi_schedule(&common->napi_rx);
1059
1060 return IRQ_HANDLED;
1061 }
1062
1063 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id)
1064 {
1065 struct am65_cpsw_tx_chn *tx_chn = dev_id;
1066
1067 disable_irq_nosync(irq);
1068 napi_schedule(&tx_chn->napi_tx);
1069
1070 return IRQ_HANDLED;
1071 }
1072
1073 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb,
1074 struct net_device *ndev)
1075 {
1076 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
1077 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc;
1078 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1079 struct device *dev = common->dev;
1080 struct am65_cpsw_tx_chn *tx_chn;
1081 struct netdev_queue *netif_txq;
1082 dma_addr_t desc_dma, buf_dma;
1083 int ret, q_idx, i;
1084 void **swdata;
1085 u32 *psdata;
1086 u32 pkt_len;
1087
1088 /* padding enabled in hw */
1089 pkt_len = skb_headlen(skb);
1090
1091 /* SKB TX timestamp */
1092 if (port->tx_ts_enabled)
1093 am65_cpts_prep_tx_timestamp(common->cpts, skb);
1094
1095 q_idx = skb_get_queue_mapping(skb);
1096 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx);
1097
1098 tx_chn = &common->tx_chns[q_idx];
1099 netif_txq = netdev_get_tx_queue(ndev, q_idx);
1100
1101 /* Map the linear buffer */
1102 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len,
1103 DMA_TO_DEVICE);
1104 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) {
1105 dev_err(dev, "Failed to map tx skb buffer\n");
1106 ndev->stats.tx_errors++;
1107 goto err_free_skb;
1108 }
1109
1110 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool);
1111 if (!first_desc) {
1112 dev_dbg(dev, "Failed to allocate descriptor\n");
1113 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len,
1114 DMA_TO_DEVICE);
1115 goto busy_stop_q;
1116 }
1117
1118 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT,
1119 AM65_CPSW_NAV_PS_DATA_SIZE);
1120 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF);
1121 cppi5_hdesc_set_pkttype(first_desc, 0x7);
1122 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id);
1123
1124 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma);
1125 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len);
1126 swdata = cppi5_hdesc_get_swdata(first_desc);
1127 *(swdata) = skb;
1128 psdata = cppi5_hdesc_get_psdata(first_desc);
1129
1130 /* HW csum offload if enabled */
1131 psdata[2] = 0;
1132 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1133 unsigned int cs_start, cs_offset;
1134
1135 cs_start = skb_transport_offset(skb);
1136 cs_offset = cs_start + skb->csum_offset;
1137 /* HW numerates bytes starting from 1 */
1138 psdata[2] = ((cs_offset + 1) << 24) |
1139 ((cs_start + 1) << 16) | (skb->len - cs_start);
1140 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]);
1141 }
1142
1143 if (!skb_is_nonlinear(skb))
1144 goto done_tx;
1145
1146 dev_dbg(dev, "fragmented SKB\n");
1147
1148 /* Handle the case where skb is fragmented in pages */
1149 cur_desc = first_desc;
1150 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1151 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1152 u32 frag_size = skb_frag_size(frag);
1153
1154 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool);
1155 if (!next_desc) {
1156 dev_err(dev, "Failed to allocate descriptor\n");
1157 goto busy_free_descs;
1158 }
1159
1160 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size,
1161 DMA_TO_DEVICE);
1162 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) {
1163 dev_err(dev, "Failed to map tx skb page\n");
1164 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc);
1165 ndev->stats.tx_errors++;
1166 goto err_free_descs;
1167 }
1168
1169 cppi5_hdesc_reset_hbdesc(next_desc);
1170 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma);
1171 cppi5_hdesc_attach_buf(next_desc,
1172 buf_dma, frag_size, buf_dma, frag_size);
1173
1174 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool,
1175 next_desc);
1176 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma);
1177 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma);
1178
1179 pkt_len += frag_size;
1180 cur_desc = next_desc;
1181 }
1182 WARN_ON(pkt_len != skb->len);
1183
1184 done_tx:
1185 skb_tx_timestamp(skb);
1186
1187 /* report bql before sending packet */
1188 netdev_tx_sent_queue(netif_txq, pkt_len);
1189
1190 cppi5_hdesc_set_pktlen(first_desc, pkt_len);
1191 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc);
1192 if (AM65_CPSW_IS_CPSW2G(common)) {
1193 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma);
1194 } else {
1195 spin_lock_bh(&tx_chn->lock);
1196 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma);
1197 spin_unlock_bh(&tx_chn->lock);
1198 }
1199 if (ret) {
1200 dev_err(dev, "can't push desc %d\n", ret);
1201 /* inform bql */
1202 netdev_tx_completed_queue(netif_txq, 1, pkt_len);
1203 ndev->stats.tx_errors++;
1204 goto err_free_descs;
1205 }
1206
1207 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) {
1208 netif_tx_stop_queue(netif_txq);
1209 /* Barrier, so that stop_queue visible to other cpus */
1210 smp_mb__after_atomic();
1211 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx);
1212
1213 /* re-check for smp */
1214 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >=
1215 MAX_SKB_FRAGS) {
1216 netif_tx_wake_queue(netif_txq);
1217 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx);
1218 }
1219 }
1220
1221 return NETDEV_TX_OK;
1222
1223 err_free_descs:
1224 am65_cpsw_nuss_xmit_free(tx_chn, first_desc);
1225 err_free_skb:
1226 ndev->stats.tx_dropped++;
1227 dev_kfree_skb_any(skb);
1228 return NETDEV_TX_OK;
1229
1230 busy_free_descs:
1231 am65_cpsw_nuss_xmit_free(tx_chn, first_desc);
1232 busy_stop_q:
1233 netif_tx_stop_queue(netif_txq);
1234 return NETDEV_TX_BUSY;
1235 }
1236
1237 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev,
1238 void *addr)
1239 {
1240 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
1241 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1242 struct sockaddr *sockaddr = (struct sockaddr *)addr;
1243 int ret;
1244
1245 ret = eth_prepare_mac_addr_change(ndev, addr);
1246 if (ret < 0)
1247 return ret;
1248
1249 ret = pm_runtime_resume_and_get(common->dev);
1250 if (ret < 0)
1251 return ret;
1252
1253 cpsw_ale_del_ucast(common->ale, ndev->dev_addr,
1254 HOST_PORT_NUM, 0, 0);
1255 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data,
1256 HOST_PORT_NUM, ALE_SECURE, 0);
1257
1258 am65_cpsw_port_set_sl_mac(port, addr);
1259 eth_commit_mac_addr_change(ndev, sockaddr);
1260
1261 pm_runtime_put(common->dev);
1262
1263 return 0;
1264 }
1265
1266 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev,
1267 struct ifreq *ifr)
1268 {
1269 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
1270 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1271 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype;
1272 struct hwtstamp_config cfg;
1273
1274 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
1275 return -EOPNOTSUPP;
1276
1277 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1278 return -EFAULT;
1279
1280 /* TX HW timestamp */
1281 switch (cfg.tx_type) {
1282 case HWTSTAMP_TX_OFF:
1283 case HWTSTAMP_TX_ON:
1284 break;
1285 default:
1286 return -ERANGE;
1287 }
1288
1289 switch (cfg.rx_filter) {
1290 case HWTSTAMP_FILTER_NONE:
1291 port->rx_ts_enabled = false;
1292 break;
1293 case HWTSTAMP_FILTER_ALL:
1294 case HWTSTAMP_FILTER_SOME:
1295 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1296 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1297 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1298 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1299 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1300 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1301 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1302 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1303 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1304 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1305 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1306 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1307 case HWTSTAMP_FILTER_NTP_ALL:
1308 port->rx_ts_enabled = true;
1309 cfg.rx_filter = HWTSTAMP_FILTER_ALL;
1310 break;
1311 default:
1312 return -ERANGE;
1313 }
1314
1315 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON);
1316
1317 /* cfg TX timestamp */
1318 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET <<
1319 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588;
1320
1321 ts_vlan_ltype = ETH_P_8021Q;
1322
1323 ts_ctrl_ltype2 = ETH_P_1588 |
1324 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 |
1325 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 |
1326 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 |
1327 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 |
1328 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 |
1329 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 |
1330 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 |
1331 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO;
1332
1333 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS <<
1334 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT;
1335
1336 if (port->tx_ts_enabled)
1337 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN |
1338 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN;
1339
1340 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG);
1341 writel(ts_vlan_ltype, port->port_base +
1342 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG);
1343 writel(ts_ctrl_ltype2, port->port_base +
1344 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2);
1345 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL);
1346
1347 /* en/dis RX timestamp */
1348 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled);
1349
1350 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1351 }
1352
1353 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev,
1354 struct ifreq *ifr)
1355 {
1356 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1357 struct hwtstamp_config cfg;
1358
1359 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
1360 return -EOPNOTSUPP;
1361
1362 cfg.flags = 0;
1363 cfg.tx_type = port->tx_ts_enabled ?
1364 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1365 cfg.rx_filter = port->rx_ts_enabled ?
1366 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
1367
1368 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1369 }
1370
1371 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev,
1372 struct ifreq *req, int cmd)
1373 {
1374 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1375
1376 if (!netif_running(ndev))
1377 return -EINVAL;
1378
1379 switch (cmd) {
1380 case SIOCSHWTSTAMP:
1381 return am65_cpsw_nuss_hwtstamp_set(ndev, req);
1382 case SIOCGHWTSTAMP:
1383 return am65_cpsw_nuss_hwtstamp_get(ndev, req);
1384 }
1385
1386 return phylink_mii_ioctl(port->slave.phylink, req, cmd);
1387 }
1388
1389 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev,
1390 struct rtnl_link_stats64 *stats)
1391 {
1392 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev);
1393 unsigned int start;
1394 int cpu;
1395
1396 for_each_possible_cpu(cpu) {
1397 struct am65_cpsw_ndev_stats *cpu_stats;
1398 u64 rx_packets;
1399 u64 rx_bytes;
1400 u64 tx_packets;
1401 u64 tx_bytes;
1402
1403 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu);
1404 do {
1405 start = u64_stats_fetch_begin(&cpu_stats->syncp);
1406 rx_packets = cpu_stats->rx_packets;
1407 rx_bytes = cpu_stats->rx_bytes;
1408 tx_packets = cpu_stats->tx_packets;
1409 tx_bytes = cpu_stats->tx_bytes;
1410 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start));
1411
1412 stats->rx_packets += rx_packets;
1413 stats->rx_bytes += rx_bytes;
1414 stats->tx_packets += tx_packets;
1415 stats->tx_bytes += tx_bytes;
1416 }
1417
1418 stats->rx_errors = dev->stats.rx_errors;
1419 stats->rx_dropped = dev->stats.rx_dropped;
1420 stats->tx_dropped = dev->stats.tx_dropped;
1421 }
1422
1423 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = {
1424 .ndo_open = am65_cpsw_nuss_ndo_slave_open,
1425 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop,
1426 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit,
1427 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode,
1428 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats,
1429 .ndo_validate_addr = eth_validate_addr,
1430 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address,
1431 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout,
1432 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid,
1433 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid,
1434 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl,
1435 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc,
1436 .ndo_set_tx_maxrate = am65_cpsw_qos_ndo_tx_p0_set_maxrate,
1437 };
1438
1439 static void am65_cpsw_disable_phy(struct phy *phy)
1440 {
1441 phy_power_off(phy);
1442 phy_exit(phy);
1443 }
1444
1445 static int am65_cpsw_enable_phy(struct phy *phy)
1446 {
1447 int ret;
1448
1449 ret = phy_init(phy);
1450 if (ret < 0)
1451 return ret;
1452
1453 ret = phy_power_on(phy);
1454 if (ret < 0) {
1455 phy_exit(phy);
1456 return ret;
1457 }
1458
1459 return 0;
1460 }
1461
1462 static void am65_cpsw_disable_serdes_phy(struct am65_cpsw_common *common)
1463 {
1464 struct am65_cpsw_port *port;
1465 struct phy *phy;
1466 int i;
1467
1468 for (i = 0; i < common->port_num; i++) {
1469 port = &common->ports[i];
1470 phy = port->slave.serdes_phy;
1471 if (phy)
1472 am65_cpsw_disable_phy(phy);
1473 }
1474 }
1475
1476 static int am65_cpsw_init_serdes_phy(struct device *dev, struct device_node *port_np,
1477 struct am65_cpsw_port *port)
1478 {
1479 const char *name = "serdes";
1480 struct phy *phy;
1481 int ret;
1482
1483 phy = devm_of_phy_optional_get(dev, port_np, name);
1484 if (IS_ERR_OR_NULL(phy))
1485 return PTR_ERR_OR_ZERO(phy);
1486
1487 /* Serdes PHY exists. Store it. */
1488 port->slave.serdes_phy = phy;
1489
1490 ret = am65_cpsw_enable_phy(phy);
1491 if (ret < 0)
1492 goto err_phy;
1493
1494 return 0;
1495
1496 err_phy:
1497 devm_phy_put(dev, phy);
1498 return ret;
1499 }
1500
1501 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode,
1502 const struct phylink_link_state *state)
1503 {
1504 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
1505 phylink_config);
1506 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
1507 struct am65_cpsw_common *common = port->common;
1508
1509 if (common->pdata.extra_modes & BIT(state->interface)) {
1510 if (state->interface == PHY_INTERFACE_MODE_SGMII) {
1511 writel(ADVERTISE_SGMII,
1512 port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);
1513 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN);
1514 } else {
1515 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN);
1516 }
1517
1518 if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
1519 cpsw_sl_ctl_set(port->slave.mac_sl,
1520 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN);
1521 } else {
1522 cpsw_sl_ctl_clr(port->slave.mac_sl,
1523 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN);
1524 }
1525
1526 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,
1527 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);
1528 }
1529 }
1530
1531 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode,
1532 phy_interface_t interface)
1533 {
1534 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
1535 phylink_config);
1536 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
1537 struct am65_cpsw_common *common = port->common;
1538 struct net_device *ndev = port->ndev;
1539 u32 mac_control;
1540 int tmo;
1541
1542 /* disable forwarding */
1543 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1544
1545 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE);
1546
1547 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100);
1548 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n",
1549 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo);
1550
1551 /* All the bits that am65_cpsw_nuss_mac_link_up() can possibly set */
1552 mac_control = CPSW_SL_CTL_GMII_EN | CPSW_SL_CTL_GIG | CPSW_SL_CTL_IFCTL_A |
1553 CPSW_SL_CTL_FULLDUPLEX | CPSW_SL_CTL_RX_FLOW_EN | CPSW_SL_CTL_TX_FLOW_EN;
1554 /* If interface mode is RGMII, CPSW_SL_CTL_EXT_EN might have been set for 10 Mbps */
1555 if (phy_interface_mode_is_rgmii(interface))
1556 mac_control |= CPSW_SL_CTL_EXT_EN;
1557 /* Only clear those bits that can be set by am65_cpsw_nuss_mac_link_up() */
1558 cpsw_sl_ctl_clr(port->slave.mac_sl, mac_control);
1559
1560 am65_cpsw_qos_link_down(ndev);
1561 netif_tx_stop_all_queues(ndev);
1562 }
1563
1564 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy,
1565 unsigned int mode, phy_interface_t interface, int speed,
1566 int duplex, bool tx_pause, bool rx_pause)
1567 {
1568 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
1569 phylink_config);
1570 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
1571 struct am65_cpsw_common *common = port->common;
1572 u32 mac_control = CPSW_SL_CTL_GMII_EN;
1573 struct net_device *ndev = port->ndev;
1574
1575 /* Bring the port out of idle state */
1576 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE);
1577
1578 if (speed == SPEED_1000)
1579 mac_control |= CPSW_SL_CTL_GIG;
1580 /* TODO: Verify whether in-band is necessary for 10 Mbps RGMII */
1581 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface))
1582 /* Can be used with in band mode only */
1583 mac_control |= CPSW_SL_CTL_EXT_EN;
1584 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII)
1585 mac_control |= CPSW_SL_CTL_IFCTL_A;
1586 if (duplex)
1587 mac_control |= CPSW_SL_CTL_FULLDUPLEX;
1588
1589 /* rx_pause/tx_pause */
1590 if (rx_pause)
1591 mac_control |= CPSW_SL_CTL_RX_FLOW_EN;
1592
1593 if (tx_pause)
1594 mac_control |= CPSW_SL_CTL_TX_FLOW_EN;
1595
1596 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control);
1597
1598 /* enable forwarding */
1599 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1600
1601 am65_cpsw_qos_link_up(ndev, speed);
1602 netif_tx_wake_all_queues(ndev);
1603 }
1604
1605 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = {
1606 .mac_config = am65_cpsw_nuss_mac_config,
1607 .mac_link_down = am65_cpsw_nuss_mac_link_down,
1608 .mac_link_up = am65_cpsw_nuss_mac_link_up,
1609 };
1610
1611 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port)
1612 {
1613 struct am65_cpsw_common *common = port->common;
1614
1615 if (!port->disabled)
1616 return;
1617
1618 cpsw_ale_control_set(common->ale, port->port_id,
1619 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1620
1621 cpsw_sl_reset(port->slave.mac_sl, 100);
1622 cpsw_sl_ctl_reset(port->slave.mac_sl);
1623 }
1624
1625 static void am65_cpsw_nuss_free_tx_chns(void *data)
1626 {
1627 struct am65_cpsw_common *common = data;
1628 int i;
1629
1630 for (i = 0; i < common->tx_ch_num; i++) {
1631 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1632
1633 if (!IS_ERR_OR_NULL(tx_chn->desc_pool))
1634 k3_cppi_desc_pool_destroy(tx_chn->desc_pool);
1635
1636 if (!IS_ERR_OR_NULL(tx_chn->tx_chn))
1637 k3_udma_glue_release_tx_chn(tx_chn->tx_chn);
1638
1639 memset(tx_chn, 0, sizeof(*tx_chn));
1640 }
1641 }
1642
1643 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common)
1644 {
1645 struct device *dev = common->dev;
1646 int i;
1647
1648 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common);
1649
1650 common->tx_ch_rate_msk = 0;
1651 for (i = 0; i < common->tx_ch_num; i++) {
1652 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1653
1654 if (tx_chn->irq)
1655 devm_free_irq(dev, tx_chn->irq, tx_chn);
1656
1657 netif_napi_del(&tx_chn->napi_tx);
1658
1659 if (!IS_ERR_OR_NULL(tx_chn->desc_pool))
1660 k3_cppi_desc_pool_destroy(tx_chn->desc_pool);
1661
1662 if (!IS_ERR_OR_NULL(tx_chn->tx_chn))
1663 k3_udma_glue_release_tx_chn(tx_chn->tx_chn);
1664
1665 memset(tx_chn, 0, sizeof(*tx_chn));
1666 }
1667 }
1668
1669 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common)
1670 {
1671 struct device *dev = common->dev;
1672 int i, ret = 0;
1673
1674 for (i = 0; i < common->tx_ch_num; i++) {
1675 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1676
1677 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx,
1678 am65_cpsw_nuss_tx_poll);
1679
1680 ret = devm_request_irq(dev, tx_chn->irq,
1681 am65_cpsw_nuss_tx_irq,
1682 IRQF_TRIGGER_HIGH,
1683 tx_chn->tx_chn_name, tx_chn);
1684 if (ret) {
1685 dev_err(dev, "failure requesting tx%u irq %u, %d\n",
1686 tx_chn->id, tx_chn->irq, ret);
1687 goto err;
1688 }
1689 }
1690
1691 err:
1692 return ret;
1693 }
1694
1695 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common)
1696 {
1697 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS);
1698 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 };
1699 struct device *dev = common->dev;
1700 struct k3_ring_cfg ring_cfg = {
1701 .elm_size = K3_RINGACC_RING_ELSIZE_8,
1702 .mode = K3_RINGACC_RING_MODE_RING,
1703 .flags = 0
1704 };
1705 u32 hdesc_size;
1706 int i, ret = 0;
1707
1708 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE,
1709 AM65_CPSW_NAV_SW_DATA_SIZE);
1710
1711 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE;
1712 tx_cfg.tx_cfg = ring_cfg;
1713 tx_cfg.txcq_cfg = ring_cfg;
1714 tx_cfg.tx_cfg.size = max_desc_num;
1715 tx_cfg.txcq_cfg.size = max_desc_num;
1716
1717 for (i = 0; i < common->tx_ch_num; i++) {
1718 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1719
1720 snprintf(tx_chn->tx_chn_name,
1721 sizeof(tx_chn->tx_chn_name), "tx%d", i);
1722
1723 spin_lock_init(&tx_chn->lock);
1724 tx_chn->common = common;
1725 tx_chn->id = i;
1726 tx_chn->descs_num = max_desc_num;
1727
1728 tx_chn->tx_chn =
1729 k3_udma_glue_request_tx_chn(dev,
1730 tx_chn->tx_chn_name,
1731 &tx_cfg);
1732 if (IS_ERR(tx_chn->tx_chn)) {
1733 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn),
1734 "Failed to request tx dma channel\n");
1735 goto err;
1736 }
1737 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn);
1738
1739 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev,
1740 tx_chn->descs_num,
1741 hdesc_size,
1742 tx_chn->tx_chn_name);
1743 if (IS_ERR(tx_chn->desc_pool)) {
1744 ret = PTR_ERR(tx_chn->desc_pool);
1745 dev_err(dev, "Failed to create poll %d\n", ret);
1746 goto err;
1747 }
1748
1749 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn);
1750 if (tx_chn->irq <= 0) {
1751 dev_err(dev, "Failed to get tx dma irq %d\n",
1752 tx_chn->irq);
1753 goto err;
1754 }
1755
1756 snprintf(tx_chn->tx_chn_name,
1757 sizeof(tx_chn->tx_chn_name), "%s-tx%d",
1758 dev_name(dev), tx_chn->id);
1759 }
1760
1761 ret = am65_cpsw_nuss_ndev_add_tx_napi(common);
1762 if (ret) {
1763 dev_err(dev, "Failed to add tx NAPI %d\n", ret);
1764 goto err;
1765 }
1766
1767 err:
1768 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common);
1769 if (i) {
1770 dev_err(dev, "Failed to add free_tx_chns action %d\n", i);
1771 return i;
1772 }
1773
1774 return ret;
1775 }
1776
1777 static void am65_cpsw_nuss_free_rx_chns(void *data)
1778 {
1779 struct am65_cpsw_common *common = data;
1780 struct am65_cpsw_rx_chn *rx_chn;
1781
1782 rx_chn = &common->rx_chns;
1783
1784 if (!IS_ERR_OR_NULL(rx_chn->desc_pool))
1785 k3_cppi_desc_pool_destroy(rx_chn->desc_pool);
1786
1787 if (!IS_ERR_OR_NULL(rx_chn->rx_chn))
1788 k3_udma_glue_release_rx_chn(rx_chn->rx_chn);
1789 }
1790
1791 static void am65_cpsw_nuss_remove_rx_chns(void *data)
1792 {
1793 struct am65_cpsw_common *common = data;
1794 struct am65_cpsw_rx_chn *rx_chn;
1795 struct device *dev = common->dev;
1796
1797 rx_chn = &common->rx_chns;
1798 devm_remove_action(dev, am65_cpsw_nuss_free_rx_chns, common);
1799
1800 if (!(rx_chn->irq < 0))
1801 devm_free_irq(dev, rx_chn->irq, common);
1802
1803 netif_napi_del(&common->napi_rx);
1804
1805 if (!IS_ERR_OR_NULL(rx_chn->desc_pool))
1806 k3_cppi_desc_pool_destroy(rx_chn->desc_pool);
1807
1808 if (!IS_ERR_OR_NULL(rx_chn->rx_chn))
1809 k3_udma_glue_release_rx_chn(rx_chn->rx_chn);
1810
1811 common->rx_flow_id_base = -1;
1812 }
1813
1814 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common)
1815 {
1816 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;
1817 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 };
1818 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC;
1819 struct device *dev = common->dev;
1820 u32 hdesc_size;
1821 u32 fdqring_id;
1822 int i, ret = 0;
1823
1824 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE,
1825 AM65_CPSW_NAV_SW_DATA_SIZE);
1826
1827 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE;
1828 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS;
1829 rx_cfg.flow_id_base = common->rx_flow_id_base;
1830
1831 /* init all flows */
1832 rx_chn->dev = dev;
1833 rx_chn->descs_num = max_desc_num;
1834
1835 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg);
1836 if (IS_ERR(rx_chn->rx_chn)) {
1837 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn),
1838 "Failed to request rx dma channel\n");
1839 goto err;
1840 }
1841 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn);
1842
1843 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev,
1844 rx_chn->descs_num,
1845 hdesc_size, "rx");
1846 if (IS_ERR(rx_chn->desc_pool)) {
1847 ret = PTR_ERR(rx_chn->desc_pool);
1848 dev_err(dev, "Failed to create rx poll %d\n", ret);
1849 goto err;
1850 }
1851
1852 common->rx_flow_id_base =
1853 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn);
1854 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base);
1855
1856 fdqring_id = K3_RINGACC_RING_ID_ANY;
1857 for (i = 0; i < rx_cfg.flow_id_num; i++) {
1858 struct k3_ring_cfg rxring_cfg = {
1859 .elm_size = K3_RINGACC_RING_ELSIZE_8,
1860 .mode = K3_RINGACC_RING_MODE_RING,
1861 .flags = 0,
1862 };
1863 struct k3_ring_cfg fdqring_cfg = {
1864 .elm_size = K3_RINGACC_RING_ELSIZE_8,
1865 .flags = K3_RINGACC_RING_SHARED,
1866 };
1867 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = {
1868 .rx_cfg = rxring_cfg,
1869 .rxfdq_cfg = fdqring_cfg,
1870 .ring_rxq_id = K3_RINGACC_RING_ID_ANY,
1871 .src_tag_lo_sel =
1872 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG,
1873 };
1874
1875 rx_flow_cfg.ring_rxfdq0_id = fdqring_id;
1876 rx_flow_cfg.rx_cfg.size = max_desc_num;
1877 rx_flow_cfg.rxfdq_cfg.size = max_desc_num;
1878 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode;
1879
1880 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn,
1881 i, &rx_flow_cfg);
1882 if (ret) {
1883 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret);
1884 goto err;
1885 }
1886 if (!i)
1887 fdqring_id =
1888 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn,
1889 i);
1890
1891 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i);
1892
1893 if (rx_chn->irq <= 0) {
1894 dev_err(dev, "Failed to get rx dma irq %d\n",
1895 rx_chn->irq);
1896 ret = -ENXIO;
1897 goto err;
1898 }
1899 }
1900
1901 netif_napi_add(common->dma_ndev, &common->napi_rx,
1902 am65_cpsw_nuss_rx_poll);
1903
1904 ret = devm_request_irq(dev, rx_chn->irq,
1905 am65_cpsw_nuss_rx_irq,
1906 IRQF_TRIGGER_HIGH, dev_name(dev), common);
1907 if (ret) {
1908 dev_err(dev, "failure requesting rx irq %u, %d\n",
1909 rx_chn->irq, ret);
1910 goto err;
1911 }
1912
1913 err:
1914 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common);
1915 if (i) {
1916 dev_err(dev, "Failed to add free_rx_chns action %d\n", i);
1917 return i;
1918 }
1919
1920 return ret;
1921 }
1922
1923 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common)
1924 {
1925 struct am65_cpsw_host *host_p = am65_common_get_host(common);
1926
1927 host_p->common = common;
1928 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE;
1929 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE;
1930
1931 return 0;
1932 }
1933
1934 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node,
1935 int slave, u8 *mac_addr)
1936 {
1937 u32 mac_lo, mac_hi, offset;
1938 struct regmap *syscon;
1939 int ret;
1940
1941 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse");
1942 if (IS_ERR(syscon)) {
1943 if (PTR_ERR(syscon) == -ENODEV)
1944 return 0;
1945 return PTR_ERR(syscon);
1946 }
1947
1948 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1,
1949 &offset);
1950 if (ret)
1951 return ret;
1952
1953 regmap_read(syscon, offset, &mac_lo);
1954 regmap_read(syscon, offset + 4, &mac_hi);
1955
1956 mac_addr[0] = (mac_hi >> 8) & 0xff;
1957 mac_addr[1] = mac_hi & 0xff;
1958 mac_addr[2] = (mac_lo >> 24) & 0xff;
1959 mac_addr[3] = (mac_lo >> 16) & 0xff;
1960 mac_addr[4] = (mac_lo >> 8) & 0xff;
1961 mac_addr[5] = mac_lo & 0xff;
1962
1963 return 0;
1964 }
1965
1966 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common)
1967 {
1968 struct device *dev = common->dev;
1969 struct device_node *node;
1970 struct am65_cpts *cpts;
1971 void __iomem *reg_base;
1972
1973 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
1974 return 0;
1975
1976 node = of_get_child_by_name(dev->of_node, "cpts");
1977 if (!node) {
1978 dev_err(dev, "%s cpts not found\n", __func__);
1979 return -ENOENT;
1980 }
1981
1982 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE;
1983 cpts = am65_cpts_create(dev, reg_base, node);
1984 if (IS_ERR(cpts)) {
1985 int ret = PTR_ERR(cpts);
1986
1987 of_node_put(node);
1988 dev_err(dev, "cpts create err %d\n", ret);
1989 return ret;
1990 }
1991 common->cpts = cpts;
1992 /* Forbid PM runtime if CPTS is running.
1993 * K3 CPSWxG modules may completely lose context during ON->OFF
1994 * transitions depending on integration.
1995 * AM65x/J721E MCU CPSW2G: false
1996 * J721E MAIN_CPSW9G: true
1997 */
1998 pm_runtime_forbid(dev);
1999
2000 return 0;
2001 }
2002
2003 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common)
2004 {
2005 struct device_node *node, *port_np;
2006 struct device *dev = common->dev;
2007 int ret;
2008
2009 node = of_get_child_by_name(dev->of_node, "ethernet-ports");
2010 if (!node)
2011 return -ENOENT;
2012
2013 for_each_child_of_node(node, port_np) {
2014 struct am65_cpsw_port *port;
2015 u32 port_id;
2016
2017 /* it is not a slave port node, continue */
2018 if (strcmp(port_np->name, "port"))
2019 continue;
2020
2021 ret = of_property_read_u32(port_np, "reg", &port_id);
2022 if (ret < 0) {
2023 dev_err(dev, "%pOF error reading port_id %d\n",
2024 port_np, ret);
2025 goto of_node_put;
2026 }
2027
2028 if (!port_id || port_id > common->port_num) {
2029 dev_err(dev, "%pOF has invalid port_id %u %s\n",
2030 port_np, port_id, port_np->name);
2031 ret = -EINVAL;
2032 goto of_node_put;
2033 }
2034
2035 port = am65_common_get_port(common, port_id);
2036 port->port_id = port_id;
2037 port->common = common;
2038 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE +
2039 AM65_CPSW_NU_PORTS_OFFSET * (port_id);
2040 if (common->pdata.extra_modes)
2041 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id);
2042 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE +
2043 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id);
2044 port->name = of_get_property(port_np, "label", NULL);
2045 port->fetch_ram_base =
2046 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE +
2047 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1));
2048
2049 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base);
2050 if (IS_ERR(port->slave.mac_sl)) {
2051 ret = PTR_ERR(port->slave.mac_sl);
2052 goto of_node_put;
2053 }
2054
2055 port->disabled = !of_device_is_available(port_np);
2056 if (port->disabled) {
2057 common->disabled_ports_mask |= BIT(port->port_id);
2058 continue;
2059 }
2060
2061 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL);
2062 if (IS_ERR(port->slave.ifphy)) {
2063 ret = PTR_ERR(port->slave.ifphy);
2064 dev_err(dev, "%pOF error retrieving port phy: %d\n",
2065 port_np, ret);
2066 goto of_node_put;
2067 }
2068
2069 /* Initialize the Serdes PHY for the port */
2070 ret = am65_cpsw_init_serdes_phy(dev, port_np, port);
2071 if (ret)
2072 goto of_node_put;
2073
2074 port->slave.mac_only =
2075 of_property_read_bool(port_np, "ti,mac-only");
2076
2077 /* get phy/link info */
2078 port->slave.phy_node = port_np;
2079 ret = of_get_phy_mode(port_np, &port->slave.phy_if);
2080 if (ret) {
2081 dev_err(dev, "%pOF read phy-mode err %d\n",
2082 port_np, ret);
2083 goto of_node_put;
2084 }
2085
2086 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if);
2087 if (ret)
2088 goto of_node_put;
2089
2090 ret = of_get_mac_address(port_np, port->slave.mac_addr);
2091 if (ret) {
2092 am65_cpsw_am654_get_efuse_macid(port_np,
2093 port->port_id,
2094 port->slave.mac_addr);
2095 if (!is_valid_ether_addr(port->slave.mac_addr)) {
2096 eth_random_addr(port->slave.mac_addr);
2097 dev_err(dev, "Use random MAC address\n");
2098 }
2099 }
2100 }
2101 of_node_put(node);
2102
2103 /* is there at least one ext.port */
2104 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) {
2105 dev_err(dev, "No Ext. port are available\n");
2106 return -ENODEV;
2107 }
2108
2109 return 0;
2110
2111 of_node_put:
2112 of_node_put(port_np);
2113 of_node_put(node);
2114 return ret;
2115 }
2116
2117 static void am65_cpsw_pcpu_stats_free(void *data)
2118 {
2119 struct am65_cpsw_ndev_stats __percpu *stats = data;
2120
2121 free_percpu(stats);
2122 }
2123
2124 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common)
2125 {
2126 struct am65_cpsw_port *port;
2127 int i;
2128
2129 for (i = 0; i < common->port_num; i++) {
2130 port = &common->ports[i];
2131 if (port->slave.phylink)
2132 phylink_destroy(port->slave.phylink);
2133 }
2134 }
2135
2136 static int
2137 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx)
2138 {
2139 struct am65_cpsw_ndev_priv *ndev_priv;
2140 struct device *dev = common->dev;
2141 struct am65_cpsw_port *port;
2142 struct phylink *phylink;
2143 int ret;
2144
2145 port = &common->ports[port_idx];
2146
2147 if (port->disabled)
2148 return 0;
2149
2150 /* alloc netdev */
2151 port->ndev = devm_alloc_etherdev_mqs(common->dev,
2152 sizeof(struct am65_cpsw_ndev_priv),
2153 AM65_CPSW_MAX_TX_QUEUES,
2154 AM65_CPSW_MAX_RX_QUEUES);
2155 if (!port->ndev) {
2156 dev_err(dev, "error allocating slave net_device %u\n",
2157 port->port_id);
2158 return -ENOMEM;
2159 }
2160
2161 ndev_priv = netdev_priv(port->ndev);
2162 ndev_priv->port = port;
2163 ndev_priv->msg_enable = AM65_CPSW_DEBUG;
2164 SET_NETDEV_DEV(port->ndev, dev);
2165
2166 eth_hw_addr_set(port->ndev, port->slave.mac_addr);
2167
2168 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE;
2169 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE;
2170 port->ndev->hw_features = NETIF_F_SG |
2171 NETIF_F_RXCSUM |
2172 NETIF_F_HW_CSUM |
2173 NETIF_F_HW_TC;
2174 port->ndev->features = port->ndev->hw_features |
2175 NETIF_F_HW_VLAN_CTAG_FILTER;
2176 port->ndev->vlan_features |= NETIF_F_SG;
2177 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops;
2178 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave;
2179
2180 /* Configuring Phylink */
2181 port->slave.phylink_config.dev = &port->ndev->dev;
2182 port->slave.phylink_config.type = PHYLINK_NETDEV;
2183 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
2184 MAC_1000FD | MAC_5000FD;
2185 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */
2186
2187 switch (port->slave.phy_if) {
2188 case PHY_INTERFACE_MODE_RGMII:
2189 case PHY_INTERFACE_MODE_RGMII_ID:
2190 case PHY_INTERFACE_MODE_RGMII_RXID:
2191 case PHY_INTERFACE_MODE_RGMII_TXID:
2192 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces);
2193 break;
2194
2195 case PHY_INTERFACE_MODE_RMII:
2196 __set_bit(PHY_INTERFACE_MODE_RMII,
2197 port->slave.phylink_config.supported_interfaces);
2198 break;
2199
2200 case PHY_INTERFACE_MODE_QSGMII:
2201 case PHY_INTERFACE_MODE_SGMII:
2202 case PHY_INTERFACE_MODE_USXGMII:
2203 if (common->pdata.extra_modes & BIT(port->slave.phy_if)) {
2204 __set_bit(port->slave.phy_if,
2205 port->slave.phylink_config.supported_interfaces);
2206 } else {
2207 dev_err(dev, "selected phy-mode is not supported\n");
2208 return -EOPNOTSUPP;
2209 }
2210 break;
2211
2212 default:
2213 dev_err(dev, "selected phy-mode is not supported\n");
2214 return -EOPNOTSUPP;
2215 }
2216
2217 phylink = phylink_create(&port->slave.phylink_config,
2218 of_node_to_fwnode(port->slave.phy_node),
2219 port->slave.phy_if,
2220 &am65_cpsw_phylink_mac_ops);
2221 if (IS_ERR(phylink))
2222 return PTR_ERR(phylink);
2223
2224 port->slave.phylink = phylink;
2225
2226 /* Disable TX checksum offload by default due to HW bug */
2227 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM)
2228 port->ndev->features &= ~NETIF_F_HW_CSUM;
2229
2230 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats);
2231 if (!ndev_priv->stats)
2232 return -ENOMEM;
2233
2234 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free,
2235 ndev_priv->stats);
2236 if (ret)
2237 dev_err(dev, "failed to add percpu stat free action %d\n", ret);
2238
2239 if (!common->dma_ndev)
2240 common->dma_ndev = port->ndev;
2241
2242 return ret;
2243 }
2244
2245 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common)
2246 {
2247 int ret;
2248 int i;
2249
2250 for (i = 0; i < common->port_num; i++) {
2251 ret = am65_cpsw_nuss_init_port_ndev(common, i);
2252 if (ret)
2253 return ret;
2254 }
2255
2256 return ret;
2257 }
2258
2259 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common)
2260 {
2261 struct am65_cpsw_port *port;
2262 int i;
2263
2264 for (i = 0; i < common->port_num; i++) {
2265 port = &common->ports[i];
2266 if (port->ndev && port->ndev->reg_state == NETREG_REGISTERED)
2267 unregister_netdev(port->ndev);
2268 }
2269 }
2270
2271 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common)
2272 {
2273 int set_val = 0;
2274 int i;
2275
2276 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask))
2277 set_val = 1;
2278
2279 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val);
2280
2281 for (i = 1; i <= common->port_num; i++) {
2282 struct am65_cpsw_port *port = am65_common_get_port(common, i);
2283 struct am65_cpsw_ndev_priv *priv;
2284
2285 if (!port->ndev)
2286 continue;
2287
2288 priv = am65_ndev_to_priv(port->ndev);
2289 priv->offload_fwd_mark = set_val;
2290 }
2291 }
2292
2293 bool am65_cpsw_port_dev_check(const struct net_device *ndev)
2294 {
2295 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) {
2296 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
2297
2298 return !common->is_emac_mode;
2299 }
2300
2301 return false;
2302 }
2303
2304 static int am65_cpsw_netdevice_port_link(struct net_device *ndev,
2305 struct net_device *br_ndev,
2306 struct netlink_ext_ack *extack)
2307 {
2308 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
2309 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev);
2310 int err;
2311
2312 if (!common->br_members) {
2313 common->hw_bridge_dev = br_ndev;
2314 } else {
2315 /* This is adding the port to a second bridge, this is
2316 * unsupported
2317 */
2318 if (common->hw_bridge_dev != br_ndev)
2319 return -EOPNOTSUPP;
2320 }
2321
2322 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL,
2323 false, extack);
2324 if (err)
2325 return err;
2326
2327 common->br_members |= BIT(priv->port->port_id);
2328
2329 am65_cpsw_port_offload_fwd_mark_update(common);
2330
2331 return NOTIFY_DONE;
2332 }
2333
2334 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev)
2335 {
2336 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
2337 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev);
2338
2339 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL);
2340
2341 common->br_members &= ~BIT(priv->port->port_id);
2342
2343 am65_cpsw_port_offload_fwd_mark_update(common);
2344
2345 if (!common->br_members)
2346 common->hw_bridge_dev = NULL;
2347 }
2348
2349 /* netdev notifier */
2350 static int am65_cpsw_netdevice_event(struct notifier_block *unused,
2351 unsigned long event, void *ptr)
2352 {
2353 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr);
2354 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
2355 struct netdev_notifier_changeupper_info *info;
2356 int ret = NOTIFY_DONE;
2357
2358 if (!am65_cpsw_port_dev_check(ndev))
2359 return NOTIFY_DONE;
2360
2361 switch (event) {
2362 case NETDEV_CHANGEUPPER:
2363 info = ptr;
2364
2365 if (netif_is_bridge_master(info->upper_dev)) {
2366 if (info->linking)
2367 ret = am65_cpsw_netdevice_port_link(ndev,
2368 info->upper_dev,
2369 extack);
2370 else
2371 am65_cpsw_netdevice_port_unlink(ndev);
2372 }
2373 break;
2374 default:
2375 return NOTIFY_DONE;
2376 }
2377
2378 return notifier_from_errno(ret);
2379 }
2380
2381 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw)
2382 {
2383 int ret = 0;
2384
2385 if (AM65_CPSW_IS_CPSW2G(cpsw) ||
2386 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV))
2387 return 0;
2388
2389 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event;
2390 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb);
2391 if (ret) {
2392 dev_err(cpsw->dev, "can't register netdevice notifier\n");
2393 return ret;
2394 }
2395
2396 ret = am65_cpsw_switchdev_register_notifiers(cpsw);
2397 if (ret)
2398 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb);
2399
2400 return ret;
2401 }
2402
2403 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw)
2404 {
2405 if (AM65_CPSW_IS_CPSW2G(cpsw) ||
2406 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV))
2407 return;
2408
2409 am65_cpsw_switchdev_unregister_notifiers(cpsw);
2410 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb);
2411 }
2412
2413 static const struct devlink_ops am65_cpsw_devlink_ops = {};
2414
2415 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw)
2416 {
2417 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0,
2418 ALE_MCAST_BLOCK_LEARN_FWD);
2419 }
2420
2421 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common)
2422 {
2423 struct am65_cpsw_host *host = am65_common_get_host(common);
2424
2425 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2426
2427 am65_cpsw_init_stp_ale_entry(common);
2428
2429 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1);
2430 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n");
2431 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0);
2432 }
2433
2434 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common)
2435 {
2436 struct am65_cpsw_host *host = am65_common_get_host(common);
2437
2438 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2439
2440 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0);
2441 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n");
2442
2443 /* learning make no sense in multi-mac mode */
2444 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1);
2445 }
2446
2447 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id,
2448 struct devlink_param_gset_ctx *ctx)
2449 {
2450 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl);
2451 struct am65_cpsw_common *common = dl_priv->common;
2452
2453 dev_dbg(common->dev, "%s id:%u\n", __func__, id);
2454
2455 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE)
2456 return -EOPNOTSUPP;
2457
2458 ctx->val.vbool = !common->is_emac_mode;
2459
2460 return 0;
2461 }
2462
2463 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port)
2464 {
2465 struct am65_cpsw_slave_data *slave = &port->slave;
2466 struct am65_cpsw_common *common = port->common;
2467 u32 port_mask;
2468
2469 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2470
2471 if (slave->mac_only)
2472 /* enable mac-only mode on port */
2473 cpsw_ale_control_set(common->ale, port->port_id,
2474 ALE_PORT_MACONLY, 1);
2475
2476 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1);
2477
2478 port_mask = BIT(port->port_id) | ALE_PORT_HOST;
2479
2480 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr,
2481 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan);
2482 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast,
2483 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2);
2484 }
2485
2486 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port)
2487 {
2488 struct am65_cpsw_slave_data *slave = &port->slave;
2489 struct am65_cpsw_common *cpsw = port->common;
2490 u32 port_mask;
2491
2492 cpsw_ale_control_set(cpsw->ale, port->port_id,
2493 ALE_PORT_NOLEARN, 0);
2494
2495 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr,
2496 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN,
2497 slave->port_vlan);
2498
2499 port_mask = BIT(port->port_id) | ALE_PORT_HOST;
2500
2501 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast,
2502 port_mask, ALE_VLAN, slave->port_vlan,
2503 ALE_MCAST_FWD_2);
2504
2505 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2506
2507 cpsw_ale_control_set(cpsw->ale, port->port_id,
2508 ALE_PORT_MACONLY, 0);
2509 }
2510
2511 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id,
2512 struct devlink_param_gset_ctx *ctx)
2513 {
2514 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl);
2515 struct am65_cpsw_common *cpsw = dl_priv->common;
2516 bool switch_en = ctx->val.vbool;
2517 bool if_running = false;
2518 int i;
2519
2520 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id);
2521
2522 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE)
2523 return -EOPNOTSUPP;
2524
2525 if (switch_en == !cpsw->is_emac_mode)
2526 return 0;
2527
2528 if (!switch_en && cpsw->br_members) {
2529 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n");
2530 return -EINVAL;
2531 }
2532
2533 rtnl_lock();
2534
2535 cpsw->is_emac_mode = !switch_en;
2536
2537 for (i = 0; i < cpsw->port_num; i++) {
2538 struct net_device *sl_ndev = cpsw->ports[i].ndev;
2539
2540 if (!sl_ndev || !netif_running(sl_ndev))
2541 continue;
2542
2543 if_running = true;
2544 }
2545
2546 if (!if_running) {
2547 /* all ndevs are down */
2548 for (i = 0; i < cpsw->port_num; i++) {
2549 struct net_device *sl_ndev = cpsw->ports[i].ndev;
2550 struct am65_cpsw_slave_data *slave;
2551
2552 if (!sl_ndev)
2553 continue;
2554
2555 slave = am65_ndev_to_slave(sl_ndev);
2556 if (switch_en)
2557 slave->port_vlan = cpsw->default_vlan;
2558 else
2559 slave->port_vlan = 0;
2560 }
2561
2562 goto exit;
2563 }
2564
2565 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1);
2566 /* clean up ALE table */
2567 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1);
2568 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT);
2569
2570 if (switch_en) {
2571 dev_info(cpsw->dev, "Enable switch mode\n");
2572
2573 am65_cpsw_init_host_port_switch(cpsw);
2574
2575 for (i = 0; i < cpsw->port_num; i++) {
2576 struct net_device *sl_ndev = cpsw->ports[i].ndev;
2577 struct am65_cpsw_slave_data *slave;
2578 struct am65_cpsw_port *port;
2579
2580 if (!sl_ndev)
2581 continue;
2582
2583 port = am65_ndev_to_port(sl_ndev);
2584 slave = am65_ndev_to_slave(sl_ndev);
2585 slave->port_vlan = cpsw->default_vlan;
2586
2587 if (netif_running(sl_ndev))
2588 am65_cpsw_init_port_switch_ale(port);
2589 }
2590
2591 } else {
2592 dev_info(cpsw->dev, "Disable switch mode\n");
2593
2594 am65_cpsw_init_host_port_emac(cpsw);
2595
2596 for (i = 0; i < cpsw->port_num; i++) {
2597 struct net_device *sl_ndev = cpsw->ports[i].ndev;
2598 struct am65_cpsw_port *port;
2599
2600 if (!sl_ndev)
2601 continue;
2602
2603 port = am65_ndev_to_port(sl_ndev);
2604 port->slave.port_vlan = 0;
2605 if (netif_running(sl_ndev))
2606 am65_cpsw_init_port_emac_ale(port);
2607 }
2608 }
2609 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0);
2610 exit:
2611 rtnl_unlock();
2612
2613 return 0;
2614 }
2615
2616 static const struct devlink_param am65_cpsw_devlink_params[] = {
2617 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode",
2618 DEVLINK_PARAM_TYPE_BOOL,
2619 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
2620 am65_cpsw_dl_switch_mode_get,
2621 am65_cpsw_dl_switch_mode_set, NULL),
2622 };
2623
2624 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common)
2625 {
2626 struct devlink_port_attrs attrs = {};
2627 struct am65_cpsw_devlink *dl_priv;
2628 struct device *dev = common->dev;
2629 struct devlink_port *dl_port;
2630 struct am65_cpsw_port *port;
2631 int ret = 0;
2632 int i;
2633
2634 common->devlink =
2635 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev);
2636 if (!common->devlink)
2637 return -ENOMEM;
2638
2639 dl_priv = devlink_priv(common->devlink);
2640 dl_priv->common = common;
2641
2642 /* Provide devlink hook to switch mode when multiple external ports
2643 * are present NUSS switchdev driver is enabled.
2644 */
2645 if (!AM65_CPSW_IS_CPSW2G(common) &&
2646 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) {
2647 ret = devlink_params_register(common->devlink,
2648 am65_cpsw_devlink_params,
2649 ARRAY_SIZE(am65_cpsw_devlink_params));
2650 if (ret) {
2651 dev_err(dev, "devlink params reg fail ret:%d\n", ret);
2652 goto dl_unreg;
2653 }
2654 }
2655
2656 for (i = 1; i <= common->port_num; i++) {
2657 port = am65_common_get_port(common, i);
2658 dl_port = &port->devlink_port;
2659
2660 if (port->ndev)
2661 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL;
2662 else
2663 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED;
2664 attrs.phys.port_number = port->port_id;
2665 attrs.switch_id.id_len = sizeof(resource_size_t);
2666 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len);
2667 devlink_port_attrs_set(dl_port, &attrs);
2668
2669 ret = devlink_port_register(common->devlink, dl_port, port->port_id);
2670 if (ret) {
2671 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n",
2672 port->port_id, ret);
2673 goto dl_port_unreg;
2674 }
2675 }
2676 devlink_register(common->devlink);
2677 return ret;
2678
2679 dl_port_unreg:
2680 for (i = i - 1; i >= 1; i--) {
2681 port = am65_common_get_port(common, i);
2682 dl_port = &port->devlink_port;
2683
2684 devlink_port_unregister(dl_port);
2685 }
2686 dl_unreg:
2687 devlink_free(common->devlink);
2688 return ret;
2689 }
2690
2691 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common)
2692 {
2693 struct devlink_port *dl_port;
2694 struct am65_cpsw_port *port;
2695 int i;
2696
2697 devlink_unregister(common->devlink);
2698
2699 for (i = 1; i <= common->port_num; i++) {
2700 port = am65_common_get_port(common, i);
2701 dl_port = &port->devlink_port;
2702
2703 devlink_port_unregister(dl_port);
2704 }
2705
2706 if (!AM65_CPSW_IS_CPSW2G(common) &&
2707 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV))
2708 devlink_params_unregister(common->devlink,
2709 am65_cpsw_devlink_params,
2710 ARRAY_SIZE(am65_cpsw_devlink_params));
2711
2712 devlink_free(common->devlink);
2713 }
2714
2715 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common)
2716 {
2717 struct device *dev = common->dev;
2718 struct am65_cpsw_port *port;
2719 int ret = 0, i;
2720
2721 /* init tx channels */
2722 ret = am65_cpsw_nuss_init_tx_chns(common);
2723 if (ret)
2724 return ret;
2725 ret = am65_cpsw_nuss_init_rx_chns(common);
2726 if (ret)
2727 return ret;
2728
2729 ret = am65_cpsw_nuss_register_devlink(common);
2730 if (ret)
2731 return ret;
2732
2733 for (i = 0; i < common->port_num; i++) {
2734 port = &common->ports[i];
2735
2736 if (!port->ndev)
2737 continue;
2738
2739 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port);
2740
2741 ret = register_netdev(port->ndev);
2742 if (ret) {
2743 dev_err(dev, "error registering slave net device%i %d\n",
2744 i, ret);
2745 goto err_cleanup_ndev;
2746 }
2747 }
2748
2749 ret = am65_cpsw_register_notifiers(common);
2750 if (ret)
2751 goto err_cleanup_ndev;
2752
2753 /* can't auto unregister ndev using devm_add_action() due to
2754 * devres release sequence in DD core for DMA
2755 */
2756
2757 return 0;
2758
2759 err_cleanup_ndev:
2760 am65_cpsw_nuss_cleanup_ndev(common);
2761 am65_cpsw_unregister_devlink(common);
2762
2763 return ret;
2764 }
2765
2766 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx)
2767 {
2768 int ret;
2769
2770 common->tx_ch_num = num_tx;
2771 ret = am65_cpsw_nuss_init_tx_chns(common);
2772
2773 return ret;
2774 }
2775
2776 struct am65_cpsw_soc_pdata {
2777 u32 quirks_dis;
2778 };
2779
2780 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = {
2781 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM,
2782 };
2783
2784 static const struct soc_device_attribute am65_cpsw_socinfo[] = {
2785 { .family = "AM65X",
2786 .revision = "SR2.0",
2787 .data = &am65x_soc_sr2_0
2788 },
2789 {/* sentinel */}
2790 };
2791
2792 static const struct am65_cpsw_pdata am65x_sr1_0 = {
2793 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM,
2794 .ale_dev_id = "am65x-cpsw2g",
2795 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
2796 };
2797
2798 static const struct am65_cpsw_pdata j721e_pdata = {
2799 .quirks = 0,
2800 .ale_dev_id = "am65x-cpsw2g",
2801 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
2802 };
2803
2804 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = {
2805 .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ,
2806 .ale_dev_id = "am64-cpswxg",
2807 .fdqring_mode = K3_RINGACC_RING_MODE_RING,
2808 };
2809
2810 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = {
2811 .quirks = 0,
2812 .ale_dev_id = "am64-cpswxg",
2813 .fdqring_mode = K3_RINGACC_RING_MODE_RING,
2814 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
2815 };
2816
2817 static const struct am65_cpsw_pdata j721e_cpswxg_pdata = {
2818 .quirks = 0,
2819 .ale_dev_id = "am64-cpswxg",
2820 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
2821 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
2822 };
2823
2824 static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = {
2825 .quirks = 0,
2826 .ale_dev_id = "am64-cpswxg",
2827 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
2828 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_USXGMII),
2829 };
2830
2831 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {
2832 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0},
2833 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata},
2834 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata},
2835 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata},
2836 { .compatible = "ti,j721e-cpswxg-nuss", .data = &j721e_cpswxg_pdata},
2837 { .compatible = "ti,j784s4-cpswxg-nuss", .data = &j784s4_cpswxg_pdata},
2838 { /* sentinel */ },
2839 };
2840 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable);
2841
2842 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common)
2843 {
2844 const struct soc_device_attribute *soc;
2845
2846 soc = soc_device_match(am65_cpsw_socinfo);
2847 if (soc && soc->data) {
2848 const struct am65_cpsw_soc_pdata *socdata = soc->data;
2849
2850 /* disable quirks */
2851 common->pdata.quirks &= ~socdata->quirks_dis;
2852 }
2853 }
2854
2855 static int am65_cpsw_nuss_probe(struct platform_device *pdev)
2856 {
2857 struct cpsw_ale_params ale_params = { 0 };
2858 const struct of_device_id *of_id;
2859 struct device *dev = &pdev->dev;
2860 struct am65_cpsw_common *common;
2861 struct device_node *node;
2862 struct resource *res;
2863 struct clk *clk;
2864 u64 id_temp;
2865 int ret, i;
2866 int ale_entries;
2867
2868 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL);
2869 if (!common)
2870 return -ENOMEM;
2871 common->dev = dev;
2872
2873 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev);
2874 if (!of_id)
2875 return -EINVAL;
2876 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data;
2877
2878 am65_cpsw_nuss_apply_socinfo(common);
2879
2880 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss");
2881 common->ss_base = devm_ioremap_resource(&pdev->dev, res);
2882 if (IS_ERR(common->ss_base))
2883 return PTR_ERR(common->ss_base);
2884 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE;
2885 /* Use device's physical base address as switch id */
2886 id_temp = cpu_to_be64(res->start);
2887 memcpy(common->switch_id, &id_temp, sizeof(res->start));
2888
2889 node = of_get_child_by_name(dev->of_node, "ethernet-ports");
2890 if (!node)
2891 return -ENOENT;
2892 common->port_num = of_get_child_count(node);
2893 of_node_put(node);
2894 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS)
2895 return -ENOENT;
2896
2897 common->rx_flow_id_base = -1;
2898 init_completion(&common->tdown_complete);
2899 common->tx_ch_num = 1;
2900 common->pf_p0_rx_ptype_rrobin = false;
2901 common->default_vlan = 1;
2902
2903 common->ports = devm_kcalloc(dev, common->port_num,
2904 sizeof(*common->ports),
2905 GFP_KERNEL);
2906 if (!common->ports)
2907 return -ENOMEM;
2908
2909 clk = devm_clk_get(dev, "fck");
2910 if (IS_ERR(clk))
2911 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n");
2912 common->bus_freq = clk_get_rate(clk);
2913
2914 pm_runtime_enable(dev);
2915 ret = pm_runtime_resume_and_get(dev);
2916 if (ret < 0) {
2917 pm_runtime_disable(dev);
2918 return ret;
2919 }
2920
2921 node = of_get_child_by_name(dev->of_node, "mdio");
2922 if (!node) {
2923 dev_warn(dev, "MDIO node not found\n");
2924 } else if (of_device_is_available(node)) {
2925 struct platform_device *mdio_pdev;
2926
2927 mdio_pdev = of_platform_device_create(node, NULL, dev);
2928 if (!mdio_pdev) {
2929 ret = -ENODEV;
2930 goto err_pm_clear;
2931 }
2932
2933 common->mdio_dev = &mdio_pdev->dev;
2934 }
2935 of_node_put(node);
2936
2937 am65_cpsw_nuss_get_ver(common);
2938
2939 ret = am65_cpsw_nuss_init_host_p(common);
2940 if (ret)
2941 goto err_of_clear;
2942
2943 ret = am65_cpsw_nuss_init_slave_ports(common);
2944 if (ret)
2945 goto err_of_clear;
2946
2947 /* init common data */
2948 ale_params.dev = dev;
2949 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT;
2950 ale_params.ale_ports = common->port_num + 1;
2951 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE;
2952 ale_params.dev_id = common->pdata.ale_dev_id;
2953 ale_params.bus_freq = common->bus_freq;
2954
2955 common->ale = cpsw_ale_create(&ale_params);
2956 if (IS_ERR(common->ale)) {
2957 dev_err(dev, "error initializing ale engine\n");
2958 ret = PTR_ERR(common->ale);
2959 goto err_of_clear;
2960 }
2961
2962 ale_entries = common->ale->params.ale_entries;
2963 common->ale_context = devm_kzalloc(dev,
2964 ale_entries * ALE_ENTRY_WORDS * sizeof(u32),
2965 GFP_KERNEL);
2966 ret = am65_cpsw_init_cpts(common);
2967 if (ret)
2968 goto err_of_clear;
2969
2970 /* init ports */
2971 for (i = 0; i < common->port_num; i++)
2972 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]);
2973
2974 dev_set_drvdata(dev, common);
2975
2976 common->is_emac_mode = true;
2977
2978 ret = am65_cpsw_nuss_init_ndevs(common);
2979 if (ret)
2980 goto err_free_phylink;
2981
2982 ret = am65_cpsw_nuss_register_ndevs(common);
2983 if (ret)
2984 goto err_free_phylink;
2985
2986 pm_runtime_put(dev);
2987 return 0;
2988
2989 err_free_phylink:
2990 am65_cpsw_nuss_phylink_cleanup(common);
2991 am65_cpts_release(common->cpts);
2992 err_of_clear:
2993 if (common->mdio_dev)
2994 of_platform_device_destroy(common->mdio_dev, NULL);
2995 err_pm_clear:
2996 pm_runtime_put_sync(dev);
2997 pm_runtime_disable(dev);
2998 return ret;
2999 }
3000
3001 static int am65_cpsw_nuss_remove(struct platform_device *pdev)
3002 {
3003 struct device *dev = &pdev->dev;
3004 struct am65_cpsw_common *common;
3005 int ret;
3006
3007 common = dev_get_drvdata(dev);
3008
3009 ret = pm_runtime_resume_and_get(&pdev->dev);
3010 if (ret < 0)
3011 return ret;
3012
3013 am65_cpsw_unregister_devlink(common);
3014 am65_cpsw_unregister_notifiers(common);
3015
3016 /* must unregister ndevs here because DD release_driver routine calls
3017 * dma_deconfigure(dev) before devres_release_all(dev)
3018 */
3019 am65_cpsw_nuss_cleanup_ndev(common);
3020 am65_cpsw_nuss_phylink_cleanup(common);
3021 am65_cpts_release(common->cpts);
3022 am65_cpsw_disable_serdes_phy(common);
3023
3024 if (common->mdio_dev)
3025 of_platform_device_destroy(common->mdio_dev, NULL);
3026
3027 pm_runtime_put_sync(&pdev->dev);
3028 pm_runtime_disable(&pdev->dev);
3029 return 0;
3030 }
3031
3032 static int am65_cpsw_nuss_suspend(struct device *dev)
3033 {
3034 struct am65_cpsw_common *common = dev_get_drvdata(dev);
3035 struct am65_cpsw_host *host_p = am65_common_get_host(common);
3036 struct am65_cpsw_port *port;
3037 struct net_device *ndev;
3038 int i, ret;
3039
3040 cpsw_ale_dump(common->ale, common->ale_context);
3041 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
3042 for (i = 0; i < common->port_num; i++) {
3043 port = &common->ports[i];
3044 ndev = port->ndev;
3045
3046 if (!ndev)
3047 continue;
3048
3049 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
3050 netif_device_detach(ndev);
3051 if (netif_running(ndev)) {
3052 rtnl_lock();
3053 ret = am65_cpsw_nuss_ndo_slave_stop(ndev);
3054 rtnl_unlock();
3055 if (ret < 0) {
3056 netdev_err(ndev, "failed to stop: %d", ret);
3057 return ret;
3058 }
3059 }
3060 }
3061
3062 am65_cpts_suspend(common->cpts);
3063
3064 am65_cpsw_nuss_remove_rx_chns(common);
3065 am65_cpsw_nuss_remove_tx_chns(common);
3066
3067 return 0;
3068 }
3069
3070 static int am65_cpsw_nuss_resume(struct device *dev)
3071 {
3072 struct am65_cpsw_common *common = dev_get_drvdata(dev);
3073 struct am65_cpsw_port *port;
3074 struct net_device *ndev;
3075 int i, ret;
3076 struct am65_cpsw_host *host_p = am65_common_get_host(common);
3077
3078 ret = am65_cpsw_nuss_init_tx_chns(common);
3079 if (ret)
3080 return ret;
3081 ret = am65_cpsw_nuss_init_rx_chns(common);
3082 if (ret)
3083 return ret;
3084
3085 /* If RX IRQ was disabled before suspend, keep it disabled */
3086 if (common->rx_irq_disabled)
3087 disable_irq(common->rx_chns.irq);
3088
3089 am65_cpts_resume(common->cpts);
3090
3091 for (i = 0; i < common->port_num; i++) {
3092 port = &common->ports[i];
3093 ndev = port->ndev;
3094
3095 if (!ndev)
3096 continue;
3097
3098 if (netif_running(ndev)) {
3099 rtnl_lock();
3100 ret = am65_cpsw_nuss_ndo_slave_open(ndev);
3101 rtnl_unlock();
3102 if (ret < 0) {
3103 netdev_err(ndev, "failed to start: %d", ret);
3104 return ret;
3105 }
3106 }
3107
3108 netif_device_attach(ndev);
3109 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
3110 }
3111
3112 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
3113 cpsw_ale_restore(common->ale, common->ale_context);
3114
3115 return 0;
3116 }
3117
3118 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = {
3119 SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume)
3120 };
3121
3122 static struct platform_driver am65_cpsw_nuss_driver = {
3123 .driver = {
3124 .name = AM65_CPSW_DRV_NAME,
3125 .of_match_table = am65_cpsw_nuss_of_mtable,
3126 .pm = &am65_cpsw_nuss_dev_pm_ops,
3127 },
3128 .probe = am65_cpsw_nuss_probe,
3129 .remove = am65_cpsw_nuss_remove,
3130 };
3131
3132 module_platform_driver(am65_cpsw_nuss_driver);
3133
3134 MODULE_LICENSE("GPL v2");
3135 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>");
3136 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver");
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git