2 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
4 * Based on skelton.c by Donald Becker.
6 * This driver is a replacement of older and less maintained version.
7 * This is a header of the older version:
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: MontaVista Software, Inc.
11 * ahennessy@mvista.com
12 * Copyright (C) 2000-2001 Toshiba Corporation
13 * static const char *version =
14 * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
21 * (C) Copyright TOSHIBA CORPORATION 2004-2005
22 * All Rights Reserved.
25 #define DRV_VERSION "1.39"
26 static const char version
[] = "tc35815.c:v" DRV_VERSION
"\n";
27 #define MODNAME "tc35815"
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/types.h>
32 #include <linux/fcntl.h>
33 #include <linux/interrupt.h>
34 #include <linux/ioport.h>
36 #include <linux/if_vlan.h>
37 #include <linux/slab.h>
38 #include <linux/string.h>
39 #include <linux/spinlock.h>
40 #include <linux/errno.h>
41 #include <linux/netdevice.h>
42 #include <linux/etherdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/delay.h>
45 #include <linux/pci.h>
46 #include <linux/phy.h>
47 #include <linux/workqueue.h>
48 #include <linux/platform_device.h>
49 #include <linux/prefetch.h>
51 #include <asm/byteorder.h>
53 enum tc35815_chiptype
{
59 /* indexed by tc35815_chiptype, above */
63 { "TOSHIBA TC35815CF 10/100BaseTX" },
64 { "TOSHIBA TC35815 with Wake on LAN" },
65 { "TOSHIBA TC35815/TX4939" },
68 static const struct pci_device_id tc35815_pci_tbl
[] = {
69 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2
, PCI_DEVICE_ID_TOSHIBA_TC35815CF
), .driver_data
= TC35815CF
},
70 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2
, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU
), .driver_data
= TC35815_NWU
},
71 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2
, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939
), .driver_data
= TC35815_TX4939
},
74 MODULE_DEVICE_TABLE(pci
, tc35815_pci_tbl
);
76 /* see MODULE_PARM_DESC */
77 static struct tc35815_options
{
86 __u32 DMA_Ctl
; /* 0x00 */
94 __u32 FDA_Lim
; /* 0x20 */
101 __u32 MAC_Ctl
; /* 0x40 */
109 __u32 CAM_Adr
; /* 0x60 */
122 /* DMA_Ctl bit assign ------------------------------------------------------- */
123 #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
124 #define DMA_RxAlign_1 0x00400000
125 #define DMA_RxAlign_2 0x00800000
126 #define DMA_RxAlign_3 0x00c00000
127 #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
128 #define DMA_IntMask 0x00040000 /* 1:Interrupt mask */
129 #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
130 #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
131 #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
132 #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
133 #define DMA_TestMode 0x00002000 /* 1:Test Mode */
134 #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
135 #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
137 /* RxFragSize bit assign ---------------------------------------------------- */
138 #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
139 #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
141 /* MAC_Ctl bit assign ------------------------------------------------------- */
142 #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
143 #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
144 #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
145 #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
146 #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
147 #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
148 #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
149 #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
150 #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
151 #define MAC_Reset 0x00000004 /* 1:Software Reset */
152 #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
153 #define MAC_HaltReq 0x00000001 /* 1:Halt request */
155 /* PROM_Ctl bit assign ------------------------------------------------------ */
156 #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
157 #define PROM_Read 0x00004000 /*10:Read operation */
158 #define PROM_Write 0x00002000 /*01:Write operation */
159 #define PROM_Erase 0x00006000 /*11:Erase operation */
160 /*00:Enable or Disable Writting, */
161 /* as specified in PROM_Addr. */
162 #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
165 /* CAM_Ctl bit assign ------------------------------------------------------- */
166 #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
167 #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
169 #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
170 #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
171 #define CAM_StationAcc 0x00000001 /* 1:unicast accept */
173 /* CAM_Ena bit assign ------------------------------------------------------- */
174 #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
175 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
176 #define CAM_Ena_Bit(index) (1 << (index))
177 #define CAM_ENTRY_DESTINATION 0
178 #define CAM_ENTRY_SOURCE 1
179 #define CAM_ENTRY_MACCTL 20
181 /* Tx_Ctl bit assign -------------------------------------------------------- */
182 #define Tx_En 0x00000001 /* 1:Transmit enable */
183 #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
184 #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
185 #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
186 #define Tx_FBack 0x00000010 /* 1:Fast Back-off */
187 #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
188 #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
189 #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
190 #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
191 #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
192 #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
193 #define Tx_EnComp 0x00004000 /* 1:Enable Completion */
195 /* Tx_Stat bit assign ------------------------------------------------------- */
196 #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
197 #define Tx_ExColl 0x00000010 /* Excessive Collision */
198 #define Tx_TXDefer 0x00000020 /* Transmit Defered */
199 #define Tx_Paused 0x00000040 /* Transmit Paused */
200 #define Tx_IntTx 0x00000080 /* Interrupt on Tx */
201 #define Tx_Under 0x00000100 /* Underrun */
202 #define Tx_Defer 0x00000200 /* Deferral */
203 #define Tx_NCarr 0x00000400 /* No Carrier */
204 #define Tx_10Stat 0x00000800 /* 10Mbps Status */
205 #define Tx_LateColl 0x00001000 /* Late Collision */
206 #define Tx_TxPar 0x00002000 /* Tx Parity Error */
207 #define Tx_Comp 0x00004000 /* Completion */
208 #define Tx_Halted 0x00008000 /* Tx Halted */
209 #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
211 /* Rx_Ctl bit assign -------------------------------------------------------- */
212 #define Rx_EnGood 0x00004000 /* 1:Enable Good */
213 #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
214 #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
215 #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
216 #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
217 #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
218 #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
219 #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
220 #define Rx_ShortEn 0x00000008 /* 1:Short Enable */
221 #define Rx_LongEn 0x00000004 /* 1:Long Enable */
222 #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
223 #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
225 /* Rx_Stat bit assign ------------------------------------------------------- */
226 #define Rx_Halted 0x00008000 /* Rx Halted */
227 #define Rx_Good 0x00004000 /* Rx Good */
228 #define Rx_RxPar 0x00002000 /* Rx Parity Error */
229 #define Rx_TypePkt 0x00001000 /* Rx Type Packet */
230 #define Rx_LongErr 0x00000800 /* Rx Long Error */
231 #define Rx_Over 0x00000400 /* Rx Overflow */
232 #define Rx_CRCErr 0x00000200 /* Rx CRC Error */
233 #define Rx_Align 0x00000100 /* Rx Alignment Error */
234 #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
235 #define Rx_IntRx 0x00000040 /* Rx Interrupt */
236 #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
237 #define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */
239 #define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */
241 /* Int_En bit assign -------------------------------------------------------- */
242 #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
243 #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
244 #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
245 #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
246 #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
247 #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
248 #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
249 #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
250 #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
251 #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
252 #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
253 #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
254 /* Exhausted Enable */
256 /* Int_Src bit assign ------------------------------------------------------- */
257 #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
258 #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
259 #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
260 #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
261 #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
262 #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
263 #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
264 #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
265 #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
266 #define Int_SWInt 0x00000020 /* 1:Software request & Clear */
267 #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
268 #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
269 #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
270 #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
271 #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
273 /* MD_CA bit assign --------------------------------------------------------- */
274 #define MD_CA_PreSup 0x00001000 /* 1:Preamble Suppress */
275 #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
276 #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
283 /* Frame descriptor */
285 volatile __u32 FDNext
;
286 volatile __u32 FDSystem
;
287 volatile __u32 FDStat
;
288 volatile __u32 FDCtl
;
291 /* Buffer descriptor */
293 volatile __u32 BuffData
;
294 volatile __u32 BDCtl
;
299 /* Frame Descriptor bit assign ---------------------------------------------- */
300 #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
301 #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
302 #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
303 #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
304 #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
305 #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
306 #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
307 #define FD_FrmOpt_Packing 0x04000000 /* Rx only */
308 #define FD_CownsFD 0x80000000 /* FD Controller owner bit */
309 #define FD_Next_EOL 0x00000001 /* FD EOL indicator */
310 #define FD_BDCnt_SHIFT 16
312 /* Buffer Descriptor bit assign --------------------------------------------- */
313 #define BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */
314 #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
315 #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
316 #define BD_CownsBD 0x80000000 /* BD Controller owner bit */
317 #define BD_RxBDID_SHIFT 16
318 #define BD_RxBDSeqN_SHIFT 24
321 /* Some useful constants. */
323 #define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \
324 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
325 Tx_En) /* maybe 0x7b01 */
326 /* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */
327 #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
328 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
329 #define INT_EN_CMD (Int_NRAbtEn | \
330 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
331 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
333 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
334 #define DMA_CTL_CMD DMA_BURST_SIZE
335 #define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
337 /* Tuning parameters */
338 #define DMA_BURST_SIZE 32
339 #define TX_THRESHOLD 1024
340 /* used threshold with packet max byte for low pci transfer ability.*/
341 #define TX_THRESHOLD_MAX 1536
342 /* setting threshold max value when overrun error occurred this count. */
343 #define TX_THRESHOLD_KEEP_LIMIT 10
345 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
346 #define FD_PAGE_NUM 4
347 #define RX_BUF_NUM 128 /* < 256 */
348 #define RX_FD_NUM 256 /* >= 32 */
349 #define TX_FD_NUM 128
350 #if RX_CTL_CMD & Rx_LongEn
351 #define RX_BUF_SIZE PAGE_SIZE
352 #elif RX_CTL_CMD & Rx_StripCRC
353 #define RX_BUF_SIZE \
354 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
356 #define RX_BUF_SIZE \
357 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
359 #define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
360 #define NAPI_WEIGHT 16
370 struct BDesc bd
[]; /* variable length */
375 struct BDesc bd
[RX_BUF_NUM
];
379 #define tc_readl(addr) ioread32(addr)
380 #define tc_writel(d, addr) iowrite32(d, addr)
382 #define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
384 /* Information that need to be kept for each controller. */
385 struct tc35815_local
{
386 struct pci_dev
*pci_dev
;
388 struct net_device
*dev
;
389 struct napi_struct napi
;
399 /* Tx control lock. This protects the transmit buffer ring
400 * state along with the "tx full" state of the driver. This
401 * means all netif_queue flow control actions are protected
402 * by this lock as well.
407 struct mii_bus
*mii_bus
;
411 struct work_struct restart_work
;
414 * Transmitting: Batch Mode.
416 * Receiving: Non-Packing Mode.
417 * 1 circular FD for Free Buffer List.
418 * RX_BUF_NUM BD in Free Buffer FD.
419 * One Free Buffer BD has ETH_FRAME_LEN data buffer.
421 void *fd_buf
; /* for TxFD, RxFD, FrFD */
422 dma_addr_t fd_buf_dma
;
423 struct TxFD
*tfd_base
;
424 unsigned int tfd_start
;
425 unsigned int tfd_end
;
426 struct RxFD
*rfd_base
;
427 struct RxFD
*rfd_limit
;
428 struct RxFD
*rfd_cur
;
429 struct FrFD
*fbl_ptr
;
430 unsigned int fbl_count
;
434 } tx_skbs
[TX_FD_NUM
], rx_skbs
[RX_BUF_NUM
];
436 enum tc35815_chiptype chiptype
;
439 static inline dma_addr_t
fd_virt_to_bus(struct tc35815_local
*lp
, void *virt
)
441 return lp
->fd_buf_dma
+ ((u8
*)virt
- (u8
*)lp
->fd_buf
);
444 static inline void *fd_bus_to_virt(struct tc35815_local
*lp
, dma_addr_t bus
)
446 return (void *)((u8
*)lp
->fd_buf
+ (bus
- lp
->fd_buf_dma
));
449 static struct sk_buff
*alloc_rxbuf_skb(struct net_device
*dev
,
450 struct pci_dev
*hwdev
,
451 dma_addr_t
*dma_handle
)
454 skb
= netdev_alloc_skb(dev
, RX_BUF_SIZE
);
457 *dma_handle
= pci_map_single(hwdev
, skb
->data
, RX_BUF_SIZE
,
459 if (pci_dma_mapping_error(hwdev
, *dma_handle
)) {
460 dev_kfree_skb_any(skb
);
463 skb_reserve(skb
, 2); /* make IP header 4byte aligned */
467 static void free_rxbuf_skb(struct pci_dev
*hwdev
, struct sk_buff
*skb
, dma_addr_t dma_handle
)
469 pci_unmap_single(hwdev
, dma_handle
, RX_BUF_SIZE
,
471 dev_kfree_skb_any(skb
);
474 /* Index to functions, as function prototypes. */
476 static int tc35815_open(struct net_device
*dev
);
477 static netdev_tx_t
tc35815_send_packet(struct sk_buff
*skb
,
478 struct net_device
*dev
);
479 static irqreturn_t
tc35815_interrupt(int irq
, void *dev_id
);
480 static int tc35815_rx(struct net_device
*dev
, int limit
);
481 static int tc35815_poll(struct napi_struct
*napi
, int budget
);
482 static void tc35815_txdone(struct net_device
*dev
);
483 static int tc35815_close(struct net_device
*dev
);
484 static struct net_device_stats
*tc35815_get_stats(struct net_device
*dev
);
485 static void tc35815_set_multicast_list(struct net_device
*dev
);
486 static void tc35815_tx_timeout(struct net_device
*dev
, unsigned int txqueue
);
487 #ifdef CONFIG_NET_POLL_CONTROLLER
488 static void tc35815_poll_controller(struct net_device
*dev
);
490 static const struct ethtool_ops tc35815_ethtool_ops
;
492 /* Example routines you must write ;->. */
493 static void tc35815_chip_reset(struct net_device
*dev
);
494 static void tc35815_chip_init(struct net_device
*dev
);
497 static void panic_queues(struct net_device
*dev
);
500 static void tc35815_restart_work(struct work_struct
*work
);
502 static int tc_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
504 struct net_device
*dev
= bus
->priv
;
505 struct tc35815_regs __iomem
*tr
=
506 (struct tc35815_regs __iomem
*)dev
->base_addr
;
507 unsigned long timeout
= jiffies
+ HZ
;
509 tc_writel(MD_CA_Busy
| (mii_id
<< 5) | (regnum
& 0x1f), &tr
->MD_CA
);
510 udelay(12); /* it takes 32 x 400ns at least */
511 while (tc_readl(&tr
->MD_CA
) & MD_CA_Busy
) {
512 if (time_after(jiffies
, timeout
))
516 return tc_readl(&tr
->MD_Data
) & 0xffff;
519 static int tc_mdio_write(struct mii_bus
*bus
, int mii_id
, int regnum
, u16 val
)
521 struct net_device
*dev
= bus
->priv
;
522 struct tc35815_regs __iomem
*tr
=
523 (struct tc35815_regs __iomem
*)dev
->base_addr
;
524 unsigned long timeout
= jiffies
+ HZ
;
526 tc_writel(val
, &tr
->MD_Data
);
527 tc_writel(MD_CA_Busy
| MD_CA_Wr
| (mii_id
<< 5) | (regnum
& 0x1f),
529 udelay(12); /* it takes 32 x 400ns at least */
530 while (tc_readl(&tr
->MD_CA
) & MD_CA_Busy
) {
531 if (time_after(jiffies
, timeout
))
538 static void tc_handle_link_change(struct net_device
*dev
)
540 struct tc35815_local
*lp
= netdev_priv(dev
);
541 struct phy_device
*phydev
= dev
->phydev
;
543 int status_change
= 0;
545 spin_lock_irqsave(&lp
->lock
, flags
);
547 (lp
->speed
!= phydev
->speed
|| lp
->duplex
!= phydev
->duplex
)) {
548 struct tc35815_regs __iomem
*tr
=
549 (struct tc35815_regs __iomem
*)dev
->base_addr
;
552 reg
= tc_readl(&tr
->MAC_Ctl
);
554 tc_writel(reg
, &tr
->MAC_Ctl
);
555 if (phydev
->duplex
== DUPLEX_FULL
)
559 tc_writel(reg
, &tr
->MAC_Ctl
);
561 tc_writel(reg
, &tr
->MAC_Ctl
);
564 * TX4939 PCFG.SPEEDn bit will be changed on
565 * NETDEV_CHANGE event.
568 * WORKAROUND: enable LostCrS only if half duplex
570 * (TX4939 does not have EnLCarr)
572 if (phydev
->duplex
== DUPLEX_HALF
&&
573 lp
->chiptype
!= TC35815_TX4939
)
574 tc_writel(tc_readl(&tr
->Tx_Ctl
) | Tx_EnLCarr
,
577 lp
->speed
= phydev
->speed
;
578 lp
->duplex
= phydev
->duplex
;
582 if (phydev
->link
!= lp
->link
) {
584 /* delayed promiscuous enabling */
585 if (dev
->flags
& IFF_PROMISC
)
586 tc35815_set_multicast_list(dev
);
591 lp
->link
= phydev
->link
;
595 spin_unlock_irqrestore(&lp
->lock
, flags
);
597 if (status_change
&& netif_msg_link(lp
)) {
598 phy_print_status(phydev
);
599 pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
601 phy_read(phydev
, MII_BMCR
),
602 phy_read(phydev
, MII_BMSR
),
603 phy_read(phydev
, MII_LPA
));
607 static int tc_mii_probe(struct net_device
*dev
)
609 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
610 struct tc35815_local
*lp
= netdev_priv(dev
);
611 struct phy_device
*phydev
;
613 phydev
= phy_find_first(lp
->mii_bus
);
615 printk(KERN_ERR
"%s: no PHY found\n", dev
->name
);
619 /* attach the mac to the phy */
620 phydev
= phy_connect(dev
, phydev_name(phydev
),
621 &tc_handle_link_change
,
622 lp
->chiptype
== TC35815_TX4939
? PHY_INTERFACE_MODE_RMII
: PHY_INTERFACE_MODE_MII
);
623 if (IS_ERR(phydev
)) {
624 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
625 return PTR_ERR(phydev
);
628 phy_attached_info(phydev
);
630 /* mask with MAC supported features */
631 phy_set_max_speed(phydev
, SPEED_100
);
632 if (options
.speed
== 10) {
633 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT
, mask
);
634 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT
, mask
);
635 } else if (options
.speed
== 100) {
636 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT
, mask
);
637 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT
, mask
);
639 if (options
.duplex
== 1) {
640 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT
, mask
);
641 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT
, mask
);
642 } else if (options
.duplex
== 2) {
643 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT
, mask
);
644 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT
, mask
);
646 linkmode_andnot(phydev
->supported
, phydev
->supported
, mask
);
647 linkmode_copy(phydev
->advertising
, phydev
->supported
);
656 static int tc_mii_init(struct net_device
*dev
)
658 struct tc35815_local
*lp
= netdev_priv(dev
);
661 lp
->mii_bus
= mdiobus_alloc();
662 if (lp
->mii_bus
== NULL
) {
667 lp
->mii_bus
->name
= "tc35815_mii_bus";
668 lp
->mii_bus
->read
= tc_mdio_read
;
669 lp
->mii_bus
->write
= tc_mdio_write
;
670 snprintf(lp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%x",
671 (lp
->pci_dev
->bus
->number
<< 8) | lp
->pci_dev
->devfn
);
672 lp
->mii_bus
->priv
= dev
;
673 lp
->mii_bus
->parent
= &lp
->pci_dev
->dev
;
674 err
= mdiobus_register(lp
->mii_bus
);
676 goto err_out_free_mii_bus
;
677 err
= tc_mii_probe(dev
);
679 goto err_out_unregister_bus
;
682 err_out_unregister_bus
:
683 mdiobus_unregister(lp
->mii_bus
);
684 err_out_free_mii_bus
:
685 mdiobus_free(lp
->mii_bus
);
690 #ifdef CONFIG_CPU_TX49XX
692 * Find a platform_device providing a MAC address. The platform code
693 * should provide a "tc35815-mac" device with a MAC address in its
696 static int tc35815_mac_match(struct device
*dev
, const void *data
)
698 struct platform_device
*plat_dev
= to_platform_device(dev
);
699 const struct pci_dev
*pci_dev
= data
;
700 unsigned int id
= pci_dev
->irq
;
701 return !strcmp(plat_dev
->name
, "tc35815-mac") && plat_dev
->id
== id
;
704 static int tc35815_read_plat_dev_addr(struct net_device
*dev
)
706 struct tc35815_local
*lp
= netdev_priv(dev
);
707 struct device
*pd
= bus_find_device(&platform_bus_type
, NULL
,
708 lp
->pci_dev
, tc35815_mac_match
);
710 if (pd
->platform_data
)
711 memcpy(dev
->dev_addr
, pd
->platform_data
, ETH_ALEN
);
713 return is_valid_ether_addr(dev
->dev_addr
) ? 0 : -ENODEV
;
718 static int tc35815_read_plat_dev_addr(struct net_device
*dev
)
724 static int tc35815_init_dev_addr(struct net_device
*dev
)
726 struct tc35815_regs __iomem
*tr
=
727 (struct tc35815_regs __iomem
*)dev
->base_addr
;
730 while (tc_readl(&tr
->PROM_Ctl
) & PROM_Busy
)
732 for (i
= 0; i
< 6; i
+= 2) {
734 tc_writel(PROM_Busy
| PROM_Read
| (i
/ 2 + 2), &tr
->PROM_Ctl
);
735 while (tc_readl(&tr
->PROM_Ctl
) & PROM_Busy
)
737 data
= tc_readl(&tr
->PROM_Data
);
738 dev
->dev_addr
[i
] = data
& 0xff;
739 dev
->dev_addr
[i
+1] = data
>> 8;
741 if (!is_valid_ether_addr(dev
->dev_addr
))
742 return tc35815_read_plat_dev_addr(dev
);
746 static const struct net_device_ops tc35815_netdev_ops
= {
747 .ndo_open
= tc35815_open
,
748 .ndo_stop
= tc35815_close
,
749 .ndo_start_xmit
= tc35815_send_packet
,
750 .ndo_get_stats
= tc35815_get_stats
,
751 .ndo_set_rx_mode
= tc35815_set_multicast_list
,
752 .ndo_tx_timeout
= tc35815_tx_timeout
,
753 .ndo_do_ioctl
= phy_do_ioctl_running
,
754 .ndo_validate_addr
= eth_validate_addr
,
755 .ndo_set_mac_address
= eth_mac_addr
,
756 #ifdef CONFIG_NET_POLL_CONTROLLER
757 .ndo_poll_controller
= tc35815_poll_controller
,
761 static int tc35815_init_one(struct pci_dev
*pdev
,
762 const struct pci_device_id
*ent
)
764 void __iomem
*ioaddr
= NULL
;
765 struct net_device
*dev
;
766 struct tc35815_local
*lp
;
769 static int printed_version
;
770 if (!printed_version
++) {
772 dev_printk(KERN_DEBUG
, &pdev
->dev
,
773 "speed:%d duplex:%d\n",
774 options
.speed
, options
.duplex
);
778 dev_warn(&pdev
->dev
, "no IRQ assigned.\n");
782 /* dev zeroed in alloc_etherdev */
783 dev
= alloc_etherdev(sizeof(*lp
));
787 SET_NETDEV_DEV(dev
, &pdev
->dev
);
788 lp
= netdev_priv(dev
);
791 /* enable device (incl. PCI PM wakeup), and bus-mastering */
792 rc
= pcim_enable_device(pdev
);
795 rc
= pcim_iomap_regions(pdev
, 1 << 1, MODNAME
);
798 pci_set_master(pdev
);
799 ioaddr
= pcim_iomap_table(pdev
)[1];
801 /* Initialize the device structure. */
802 dev
->netdev_ops
= &tc35815_netdev_ops
;
803 dev
->ethtool_ops
= &tc35815_ethtool_ops
;
804 dev
->watchdog_timeo
= TC35815_TX_TIMEOUT
;
805 netif_napi_add(dev
, &lp
->napi
, tc35815_poll
, NAPI_WEIGHT
);
807 dev
->irq
= pdev
->irq
;
808 dev
->base_addr
= (unsigned long)ioaddr
;
810 INIT_WORK(&lp
->restart_work
, tc35815_restart_work
);
811 spin_lock_init(&lp
->lock
);
812 spin_lock_init(&lp
->rx_lock
);
814 lp
->chiptype
= ent
->driver_data
;
816 lp
->msg_enable
= NETIF_MSG_TX_ERR
| NETIF_MSG_HW
| NETIF_MSG_DRV
| NETIF_MSG_LINK
;
817 pci_set_drvdata(pdev
, dev
);
819 /* Soft reset the chip. */
820 tc35815_chip_reset(dev
);
822 /* Retrieve the ethernet address. */
823 if (tc35815_init_dev_addr(dev
)) {
824 dev_warn(&pdev
->dev
, "not valid ether addr\n");
825 eth_hw_addr_random(dev
);
828 rc
= register_netdev(dev
);
832 printk(KERN_INFO
"%s: %s at 0x%lx, %pM, IRQ %d\n",
834 chip_info
[ent
->driver_data
].name
,
839 rc
= tc_mii_init(dev
);
841 goto err_out_unregister
;
846 unregister_netdev(dev
);
853 static void tc35815_remove_one(struct pci_dev
*pdev
)
855 struct net_device
*dev
= pci_get_drvdata(pdev
);
856 struct tc35815_local
*lp
= netdev_priv(dev
);
858 phy_disconnect(dev
->phydev
);
859 mdiobus_unregister(lp
->mii_bus
);
860 mdiobus_free(lp
->mii_bus
);
861 unregister_netdev(dev
);
866 tc35815_init_queues(struct net_device
*dev
)
868 struct tc35815_local
*lp
= netdev_priv(dev
);
870 unsigned long fd_addr
;
873 BUG_ON(sizeof(struct FDesc
) +
874 sizeof(struct BDesc
) * RX_BUF_NUM
+
875 sizeof(struct FDesc
) * RX_FD_NUM
+
876 sizeof(struct TxFD
) * TX_FD_NUM
>
877 PAGE_SIZE
* FD_PAGE_NUM
);
879 lp
->fd_buf
= pci_alloc_consistent(lp
->pci_dev
,
880 PAGE_SIZE
* FD_PAGE_NUM
,
884 for (i
= 0; i
< RX_BUF_NUM
; i
++) {
886 alloc_rxbuf_skb(dev
, lp
->pci_dev
,
887 &lp
->rx_skbs
[i
].skb_dma
);
888 if (!lp
->rx_skbs
[i
].skb
) {
890 free_rxbuf_skb(lp
->pci_dev
,
892 lp
->rx_skbs
[i
].skb_dma
);
893 lp
->rx_skbs
[i
].skb
= NULL
;
895 pci_free_consistent(lp
->pci_dev
,
896 PAGE_SIZE
* FD_PAGE_NUM
,
903 printk(KERN_DEBUG
"%s: FD buf %p DataBuf",
904 dev
->name
, lp
->fd_buf
);
907 for (i
= 0; i
< FD_PAGE_NUM
; i
++)
908 clear_page((void *)((unsigned long)lp
->fd_buf
+
911 fd_addr
= (unsigned long)lp
->fd_buf
;
913 /* Free Descriptors (for Receive) */
914 lp
->rfd_base
= (struct RxFD
*)fd_addr
;
915 fd_addr
+= sizeof(struct RxFD
) * RX_FD_NUM
;
916 for (i
= 0; i
< RX_FD_NUM
; i
++)
917 lp
->rfd_base
[i
].fd
.FDCtl
= cpu_to_le32(FD_CownsFD
);
918 lp
->rfd_cur
= lp
->rfd_base
;
919 lp
->rfd_limit
= (struct RxFD
*)fd_addr
- (RX_FD_RESERVE
+ 1);
921 /* Transmit Descriptors */
922 lp
->tfd_base
= (struct TxFD
*)fd_addr
;
923 fd_addr
+= sizeof(struct TxFD
) * TX_FD_NUM
;
924 for (i
= 0; i
< TX_FD_NUM
; i
++) {
925 lp
->tfd_base
[i
].fd
.FDNext
= cpu_to_le32(fd_virt_to_bus(lp
, &lp
->tfd_base
[i
+1]));
926 lp
->tfd_base
[i
].fd
.FDSystem
= cpu_to_le32(0xffffffff);
927 lp
->tfd_base
[i
].fd
.FDCtl
= cpu_to_le32(0);
929 lp
->tfd_base
[TX_FD_NUM
-1].fd
.FDNext
= cpu_to_le32(fd_virt_to_bus(lp
, &lp
->tfd_base
[0]));
933 /* Buffer List (for Receive) */
934 lp
->fbl_ptr
= (struct FrFD
*)fd_addr
;
935 lp
->fbl_ptr
->fd
.FDNext
= cpu_to_le32(fd_virt_to_bus(lp
, lp
->fbl_ptr
));
936 lp
->fbl_ptr
->fd
.FDCtl
= cpu_to_le32(RX_BUF_NUM
| FD_CownsFD
);
938 * move all allocated skbs to head of rx_skbs[] array.
939 * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
940 * tc35815_rx() had failed.
943 for (i
= 0; i
< RX_BUF_NUM
; i
++) {
944 if (lp
->rx_skbs
[i
].skb
) {
945 if (i
!= lp
->fbl_count
) {
946 lp
->rx_skbs
[lp
->fbl_count
].skb
=
948 lp
->rx_skbs
[lp
->fbl_count
].skb_dma
=
949 lp
->rx_skbs
[i
].skb_dma
;
954 for (i
= 0; i
< RX_BUF_NUM
; i
++) {
955 if (i
>= lp
->fbl_count
) {
956 lp
->fbl_ptr
->bd
[i
].BuffData
= 0;
957 lp
->fbl_ptr
->bd
[i
].BDCtl
= 0;
960 lp
->fbl_ptr
->bd
[i
].BuffData
=
961 cpu_to_le32(lp
->rx_skbs
[i
].skb_dma
);
962 /* BDID is index of FrFD.bd[] */
963 lp
->fbl_ptr
->bd
[i
].BDCtl
=
964 cpu_to_le32(BD_CownsBD
| (i
<< BD_RxBDID_SHIFT
) |
968 printk(KERN_DEBUG
"%s: TxFD %p RxFD %p FrFD %p\n",
969 dev
->name
, lp
->tfd_base
, lp
->rfd_base
, lp
->fbl_ptr
);
974 tc35815_clear_queues(struct net_device
*dev
)
976 struct tc35815_local
*lp
= netdev_priv(dev
);
979 for (i
= 0; i
< TX_FD_NUM
; i
++) {
980 u32 fdsystem
= le32_to_cpu(lp
->tfd_base
[i
].fd
.FDSystem
);
981 struct sk_buff
*skb
=
982 fdsystem
!= 0xffffffff ?
983 lp
->tx_skbs
[fdsystem
].skb
: NULL
;
985 if (lp
->tx_skbs
[i
].skb
!= skb
) {
986 printk("%s: tx_skbs mismatch(%d).\n", dev
->name
, i
);
990 BUG_ON(lp
->tx_skbs
[i
].skb
!= skb
);
993 pci_unmap_single(lp
->pci_dev
, lp
->tx_skbs
[i
].skb_dma
, skb
->len
, PCI_DMA_TODEVICE
);
994 lp
->tx_skbs
[i
].skb
= NULL
;
995 lp
->tx_skbs
[i
].skb_dma
= 0;
996 dev_kfree_skb_any(skb
);
998 lp
->tfd_base
[i
].fd
.FDSystem
= cpu_to_le32(0xffffffff);
1001 tc35815_init_queues(dev
);
1005 tc35815_free_queues(struct net_device
*dev
)
1007 struct tc35815_local
*lp
= netdev_priv(dev
);
1011 for (i
= 0; i
< TX_FD_NUM
; i
++) {
1012 u32 fdsystem
= le32_to_cpu(lp
->tfd_base
[i
].fd
.FDSystem
);
1013 struct sk_buff
*skb
=
1014 fdsystem
!= 0xffffffff ?
1015 lp
->tx_skbs
[fdsystem
].skb
: NULL
;
1017 if (lp
->tx_skbs
[i
].skb
!= skb
) {
1018 printk("%s: tx_skbs mismatch(%d).\n", dev
->name
, i
);
1022 BUG_ON(lp
->tx_skbs
[i
].skb
!= skb
);
1025 pci_unmap_single(lp
->pci_dev
, lp
->tx_skbs
[i
].skb_dma
, skb
->len
, PCI_DMA_TODEVICE
);
1027 lp
->tx_skbs
[i
].skb
= NULL
;
1028 lp
->tx_skbs
[i
].skb_dma
= 0;
1030 lp
->tfd_base
[i
].fd
.FDSystem
= cpu_to_le32(0xffffffff);
1034 lp
->rfd_base
= NULL
;
1035 lp
->rfd_limit
= NULL
;
1039 for (i
= 0; i
< RX_BUF_NUM
; i
++) {
1040 if (lp
->rx_skbs
[i
].skb
) {
1041 free_rxbuf_skb(lp
->pci_dev
, lp
->rx_skbs
[i
].skb
,
1042 lp
->rx_skbs
[i
].skb_dma
);
1043 lp
->rx_skbs
[i
].skb
= NULL
;
1047 pci_free_consistent(lp
->pci_dev
, PAGE_SIZE
* FD_PAGE_NUM
,
1048 lp
->fd_buf
, lp
->fd_buf_dma
);
1054 dump_txfd(struct TxFD
*fd
)
1056 printk("TxFD(%p): %08x %08x %08x %08x\n", fd
,
1057 le32_to_cpu(fd
->fd
.FDNext
),
1058 le32_to_cpu(fd
->fd
.FDSystem
),
1059 le32_to_cpu(fd
->fd
.FDStat
),
1060 le32_to_cpu(fd
->fd
.FDCtl
));
1062 printk(" %08x %08x",
1063 le32_to_cpu(fd
->bd
.BuffData
),
1064 le32_to_cpu(fd
->bd
.BDCtl
));
1069 dump_rxfd(struct RxFD
*fd
)
1071 int i
, bd_count
= (le32_to_cpu(fd
->fd
.FDCtl
) & FD_BDCnt_MASK
) >> FD_BDCnt_SHIFT
;
1074 printk("RxFD(%p): %08x %08x %08x %08x\n", fd
,
1075 le32_to_cpu(fd
->fd
.FDNext
),
1076 le32_to_cpu(fd
->fd
.FDSystem
),
1077 le32_to_cpu(fd
->fd
.FDStat
),
1078 le32_to_cpu(fd
->fd
.FDCtl
));
1079 if (le32_to_cpu(fd
->fd
.FDCtl
) & FD_CownsFD
)
1082 for (i
= 0; i
< bd_count
; i
++)
1083 printk(" %08x %08x",
1084 le32_to_cpu(fd
->bd
[i
].BuffData
),
1085 le32_to_cpu(fd
->bd
[i
].BDCtl
));
1092 dump_frfd(struct FrFD
*fd
)
1095 printk("FrFD(%p): %08x %08x %08x %08x\n", fd
,
1096 le32_to_cpu(fd
->fd
.FDNext
),
1097 le32_to_cpu(fd
->fd
.FDSystem
),
1098 le32_to_cpu(fd
->fd
.FDStat
),
1099 le32_to_cpu(fd
->fd
.FDCtl
));
1101 for (i
= 0; i
< RX_BUF_NUM
; i
++)
1102 printk(" %08x %08x",
1103 le32_to_cpu(fd
->bd
[i
].BuffData
),
1104 le32_to_cpu(fd
->bd
[i
].BDCtl
));
1109 panic_queues(struct net_device
*dev
)
1111 struct tc35815_local
*lp
= netdev_priv(dev
);
1114 printk("TxFD base %p, start %u, end %u\n",
1115 lp
->tfd_base
, lp
->tfd_start
, lp
->tfd_end
);
1116 printk("RxFD base %p limit %p cur %p\n",
1117 lp
->rfd_base
, lp
->rfd_limit
, lp
->rfd_cur
);
1118 printk("FrFD %p\n", lp
->fbl_ptr
);
1119 for (i
= 0; i
< TX_FD_NUM
; i
++)
1120 dump_txfd(&lp
->tfd_base
[i
]);
1121 for (i
= 0; i
< RX_FD_NUM
; i
++) {
1122 int bd_count
= dump_rxfd(&lp
->rfd_base
[i
]);
1123 i
+= (bd_count
+ 1) / 2; /* skip BDs */
1125 dump_frfd(lp
->fbl_ptr
);
1126 panic("%s: Illegal queue state.", dev
->name
);
1130 static void print_eth(const u8
*add
)
1132 printk(KERN_DEBUG
"print_eth(%p)\n", add
);
1133 printk(KERN_DEBUG
" %pM => %pM : %02x%02x\n",
1134 add
+ 6, add
, add
[12], add
[13]);
1137 static int tc35815_tx_full(struct net_device
*dev
)
1139 struct tc35815_local
*lp
= netdev_priv(dev
);
1140 return (lp
->tfd_start
+ 1) % TX_FD_NUM
== lp
->tfd_end
;
1143 static void tc35815_restart(struct net_device
*dev
)
1145 struct tc35815_local
*lp
= netdev_priv(dev
);
1149 ret
= phy_init_hw(dev
->phydev
);
1151 printk(KERN_ERR
"%s: PHY init failed.\n", dev
->name
);
1154 spin_lock_bh(&lp
->rx_lock
);
1155 spin_lock_irq(&lp
->lock
);
1156 tc35815_chip_reset(dev
);
1157 tc35815_clear_queues(dev
);
1158 tc35815_chip_init(dev
);
1159 /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1160 tc35815_set_multicast_list(dev
);
1161 spin_unlock_irq(&lp
->lock
);
1162 spin_unlock_bh(&lp
->rx_lock
);
1164 netif_wake_queue(dev
);
1167 static void tc35815_restart_work(struct work_struct
*work
)
1169 struct tc35815_local
*lp
=
1170 container_of(work
, struct tc35815_local
, restart_work
);
1171 struct net_device
*dev
= lp
->dev
;
1173 tc35815_restart(dev
);
1176 static void tc35815_schedule_restart(struct net_device
*dev
)
1178 struct tc35815_local
*lp
= netdev_priv(dev
);
1179 struct tc35815_regs __iomem
*tr
=
1180 (struct tc35815_regs __iomem
*)dev
->base_addr
;
1181 unsigned long flags
;
1183 /* disable interrupts */
1184 spin_lock_irqsave(&lp
->lock
, flags
);
1185 tc_writel(0, &tr
->Int_En
);
1186 tc_writel(tc_readl(&tr
->DMA_Ctl
) | DMA_IntMask
, &tr
->DMA_Ctl
);
1187 schedule_work(&lp
->restart_work
);
1188 spin_unlock_irqrestore(&lp
->lock
, flags
);
1191 static void tc35815_tx_timeout(struct net_device
*dev
, unsigned int txqueue
)
1193 struct tc35815_regs __iomem
*tr
=
1194 (struct tc35815_regs __iomem
*)dev
->base_addr
;
1196 printk(KERN_WARNING
"%s: transmit timed out, status %#x\n",
1197 dev
->name
, tc_readl(&tr
->Tx_Stat
));
1199 /* Try to restart the adaptor. */
1200 tc35815_schedule_restart(dev
);
1201 dev
->stats
.tx_errors
++;
1205 * Open/initialize the controller. This is called (in the current kernel)
1206 * sometime after booting when the 'ifconfig' program is run.
1208 * This routine should set everything up anew at each open, even
1209 * registers that "should" only need to be set once at boot, so that
1210 * there is non-reboot way to recover if something goes wrong.
1213 tc35815_open(struct net_device
*dev
)
1215 struct tc35815_local
*lp
= netdev_priv(dev
);
1218 * This is used if the interrupt line can turned off (shared).
1219 * See 3c503.c for an example of selecting the IRQ at config-time.
1221 if (request_irq(dev
->irq
, tc35815_interrupt
, IRQF_SHARED
,
1225 tc35815_chip_reset(dev
);
1227 if (tc35815_init_queues(dev
) != 0) {
1228 free_irq(dev
->irq
, dev
);
1232 napi_enable(&lp
->napi
);
1234 /* Reset the hardware here. Don't forget to set the station address. */
1235 spin_lock_irq(&lp
->lock
);
1236 tc35815_chip_init(dev
);
1237 spin_unlock_irq(&lp
->lock
);
1239 netif_carrier_off(dev
);
1240 /* schedule a link state check */
1241 phy_start(dev
->phydev
);
1243 /* We are now ready to accept transmit requeusts from
1244 * the queueing layer of the networking.
1246 netif_start_queue(dev
);
1251 /* This will only be invoked if your driver is _not_ in XOFF state.
1252 * What this means is that you need not check it, and that this
1253 * invariant will hold if you make sure that the netif_*_queue()
1254 * calls are done at the proper times.
1257 tc35815_send_packet(struct sk_buff
*skb
, struct net_device
*dev
)
1259 struct tc35815_local
*lp
= netdev_priv(dev
);
1261 unsigned long flags
;
1263 /* If some error occurs while trying to transmit this
1264 * packet, you should return '1' from this function.
1265 * In such a case you _may not_ do anything to the
1266 * SKB, it is still owned by the network queueing
1267 * layer when an error is returned. This means you
1268 * may not modify any SKB fields, you may not free
1272 /* This is the most common case for modern hardware.
1273 * The spinlock protects this code from the TX complete
1274 * hardware interrupt handler. Queue flow control is
1275 * thus managed under this lock as well.
1277 spin_lock_irqsave(&lp
->lock
, flags
);
1279 /* failsafe... (handle txdone now if half of FDs are used) */
1280 if ((lp
->tfd_start
+ TX_FD_NUM
- lp
->tfd_end
) % TX_FD_NUM
>
1282 tc35815_txdone(dev
);
1284 if (netif_msg_pktdata(lp
))
1285 print_eth(skb
->data
);
1287 if (lp
->tx_skbs
[lp
->tfd_start
].skb
) {
1288 printk("%s: tx_skbs conflict.\n", dev
->name
);
1292 BUG_ON(lp
->tx_skbs
[lp
->tfd_start
].skb
);
1294 lp
->tx_skbs
[lp
->tfd_start
].skb
= skb
;
1295 lp
->tx_skbs
[lp
->tfd_start
].skb_dma
= pci_map_single(lp
->pci_dev
, skb
->data
, skb
->len
, PCI_DMA_TODEVICE
);
1298 txfd
= &lp
->tfd_base
[lp
->tfd_start
];
1299 txfd
->bd
.BuffData
= cpu_to_le32(lp
->tx_skbs
[lp
->tfd_start
].skb_dma
);
1300 txfd
->bd
.BDCtl
= cpu_to_le32(skb
->len
);
1301 txfd
->fd
.FDSystem
= cpu_to_le32(lp
->tfd_start
);
1302 txfd
->fd
.FDCtl
= cpu_to_le32(FD_CownsFD
| (1 << FD_BDCnt_SHIFT
));
1304 if (lp
->tfd_start
== lp
->tfd_end
) {
1305 struct tc35815_regs __iomem
*tr
=
1306 (struct tc35815_regs __iomem
*)dev
->base_addr
;
1307 /* Start DMA Transmitter. */
1308 txfd
->fd
.FDNext
|= cpu_to_le32(FD_Next_EOL
);
1309 txfd
->fd
.FDCtl
|= cpu_to_le32(FD_FrmOpt_IntTx
);
1310 if (netif_msg_tx_queued(lp
)) {
1311 printk("%s: starting TxFD.\n", dev
->name
);
1314 tc_writel(fd_virt_to_bus(lp
, txfd
), &tr
->TxFrmPtr
);
1316 txfd
->fd
.FDNext
&= cpu_to_le32(~FD_Next_EOL
);
1317 if (netif_msg_tx_queued(lp
)) {
1318 printk("%s: queueing TxFD.\n", dev
->name
);
1322 lp
->tfd_start
= (lp
->tfd_start
+ 1) % TX_FD_NUM
;
1324 /* If we just used up the very last entry in the
1325 * TX ring on this device, tell the queueing
1326 * layer to send no more.
1328 if (tc35815_tx_full(dev
)) {
1329 if (netif_msg_tx_queued(lp
))
1330 printk(KERN_WARNING
"%s: TxFD Exhausted.\n", dev
->name
);
1331 netif_stop_queue(dev
);
1334 /* When the TX completion hw interrupt arrives, this
1335 * is when the transmit statistics are updated.
1338 spin_unlock_irqrestore(&lp
->lock
, flags
);
1339 return NETDEV_TX_OK
;
1342 #define FATAL_ERROR_INT \
1343 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1344 static void tc35815_fatal_error_interrupt(struct net_device
*dev
, u32 status
)
1347 printk(KERN_WARNING
"%s: Fatal Error Interrupt (%#x):",
1349 if (status
& Int_IntPCI
)
1351 if (status
& Int_DmParErr
)
1352 printk(" DmParErr");
1353 if (status
& Int_IntNRAbt
)
1354 printk(" IntNRAbt");
1357 panic("%s: Too many fatal errors.", dev
->name
);
1358 printk(KERN_WARNING
"%s: Resetting ...\n", dev
->name
);
1359 /* Try to restart the adaptor. */
1360 tc35815_schedule_restart(dev
);
1363 static int tc35815_do_interrupt(struct net_device
*dev
, u32 status
, int limit
)
1365 struct tc35815_local
*lp
= netdev_priv(dev
);
1368 /* Fatal errors... */
1369 if (status
& FATAL_ERROR_INT
) {
1370 tc35815_fatal_error_interrupt(dev
, status
);
1373 /* recoverable errors */
1374 if (status
& Int_IntFDAEx
) {
1375 if (netif_msg_rx_err(lp
))
1377 "Free Descriptor Area Exhausted (%#x).\n",
1379 dev
->stats
.rx_dropped
++;
1382 if (status
& Int_IntBLEx
) {
1383 if (netif_msg_rx_err(lp
))
1385 "Buffer List Exhausted (%#x).\n",
1387 dev
->stats
.rx_dropped
++;
1390 if (status
& Int_IntExBD
) {
1391 if (netif_msg_rx_err(lp
))
1393 "Excessive Buffer Descriptors (%#x).\n",
1395 dev
->stats
.rx_length_errors
++;
1399 /* normal notification */
1400 if (status
& Int_IntMacRx
) {
1401 /* Got a packet(s). */
1402 ret
= tc35815_rx(dev
, limit
);
1403 lp
->lstats
.rx_ints
++;
1405 if (status
& Int_IntMacTx
) {
1406 /* Transmit complete. */
1407 lp
->lstats
.tx_ints
++;
1408 spin_lock_irq(&lp
->lock
);
1409 tc35815_txdone(dev
);
1410 spin_unlock_irq(&lp
->lock
);
1418 * The typical workload of the driver:
1419 * Handle the network interface interrupts.
1421 static irqreturn_t
tc35815_interrupt(int irq
, void *dev_id
)
1423 struct net_device
*dev
= dev_id
;
1424 struct tc35815_local
*lp
= netdev_priv(dev
);
1425 struct tc35815_regs __iomem
*tr
=
1426 (struct tc35815_regs __iomem
*)dev
->base_addr
;
1427 u32 dmactl
= tc_readl(&tr
->DMA_Ctl
);
1429 if (!(dmactl
& DMA_IntMask
)) {
1430 /* disable interrupts */
1431 tc_writel(dmactl
| DMA_IntMask
, &tr
->DMA_Ctl
);
1432 if (napi_schedule_prep(&lp
->napi
))
1433 __napi_schedule(&lp
->napi
);
1435 printk(KERN_ERR
"%s: interrupt taken in poll\n",
1439 (void)tc_readl(&tr
->Int_Src
); /* flush */
1445 #ifdef CONFIG_NET_POLL_CONTROLLER
1446 static void tc35815_poll_controller(struct net_device
*dev
)
1448 disable_irq(dev
->irq
);
1449 tc35815_interrupt(dev
->irq
, dev
);
1450 enable_irq(dev
->irq
);
1454 /* We have a good packet(s), get it/them out of the buffers. */
1456 tc35815_rx(struct net_device
*dev
, int limit
)
1458 struct tc35815_local
*lp
= netdev_priv(dev
);
1463 while (!((fdctl
= le32_to_cpu(lp
->rfd_cur
->fd
.FDCtl
)) & FD_CownsFD
)) {
1464 int status
= le32_to_cpu(lp
->rfd_cur
->fd
.FDStat
);
1465 int pkt_len
= fdctl
& FD_FDLength_MASK
;
1466 int bd_count
= (fdctl
& FD_BDCnt_MASK
) >> FD_BDCnt_SHIFT
;
1468 struct RxFD
*next_rfd
;
1470 #if (RX_CTL_CMD & Rx_StripCRC) == 0
1471 pkt_len
-= ETH_FCS_LEN
;
1474 if (netif_msg_rx_status(lp
))
1475 dump_rxfd(lp
->rfd_cur
);
1476 if (status
& Rx_Good
) {
1477 struct sk_buff
*skb
;
1478 unsigned char *data
;
1483 BUG_ON(bd_count
> 1);
1484 cur_bd
= (le32_to_cpu(lp
->rfd_cur
->bd
[0].BDCtl
)
1485 & BD_RxBDID_MASK
) >> BD_RxBDID_SHIFT
;
1487 if (cur_bd
>= RX_BUF_NUM
) {
1488 printk("%s: invalid BDID.\n", dev
->name
);
1491 BUG_ON(lp
->rx_skbs
[cur_bd
].skb_dma
!=
1492 (le32_to_cpu(lp
->rfd_cur
->bd
[0].BuffData
) & ~3));
1493 if (!lp
->rx_skbs
[cur_bd
].skb
) {
1494 printk("%s: NULL skb.\n", dev
->name
);
1498 BUG_ON(cur_bd
>= RX_BUF_NUM
);
1500 skb
= lp
->rx_skbs
[cur_bd
].skb
;
1501 prefetch(skb
->data
);
1502 lp
->rx_skbs
[cur_bd
].skb
= NULL
;
1503 pci_unmap_single(lp
->pci_dev
,
1504 lp
->rx_skbs
[cur_bd
].skb_dma
,
1505 RX_BUF_SIZE
, PCI_DMA_FROMDEVICE
);
1506 if (!HAVE_DMA_RXALIGN(lp
) && NET_IP_ALIGN
!= 0)
1507 memmove(skb
->data
, skb
->data
- NET_IP_ALIGN
,
1509 data
= skb_put(skb
, pkt_len
);
1510 if (netif_msg_pktdata(lp
))
1512 skb
->protocol
= eth_type_trans(skb
, dev
);
1513 netif_receive_skb(skb
);
1515 dev
->stats
.rx_packets
++;
1516 dev
->stats
.rx_bytes
+= pkt_len
;
1518 dev
->stats
.rx_errors
++;
1519 if (netif_msg_rx_err(lp
))
1520 dev_info(&dev
->dev
, "Rx error (status %x)\n",
1521 status
& Rx_Stat_Mask
);
1522 /* WORKAROUND: LongErr and CRCErr means Overflow. */
1523 if ((status
& Rx_LongErr
) && (status
& Rx_CRCErr
)) {
1524 status
&= ~(Rx_LongErr
|Rx_CRCErr
);
1527 if (status
& Rx_LongErr
)
1528 dev
->stats
.rx_length_errors
++;
1529 if (status
& Rx_Over
)
1530 dev
->stats
.rx_fifo_errors
++;
1531 if (status
& Rx_CRCErr
)
1532 dev
->stats
.rx_crc_errors
++;
1533 if (status
& Rx_Align
)
1534 dev
->stats
.rx_frame_errors
++;
1538 /* put Free Buffer back to controller */
1539 int bdctl
= le32_to_cpu(lp
->rfd_cur
->bd
[bd_count
- 1].BDCtl
);
1541 (bdctl
& BD_RxBDID_MASK
) >> BD_RxBDID_SHIFT
;
1543 if (id
>= RX_BUF_NUM
) {
1544 printk("%s: invalid BDID.\n", dev
->name
);
1548 BUG_ON(id
>= RX_BUF_NUM
);
1550 /* free old buffers */
1552 while (lp
->fbl_count
< RX_BUF_NUM
)
1554 unsigned char curid
=
1555 (id
+ 1 + lp
->fbl_count
) % RX_BUF_NUM
;
1556 struct BDesc
*bd
= &lp
->fbl_ptr
->bd
[curid
];
1558 bdctl
= le32_to_cpu(bd
->BDCtl
);
1559 if (bdctl
& BD_CownsBD
) {
1560 printk("%s: Freeing invalid BD.\n",
1565 /* pass BD to controller */
1566 if (!lp
->rx_skbs
[curid
].skb
) {
1567 lp
->rx_skbs
[curid
].skb
=
1568 alloc_rxbuf_skb(dev
,
1570 &lp
->rx_skbs
[curid
].skb_dma
);
1571 if (!lp
->rx_skbs
[curid
].skb
)
1572 break; /* try on next reception */
1573 bd
->BuffData
= cpu_to_le32(lp
->rx_skbs
[curid
].skb_dma
);
1575 /* Note: BDLength was modified by chip. */
1576 bd
->BDCtl
= cpu_to_le32(BD_CownsBD
|
1577 (curid
<< BD_RxBDID_SHIFT
) |
1583 /* put RxFD back to controller */
1585 next_rfd
= fd_bus_to_virt(lp
,
1586 le32_to_cpu(lp
->rfd_cur
->fd
.FDNext
));
1587 if (next_rfd
< lp
->rfd_base
|| next_rfd
> lp
->rfd_limit
) {
1588 printk("%s: RxFD FDNext invalid.\n", dev
->name
);
1592 for (i
= 0; i
< (bd_count
+ 1) / 2 + 1; i
++) {
1593 /* pass FD to controller */
1595 lp
->rfd_cur
->fd
.FDNext
= cpu_to_le32(0xdeaddead);
1597 lp
->rfd_cur
->fd
.FDNext
= cpu_to_le32(FD_Next_EOL
);
1599 lp
->rfd_cur
->fd
.FDCtl
= cpu_to_le32(FD_CownsFD
);
1602 if (lp
->rfd_cur
> lp
->rfd_limit
)
1603 lp
->rfd_cur
= lp
->rfd_base
;
1605 if (lp
->rfd_cur
!= next_rfd
)
1606 printk("rfd_cur = %p, next_rfd %p\n",
1607 lp
->rfd_cur
, next_rfd
);
1614 static int tc35815_poll(struct napi_struct
*napi
, int budget
)
1616 struct tc35815_local
*lp
= container_of(napi
, struct tc35815_local
, napi
);
1617 struct net_device
*dev
= lp
->dev
;
1618 struct tc35815_regs __iomem
*tr
=
1619 (struct tc35815_regs __iomem
*)dev
->base_addr
;
1620 int received
= 0, handled
;
1626 spin_lock(&lp
->rx_lock
);
1627 status
= tc_readl(&tr
->Int_Src
);
1629 /* BLEx, FDAEx will be cleared later */
1630 tc_writel(status
& ~(Int_BLEx
| Int_FDAEx
),
1631 &tr
->Int_Src
); /* write to clear */
1633 handled
= tc35815_do_interrupt(dev
, status
, budget
- received
);
1634 if (status
& (Int_BLEx
| Int_FDAEx
))
1635 tc_writel(status
& (Int_BLEx
| Int_FDAEx
),
1638 received
+= handled
;
1639 if (received
>= budget
)
1642 status
= tc_readl(&tr
->Int_Src
);
1644 spin_unlock(&lp
->rx_lock
);
1646 if (received
< budget
) {
1647 napi_complete_done(napi
, received
);
1648 /* enable interrupts */
1649 tc_writel(tc_readl(&tr
->DMA_Ctl
) & ~DMA_IntMask
, &tr
->DMA_Ctl
);
1654 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1657 tc35815_check_tx_stat(struct net_device
*dev
, int status
)
1659 struct tc35815_local
*lp
= netdev_priv(dev
);
1660 const char *msg
= NULL
;
1662 /* count collisions */
1663 if (status
& Tx_ExColl
)
1664 dev
->stats
.collisions
+= 16;
1665 if (status
& Tx_TxColl_MASK
)
1666 dev
->stats
.collisions
+= status
& Tx_TxColl_MASK
;
1668 /* TX4939 does not have NCarr */
1669 if (lp
->chiptype
== TC35815_TX4939
)
1670 status
&= ~Tx_NCarr
;
1671 /* WORKAROUND: ignore LostCrS in full duplex operation */
1672 if (!lp
->link
|| lp
->duplex
== DUPLEX_FULL
)
1673 status
&= ~Tx_NCarr
;
1675 if (!(status
& TX_STA_ERR
)) {
1677 dev
->stats
.tx_packets
++;
1681 dev
->stats
.tx_errors
++;
1682 if (status
& Tx_ExColl
) {
1683 dev
->stats
.tx_aborted_errors
++;
1684 msg
= "Excessive Collision.";
1686 if (status
& Tx_Under
) {
1687 dev
->stats
.tx_fifo_errors
++;
1688 msg
= "Tx FIFO Underrun.";
1689 if (lp
->lstats
.tx_underrun
< TX_THRESHOLD_KEEP_LIMIT
) {
1690 lp
->lstats
.tx_underrun
++;
1691 if (lp
->lstats
.tx_underrun
>= TX_THRESHOLD_KEEP_LIMIT
) {
1692 struct tc35815_regs __iomem
*tr
=
1693 (struct tc35815_regs __iomem
*)dev
->base_addr
;
1694 tc_writel(TX_THRESHOLD_MAX
, &tr
->TxThrsh
);
1695 msg
= "Tx FIFO Underrun.Change Tx threshold to max.";
1699 if (status
& Tx_Defer
) {
1700 dev
->stats
.tx_fifo_errors
++;
1701 msg
= "Excessive Deferral.";
1703 if (status
& Tx_NCarr
) {
1704 dev
->stats
.tx_carrier_errors
++;
1705 msg
= "Lost Carrier Sense.";
1707 if (status
& Tx_LateColl
) {
1708 dev
->stats
.tx_aborted_errors
++;
1709 msg
= "Late Collision.";
1711 if (status
& Tx_TxPar
) {
1712 dev
->stats
.tx_fifo_errors
++;
1713 msg
= "Transmit Parity Error.";
1715 if (status
& Tx_SQErr
) {
1716 dev
->stats
.tx_heartbeat_errors
++;
1717 msg
= "Signal Quality Error.";
1719 if (msg
&& netif_msg_tx_err(lp
))
1720 printk(KERN_WARNING
"%s: %s (%#x)\n", dev
->name
, msg
, status
);
1723 /* This handles TX complete events posted by the device
1727 tc35815_txdone(struct net_device
*dev
)
1729 struct tc35815_local
*lp
= netdev_priv(dev
);
1733 txfd
= &lp
->tfd_base
[lp
->tfd_end
];
1734 while (lp
->tfd_start
!= lp
->tfd_end
&&
1735 !((fdctl
= le32_to_cpu(txfd
->fd
.FDCtl
)) & FD_CownsFD
)) {
1736 int status
= le32_to_cpu(txfd
->fd
.FDStat
);
1737 struct sk_buff
*skb
;
1738 unsigned long fdnext
= le32_to_cpu(txfd
->fd
.FDNext
);
1739 u32 fdsystem
= le32_to_cpu(txfd
->fd
.FDSystem
);
1741 if (netif_msg_tx_done(lp
)) {
1742 printk("%s: complete TxFD.\n", dev
->name
);
1745 tc35815_check_tx_stat(dev
, status
);
1747 skb
= fdsystem
!= 0xffffffff ?
1748 lp
->tx_skbs
[fdsystem
].skb
: NULL
;
1750 if (lp
->tx_skbs
[lp
->tfd_end
].skb
!= skb
) {
1751 printk("%s: tx_skbs mismatch.\n", dev
->name
);
1755 BUG_ON(lp
->tx_skbs
[lp
->tfd_end
].skb
!= skb
);
1758 dev
->stats
.tx_bytes
+= skb
->len
;
1759 pci_unmap_single(lp
->pci_dev
, lp
->tx_skbs
[lp
->tfd_end
].skb_dma
, skb
->len
, PCI_DMA_TODEVICE
);
1760 lp
->tx_skbs
[lp
->tfd_end
].skb
= NULL
;
1761 lp
->tx_skbs
[lp
->tfd_end
].skb_dma
= 0;
1762 dev_kfree_skb_any(skb
);
1764 txfd
->fd
.FDSystem
= cpu_to_le32(0xffffffff);
1766 lp
->tfd_end
= (lp
->tfd_end
+ 1) % TX_FD_NUM
;
1767 txfd
= &lp
->tfd_base
[lp
->tfd_end
];
1769 if ((fdnext
& ~FD_Next_EOL
) != fd_virt_to_bus(lp
, txfd
)) {
1770 printk("%s: TxFD FDNext invalid.\n", dev
->name
);
1774 if (fdnext
& FD_Next_EOL
) {
1775 /* DMA Transmitter has been stopping... */
1776 if (lp
->tfd_end
!= lp
->tfd_start
) {
1777 struct tc35815_regs __iomem
*tr
=
1778 (struct tc35815_regs __iomem
*)dev
->base_addr
;
1779 int head
= (lp
->tfd_start
+ TX_FD_NUM
- 1) % TX_FD_NUM
;
1780 struct TxFD
*txhead
= &lp
->tfd_base
[head
];
1781 int qlen
= (lp
->tfd_start
+ TX_FD_NUM
1782 - lp
->tfd_end
) % TX_FD_NUM
;
1785 if (!(le32_to_cpu(txfd
->fd
.FDCtl
) & FD_CownsFD
)) {
1786 printk("%s: TxFD FDCtl invalid.\n", dev
->name
);
1790 /* log max queue length */
1791 if (lp
->lstats
.max_tx_qlen
< qlen
)
1792 lp
->lstats
.max_tx_qlen
= qlen
;
1795 /* start DMA Transmitter again */
1796 txhead
->fd
.FDNext
|= cpu_to_le32(FD_Next_EOL
);
1797 txhead
->fd
.FDCtl
|= cpu_to_le32(FD_FrmOpt_IntTx
);
1798 if (netif_msg_tx_queued(lp
)) {
1799 printk("%s: start TxFD on queue.\n",
1803 tc_writel(fd_virt_to_bus(lp
, txfd
), &tr
->TxFrmPtr
);
1809 /* If we had stopped the queue due to a "tx full"
1810 * condition, and space has now been made available,
1811 * wake up the queue.
1813 if (netif_queue_stopped(dev
) && !tc35815_tx_full(dev
))
1814 netif_wake_queue(dev
);
1817 /* The inverse routine to tc35815_open(). */
1819 tc35815_close(struct net_device
*dev
)
1821 struct tc35815_local
*lp
= netdev_priv(dev
);
1823 netif_stop_queue(dev
);
1824 napi_disable(&lp
->napi
);
1826 phy_stop(dev
->phydev
);
1827 cancel_work_sync(&lp
->restart_work
);
1829 /* Flush the Tx and disable Rx here. */
1830 tc35815_chip_reset(dev
);
1831 free_irq(dev
->irq
, dev
);
1833 tc35815_free_queues(dev
);
1840 * Get the current statistics.
1841 * This may be called with the card open or closed.
1843 static struct net_device_stats
*tc35815_get_stats(struct net_device
*dev
)
1845 struct tc35815_regs __iomem
*tr
=
1846 (struct tc35815_regs __iomem
*)dev
->base_addr
;
1847 if (netif_running(dev
))
1848 /* Update the statistics from the device registers. */
1849 dev
->stats
.rx_missed_errors
+= tc_readl(&tr
->Miss_Cnt
);
1854 static void tc35815_set_cam_entry(struct net_device
*dev
, int index
, unsigned char *addr
)
1856 struct tc35815_local
*lp
= netdev_priv(dev
);
1857 struct tc35815_regs __iomem
*tr
=
1858 (struct tc35815_regs __iomem
*)dev
->base_addr
;
1859 int cam_index
= index
* 6;
1863 saved_addr
= tc_readl(&tr
->CAM_Adr
);
1865 if (netif_msg_hw(lp
))
1866 printk(KERN_DEBUG
"%s: CAM %d: %pM\n",
1867 dev
->name
, index
, addr
);
1869 /* read modify write */
1870 tc_writel(cam_index
- 2, &tr
->CAM_Adr
);
1871 cam_data
= tc_readl(&tr
->CAM_Data
) & 0xffff0000;
1872 cam_data
|= addr
[0] << 8 | addr
[1];
1873 tc_writel(cam_data
, &tr
->CAM_Data
);
1874 /* write whole word */
1875 tc_writel(cam_index
+ 2, &tr
->CAM_Adr
);
1876 cam_data
= (addr
[2] << 24) | (addr
[3] << 16) | (addr
[4] << 8) | addr
[5];
1877 tc_writel(cam_data
, &tr
->CAM_Data
);
1879 /* write whole word */
1880 tc_writel(cam_index
, &tr
->CAM_Adr
);
1881 cam_data
= (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3];
1882 tc_writel(cam_data
, &tr
->CAM_Data
);
1883 /* read modify write */
1884 tc_writel(cam_index
+ 4, &tr
->CAM_Adr
);
1885 cam_data
= tc_readl(&tr
->CAM_Data
) & 0x0000ffff;
1886 cam_data
|= addr
[4] << 24 | (addr
[5] << 16);
1887 tc_writel(cam_data
, &tr
->CAM_Data
);
1890 tc_writel(saved_addr
, &tr
->CAM_Adr
);
1895 * Set or clear the multicast filter for this adaptor.
1896 * num_addrs == -1 Promiscuous mode, receive all packets
1897 * num_addrs == 0 Normal mode, clear multicast list
1898 * num_addrs > 0 Multicast mode, receive normal and MC packets,
1899 * and do best-effort filtering.
1902 tc35815_set_multicast_list(struct net_device
*dev
)
1904 struct tc35815_regs __iomem
*tr
=
1905 (struct tc35815_regs __iomem
*)dev
->base_addr
;
1907 if (dev
->flags
& IFF_PROMISC
) {
1908 /* With some (all?) 100MHalf HUB, controller will hang
1909 * if we enabled promiscuous mode before linkup... */
1910 struct tc35815_local
*lp
= netdev_priv(dev
);
1914 /* Enable promiscuous mode */
1915 tc_writel(CAM_CompEn
| CAM_BroadAcc
| CAM_GroupAcc
| CAM_StationAcc
, &tr
->CAM_Ctl
);
1916 } else if ((dev
->flags
& IFF_ALLMULTI
) ||
1917 netdev_mc_count(dev
) > CAM_ENTRY_MAX
- 3) {
1918 /* CAM 0, 1, 20 are reserved. */
1919 /* Disable promiscuous mode, use normal mode. */
1920 tc_writel(CAM_CompEn
| CAM_BroadAcc
| CAM_GroupAcc
, &tr
->CAM_Ctl
);
1921 } else if (!netdev_mc_empty(dev
)) {
1922 struct netdev_hw_addr
*ha
;
1924 int ena_bits
= CAM_Ena_Bit(CAM_ENTRY_SOURCE
);
1926 tc_writel(0, &tr
->CAM_Ctl
);
1927 /* Walk the address list, and load the filter */
1929 netdev_for_each_mc_addr(ha
, dev
) {
1930 /* entry 0,1 is reserved. */
1931 tc35815_set_cam_entry(dev
, i
+ 2, ha
->addr
);
1932 ena_bits
|= CAM_Ena_Bit(i
+ 2);
1935 tc_writel(ena_bits
, &tr
->CAM_Ena
);
1936 tc_writel(CAM_CompEn
| CAM_BroadAcc
, &tr
->CAM_Ctl
);
1938 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE
), &tr
->CAM_Ena
);
1939 tc_writel(CAM_CompEn
| CAM_BroadAcc
, &tr
->CAM_Ctl
);
1943 static void tc35815_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1945 struct tc35815_local
*lp
= netdev_priv(dev
);
1947 strlcpy(info
->driver
, MODNAME
, sizeof(info
->driver
));
1948 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
1949 strlcpy(info
->bus_info
, pci_name(lp
->pci_dev
), sizeof(info
->bus_info
));
1952 static u32
tc35815_get_msglevel(struct net_device
*dev
)
1954 struct tc35815_local
*lp
= netdev_priv(dev
);
1955 return lp
->msg_enable
;
1958 static void tc35815_set_msglevel(struct net_device
*dev
, u32 datum
)
1960 struct tc35815_local
*lp
= netdev_priv(dev
);
1961 lp
->msg_enable
= datum
;
1964 static int tc35815_get_sset_count(struct net_device
*dev
, int sset
)
1966 struct tc35815_local
*lp
= netdev_priv(dev
);
1970 return sizeof(lp
->lstats
) / sizeof(int);
1976 static void tc35815_get_ethtool_stats(struct net_device
*dev
, struct ethtool_stats
*stats
, u64
*data
)
1978 struct tc35815_local
*lp
= netdev_priv(dev
);
1979 data
[0] = lp
->lstats
.max_tx_qlen
;
1980 data
[1] = lp
->lstats
.tx_ints
;
1981 data
[2] = lp
->lstats
.rx_ints
;
1982 data
[3] = lp
->lstats
.tx_underrun
;
1986 const char str
[ETH_GSTRING_LEN
];
1987 } ethtool_stats_keys
[] = {
1994 static void tc35815_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1996 memcpy(data
, ethtool_stats_keys
, sizeof(ethtool_stats_keys
));
1999 static const struct ethtool_ops tc35815_ethtool_ops
= {
2000 .get_drvinfo
= tc35815_get_drvinfo
,
2001 .get_link
= ethtool_op_get_link
,
2002 .get_msglevel
= tc35815_get_msglevel
,
2003 .set_msglevel
= tc35815_set_msglevel
,
2004 .get_strings
= tc35815_get_strings
,
2005 .get_sset_count
= tc35815_get_sset_count
,
2006 .get_ethtool_stats
= tc35815_get_ethtool_stats
,
2007 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
2008 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
2011 static void tc35815_chip_reset(struct net_device
*dev
)
2013 struct tc35815_regs __iomem
*tr
=
2014 (struct tc35815_regs __iomem
*)dev
->base_addr
;
2016 /* reset the controller */
2017 tc_writel(MAC_Reset
, &tr
->MAC_Ctl
);
2018 udelay(4); /* 3200ns */
2020 while (tc_readl(&tr
->MAC_Ctl
) & MAC_Reset
) {
2022 printk(KERN_ERR
"%s: MAC reset failed.\n", dev
->name
);
2027 tc_writel(0, &tr
->MAC_Ctl
);
2029 /* initialize registers to default value */
2030 tc_writel(0, &tr
->DMA_Ctl
);
2031 tc_writel(0, &tr
->TxThrsh
);
2032 tc_writel(0, &tr
->TxPollCtr
);
2033 tc_writel(0, &tr
->RxFragSize
);
2034 tc_writel(0, &tr
->Int_En
);
2035 tc_writel(0, &tr
->FDA_Bas
);
2036 tc_writel(0, &tr
->FDA_Lim
);
2037 tc_writel(0xffffffff, &tr
->Int_Src
); /* Write 1 to clear */
2038 tc_writel(0, &tr
->CAM_Ctl
);
2039 tc_writel(0, &tr
->Tx_Ctl
);
2040 tc_writel(0, &tr
->Rx_Ctl
);
2041 tc_writel(0, &tr
->CAM_Ena
);
2042 (void)tc_readl(&tr
->Miss_Cnt
); /* Read to clear */
2044 /* initialize internal SRAM */
2045 tc_writel(DMA_TestMode
, &tr
->DMA_Ctl
);
2046 for (i
= 0; i
< 0x1000; i
+= 4) {
2047 tc_writel(i
, &tr
->CAM_Adr
);
2048 tc_writel(0, &tr
->CAM_Data
);
2050 tc_writel(0, &tr
->DMA_Ctl
);
2053 static void tc35815_chip_init(struct net_device
*dev
)
2055 struct tc35815_local
*lp
= netdev_priv(dev
);
2056 struct tc35815_regs __iomem
*tr
=
2057 (struct tc35815_regs __iomem
*)dev
->base_addr
;
2058 unsigned long txctl
= TX_CTL_CMD
;
2060 /* load station address to CAM */
2061 tc35815_set_cam_entry(dev
, CAM_ENTRY_SOURCE
, dev
->dev_addr
);
2063 /* Enable CAM (broadcast and unicast) */
2064 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE
), &tr
->CAM_Ena
);
2065 tc_writel(CAM_CompEn
| CAM_BroadAcc
, &tr
->CAM_Ctl
);
2067 /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2068 if (HAVE_DMA_RXALIGN(lp
))
2069 tc_writel(DMA_BURST_SIZE
| DMA_RxAlign_2
, &tr
->DMA_Ctl
);
2071 tc_writel(DMA_BURST_SIZE
, &tr
->DMA_Ctl
);
2072 tc_writel(0, &tr
->TxPollCtr
); /* Batch mode */
2073 tc_writel(TX_THRESHOLD
, &tr
->TxThrsh
);
2074 tc_writel(INT_EN_CMD
, &tr
->Int_En
);
2077 tc_writel(fd_virt_to_bus(lp
, lp
->rfd_base
), &tr
->FDA_Bas
);
2078 tc_writel((unsigned long)lp
->rfd_limit
- (unsigned long)lp
->rfd_base
,
2081 * Activation method:
2082 * First, enable the MAC Transmitter and the DMA Receive circuits.
2083 * Then enable the DMA Transmitter and the MAC Receive circuits.
2085 tc_writel(fd_virt_to_bus(lp
, lp
->fbl_ptr
), &tr
->BLFrmPtr
); /* start DMA receiver */
2086 tc_writel(RX_CTL_CMD
, &tr
->Rx_Ctl
); /* start MAC receiver */
2088 /* start MAC transmitter */
2089 /* TX4939 does not have EnLCarr */
2090 if (lp
->chiptype
== TC35815_TX4939
)
2091 txctl
&= ~Tx_EnLCarr
;
2092 /* WORKAROUND: ignore LostCrS in full duplex operation */
2093 if (!dev
->phydev
|| !lp
->link
|| lp
->duplex
== DUPLEX_FULL
)
2094 txctl
&= ~Tx_EnLCarr
;
2095 tc_writel(txctl
, &tr
->Tx_Ctl
);
2099 static int tc35815_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2101 struct net_device
*dev
= pci_get_drvdata(pdev
);
2102 struct tc35815_local
*lp
= netdev_priv(dev
);
2103 unsigned long flags
;
2105 pci_save_state(pdev
);
2106 if (!netif_running(dev
))
2108 netif_device_detach(dev
);
2110 phy_stop(dev
->phydev
);
2111 spin_lock_irqsave(&lp
->lock
, flags
);
2112 tc35815_chip_reset(dev
);
2113 spin_unlock_irqrestore(&lp
->lock
, flags
);
2114 pci_set_power_state(pdev
, PCI_D3hot
);
2118 static int tc35815_resume(struct pci_dev
*pdev
)
2120 struct net_device
*dev
= pci_get_drvdata(pdev
);
2122 pci_restore_state(pdev
);
2123 if (!netif_running(dev
))
2125 pci_set_power_state(pdev
, PCI_D0
);
2126 tc35815_restart(dev
);
2127 netif_carrier_off(dev
);
2129 phy_start(dev
->phydev
);
2130 netif_device_attach(dev
);
2133 #endif /* CONFIG_PM */
2135 static struct pci_driver tc35815_pci_driver
= {
2137 .id_table
= tc35815_pci_tbl
,
2138 .probe
= tc35815_init_one
,
2139 .remove
= tc35815_remove_one
,
2141 .suspend
= tc35815_suspend
,
2142 .resume
= tc35815_resume
,
2146 module_param_named(speed
, options
.speed
, int, 0);
2147 MODULE_PARM_DESC(speed
, "0:auto, 10:10Mbps, 100:100Mbps");
2148 module_param_named(duplex
, options
.duplex
, int, 0);
2149 MODULE_PARM_DESC(duplex
, "0:auto, 1:half, 2:full");
2151 module_pci_driver(tc35815_pci_driver
);
2152 MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2153 MODULE_LICENSE("GPL");