]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/net/ethoc.c
2 * Opencore 10/100 ethernet mac driver
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 * Thierry Reding <thierry.reding@avionic-design.de>
7 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
8 * Copyright (C) 2016 Cadence Design Systems Inc.
10 * SPDX-License-Identifier: GPL-2.0
15 #include <dm/platform_data/net_ethoc.h>
20 #include <asm/cache.h>
23 /* register offsets */
25 #define INT_SOURCE 0x04
30 #define PACKETLEN 0x18
32 #define TX_BD_NUM 0x20
33 #define CTRLMODER 0x24
35 #define MIICOMMAND 0x2c
36 #define MIIADDRESS 0x30
37 #define MIITX_DATA 0x34
38 #define MIIRX_DATA 0x38
39 #define MIISTATUS 0x3c
40 #define MAC_ADDR0 0x40
41 #define MAC_ADDR1 0x44
42 #define ETH_HASH0 0x48
43 #define ETH_HASH1 0x4c
44 #define ETH_TXCTRL 0x50
47 #define MODER_RXEN (1 << 0) /* receive enable */
48 #define MODER_TXEN (1 << 1) /* transmit enable */
49 #define MODER_NOPRE (1 << 2) /* no preamble */
50 #define MODER_BRO (1 << 3) /* broadcast address */
51 #define MODER_IAM (1 << 4) /* individual address mode */
52 #define MODER_PRO (1 << 5) /* promiscuous mode */
53 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
54 #define MODER_LOOP (1 << 7) /* loopback */
55 #define MODER_NBO (1 << 8) /* no back-off */
56 #define MODER_EDE (1 << 9) /* excess defer enable */
57 #define MODER_FULLD (1 << 10) /* full duplex */
58 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
59 #define MODER_DCRC (1 << 12) /* delayed CRC enable */
60 #define MODER_CRC (1 << 13) /* CRC enable */
61 #define MODER_HUGE (1 << 14) /* huge packets enable */
62 #define MODER_PAD (1 << 15) /* padding enabled */
63 #define MODER_RSM (1 << 16) /* receive small packets */
65 /* interrupt source and mask registers */
66 #define INT_MASK_TXF (1 << 0) /* transmit frame */
67 #define INT_MASK_TXE (1 << 1) /* transmit error */
68 #define INT_MASK_RXF (1 << 2) /* receive frame */
69 #define INT_MASK_RXE (1 << 3) /* receive error */
70 #define INT_MASK_BUSY (1 << 4)
71 #define INT_MASK_TXC (1 << 5) /* transmit control frame */
72 #define INT_MASK_RXC (1 << 6) /* receive control frame */
74 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
75 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
77 #define INT_MASK_ALL ( \
78 INT_MASK_TXF | INT_MASK_TXE | \
79 INT_MASK_RXF | INT_MASK_RXE | \
80 INT_MASK_TXC | INT_MASK_RXC | \
84 /* packet length register */
85 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
86 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
87 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
90 /* transmit buffer number register */
91 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
93 /* control module mode register */
94 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
95 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
96 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
98 /* MII mode register */
99 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
100 #define MIIMODER_NOPRE (1 << 8) /* no preamble */
102 /* MII command register */
103 #define MIICOMMAND_SCAN (1 << 0) /* scan status */
104 #define MIICOMMAND_READ (1 << 1) /* read status */
105 #define MIICOMMAND_WRITE (1 << 2) /* write control data */
107 /* MII address register */
108 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
109 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
110 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
111 MIIADDRESS_RGAD(reg))
113 /* MII transmit data register */
114 #define MIITX_DATA_VAL(x) ((x) & 0xffff)
116 /* MII receive data register */
117 #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
119 /* MII status register */
120 #define MIISTATUS_LINKFAIL (1 << 0)
121 #define MIISTATUS_BUSY (1 << 1)
122 #define MIISTATUS_INVALID (1 << 2)
124 /* TX buffer descriptor */
125 #define TX_BD_CS (1 << 0) /* carrier sense lost */
126 #define TX_BD_DF (1 << 1) /* defer indication */
127 #define TX_BD_LC (1 << 2) /* late collision */
128 #define TX_BD_RL (1 << 3) /* retransmission limit */
129 #define TX_BD_RETRY_MASK (0x00f0)
130 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
131 #define TX_BD_UR (1 << 8) /* transmitter underrun */
132 #define TX_BD_CRC (1 << 11) /* TX CRC enable */
133 #define TX_BD_PAD (1 << 12) /* pad enable */
134 #define TX_BD_WRAP (1 << 13)
135 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
136 #define TX_BD_READY (1 << 15) /* TX buffer ready */
137 #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
138 #define TX_BD_LEN_MASK (0xffff << 16)
140 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
141 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
143 /* RX buffer descriptor */
144 #define RX_BD_LC (1 << 0) /* late collision */
145 #define RX_BD_CRC (1 << 1) /* RX CRC error */
146 #define RX_BD_SF (1 << 2) /* short frame */
147 #define RX_BD_TL (1 << 3) /* too long */
148 #define RX_BD_DN (1 << 4) /* dribble nibble */
149 #define RX_BD_IS (1 << 5) /* invalid symbol */
150 #define RX_BD_OR (1 << 6) /* receiver overrun */
151 #define RX_BD_MISS (1 << 7)
152 #define RX_BD_CF (1 << 8) /* control frame */
153 #define RX_BD_WRAP (1 << 13)
154 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
155 #define RX_BD_EMPTY (1 << 15)
156 #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
158 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
159 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
161 #define ETHOC_BUFSIZ 1536
162 #define ETHOC_ZLEN 64
163 #define ETHOC_BD_BASE 0x400
164 #define ETHOC_TIMEOUT (HZ / 2)
165 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
166 #define ETHOC_IOSIZE 0x54
169 * struct ethoc - driver-private device structure
170 * @num_tx: number of send buffers
171 * @cur_tx: last send buffer written
172 * @dty_tx: last buffer actually sent
173 * @num_rx: number of receive buffers
174 * @cur_rx: current receive buffer
182 void __iomem
*iobase
;
183 void __iomem
*packet
;
184 phys_addr_t packet_phys
;
188 struct phy_device
*phydev
;
193 * struct ethoc_bd - buffer descriptor
194 * @stat: buffer statistics
195 * @addr: physical memory address
202 static inline u32
*ethoc_reg(struct ethoc
*priv
, size_t offset
)
204 return priv
->iobase
+ offset
;
207 static inline u32
ethoc_read(struct ethoc
*priv
, size_t offset
)
209 return readl(ethoc_reg(priv
, offset
));
212 static inline void ethoc_write(struct ethoc
*priv
, size_t offset
, u32 data
)
214 writel(data
, ethoc_reg(priv
, offset
));
217 static inline void ethoc_read_bd(struct ethoc
*priv
, int index
,
220 size_t offset
= ETHOC_BD_BASE
+ (index
* sizeof(struct ethoc_bd
));
221 bd
->stat
= ethoc_read(priv
, offset
+ 0);
222 bd
->addr
= ethoc_read(priv
, offset
+ 4);
225 static inline void ethoc_write_bd(struct ethoc
*priv
, int index
,
226 const struct ethoc_bd
*bd
)
228 size_t offset
= ETHOC_BD_BASE
+ (index
* sizeof(struct ethoc_bd
));
229 ethoc_write(priv
, offset
+ 0, bd
->stat
);
230 ethoc_write(priv
, offset
+ 4, bd
->addr
);
233 static int ethoc_write_hwaddr_common(struct ethoc
*priv
, u8
*mac
)
235 ethoc_write(priv
, MAC_ADDR0
, (mac
[2] << 24) | (mac
[3] << 16) |
236 (mac
[4] << 8) | (mac
[5] << 0));
237 ethoc_write(priv
, MAC_ADDR1
, (mac
[0] << 8) | (mac
[1] << 0));
241 static inline void ethoc_ack_irq(struct ethoc
*priv
, u32 mask
)
243 ethoc_write(priv
, INT_SOURCE
, mask
);
246 static inline void ethoc_enable_rx_and_tx(struct ethoc
*priv
)
248 u32 mode
= ethoc_read(priv
, MODER
);
249 mode
|= MODER_RXEN
| MODER_TXEN
;
250 ethoc_write(priv
, MODER
, mode
);
253 static inline void ethoc_disable_rx_and_tx(struct ethoc
*priv
)
255 u32 mode
= ethoc_read(priv
, MODER
);
256 mode
&= ~(MODER_RXEN
| MODER_TXEN
);
257 ethoc_write(priv
, MODER
, mode
);
260 static int ethoc_init_ring(struct ethoc
*priv
)
263 phys_addr_t addr
= priv
->packet_phys
;
270 /* setup transmission buffers */
271 bd
.stat
= TX_BD_IRQ
| TX_BD_CRC
;
274 for (i
= 0; i
< priv
->num_tx
; i
++) {
277 addr
+= PKTSIZE_ALIGN
;
279 if (i
== priv
->num_tx
- 1)
280 bd
.stat
|= TX_BD_WRAP
;
282 ethoc_write_bd(priv
, i
, &bd
);
285 bd
.stat
= RX_BD_EMPTY
| RX_BD_IRQ
;
287 for (i
= 0; i
< priv
->num_rx
; i
++) {
290 addr
+= PKTSIZE_ALIGN
;
292 bd
.addr
= virt_to_phys(net_rx_packets
[i
]);
294 if (i
== priv
->num_rx
- 1)
295 bd
.stat
|= RX_BD_WRAP
;
297 flush_dcache_range((ulong
)net_rx_packets
[i
],
298 (ulong
)net_rx_packets
[i
] + PKTSIZE_ALIGN
);
299 ethoc_write_bd(priv
, priv
->num_tx
+ i
, &bd
);
305 static int ethoc_reset(struct ethoc
*priv
)
309 /* TODO: reset controller? */
311 ethoc_disable_rx_and_tx(priv
);
313 /* TODO: setup registers */
315 /* enable FCS generation and automatic padding */
316 mode
= ethoc_read(priv
, MODER
);
317 mode
|= MODER_CRC
| MODER_PAD
;
318 ethoc_write(priv
, MODER
, mode
);
320 /* set full-duplex mode */
321 mode
= ethoc_read(priv
, MODER
);
323 ethoc_write(priv
, MODER
, mode
);
324 ethoc_write(priv
, IPGT
, 0x15);
326 ethoc_ack_irq(priv
, INT_MASK_ALL
);
327 ethoc_enable_rx_and_tx(priv
);
331 static int ethoc_init_common(struct ethoc
*priv
)
336 priv
->num_rx
= PKTBUFSRX
;
337 ethoc_write(priv
, TX_BD_NUM
, priv
->num_tx
);
338 ethoc_init_ring(priv
);
342 ret
= phy_startup(priv
->phydev
);
344 printf("Could not initialize PHY %s\n",
345 priv
->phydev
->dev
->name
);
352 static void ethoc_stop_common(struct ethoc
*priv
)
354 ethoc_disable_rx_and_tx(priv
);
356 phy_shutdown(priv
->phydev
);
360 static int ethoc_update_rx_stats(struct ethoc_bd
*bd
)
364 if (bd
->stat
& RX_BD_TL
) {
365 debug("ETHOC: " "RX: frame too long\n");
369 if (bd
->stat
& RX_BD_SF
) {
370 debug("ETHOC: " "RX: frame too short\n");
374 if (bd
->stat
& RX_BD_DN
)
375 debug("ETHOC: " "RX: dribble nibble\n");
377 if (bd
->stat
& RX_BD_CRC
) {
378 debug("ETHOC: " "RX: wrong CRC\n");
382 if (bd
->stat
& RX_BD_OR
) {
383 debug("ETHOC: " "RX: overrun\n");
387 if (bd
->stat
& RX_BD_LC
) {
388 debug("ETHOC: " "RX: late collision\n");
395 static int ethoc_rx_common(struct ethoc
*priv
, uchar
**packetp
)
398 u32 i
= priv
->cur_rx
% priv
->num_rx
;
399 u32 entry
= priv
->num_tx
+ i
;
401 ethoc_read_bd(priv
, entry
, &bd
);
402 if (bd
.stat
& RX_BD_EMPTY
)
405 debug("%s(): RX buffer %d, %x received\n",
406 __func__
, priv
->cur_rx
, bd
.stat
);
407 if (ethoc_update_rx_stats(&bd
) == 0) {
408 int size
= bd
.stat
>> 16;
410 size
-= 4; /* strip the CRC */
412 *packetp
= priv
->packet
+ entry
* PKTSIZE_ALIGN
;
414 *packetp
= net_rx_packets
[i
];
421 static int ethoc_is_new_packet_received(struct ethoc
*priv
)
425 pending
= ethoc_read(priv
, INT_SOURCE
);
426 ethoc_ack_irq(priv
, pending
);
427 if (pending
& INT_MASK_BUSY
)
428 debug("%s(): packet dropped\n", __func__
);
429 if (pending
& INT_MASK_RX
) {
430 debug("%s(): rx irq\n", __func__
);
437 static int ethoc_update_tx_stats(struct ethoc_bd
*bd
)
439 if (bd
->stat
& TX_BD_LC
)
440 debug("ETHOC: " "TX: late collision\n");
442 if (bd
->stat
& TX_BD_RL
)
443 debug("ETHOC: " "TX: retransmit limit\n");
445 if (bd
->stat
& TX_BD_UR
)
446 debug("ETHOC: " "TX: underrun\n");
448 if (bd
->stat
& TX_BD_CS
)
449 debug("ETHOC: " "TX: carrier sense lost\n");
454 static void ethoc_tx(struct ethoc
*priv
)
456 u32 entry
= priv
->dty_tx
% priv
->num_tx
;
459 ethoc_read_bd(priv
, entry
, &bd
);
460 if ((bd
.stat
& TX_BD_READY
) == 0)
461 (void)ethoc_update_tx_stats(&bd
);
464 static int ethoc_send_common(struct ethoc
*priv
, void *packet
, int length
)
471 entry
= priv
->cur_tx
% priv
->num_tx
;
472 ethoc_read_bd(priv
, entry
, &bd
);
473 if (unlikely(length
< ETHOC_ZLEN
))
474 bd
.stat
|= TX_BD_PAD
;
476 bd
.stat
&= ~TX_BD_PAD
;
479 void *p
= priv
->packet
+ entry
* PKTSIZE_ALIGN
;
481 memcpy(p
, packet
, length
);
484 bd
.addr
= virt_to_phys(packet
);
486 flush_dcache_range((ulong
)packet
, (ulong
)packet
+ length
);
487 bd
.stat
&= ~(TX_BD_STATS
| TX_BD_LEN_MASK
);
488 bd
.stat
|= TX_BD_LEN(length
);
489 ethoc_write_bd(priv
, entry
, &bd
);
492 bd
.stat
|= TX_BD_READY
;
493 ethoc_write_bd(priv
, entry
, &bd
);
495 /* wait for transfer to succeed */
496 tmo
= get_timer(0) + 5 * CONFIG_SYS_HZ
;
498 pending
= ethoc_read(priv
, INT_SOURCE
);
499 ethoc_ack_irq(priv
, pending
& ~INT_MASK_RX
);
500 if (pending
& INT_MASK_BUSY
)
501 debug("%s(): packet dropped\n", __func__
);
503 if (pending
& INT_MASK_TX
) {
507 if (get_timer(0) >= tmo
) {
508 debug("%s(): timed out\n", __func__
);
513 debug("%s(): packet sent\n", __func__
);
517 static int ethoc_free_pkt_common(struct ethoc
*priv
)
520 u32 i
= priv
->cur_rx
% priv
->num_rx
;
521 u32 entry
= priv
->num_tx
+ i
;
524 ethoc_read_bd(priv
, entry
, &bd
);
527 src
= priv
->packet
+ entry
* PKTSIZE_ALIGN
;
529 src
= net_rx_packets
[i
];
530 /* clear the buffer descriptor so it can be reused */
531 flush_dcache_range((ulong
)src
,
532 (ulong
)src
+ PKTSIZE_ALIGN
);
533 bd
.stat
&= ~RX_BD_STATS
;
534 bd
.stat
|= RX_BD_EMPTY
;
535 ethoc_write_bd(priv
, entry
, &bd
);
543 static int ethoc_mdio_read(struct mii_dev
*bus
, int addr
, int devad
, int reg
)
545 struct ethoc
*priv
= bus
->priv
;
548 ethoc_write(priv
, MIIADDRESS
, MIIADDRESS_ADDR(addr
, reg
));
549 ethoc_write(priv
, MIICOMMAND
, MIICOMMAND_READ
);
551 rc
= wait_for_bit_le32(ethoc_reg(priv
, MIISTATUS
),
552 MIISTATUS_BUSY
, false, CONFIG_SYS_HZ
, false);
555 u32 data
= ethoc_read(priv
, MIIRX_DATA
);
557 /* reset MII command register */
558 ethoc_write(priv
, MIICOMMAND
, 0);
564 static int ethoc_mdio_write(struct mii_dev
*bus
, int addr
, int devad
, int reg
,
567 struct ethoc
*priv
= bus
->priv
;
570 ethoc_write(priv
, MIIADDRESS
, MIIADDRESS_ADDR(addr
, reg
));
571 ethoc_write(priv
, MIITX_DATA
, val
);
572 ethoc_write(priv
, MIICOMMAND
, MIICOMMAND_WRITE
);
574 rc
= wait_for_bit_le32(ethoc_reg(priv
, MIISTATUS
),
575 MIISTATUS_BUSY
, false, CONFIG_SYS_HZ
, false);
578 /* reset MII command register */
579 ethoc_write(priv
, MIICOMMAND
, 0);
584 static int ethoc_mdio_init(const char *name
, struct ethoc
*priv
)
586 struct mii_dev
*bus
= mdio_alloc();
590 printf("Failed to allocate MDIO bus\n");
594 bus
->read
= ethoc_mdio_read
;
595 bus
->write
= ethoc_mdio_write
;
596 snprintf(bus
->name
, sizeof(bus
->name
), "%s", name
);
599 ret
= mdio_register(bus
);
603 priv
->bus
= miiphy_get_dev_by_name(name
);
607 static int ethoc_phy_init(struct ethoc
*priv
, void *dev
)
609 struct phy_device
*phydev
;
610 int mask
= 0xffffffff;
612 #ifdef CONFIG_PHY_ADDR
613 mask
= 1 << CONFIG_PHY_ADDR
;
616 phydev
= phy_find_by_mask(priv
->bus
, mask
, PHY_INTERFACE_MODE_MII
);
620 phy_connect_dev(phydev
, dev
);
622 phydev
->supported
&= PHY_BASIC_FEATURES
;
623 phydev
->advertising
= phydev
->supported
;
625 priv
->phydev
= phydev
;
633 static inline int ethoc_mdio_init(const char *name
, struct ethoc
*priv
)
638 static inline int ethoc_phy_init(struct ethoc
*priv
, void *dev
)
647 static int ethoc_write_hwaddr(struct udevice
*dev
)
649 struct ethoc_eth_pdata
*pdata
= dev_get_platdata(dev
);
650 struct ethoc
*priv
= dev_get_priv(dev
);
651 u8
*mac
= pdata
->eth_pdata
.enetaddr
;
653 return ethoc_write_hwaddr_common(priv
, mac
);
656 static int ethoc_send(struct udevice
*dev
, void *packet
, int length
)
658 return ethoc_send_common(dev_get_priv(dev
), packet
, length
);
661 static int ethoc_free_pkt(struct udevice
*dev
, uchar
*packet
, int length
)
663 return ethoc_free_pkt_common(dev_get_priv(dev
));
666 static int ethoc_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
668 struct ethoc
*priv
= dev_get_priv(dev
);
670 if (flags
& ETH_RECV_CHECK_DEVICE
)
671 if (!ethoc_is_new_packet_received(priv
))
674 return ethoc_rx_common(priv
, packetp
);
677 static int ethoc_start(struct udevice
*dev
)
679 return ethoc_init_common(dev_get_priv(dev
));
682 static void ethoc_stop(struct udevice
*dev
)
684 ethoc_stop_common(dev_get_priv(dev
));
687 static int ethoc_ofdata_to_platdata(struct udevice
*dev
)
689 struct ethoc_eth_pdata
*pdata
= dev_get_platdata(dev
);
692 pdata
->eth_pdata
.iobase
= devfdt_get_addr(dev
);
693 addr
= devfdt_get_addr_index(dev
, 1);
694 if (addr
!= FDT_ADDR_T_NONE
)
695 pdata
->packet_base
= addr
;
699 static int ethoc_probe(struct udevice
*dev
)
701 struct ethoc_eth_pdata
*pdata
= dev_get_platdata(dev
);
702 struct ethoc
*priv
= dev_get_priv(dev
);
704 priv
->iobase
= ioremap(pdata
->eth_pdata
.iobase
, ETHOC_IOSIZE
);
705 if (pdata
->packet_base
) {
706 priv
->packet_phys
= pdata
->packet_base
;
707 priv
->packet
= ioremap(pdata
->packet_base
,
708 (1 + PKTBUFSRX
) * PKTSIZE_ALIGN
);
711 ethoc_mdio_init(dev
->name
, priv
);
712 ethoc_phy_init(priv
, dev
);
717 static int ethoc_remove(struct udevice
*dev
)
719 struct ethoc
*priv
= dev_get_priv(dev
);
723 mdio_unregister(priv
->bus
);
724 mdio_free(priv
->bus
);
726 iounmap(priv
->iobase
);
730 static const struct eth_ops ethoc_ops
= {
731 .start
= ethoc_start
,
735 .free_pkt
= ethoc_free_pkt
,
736 .write_hwaddr
= ethoc_write_hwaddr
,
739 static const struct udevice_id ethoc_ids
[] = {
740 { .compatible
= "opencores,ethoc" },
744 U_BOOT_DRIVER(ethoc
) = {
747 .of_match
= ethoc_ids
,
748 .ofdata_to_platdata
= ethoc_ofdata_to_platdata
,
749 .probe
= ethoc_probe
,
750 .remove
= ethoc_remove
,
752 .priv_auto_alloc_size
= sizeof(struct ethoc
),
753 .platdata_auto_alloc_size
= sizeof(struct ethoc_eth_pdata
),
758 static int ethoc_init(struct eth_device
*dev
, bd_t
*bd
)
760 struct ethoc
*priv
= (struct ethoc
*)dev
->priv
;
762 return ethoc_init_common(priv
);
765 static int ethoc_write_hwaddr(struct eth_device
*dev
)
767 struct ethoc
*priv
= (struct ethoc
*)dev
->priv
;
768 u8
*mac
= dev
->enetaddr
;
770 return ethoc_write_hwaddr_common(priv
, mac
);
773 static int ethoc_send(struct eth_device
*dev
, void *packet
, int length
)
775 return ethoc_send_common(dev
->priv
, packet
, length
);
778 static void ethoc_halt(struct eth_device
*dev
)
780 ethoc_disable_rx_and_tx(dev
->priv
);
783 static int ethoc_recv(struct eth_device
*dev
)
785 struct ethoc
*priv
= (struct ethoc
*)dev
->priv
;
788 if (!ethoc_is_new_packet_received(priv
))
791 for (count
= 0; count
< PKTBUFSRX
; ++count
) {
793 int size
= ethoc_rx_common(priv
, &packetp
);
798 net_process_received_packet(packetp
, size
);
799 ethoc_free_pkt_common(priv
);
804 int ethoc_initialize(u8 dev_num
, int base_addr
)
807 struct eth_device
*dev
;
809 priv
= malloc(sizeof(*priv
));
812 dev
= malloc(sizeof(*dev
));
818 memset(dev
, 0, sizeof(*dev
));
820 dev
->iobase
= base_addr
;
821 dev
->init
= ethoc_init
;
822 dev
->halt
= ethoc_halt
;
823 dev
->send
= ethoc_send
;
824 dev
->recv
= ethoc_recv
;
825 dev
->write_hwaddr
= ethoc_write_hwaddr
;
826 sprintf(dev
->name
, "%s-%hu", "ETHOC", dev_num
);
827 priv
->iobase
= ioremap(dev
->iobase
, ETHOC_IOSIZE
);
831 ethoc_mdio_init(dev
->name
, priv
);
832 ethoc_phy_init(priv
, dev
);