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[thirdparty/u-boot.git] / drivers / net / fm / eth.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020 NXP
5 * Dave Liu <daveliu@freescale.com>
6 */
7 #include <common.h>
8 #include <asm/io.h>
9 #ifdef CONFIG_DM_ETH
10 #include <dm.h>
11 #include <dm/ofnode.h>
12 #include <linux/compat.h>
13 #include <phy_interface.h>
14 #endif
15 #include <malloc.h>
16 #include <net.h>
17 #include <hwconfig.h>
18 #include <fm_eth.h>
19 #include <fsl_mdio.h>
20 #include <miiphy.h>
21 #include <phy.h>
22 #include <fsl_dtsec.h>
23 #include <fsl_tgec.h>
24 #include <fsl_memac.h>
25
26 #include "fm.h"
27
28 #ifndef CONFIG_DM_ETH
29 static struct eth_device *devlist[NUM_FM_PORTS];
30 static int num_controllers;
31 #endif
32
33 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
34
35 #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
36 TBIANA_FULL_DUPLEX)
37
38 #define TBIANA_SGMII_ACK 0x4001
39
40 #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
41 TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
42
43 /* Configure the TBI for SGMII operation */
44 static void dtsec_configure_serdes(struct fm_eth *priv)
45 {
46 #ifdef CONFIG_SYS_FMAN_V3
47 u32 value;
48 struct mii_dev bus;
49 bool sgmii_2500 = (priv->enet_if ==
50 PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
51 int i = 0, j;
52
53 #ifndef CONFIG_DM_ETH
54 bus.priv = priv->mac->phyregs;
55 #else
56 bus.priv = priv->pcs_mdio;
57 #endif
58 bus.read = memac_mdio_read;
59 bus.write = memac_mdio_write;
60 bus.reset = memac_mdio_reset;
61
62 qsgmii_loop:
63 /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
64 if (sgmii_2500)
65 value = PHY_SGMII_CR_PHY_RESET |
66 PHY_SGMII_IF_SPEED_GIGABIT |
67 PHY_SGMII_IF_MODE_SGMII;
68 else
69 value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
70
71 for (j = 0; j <= 3; j++)
72 debug("dump PCS reg %#x: %#x\n", j,
73 memac_mdio_read(&bus, i, MDIO_DEVAD_NONE, j));
74
75 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
76
77 /* Dev ability according to SGMII specification */
78 value = PHY_SGMII_DEV_ABILITY_SGMII;
79 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
80
81 if (sgmii_2500) {
82 /* Adjust link timer for 2.5G SGMII,
83 * 1.6 ms in units of 3.2 ns:
84 * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
85 */
86 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
87 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
88 } else {
89 /* Adjust link timer for SGMII,
90 * 1.6 ms in units of 8 ns:
91 * 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
92 */
93 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
94 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
95 }
96
97 /* Restart AN */
98 value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
99 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
100
101 if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
102 i++;
103 goto qsgmii_loop;
104 }
105 #else
106 struct dtsec *regs = priv->mac->base;
107 struct tsec_mii_mng *phyregs = priv->mac->phyregs;
108
109 /*
110 * Access TBI PHY registers at given TSEC register offset as
111 * opposed to the register offset used for external PHY accesses
112 */
113 tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
114 TBICON_CLK_SELECT);
115 tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
116 TBIANA_SGMII_ACK);
117 tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
118 TBI_CR, TBICR_SETTINGS);
119 #endif
120 }
121
122 static void dtsec_init_phy(struct fm_eth *fm_eth)
123 {
124 #ifndef CONFIG_SYS_FMAN_V3
125 struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
126
127 /* Assign a Physical address to the TBI */
128 out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
129 #endif
130
131 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
132 fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
133 fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
134 dtsec_configure_serdes(fm_eth);
135 }
136
137 #ifndef CONFIG_DM_ETH
138 #ifdef CONFIG_PHYLIB
139 static int tgec_is_fibre(struct fm_eth *fm)
140 {
141 char phyopt[20];
142
143 sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
144
145 return hwconfig_arg_cmp(phyopt, "xfi");
146 }
147 #endif
148 #endif /* CONFIG_DM_ETH */
149 #endif
150
151 static u16 muram_readw(u16 *addr)
152 {
153 ulong base = (ulong)addr & ~0x3UL;
154 u32 val32 = in_be32((void *)base);
155 int byte_pos;
156 u16 ret;
157
158 byte_pos = (ulong)addr & 0x3UL;
159 if (byte_pos)
160 ret = (u16)(val32 & 0x0000ffff);
161 else
162 ret = (u16)((val32 & 0xffff0000) >> 16);
163
164 return ret;
165 }
166
167 static void muram_writew(u16 *addr, u16 val)
168 {
169 ulong base = (ulong)addr & ~0x3UL;
170 u32 org32 = in_be32((void *)base);
171 u32 val32;
172 int byte_pos;
173
174 byte_pos = (ulong)addr & 0x3UL;
175 if (byte_pos)
176 val32 = (org32 & 0xffff0000) | val;
177 else
178 val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
179
180 out_be32((void *)base, val32);
181 }
182
183 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
184 {
185 int timeout = 1000000;
186
187 clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
188
189 /* wait until the rx port is not busy */
190 while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
191 ;
192 if (!timeout)
193 printf("%s - timeout\n", __func__);
194 }
195
196 static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
197 {
198 /* set BMI to independent mode, Rx port disable */
199 out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
200 /* clear FOF in IM case */
201 out_be32(&rx_port->fmbm_rim, 0);
202 /* Rx frame next engine -RISC */
203 out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
204 /* Rx command attribute - no order, MR[3] = 1 */
205 clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
206 setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
207 /* enable Rx statistic counters */
208 out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
209 /* disable Rx performance counters */
210 out_be32(&rx_port->fmbm_rpc, 0);
211 }
212
213 static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
214 {
215 int timeout = 1000000;
216
217 clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
218
219 /* wait until the tx port is not busy */
220 while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
221 ;
222 if (!timeout)
223 printf("%s - timeout\n", __func__);
224 }
225
226 static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
227 {
228 /* set BMI to independent mode, Tx port disable */
229 out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
230 /* Tx frame next engine -RISC */
231 out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
232 out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
233 /* Tx command attribute - no order, MR[3] = 1 */
234 clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
235 setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
236 /* enable Tx statistic counters */
237 out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
238 /* disable Tx performance counters */
239 out_be32(&tx_port->fmbm_tpc, 0);
240 }
241
242 static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
243 {
244 struct fm_port_global_pram *pram;
245 u32 pram_page_offset;
246 void *rx_bd_ring_base;
247 void *rx_buf_pool;
248 u32 bd_ring_base_lo, bd_ring_base_hi;
249 u32 buf_lo, buf_hi;
250 struct fm_port_bd *rxbd;
251 struct fm_port_qd *rxqd;
252 struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
253 int i;
254
255 /* alloc global parameter ram at MURAM */
256 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
257 FM_PRAM_SIZE, FM_PRAM_ALIGN);
258 if (!pram) {
259 printf("%s: No muram for Rx global parameter\n", __func__);
260 return -ENOMEM;
261 }
262
263 fm_eth->rx_pram = pram;
264
265 /* parameter page offset to MURAM */
266 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
267
268 /* enable global mode- snooping data buffers and BDs */
269 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
270
271 /* init the Rx queue descriptor pionter */
272 out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
273
274 /* set the max receive buffer length, power of 2 */
275 muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
276
277 /* alloc Rx buffer descriptors from main memory */
278 rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
279 * RX_BD_RING_SIZE);
280 if (!rx_bd_ring_base)
281 return -ENOMEM;
282
283 memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
284 * RX_BD_RING_SIZE);
285
286 /* alloc Rx buffer from main memory */
287 rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
288 if (!rx_buf_pool)
289 return -ENOMEM;
290
291 memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
292 debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
293
294 /* save them to fm_eth */
295 fm_eth->rx_bd_ring = rx_bd_ring_base;
296 fm_eth->cur_rxbd = rx_bd_ring_base;
297 fm_eth->rx_buf = rx_buf_pool;
298
299 /* init Rx BDs ring */
300 rxbd = (struct fm_port_bd *)rx_bd_ring_base;
301 for (i = 0; i < RX_BD_RING_SIZE; i++) {
302 muram_writew(&rxbd->status, RxBD_EMPTY);
303 muram_writew(&rxbd->len, 0);
304 buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
305 i * MAX_RXBUF_LEN));
306 buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
307 i * MAX_RXBUF_LEN));
308 muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
309 out_be32(&rxbd->buf_ptr_lo, buf_lo);
310 rxbd++;
311 }
312
313 /* set the Rx queue descriptor */
314 rxqd = &pram->rxqd;
315 muram_writew(&rxqd->gen, 0);
316 bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
317 bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
318 muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
319 out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
320 muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
321 * RX_BD_RING_SIZE);
322 muram_writew(&rxqd->offset_in, 0);
323 muram_writew(&rxqd->offset_out, 0);
324
325 /* set IM parameter ram pointer to Rx Frame Queue ID */
326 out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
327
328 return 0;
329 }
330
331 static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
332 {
333 struct fm_port_global_pram *pram;
334 u32 pram_page_offset;
335 void *tx_bd_ring_base;
336 u32 bd_ring_base_lo, bd_ring_base_hi;
337 struct fm_port_bd *txbd;
338 struct fm_port_qd *txqd;
339 struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
340 int i;
341
342 /* alloc global parameter ram at MURAM */
343 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
344 FM_PRAM_SIZE, FM_PRAM_ALIGN);
345 if (!pram) {
346 printf("%s: No muram for Tx global parameter\n", __func__);
347 return -ENOMEM;
348 }
349 fm_eth->tx_pram = pram;
350
351 /* parameter page offset to MURAM */
352 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
353
354 /* enable global mode- snooping data buffers and BDs */
355 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
356
357 /* init the Tx queue descriptor pionter */
358 out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
359
360 /* alloc Tx buffer descriptors from main memory */
361 tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
362 * TX_BD_RING_SIZE);
363 if (!tx_bd_ring_base)
364 return -ENOMEM;
365
366 memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
367 * TX_BD_RING_SIZE);
368 /* save it to fm_eth */
369 fm_eth->tx_bd_ring = tx_bd_ring_base;
370 fm_eth->cur_txbd = tx_bd_ring_base;
371
372 /* init Tx BDs ring */
373 txbd = (struct fm_port_bd *)tx_bd_ring_base;
374 for (i = 0; i < TX_BD_RING_SIZE; i++) {
375 muram_writew(&txbd->status, TxBD_LAST);
376 muram_writew(&txbd->len, 0);
377 muram_writew(&txbd->buf_ptr_hi, 0);
378 out_be32(&txbd->buf_ptr_lo, 0);
379 txbd++;
380 }
381
382 /* set the Tx queue decriptor */
383 txqd = &pram->txqd;
384 bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
385 bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
386 muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
387 out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
388 muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
389 * TX_BD_RING_SIZE);
390 muram_writew(&txqd->offset_in, 0);
391 muram_writew(&txqd->offset_out, 0);
392
393 /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
394 out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
395
396 return 0;
397 }
398
399 static int fm_eth_init(struct fm_eth *fm_eth)
400 {
401 int ret;
402
403 ret = fm_eth_rx_port_parameter_init(fm_eth);
404 if (ret)
405 return ret;
406
407 ret = fm_eth_tx_port_parameter_init(fm_eth);
408 if (ret)
409 return ret;
410
411 return 0;
412 }
413
414 static int fm_eth_startup(struct fm_eth *fm_eth)
415 {
416 struct fsl_enet_mac *mac;
417 int ret;
418
419 mac = fm_eth->mac;
420
421 /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
422 ret = fm_eth_init(fm_eth);
423 if (ret)
424 return ret;
425 /* setup the MAC controller */
426 mac->init_mac(mac);
427
428 /* For some reason we need to set SPEED_100 */
429 if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
430 (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
431 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
432 mac->set_if_mode)
433 mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
434
435 /* init bmi rx port, IM mode and disable */
436 bmi_rx_port_init(fm_eth->rx_port);
437 /* init bmi tx port, IM mode and disable */
438 bmi_tx_port_init(fm_eth->tx_port);
439
440 return 0;
441 }
442
443 static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
444 {
445 struct fm_port_global_pram *pram;
446
447 pram = fm_eth->tx_pram;
448 /* graceful stop transmission of frames */
449 setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
450 sync();
451 }
452
453 static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
454 {
455 struct fm_port_global_pram *pram;
456
457 pram = fm_eth->tx_pram;
458 /* re-enable transmission of frames */
459 clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
460 sync();
461 }
462
463 #ifndef CONFIG_DM_ETH
464 static int fm_eth_open(struct eth_device *dev, bd_t *bd)
465 #else
466 static int fm_eth_open(struct udevice *dev)
467 #endif
468 {
469 #ifndef CONFIG_DM_ETH
470 struct fm_eth *fm_eth = dev->priv;
471 #else
472 struct eth_pdata *pdata = dev_get_platdata(dev);
473 struct fm_eth *fm_eth = dev_get_priv(dev);
474 #endif
475 unsigned char *enetaddr;
476 struct fsl_enet_mac *mac;
477 #ifdef CONFIG_PHYLIB
478 int ret;
479 #endif
480
481 mac = fm_eth->mac;
482
483 #ifndef CONFIG_DM_ETH
484 enetaddr = &dev->enetaddr[0];
485 #else
486 enetaddr = pdata->enetaddr;
487 #endif
488
489 /* setup the MAC address */
490 if (enetaddr[0] & 0x01) {
491 printf("%s: MacAddress is multicast address\n", __func__);
492 enetaddr[0] = 0;
493 enetaddr[5] = fm_eth->num;
494 }
495 mac->set_mac_addr(mac, enetaddr);
496
497 /* enable bmi Rx port */
498 setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
499 /* enable MAC rx/tx port */
500 mac->enable_mac(mac);
501 /* enable bmi Tx port */
502 setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
503 /* re-enable transmission of frame */
504 fmc_tx_port_graceful_stop_disable(fm_eth);
505
506 #ifdef CONFIG_PHYLIB
507 if (fm_eth->phydev) {
508 ret = phy_startup(fm_eth->phydev);
509 if (ret) {
510 #ifndef CONFIG_DM_ETH
511 printf("%s: Could not initialize\n",
512 fm_eth->phydev->dev->name);
513 #else
514 printf("%s: Could not initialize\n", dev->name);
515 #endif
516 return ret;
517 }
518 } else {
519 return 0;
520 }
521 #else
522 fm_eth->phydev->speed = SPEED_1000;
523 fm_eth->phydev->link = 1;
524 fm_eth->phydev->duplex = DUPLEX_FULL;
525 #endif
526
527 /* set the MAC-PHY mode */
528 mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
529 debug("MAC IF mode %d, speed %d, link %d\n", fm_eth->enet_if,
530 fm_eth->phydev->speed, fm_eth->phydev->link);
531
532 if (!fm_eth->phydev->link)
533 printf("%s: No link.\n", fm_eth->phydev->dev->name);
534
535 return fm_eth->phydev->link ? 0 : -1;
536 }
537
538 #ifndef CONFIG_DM_ETH
539 static void fm_eth_halt(struct eth_device *dev)
540 #else
541 static void fm_eth_halt(struct udevice *dev)
542 #endif
543 {
544 struct fm_eth *fm_eth;
545 struct fsl_enet_mac *mac;
546
547 fm_eth = (struct fm_eth *)dev->priv;
548 mac = fm_eth->mac;
549
550 /* graceful stop the transmission of frames */
551 fmc_tx_port_graceful_stop_enable(fm_eth);
552 /* disable bmi Tx port */
553 bmi_tx_port_disable(fm_eth->tx_port);
554 /* disable MAC rx/tx port */
555 mac->disable_mac(mac);
556 /* disable bmi Rx port */
557 bmi_rx_port_disable(fm_eth->rx_port);
558
559 #ifdef CONFIG_PHYLIB
560 if (fm_eth->phydev)
561 phy_shutdown(fm_eth->phydev);
562 #endif
563 }
564
565 #ifndef CONFIG_DM_ETH
566 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
567 #else
568 static int fm_eth_send(struct udevice *dev, void *buf, int len)
569 #endif
570 {
571 struct fm_eth *fm_eth;
572 struct fm_port_global_pram *pram;
573 struct fm_port_bd *txbd, *txbd_base;
574 u16 offset_in;
575 int i;
576
577 fm_eth = (struct fm_eth *)dev->priv;
578 pram = fm_eth->tx_pram;
579 txbd = fm_eth->cur_txbd;
580
581 /* find one empty TxBD */
582 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
583 udelay(100);
584 if (i > 0x1000) {
585 printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
586 dev->name, muram_readw(&txbd->status));
587 return 0;
588 }
589 }
590 /* setup TxBD */
591 muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
592 out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
593 muram_writew(&txbd->len, len);
594 sync();
595 muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
596 sync();
597
598 /* update TxQD, let RISC to send the packet */
599 offset_in = muram_readw(&pram->txqd.offset_in);
600 offset_in += sizeof(struct fm_port_bd);
601 if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
602 offset_in = 0;
603 muram_writew(&pram->txqd.offset_in, offset_in);
604 sync();
605
606 /* wait for buffer to be transmitted */
607 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
608 udelay(100);
609 if (i > 0x10000) {
610 printf("%s: Tx error, txbd->status = 0x%x\n",
611 dev->name, muram_readw(&txbd->status));
612 return 0;
613 }
614 }
615
616 /* advance the TxBD */
617 txbd++;
618 txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
619 if (txbd >= (txbd_base + TX_BD_RING_SIZE))
620 txbd = txbd_base;
621 /* update current txbd */
622 fm_eth->cur_txbd = (void *)txbd;
623
624 return 1;
625 }
626
627 static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
628 struct fm_port_bd *rxbd)
629 {
630 struct fm_port_global_pram *pram;
631 struct fm_port_bd *rxbd_base;
632 u16 offset_out;
633
634 pram = fm_eth->rx_pram;
635
636 /* clear the RxBDs */
637 muram_writew(&rxbd->status, RxBD_EMPTY);
638 muram_writew(&rxbd->len, 0);
639 sync();
640
641 /* advance RxBD */
642 rxbd++;
643 rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
644 if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
645 rxbd = rxbd_base;
646
647 /* update RxQD */
648 offset_out = muram_readw(&pram->rxqd.offset_out);
649 offset_out += sizeof(struct fm_port_bd);
650 if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
651 offset_out = 0;
652 muram_writew(&pram->rxqd.offset_out, offset_out);
653 sync();
654
655 return rxbd;
656 }
657
658 #ifndef CONFIG_DM_ETH
659 static int fm_eth_recv(struct eth_device *dev)
660 #else
661 static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
662 #endif
663 {
664 struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
665 struct fm_port_bd *rxbd = fm_eth->cur_rxbd;
666 u32 buf_lo, buf_hi;
667 u16 status, len;
668 int ret = -1;
669 u8 *data;
670
671 status = muram_readw(&rxbd->status);
672
673 while (!(status & RxBD_EMPTY)) {
674 if (!(status & RxBD_ERROR)) {
675 buf_hi = muram_readw(&rxbd->buf_ptr_hi);
676 buf_lo = in_be32(&rxbd->buf_ptr_lo);
677 data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
678 len = muram_readw(&rxbd->len);
679 #ifndef CONFIG_DM_ETH
680 net_process_received_packet(data, len);
681 #else
682 *packetp = data;
683 return len;
684 #endif
685 } else {
686 printf("%s: Rx error\n", dev->name);
687 ret = 0;
688 }
689
690 /* free current bd, advance to next one */
691 rxbd = fm_eth_free_one(fm_eth, rxbd);
692
693 /* read next status */
694 status = muram_readw(&rxbd->status);
695 }
696 fm_eth->cur_rxbd = (void *)rxbd;
697
698 return ret;
699 }
700
701 #ifdef CONFIG_DM_ETH
702 static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
703 {
704 struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
705
706 fm_eth->cur_rxbd = fm_eth_free_one(fm_eth, fm_eth->cur_rxbd);
707
708 return 0;
709 }
710 #endif /* CONFIG_DM_ETH */
711
712 #ifndef CONFIG_DM_ETH
713 static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
714 {
715 struct fsl_enet_mac *mac;
716 int num;
717 void *base, *phyregs = NULL;
718
719 num = fm_eth->num;
720
721 #ifdef CONFIG_SYS_FMAN_V3
722 #ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
723 if (fm_eth->type == FM_ETH_10G_E) {
724 /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
725 * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
726 * 10GEC1 uses mEMAC1 on T1024.
727 * so it needs to change the num.
728 */
729 if (fm_eth->num >= 2)
730 num -= 2;
731 else
732 num += 8;
733 }
734 #endif
735 base = &reg->memac[num].fm_memac;
736 phyregs = &reg->memac[num].fm_memac_mdio;
737 #else
738 /* Get the mac registers base address */
739 if (fm_eth->type == FM_ETH_1G_E) {
740 base = &reg->mac_1g[num].fm_dtesc;
741 phyregs = &reg->mac_1g[num].fm_mdio.miimcfg;
742 } else {
743 base = &reg->mac_10g[num].fm_10gec;
744 phyregs = &reg->mac_10g[num].fm_10gec_mdio;
745 }
746 #endif
747
748 /* alloc mac controller */
749 mac = malloc(sizeof(struct fsl_enet_mac));
750 if (!mac)
751 return -ENOMEM;
752 memset(mac, 0, sizeof(struct fsl_enet_mac));
753
754 /* save the mac to fm_eth struct */
755 fm_eth->mac = mac;
756
757 #ifdef CONFIG_SYS_FMAN_V3
758 init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
759 #else
760 if (fm_eth->type == FM_ETH_1G_E)
761 init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
762 else
763 init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
764 #endif
765
766 return 0;
767 }
768 #else /* CONFIG_DM_ETH */
769 static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
770 {
771 #ifndef CONFIG_SYS_FMAN_V3
772 void *mdio;
773 #endif
774
775 fm_eth->mac = kzalloc(sizeof(*fm_eth->mac), GFP_KERNEL);
776 if (!fm_eth->mac)
777 return -ENOMEM;
778
779 #ifndef CONFIG_SYS_FMAN_V3
780 mdio = fman_mdio(fm_eth->dev->parent, fm_eth->mac_type, fm_eth->num);
781 debug("MDIO %d @ %p\n", fm_eth->num, mdio);
782 #endif
783
784 switch (fm_eth->mac_type) {
785 #ifdef CONFIG_SYS_FMAN_V3
786 case FM_MEMAC:
787 init_memac(fm_eth->mac, reg, NULL, MAX_RXBUF_LEN);
788 break;
789 #else
790 case FM_DTSEC:
791 init_dtsec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
792 break;
793 case FM_TGEC:
794 init_tgec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
795 break;
796 #endif
797 }
798
799 return 0;
800 }
801 #endif /* CONFIG_DM_ETH */
802
803 static int init_phy(struct fm_eth *fm_eth)
804 {
805 #ifdef CONFIG_PHYLIB
806 u32 supported = PHY_GBIT_FEATURES;
807 #ifndef CONFIG_DM_ETH
808 struct phy_device *phydev = NULL;
809 #endif
810
811 if (fm_eth->type == FM_ETH_10G_E)
812 supported = PHY_10G_FEATURES;
813 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
814 supported |= SUPPORTED_2500baseX_Full;
815 #endif
816
817 if (fm_eth->type == FM_ETH_1G_E)
818 dtsec_init_phy(fm_eth);
819
820 #ifdef CONFIG_DM_ETH
821 #ifdef CONFIG_PHYLIB
822 #ifdef CONFIG_DM_MDIO
823 fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
824 if (!fm_eth->phydev)
825 return -ENODEV;
826 #endif
827 fm_eth->phydev->advertising &= supported;
828 fm_eth->phydev->supported &= supported;
829
830 phy_config(fm_eth->phydev);
831 #endif
832 #else /* CONFIG_DM_ETH */
833 #ifdef CONFIG_PHYLIB
834 if (fm_eth->bus) {
835 phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
836 fm_eth->enet_if);
837 if (!phydev) {
838 printf("Failed to connect\n");
839 return -1;
840 }
841 } else {
842 return 0;
843 }
844
845 if (fm_eth->type == FM_ETH_1G_E) {
846 supported = (SUPPORTED_10baseT_Half |
847 SUPPORTED_10baseT_Full |
848 SUPPORTED_100baseT_Half |
849 SUPPORTED_100baseT_Full |
850 SUPPORTED_1000baseT_Full);
851 } else {
852 supported = SUPPORTED_10000baseT_Full;
853
854 if (tgec_is_fibre(fm_eth))
855 phydev->port = PORT_FIBRE;
856 }
857
858 phydev->supported &= supported;
859 phydev->advertising = phydev->supported;
860
861 fm_eth->phydev = phydev;
862
863 phy_config(phydev);
864 #endif
865 #endif /* CONFIG_DM_ETH */
866 return 0;
867 }
868
869 #ifndef CONFIG_DM_ETH
870 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
871 {
872 struct eth_device *dev;
873 struct fm_eth *fm_eth;
874 int i, num = info->num;
875 int ret;
876
877 /* alloc eth device */
878 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
879 if (!dev)
880 return -ENOMEM;
881 memset(dev, 0, sizeof(struct eth_device));
882
883 /* alloc the FMan ethernet private struct */
884 fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
885 if (!fm_eth)
886 return -ENOMEM;
887 memset(fm_eth, 0, sizeof(struct fm_eth));
888
889 /* save off some things we need from the info struct */
890 fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
891 fm_eth->num = num;
892 fm_eth->type = info->type;
893
894 fm_eth->rx_port = (void *)&reg->port[info->rx_port_id - 1].fm_bmi;
895 fm_eth->tx_port = (void *)&reg->port[info->tx_port_id - 1].fm_bmi;
896
897 /* set the ethernet max receive length */
898 fm_eth->max_rx_len = MAX_RXBUF_LEN;
899
900 /* init global mac structure */
901 ret = fm_eth_init_mac(fm_eth, reg);
902 if (ret)
903 return ret;
904
905 /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
906 if (fm_eth->type == FM_ETH_1G_E)
907 sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
908 else
909 sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
910
911 devlist[num_controllers++] = dev;
912 dev->iobase = 0;
913 dev->priv = (void *)fm_eth;
914 dev->init = fm_eth_open;
915 dev->halt = fm_eth_halt;
916 dev->send = fm_eth_send;
917 dev->recv = fm_eth_recv;
918 fm_eth->dev = dev;
919 fm_eth->bus = info->bus;
920 fm_eth->phyaddr = info->phy_addr;
921 fm_eth->enet_if = info->enet_if;
922
923 /* startup the FM im */
924 ret = fm_eth_startup(fm_eth);
925 if (ret)
926 return ret;
927
928 init_phy(fm_eth);
929
930 /* clear the ethernet address */
931 for (i = 0; i < 6; i++)
932 dev->enetaddr[i] = 0;
933 eth_register(dev);
934
935 return 0;
936 }
937 #else /* CONFIG_DM_ETH */
938 #ifdef CONFIG_PHYLIB
939 phy_interface_t fman_read_sys_if(struct udevice *dev)
940 {
941 const char *if_str;
942
943 if_str = ofnode_read_string(dev->node, "phy-connection-type");
944 debug("MAC system interface mode %s\n", if_str);
945
946 return phy_get_interface_by_name(if_str);
947 }
948 #endif
949
950 static int fm_eth_bind(struct udevice *dev)
951 {
952 char mac_name[11];
953 u32 fm, num;
954
955 if (ofnode_read_u32(ofnode_get_parent(dev->node), "cell-index", &fm)) {
956 printf("FMan node property cell-index missing\n");
957 return -EINVAL;
958 }
959
960 if (dev && dev_read_u32(dev, "cell-index", &num)) {
961 printf("FMan MAC node property cell-index missing\n");
962 return -EINVAL;
963 }
964
965 sprintf(mac_name, "fm%d-mac%d", fm + 1, num + 1);
966 device_set_name(dev, mac_name);
967
968 debug("%s - binding %s\n", __func__, mac_name);
969
970 return 0;
971 }
972
973 static struct udevice *fm_get_internal_mdio(struct udevice *dev)
974 {
975 struct ofnode_phandle_args phandle = {.node = ofnode_null()};
976 struct udevice *mdiodev;
977
978 if (dev_read_phandle_with_args(dev, "pcsphy-handle", NULL,
979 0, 0, &phandle) ||
980 !ofnode_valid(phandle.node)) {
981 if (dev_read_phandle_with_args(dev, "tbi-handle", NULL,
982 0, 0, &phandle) ||
983 !ofnode_valid(phandle.node)) {
984 printf("Issue reading pcsphy-handle/tbi-handle for MAC %s\n",
985 dev->name);
986 return NULL;
987 }
988 }
989
990 if (uclass_get_device_by_ofnode(UCLASS_MDIO,
991 ofnode_get_parent(phandle.node),
992 &mdiodev)) {
993 printf("can't find MDIO bus for node %s\n",
994 ofnode_get_name(ofnode_get_parent(phandle.node)));
995 return NULL;
996 }
997 debug("Found internal MDIO bus %p\n", mdiodev);
998
999 return mdiodev;
1000 }
1001
1002 static int fm_eth_probe(struct udevice *dev)
1003 {
1004 struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
1005 struct ofnode_phandle_args args;
1006 void *reg;
1007 int ret, index;
1008
1009 debug("%s enter for dev %p fm_eth %p - %s\n", __func__, dev, fm_eth,
1010 (dev) ? dev->name : "-");
1011
1012 if (fm_eth->dev) {
1013 printf("%s already probed, exit\n", (dev) ? dev->name : "-");
1014 return 0;
1015 }
1016
1017 fm_eth->dev = dev;
1018 fm_eth->fm_index = fman_id(dev->parent);
1019 reg = (void *)(uintptr_t)dev_read_addr(dev);
1020 fm_eth->mac_type = dev_get_driver_data(dev);
1021 #ifdef CONFIG_PHYLIB
1022 fm_eth->enet_if = fman_read_sys_if(dev);
1023 #else
1024 fm_eth->enet_if = PHY_INTERFACE_MODE_SGMII;
1025 printf("%s: warning - unable to determine interface type\n", __func__);
1026 #endif
1027 switch (fm_eth->mac_type) {
1028 #ifndef CONFIG_SYS_FMAN_V3
1029 case FM_TGEC:
1030 fm_eth->type = FM_ETH_10G_E;
1031 break;
1032 case FM_DTSEC:
1033 #else
1034 case FM_MEMAC:
1035 /* default to 1G, 10G is indicated by port property in dts */
1036 #endif
1037 fm_eth->type = FM_ETH_1G_E;
1038 break;
1039 }
1040
1041 if (dev_read_u32(dev, "cell-index", &fm_eth->num)) {
1042 printf("FMan MAC node property cell-index missing\n");
1043 return -EINVAL;
1044 }
1045
1046 if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
1047 0, 0, &args))
1048 goto ports_ref_failure;
1049 index = ofnode_read_u32_default(args.node, "cell-index", 0);
1050 if (index <= 0)
1051 goto ports_ref_failure;
1052 fm_eth->rx_port = fman_port(dev->parent, index);
1053
1054 if (ofnode_read_bool(args.node, "fsl,fman-10g-port"))
1055 fm_eth->type = FM_ETH_10G_E;
1056
1057 if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
1058 0, 1, &args))
1059 goto ports_ref_failure;
1060 index = ofnode_read_u32_default(args.node, "cell-index", 0);
1061 if (index <= 0)
1062 goto ports_ref_failure;
1063 fm_eth->tx_port = fman_port(dev->parent, index);
1064
1065 /* set the ethernet max receive length */
1066 fm_eth->max_rx_len = MAX_RXBUF_LEN;
1067
1068 switch (fm_eth->enet_if) {
1069 case PHY_INTERFACE_MODE_QSGMII:
1070 /* all PCS blocks are accessed on one controller */
1071 if (fm_eth->num != 0)
1072 break;
1073 case PHY_INTERFACE_MODE_SGMII:
1074 case PHY_INTERFACE_MODE_SGMII_2500:
1075 fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
1076 break;
1077 default:
1078 break;
1079 }
1080
1081 /* init global mac structure */
1082 ret = fm_eth_init_mac(fm_eth, reg);
1083 if (ret)
1084 return ret;
1085
1086 /* startup the FM im */
1087 ret = fm_eth_startup(fm_eth);
1088
1089 if (!ret)
1090 ret = init_phy(fm_eth);
1091
1092 return ret;
1093
1094 ports_ref_failure:
1095 printf("Issue reading fsl,fman-ports for MAC %s\n", dev->name);
1096 return -ENOENT;
1097 }
1098
1099 static int fm_eth_remove(struct udevice *dev)
1100 {
1101 return 0;
1102 }
1103
1104 static const struct eth_ops fm_eth_ops = {
1105 .start = fm_eth_open,
1106 .send = fm_eth_send,
1107 .recv = fm_eth_recv,
1108 .free_pkt = fm_eth_free_pkt,
1109 .stop = fm_eth_halt,
1110 };
1111
1112 static const struct udevice_id fm_eth_ids[] = {
1113 #ifdef CONFIG_SYS_FMAN_V3
1114 { .compatible = "fsl,fman-memac", .data = FM_MEMAC },
1115 #else
1116 { .compatible = "fsl,fman-dtsec", .data = FM_DTSEC },
1117 { .compatible = "fsl,fman-xgec", .data = FM_TGEC },
1118 #endif
1119 {}
1120 };
1121
1122 U_BOOT_DRIVER(eth_fman) = {
1123 .name = "eth_fman",
1124 .id = UCLASS_ETH,
1125 .of_match = fm_eth_ids,
1126 .bind = fm_eth_bind,
1127 .probe = fm_eth_probe,
1128 .remove = fm_eth_remove,
1129 .ops = &fm_eth_ops,
1130 .priv_auto_alloc_size = sizeof(struct fm_eth),
1131 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1132 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1133 };
1134 #endif /* CONFIG_DM_ETH */
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