2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/errno.h>
13 #include <fsl_qe.h> /* For struct qe_firmware */
15 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
17 #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
18 #include <spi_flash.h>
19 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
23 struct fm_muram muram
[CONFIG_SYS_NUM_FMAN
];
25 void *fm_muram_base(int fm_idx
)
27 return muram
[fm_idx
].base
;
30 void *fm_muram_alloc(int fm_idx
, size_t size
, ulong align
)
37 align_mask
= align
- 1;
38 save
= muram
[fm_idx
].alloc
;
40 off
= (ulong
)save
& align_mask
;
42 muram
[fm_idx
].alloc
+= (align
- off
);
43 off
= size
& align_mask
;
45 size
+= (align
- off
);
46 if ((muram
[fm_idx
].alloc
+ size
) >= muram
[fm_idx
].top
) {
47 muram
[fm_idx
].alloc
= save
;
48 printf("%s: run out of ram.\n", __func__
);
52 ret
= muram
[fm_idx
].alloc
;
53 muram
[fm_idx
].alloc
+= size
;
54 memset((void *)ret
, 0, size
);
59 static void fm_init_muram(int fm_idx
, void *reg
)
63 muram
[fm_idx
].base
= base
;
64 muram
[fm_idx
].size
= CONFIG_SYS_FM_MURAM_SIZE
;
65 muram
[fm_idx
].alloc
= base
+ FM_MURAM_RES_SIZE
;
66 muram
[fm_idx
].top
= base
+ CONFIG_SYS_FM_MURAM_SIZE
;
70 * fm_upload_ucode - Fman microcode upload worker function
72 * This function does the actual uploading of an Fman microcode
75 static void fm_upload_ucode(int fm_idx
, struct fm_imem
*imem
,
76 u32
*ucode
, unsigned int size
)
79 unsigned int timeout
= 1000000;
81 /* enable address auto increase */
82 out_be32(&imem
->iadd
, IRAM_IADD_AIE
);
83 /* write microcode to IRAM */
84 for (i
= 0; i
< size
/ 4; i
++)
85 out_be32(&imem
->idata
, (be32_to_cpu(ucode
[i
])));
87 /* verify if the writing is over */
88 out_be32(&imem
->iadd
, 0);
89 while ((in_be32(&imem
->idata
) != be32_to_cpu(ucode
[0])) && --timeout
)
92 printf("Fman%u: microcode upload timeout\n", fm_idx
+ 1);
94 /* enable microcode from IRAM */
95 out_be32(&imem
->iready
, IRAM_READY
);
99 * Upload an Fman firmware
101 * This function is similar to qe_upload_firmware(), exception that it uploads
102 * a microcode to the Fman instead of the QE.
104 * Because the process for uploading a microcode to the Fman is similar for
105 * that of the QE, the QE firmware binary format is used for Fman microcode.
106 * It should be possible to unify these two functions, but for now we keep them
109 static int fman_upload_firmware(int fm_idx
,
110 struct fm_imem
*fm_imem
,
111 const struct qe_firmware
*firmware
)
115 size_t calc_size
= sizeof(struct qe_firmware
);
117 const struct qe_header
*hdr
;
120 printf("Fman%u: Invalid address for firmware\n", fm_idx
+ 1);
124 hdr
= &firmware
->header
;
125 length
= be32_to_cpu(hdr
->length
);
127 /* Check the magic */
128 if ((hdr
->magic
[0] != 'Q') || (hdr
->magic
[1] != 'E') ||
129 (hdr
->magic
[2] != 'F')) {
130 printf("Fman%u: Data at %p is not a firmware\n", fm_idx
+ 1,
135 /* Check the version */
136 if (hdr
->version
!= 1) {
137 printf("Fman%u: Unsupported firmware version %u\n", fm_idx
+ 1,
142 /* Validate some of the fields */
143 if ((firmware
->count
!= 1)) {
144 printf("Fman%u: Invalid data in firmware header\n", fm_idx
+ 1);
148 /* Validate the length and check if there's a CRC */
149 calc_size
+= (firmware
->count
- 1) * sizeof(struct qe_microcode
);
151 for (i
= 0; i
< firmware
->count
; i
++)
153 * For situations where the second RISC uses the same microcode
154 * as the first, the 'code_offset' and 'count' fields will be
155 * zero, so it's okay to add those.
157 calc_size
+= sizeof(u32
) *
158 be32_to_cpu(firmware
->microcode
[i
].count
);
160 /* Validate the length */
161 if (length
!= calc_size
+ sizeof(u32
)) {
162 printf("Fman%u: Invalid length in firmware header\n",
168 * Validate the CRC. We would normally call crc32_no_comp(), but that
169 * function isn't available unless you turn on JFFS support.
171 crc
= be32_to_cpu(*(u32
*)((void *)firmware
+ calc_size
));
172 if (crc
!= (crc32(-1, (const void *)firmware
, calc_size
) ^ -1)) {
173 printf("Fman%u: Firmware CRC is invalid\n", fm_idx
+ 1);
177 /* Loop through each microcode. */
178 for (i
= 0; i
< firmware
->count
; i
++) {
179 const struct qe_microcode
*ucode
= &firmware
->microcode
[i
];
181 /* Upload a microcode if it's present */
182 if (be32_to_cpu(ucode
->code_offset
)) {
185 printf("Fman%u: Uploading microcode version %u.%u.%u\n",
186 fm_idx
+ 1, ucode
->major
, ucode
->minor
,
188 code
= (void *)firmware
+
189 be32_to_cpu(ucode
->code_offset
);
190 ucode_size
= sizeof(u32
) * be32_to_cpu(ucode
->count
);
191 fm_upload_ucode(fm_idx
, fm_imem
, code
, ucode_size
);
198 static u32
fm_assign_risc(int port_id
)
201 risc_sel
= (port_id
& 0x1) ? FMFPPRC_RISC2
: FMFPPRC_RISC1
;
202 val
= (port_id
<< FMFPPRC_PORTID_SHIFT
) & FMFPPRC_PORTID_MASK
;
203 val
|= ((risc_sel
<< FMFPPRC_ORA_SHIFT
) | risc_sel
);
208 static void fm_init_fpm(struct fm_fpm
*fpm
)
213 setbits_be32(&fpm
->fmfpee
, FMFPEE_EHM
| FMFPEE_UEC
|
214 FMFPEE_CER
| FMFPEE_DER
);
216 /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
218 /* offline/parser port */
219 for (i
= 0; i
< MAX_NUM_OH_PORT
; i
++) {
220 port_id
= OH_PORT_ID_BASE
+ i
;
221 val
= fm_assign_risc(port_id
);
222 out_be32(&fpm
->fpmprc
, val
);
225 for (i
= 0; i
< MAX_NUM_RX_PORT_1G
; i
++) {
226 port_id
= RX_PORT_1G_BASE
+ i
;
227 val
= fm_assign_risc(port_id
);
228 out_be32(&fpm
->fpmprc
, val
);
231 for (i
= 0; i
< MAX_NUM_TX_PORT_1G
; i
++) {
232 port_id
= TX_PORT_1G_BASE
+ i
;
233 val
= fm_assign_risc(port_id
);
234 out_be32(&fpm
->fpmprc
, val
);
237 port_id
= RX_PORT_10G_BASE
;
238 val
= fm_assign_risc(port_id
);
239 out_be32(&fpm
->fpmprc
, val
);
241 port_id
= TX_PORT_10G_BASE
;
242 val
= fm_assign_risc(port_id
);
243 out_be32(&fpm
->fpmprc
, val
);
245 /* disable the dispatch limit in IM case */
246 out_be32(&fpm
->fpmflc
, FMFP_FLC_DISP_LIM_NONE
);
248 out_be32(&fpm
->fmfpee
, FMFPEE_CLEAR_EVENT
);
250 /* clear risc events */
251 for (i
= 0; i
< 4; i
++)
252 out_be32(&fpm
->fpmcev
[i
], 0xffffffff);
255 out_be32(&fpm
->fpmrcr
, FMFP_RCR_MDEC
| FMFP_RCR_IDEC
);
258 static int fm_init_bmi(int fm_idx
, struct fm_bmi_common
*bmi
)
265 /* alloc free buffer pool in MURAM */
266 base
= fm_muram_alloc(fm_idx
, FM_FREE_POOL_SIZE
, FM_FREE_POOL_ALIGN
);
268 printf("%s: no muram for free buffer pool\n", __func__
);
271 offset
= base
- fm_muram_base(fm_idx
);
273 /* Need 128KB total free buffer pool size */
275 blk
= FM_FREE_POOL_SIZE
/ 256;
276 /* in IM, we must not begin from offset 0 in MURAM */
277 val
|= ((blk
- 1) << FMBM_CFG1_FBPS_SHIFT
);
278 out_be32(&bmi
->fmbm_cfg1
, val
);
280 /* disable all BMI interrupt */
281 out_be32(&bmi
->fmbm_ier
, FMBM_IER_DISABLE_ALL
);
283 /* clear all events */
284 out_be32(&bmi
->fmbm_ievr
, FMBM_IEVR_CLEAR_ALL
);
287 * set port parameters - FMBM_PP_x
288 * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
289 * max dma 10G Rx/Tx=3, others is 1
290 * set port FIFO size - FMBM_PFS_x
291 * 4KB for all Rx and Tx ports
293 /* offline/parser port */
294 for (i
= 0; i
< MAX_NUM_OH_PORT
; i
++) {
295 port_id
= OH_PORT_ID_BASE
+ i
- 1;
296 /* max tasks=1, max dma=1, no extra */
297 out_be32(&bmi
->fmbm_pp
[port_id
], 0);
298 /* port FIFO size - 256 bytes, no extra */
299 out_be32(&bmi
->fmbm_pfs
[port_id
], 0);
302 for (i
= 0; i
< MAX_NUM_RX_PORT_1G
; i
++) {
303 port_id
= RX_PORT_1G_BASE
+ i
- 1;
304 /* max tasks=4, max dma=1, no extra */
305 out_be32(&bmi
->fmbm_pp
[port_id
], FMBM_PP_MXT(4));
306 /* FIFO size - 4KB, no extra */
307 out_be32(&bmi
->fmbm_pfs
[port_id
], FMBM_PFS_IFSZ(0xf));
309 /* Tx 1G port FIFO size - 4KB, no extra */
310 for (i
= 0; i
< MAX_NUM_TX_PORT_1G
; i
++) {
311 port_id
= TX_PORT_1G_BASE
+ i
- 1;
312 /* max tasks=4, max dma=1, no extra */
313 out_be32(&bmi
->fmbm_pp
[port_id
], FMBM_PP_MXT(4));
314 /* FIFO size - 4KB, no extra */
315 out_be32(&bmi
->fmbm_pfs
[port_id
], FMBM_PFS_IFSZ(0xf));
318 port_id
= RX_PORT_10G_BASE
- 1;
319 /* max tasks=12, max dma=3, no extra */
320 out_be32(&bmi
->fmbm_pp
[port_id
], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
321 /* FIFO size - 4KB, no extra */
322 out_be32(&bmi
->fmbm_pfs
[port_id
], FMBM_PFS_IFSZ(0xf));
325 port_id
= TX_PORT_10G_BASE
- 1;
326 /* max tasks=12, max dma=3, no extra */
327 out_be32(&bmi
->fmbm_pp
[port_id
], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
328 /* FIFO size - 4KB, no extra */
329 out_be32(&bmi
->fmbm_pfs
[port_id
], FMBM_PFS_IFSZ(0xf));
331 /* initialize internal buffers data base (linked list) */
332 out_be32(&bmi
->fmbm_init
, FMBM_INIT_START
);
337 static void fm_init_qmi(struct fm_qmi_common
*qmi
)
339 /* disable all error interrupts */
340 out_be32(&qmi
->fmqm_eien
, FMQM_EIEN_DISABLE_ALL
);
341 /* clear all error events */
342 out_be32(&qmi
->fmqm_eie
, FMQM_EIE_CLEAR_ALL
);
344 /* disable all interrupts */
345 out_be32(&qmi
->fmqm_ien
, FMQM_IEN_DISABLE_ALL
);
346 /* clear all interrupts */
347 out_be32(&qmi
->fmqm_ie
, FMQM_IE_CLEAR_ALL
);
350 /* Init common part of FM, index is fm num# like fm as above */
351 int fm_init_common(int index
, struct ccsr_fman
*reg
)
354 #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
355 void *addr
= (void *)CONFIG_SYS_FMAN_FW_ADDR
;
356 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
357 size_t fw_length
= CONFIG_SYS_QE_FMAN_FW_LENGTH
;
358 void *addr
= malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH
);
360 rc
= nand_read(nand_info
[0], (loff_t
)CONFIG_SYS_FMAN_FW_ADDR
,
361 &fw_length
, (u_char
*)addr
);
362 if (rc
== -EUCLEAN
) {
363 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
364 CONFIG_SYS_FMAN_FW_ADDR
, rc
);
366 #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
367 struct spi_flash
*ucode_flash
;
368 void *addr
= malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH
);
371 ucode_flash
= spi_flash_probe(CONFIG_ENV_SPI_BUS
, CONFIG_ENV_SPI_CS
,
372 CONFIG_ENV_SPI_MAX_HZ
, CONFIG_ENV_SPI_MODE
);
374 printf("SF: probe for ucode failed\n");
376 ret
= spi_flash_read(ucode_flash
, CONFIG_SYS_FMAN_FW_ADDR
,
377 CONFIG_SYS_QE_FMAN_FW_LENGTH
, addr
);
379 printf("SF: read for ucode failed\n");
380 spi_flash_free(ucode_flash
);
382 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
383 int dev
= CONFIG_SYS_MMC_ENV_DEV
;
384 void *addr
= malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH
);
385 u32 cnt
= CONFIG_SYS_QE_FMAN_FW_LENGTH
/ 512;
386 u32 blk
= CONFIG_SYS_FMAN_FW_ADDR
/ 512;
387 struct mmc
*mmc
= find_mmc_device(CONFIG_SYS_MMC_ENV_DEV
);
390 printf("\nMMC cannot find device for ucode\n");
392 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
395 (void)mmc
->block_dev
.block_read(&mmc
->block_dev
, blk
, cnt
,
397 /* flush cache after read */
398 flush_cache((ulong
)addr
, cnt
* 512);
400 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
401 void *addr
= (void *)CONFIG_SYS_FMAN_FW_ADDR
;
406 /* Upload the Fman microcode if it's present */
407 rc
= fman_upload_firmware(index
, ®
->fm_imem
, addr
);
410 setenv_addr("fman_ucode", addr
);
412 fm_init_muram(index
, ®
->muram
);
413 fm_init_qmi(®
->fm_qmi_common
);
414 fm_init_fpm(®
->fm_fpm
);
416 /* clear DMA status */
417 setbits_be32(®
->fm_dma
.fmdmsr
, FMDMSR_CLEAR_ALL
);
420 setbits_be32(®
->fm_dma
.fmdmmr
, FMDMMR_SBER
);
422 return fm_init_bmi(index
, ®
->fm_bmi_common
);