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git.ipfire.org Git - thirdparty/u-boot.git/blob - drivers/net/fm/fm.h
2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/fsl_fman.h>
16 #define OH_PORT_ID_BASE 0x01
17 #define MAX_NUM_OH_PORT 7
18 #define RX_PORT_1G_BASE 0x08
19 #define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
20 #define RX_PORT_10G_BASE 0x10
21 #define RX_PORT_10G_BASE2 0x08
22 #define TX_PORT_1G_BASE 0x28
23 #define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
24 #define TX_PORT_10G_BASE 0x30
25 #define TX_PORT_10G_BASE2 0x28
26 #define MIIM_TIMEOUT 0xFFFF
34 #define FM_MURAM_RES_SIZE 0x01000
36 /* Rx/Tx buffer descriptor */
47 #define BD_LAST 0x0800
49 /* Rx BD status flags */
50 #define RxBD_EMPTY 0x8000
51 #define RxBD_LAST BD_LAST
52 #define RxBD_FIRST 0x0400
53 #define RxBD_PHYS_ERR 0x0008
54 #define RxBD_SIZE_ERR 0x0004
55 #define RxBD_ERROR (RxBD_PHYS_ERR | RxBD_SIZE_ERR)
57 /* Tx BD status flags */
58 #define TxBD_READY 0x8000
59 #define TxBD_LAST BD_LAST
61 /* Rx/Tx queue descriptor */
73 /* IM global parameter RAM */
74 struct fm_port_global_pram
{
75 u32 mode
; /* independent mode register */
76 u32 rxqd_ptr
; /* Rx queue descriptor pointer */
77 u32 txqd_ptr
; /* Tx queue descriptor pointer */
78 u16 mrblr
; /* max Rx buffer length */
79 u16 rxqd_bsy_cnt
; /* RxQD busy counter, should be cleared */
81 struct fm_port_qd rxqd
; /* Rx queue descriptor */
82 struct fm_port_qd txqd
; /* Tx queue descriptor */
86 #define FM_PRAM_SIZE sizeof(struct fm_port_global_pram)
87 #define FM_PRAM_ALIGN 256
88 #define PRAM_MODE_GLOBAL 0x20000000
89 #define PRAM_MODE_GRACEFUL_STOP 0x00800000
91 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
92 #define FM_FREE_POOL_SIZE 0x2000 /* 8K bytes */
94 #define FM_FREE_POOL_SIZE 0x20000 /* 128K bytes */
96 #define FM_FREE_POOL_ALIGN 256
98 u32
fm_muram_alloc(int fm_idx
, u32 size
, u32 align
);
99 u32
fm_muram_base(int fm_idx
);
100 int fm_init_common(int index
, struct ccsr_fman
*reg
);
101 int fm_eth_initialize(struct ccsr_fman
*reg
, struct fm_eth_info
*info
);
102 phy_interface_t
fman_port_enet_if(enum fm_port port
);
103 void fman_disable_port(enum fm_port port
);
104 void fman_enable_port(enum fm_port port
);
106 struct fsl_enet_mac
{
107 void *base
; /* MAC controller registers base address */
110 void (*init_mac
)(struct fsl_enet_mac
*mac
);
111 void (*enable_mac
)(struct fsl_enet_mac
*mac
);
112 void (*disable_mac
)(struct fsl_enet_mac
*mac
);
113 void (*set_mac_addr
)(struct fsl_enet_mac
*mac
, u8
*mac_addr
);
114 void (*set_if_mode
)(struct fsl_enet_mac
*mac
, phy_interface_t type
,
118 /* Fman ethernet private struct */
120 int fm_index
; /* Fman index */
121 u32 num
; /* 0..n-1 for give type */
122 struct fm_bmi_tx_port
*tx_port
;
123 struct fm_bmi_rx_port
*rx_port
;
124 enum fm_eth_type type
; /* 1G or 10G ethernet */
125 phy_interface_t enet_if
;
126 struct fsl_enet_mac
*mac
; /* MAC controller */
128 struct phy_device
*phydev
;
130 struct eth_device
*dev
;
132 struct fm_port_global_pram
*rx_pram
; /* Rx parameter table */
133 struct fm_port_global_pram
*tx_pram
; /* Tx parameter table */
134 void *rx_bd_ring
; /* Rx BD ring base */
135 void *cur_rxbd
; /* current Rx BD */
136 void *rx_buf
; /* Rx buffer base */
137 void *tx_bd_ring
; /* Tx BD ring base */
138 void *cur_txbd
; /* current Tx BD */
141 #define RX_BD_RING_SIZE 8
142 #define TX_BD_RING_SIZE 8
143 #define MAX_RXBUF_LOG2 11
144 #define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2)
146 #define PORT_IS_ENABLED(port) (fm_port_to_index(port) == -1 ? \
147 0 : fm_info[fm_port_to_index(port)].enabled)
149 #endif /* __FM_H__ */