drivers/net/fm/p4080.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <phy.h>
   8 #include <fm_eth.h>
   9 #include <asm/io.h>
  10 #include <asm/immap_85xx.h>
  11 #include <asm/fsl_serdes.h>
  12
  13 static u32 port_to_devdisr[] = {
  14         [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
  15         [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
  16         [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
  17         [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
  18         [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
  19         [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
  20         [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
  21         [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
  22         [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
  23         [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
  24 };
  25
  26 static int is_device_disabled(enum fm_port port)
  27 {
  28         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  29         u32 devdisr2 = in_be32(&gur->devdisr2);
  30
  31         return port_to_devdisr[port] & devdisr2;
  32 }
  33
  34 void fman_disable_port(enum fm_port port)
  35 {
  36         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  37
  38         /* don't allow disabling of DTSEC1 as its needed for MDIO */
  39         if (port == FM1_DTSEC1)
  40                 return;
  41
  42         setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  43 }
  44
  45 void fman_enable_port(enum fm_port port)
  46 {
  47         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  48
  49         clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  50 }
  51
  52 phy_interface_t fman_port_enet_if(enum fm_port port)
  53 {
  54         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  55         u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
  56
  57         if (is_device_disabled(port))
  58                 return PHY_INTERFACE_MODE_NONE;
  59
  60         if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
  61                 return PHY_INTERFACE_MODE_XGMII;
  62
  63         if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
  64                 return PHY_INTERFACE_MODE_XGMII;
  65
  66         /* handle RGMII first */
  67         if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
  68                 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
  69                 return PHY_INTERFACE_MODE_RGMII;
  70
  71         if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  72                 FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
  73                 return PHY_INTERFACE_MODE_RGMII;
  74
  75         if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  76                 FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
  77                 return PHY_INTERFACE_MODE_RGMII;
  78
  79         switch (port) {
  80         case FM1_DTSEC1:
  81         case FM1_DTSEC2:
  82         case FM1_DTSEC3:
  83         case FM1_DTSEC4:
  84                 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  85                         return PHY_INTERFACE_MODE_SGMII;
  86                 break;
  87         case FM2_DTSEC1:
  88         case FM2_DTSEC2:
  89         case FM2_DTSEC3:
  90         case FM2_DTSEC4:
  91                 if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
  92                         return PHY_INTERFACE_MODE_SGMII;
  93                 break;
  94         default:
  95                 return PHY_INTERFACE_MODE_NONE;
  96         }
  97
  98         return PHY_INTERFACE_MODE_NONE;
  99 }