]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/net/greth.c
1 /* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
3 * Driver use polling mode (no Interrupt)
6 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
8 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/processor.h>
24 /* Default to 3s timeout on autonegotiation */
25 #ifndef GRETH_PHY_TIMEOUT_MS
26 #define GRETH_PHY_TIMEOUT_MS 3000
29 /* Default to PHY adrress 0 not not specified */
30 #ifdef CONFIG_SYS_GRLIB_GRETH_PHYADDR
31 #define GRETH_PHY_ADR_DEFAULT CONFIG_SYS_GRLIB_GRETH_PHYADDR
33 #define GRETH_PHY_ADR_DEFAULT 0
36 /* ByPass Cache when reading regs */
37 #define GRETH_REGLOAD(addr) SPARC_NOCACHE_READ(addr)
38 /* Write-through cache ==> no bypassing needed on writes */
39 #define GRETH_REGSAVE(addr,data) (*(volatile unsigned int *)(addr) = (data))
40 #define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data)
41 #define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data)
43 #define GRETH_RXBD_CNT 4
44 #define GRETH_TXBD_CNT 1
46 #define GRETH_RXBUF_SIZE 1540
47 #define GRETH_BUF_ALIGN 4
48 #define GRETH_RXBUF_EFF_SIZE \
49 ( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN )
54 struct eth_device
*dev
;
57 unsigned char phyaddr
;
60 /* Current operating Mode */
62 int fd
; /* Full Duplex */
63 int sp
; /* 10/100Mbps speed (1=100,0=10) */
64 int auto_neg
; /* Auto negotiate done */
66 unsigned char hwaddr
[6]; /* MAC Address */
69 greth_bd
*rxbd_base
, *rxbd_max
;
70 greth_bd
*txbd_base
, *txbd_max
;
74 /* rx buffers in rx descriptors */
75 void *rxbuf_base
; /* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */
77 /* unused for gbit_mac, temp buffer for sending packets with unligned
79 * Pointer to packet allocated with malloc.
85 unsigned int rx_packets
,
86 rx_crc_errors
, rx_frame_errors
, rx_length_errors
, rx_errors
;
89 unsigned int tx_packets
,
91 tx_underrun_errors
, tx_limit_errors
, tx_errors
;
95 /* Read MII register 'addr' from core 'regs' */
96 static int read_mii(int phyaddr
, int regaddr
, volatile greth_regs
* regs
)
98 while (GRETH_REGLOAD(®s
->mdio
) & GRETH_MII_BUSY
) {
101 GRETH_REGSAVE(®s
->mdio
, ((phyaddr
& 0x1F) << 11) | ((regaddr
& 0x1F) << 6) | 2);
103 while (GRETH_REGLOAD(®s
->mdio
) & GRETH_MII_BUSY
) {
106 if (!(GRETH_REGLOAD(®s
->mdio
) & GRETH_MII_NVALID
)) {
107 return (GRETH_REGLOAD(®s
->mdio
) >> 16) & 0xFFFF;
113 static void write_mii(int phyaddr
, int regaddr
, int data
, volatile greth_regs
* regs
)
115 while (GRETH_REGLOAD(®s
->mdio
) & GRETH_MII_BUSY
) {
118 GRETH_REGSAVE(®s
->mdio
,
119 ((data
& 0xFFFF) << 16) | ((phyaddr
& 0x1F) << 11) |
120 ((regaddr
& 0x1F) << 6) | 1);
122 while (GRETH_REGLOAD(®s
->mdio
) & GRETH_MII_BUSY
) {
127 /* init/start hardware and allocate descriptor buffers for rx side
130 int greth_init(struct eth_device
*dev
, bd_t
* bis
)
134 greth_priv
*greth
= dev
->priv
;
135 greth_regs
*regs
= greth
->regs
;
137 debug("greth_init\n");
140 GRETH_REGSAVE(®s
->control
, (GRETH_RESET
| (greth
->gb
<< 8) |
141 (greth
->sp
<< 7) | (greth
->fd
<< 4)));
143 /* Wait for Reset to complete */
144 while ( GRETH_REGLOAD(®s
->control
) & GRETH_RESET
) ;
146 GRETH_REGSAVE(®s
->control
,
147 ((greth
->gb
<< 8) | (greth
->sp
<< 7) | (greth
->fd
<< 4)));
149 if (!greth
->rxbd_base
) {
151 /* allocate descriptors */
152 greth
->rxbd_base
= (greth_bd
*)
153 memalign(0x1000, GRETH_RXBD_CNT
* sizeof(greth_bd
));
154 greth
->txbd_base
= (greth_bd
*)
155 memalign(0x1000, GRETH_TXBD_CNT
* sizeof(greth_bd
));
157 /* allocate buffers to all descriptors */
159 malloc(GRETH_RXBUF_EFF_SIZE
* GRETH_RXBD_CNT
);
162 /* initate rx decriptors */
163 for (i
= 0; i
< GRETH_RXBD_CNT
; i
++) {
164 greth
->rxbd_base
[i
].addr
= (unsigned int)
165 greth
->rxbuf_base
+ (GRETH_RXBUF_EFF_SIZE
* i
);
166 /* enable desciptor & set wrap bit if last descriptor */
167 if (i
>= (GRETH_RXBD_CNT
- 1)) {
168 greth
->rxbd_base
[i
].stat
= GRETH_BD_EN
| GRETH_BD_WR
;
170 greth
->rxbd_base
[i
].stat
= GRETH_BD_EN
;
174 /* initiate indexes */
175 greth
->rxbd_curr
= greth
->rxbd_base
;
176 greth
->rxbd_max
= greth
->rxbd_base
+ (GRETH_RXBD_CNT
- 1);
177 greth
->txbd_max
= greth
->txbd_base
+ (GRETH_TXBD_CNT
- 1);
179 * greth->txbd_base->addr = 0;
180 * greth->txbd_base->stat = GRETH_BD_WR;
183 /* initate tx decriptors */
184 for (i
= 0; i
< GRETH_TXBD_CNT
; i
++) {
185 greth
->txbd_base
[i
].addr
= 0;
186 /* enable desciptor & set wrap bit if last descriptor */
187 if (i
>= (GRETH_TXBD_CNT
- 1)) {
188 greth
->txbd_base
[i
].stat
= GRETH_BD_WR
;
190 greth
->txbd_base
[i
].stat
= 0;
194 /**** SET HARDWARE REGS ****/
196 /* Set pointer to tx/rx descriptor areas */
197 GRETH_REGSAVE(®s
->rx_desc_p
, (unsigned int)&greth
->rxbd_base
[0]);
198 GRETH_REGSAVE(®s
->tx_desc_p
, (unsigned int)&greth
->txbd_base
[0]);
200 /* Enable Transmitter, GRETH will now scan descriptors for packets
202 debug("greth_init: enabling receiver\n");
203 GRETH_REGORIN(®s
->control
, GRETH_RXEN
);
208 /* Initiate PHY to a relevant speed
213 int greth_init_phy(greth_priv
* dev
, bd_t
* bis
)
215 greth_regs
*regs
= dev
->regs
;
216 int tmp
, tmp1
, tmp2
, i
;
217 unsigned int start
, timeout
;
218 int phyaddr
= GRETH_PHY_ADR_DEFAULT
;
220 #ifndef CONFIG_SYS_GRLIB_GRETH_PHYADDR
221 /* If BSP doesn't provide a hardcoded PHY address the driver will
222 * try to autodetect PHY address by stopping the search on the first
223 * PHY address which has REG0 implemented.
225 for (i
=0; i
<32; i
++) {
226 tmp
= read_mii(i
, 0, regs
);
227 if ( (tmp
!= 0) && (tmp
!= 0xffff) ) {
234 /* Save PHY Address */
235 dev
->phyaddr
= phyaddr
;
237 debug("GRETH PHY ADDRESS: %d\n", phyaddr
);
239 /* X msecs to ticks */
240 timeout
= usec2ticks(GRETH_PHY_TIMEOUT_MS
* 1000);
242 /* Get system timer0 current value
243 * Total timeout is 5s
245 start
= get_timer(0);
247 /* get phy control register default values */
249 while ((tmp
= read_mii(phyaddr
, 0, regs
)) & 0x8000) {
250 if (get_timer(start
) > timeout
) {
251 debug("greth_init_phy: PHY read 1 failed\n");
256 /* reset PHY and wait for completion */
257 write_mii(phyaddr
, 0, 0x8000 | tmp
, regs
);
259 while (((tmp
= read_mii(phyaddr
, 0, regs
))) & 0x8000) {
260 if (get_timer(start
) > timeout
) {
261 debug("greth_init_phy: PHY read 2 failed\n");
266 /* Check if PHY is autoneg capable and then determine operating
267 * mode, otherwise force it to 10 Mbit halfduplex
273 if (!((tmp
>> 12) & 1)) {
274 write_mii(phyaddr
, 0, 0, regs
);
276 /* wait for auto negotiation to complete and then check operating mode */
279 while (!(((tmp
= read_mii(phyaddr
, 1, regs
)) >> 5) & 1)) {
280 if (get_timer(start
) > timeout
) {
281 printf("Auto negotiation timed out. "
282 "Selecting default config\n");
283 tmp
= read_mii(phyaddr
, 0, regs
);
284 dev
->gb
= ((tmp
>> 6) & 1)
285 && !((tmp
>> 13) & 1);
286 dev
->sp
= !((tmp
>> 6) & 1)
287 && ((tmp
>> 13) & 1);
288 dev
->fd
= (tmp
>> 8) & 1;
292 if ((tmp
>> 8) & 1) {
293 tmp1
= read_mii(phyaddr
, 9, regs
);
294 tmp2
= read_mii(phyaddr
, 10, regs
);
295 if ((tmp1
& GRETH_MII_EXTADV_1000FD
) &&
296 (tmp2
& GRETH_MII_EXTPRT_1000FD
)) {
300 if ((tmp1
& GRETH_MII_EXTADV_1000HD
) &&
301 (tmp2
& GRETH_MII_EXTPRT_1000HD
)) {
306 if ((dev
->gb
== 0) || ((dev
->gb
== 1) && (dev
->gbit_mac
== 0))) {
307 tmp1
= read_mii(phyaddr
, 4, regs
);
308 tmp2
= read_mii(phyaddr
, 5, regs
);
309 if ((tmp1
& GRETH_MII_100TXFD
) &&
310 (tmp2
& GRETH_MII_100TXFD
)) {
314 if ((tmp1
& GRETH_MII_100TXHD
) &&
315 (tmp2
& GRETH_MII_100TXHD
)) {
319 if ((tmp1
& GRETH_MII_10FD
) && (tmp2
& GRETH_MII_10FD
)) {
322 if ((dev
->gb
== 1) && (dev
->gbit_mac
== 0)) {
325 write_mii(phyaddr
, 0, dev
->sp
<< 13, regs
);
331 debug("%s GRETH Ethermac at [0x%x] irq %d. Running \
332 %d Mbps %s duplex\n", dev
->gbit_mac
? "10/100/1000" : "10/100", (unsigned int)(regs
), (unsigned int)(dev
->irq
), dev
->gb
? 1000 : (dev
->sp
? 100 : 10), dev
->fd
? "full" : "half");
333 /* Read out PHY info if extended registers are available */
335 tmp1
= read_mii(phyaddr
, 2, regs
);
336 tmp2
= read_mii(phyaddr
, 3, regs
);
337 tmp1
= (tmp1
<< 6) | ((tmp2
>> 10) & 0x3F);
340 tmp2
= (tmp2
>> 4) & 0x3F;
341 debug("PHY: Vendor %x Device %x Revision %d\n", tmp1
,
344 printf("PHY info not available\n");
347 /* set speed and duplex bits in control register */
348 GRETH_REGORIN(®s
->control
,
349 (dev
->gb
<< 8) | (dev
->sp
<< 7) | (dev
->fd
<< 4));
354 void greth_halt(struct eth_device
*dev
)
360 debug("greth_halt\n");
362 if (!dev
|| !dev
->priv
)
371 /* disable receiver/transmitter by clearing the enable bits */
372 GRETH_REGANDIN(®s
->control
, ~(GRETH_RXEN
| GRETH_TXEN
));
374 /* reset rx/tx descriptors */
375 if (greth
->rxbd_base
) {
376 for (i
= 0; i
< GRETH_RXBD_CNT
; i
++) {
377 greth
->rxbd_base
[i
].stat
=
378 (i
>= (GRETH_RXBD_CNT
- 1)) ? GRETH_BD_WR
: 0;
382 if (greth
->txbd_base
) {
383 for (i
= 0; i
< GRETH_TXBD_CNT
; i
++) {
384 greth
->txbd_base
[i
].stat
=
385 (i
>= (GRETH_TXBD_CNT
- 1)) ? GRETH_BD_WR
: 0;
390 int greth_send(struct eth_device
*dev
, void *eth_data
, int data_length
)
392 greth_priv
*greth
= dev
->priv
;
393 greth_regs
*regs
= greth
->regs
;
398 debug("greth_send\n");
400 /* send data, wait for data to be sent, then return */
401 if (((unsigned int)eth_data
& (GRETH_BUF_ALIGN
- 1))
402 && !greth
->gbit_mac
) {
403 /* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer
404 * and copy data to before giving it to GRETH.
407 greth
->txbuf
= malloc(GRETH_RXBUF_SIZE
);
410 txbuf
= greth
->txbuf
;
412 /* copy data info buffer */
413 memcpy((char *)txbuf
, (char *)eth_data
, data_length
);
415 /* keep buffer to next time */
417 txbuf
= (void *)eth_data
;
419 /* get descriptor to use, only 1 supported... hehe easy */
420 txbd
= greth
->txbd_base
;
422 /* setup descriptor to wrap around to it self */
423 txbd
->addr
= (unsigned int)txbuf
;
424 txbd
->stat
= GRETH_BD_EN
| GRETH_BD_WR
| data_length
;
426 /* Remind Core which descriptor to use when sending */
427 GRETH_REGSAVE(®s
->tx_desc_p
, (unsigned int)txbd
);
429 /* initate send by enabling transmitter */
430 GRETH_REGORIN(®s
->control
, GRETH_TXEN
);
432 /* Wait for data to be sent */
433 while ((status
= GRETH_REGLOAD(&txbd
->stat
)) & GRETH_BD_EN
) {
437 /* was the packet transmitted succesfully? */
438 if (status
& GRETH_TXBD_ERR_AL
) {
439 greth
->stats
.tx_limit_errors
++;
442 if (status
& GRETH_TXBD_ERR_UE
) {
443 greth
->stats
.tx_underrun_errors
++;
446 if (status
& GRETH_TXBD_ERR_LC
) {
447 greth
->stats
.tx_latecol_errors
++;
451 (GRETH_TXBD_ERR_LC
| GRETH_TXBD_ERR_UE
| GRETH_TXBD_ERR_AL
)) {
453 greth
->stats
.tx_errors
++;
457 /* bump tx packet counter */
458 greth
->stats
.tx_packets
++;
460 /* return succefully */
464 int greth_recv(struct eth_device
*dev
)
466 greth_priv
*greth
= dev
->priv
;
467 greth_regs
*regs
= greth
->regs
;
469 unsigned int status
, len
= 0, bad
;
474 /* Receive One packet only, but clear as many error packets as there are
478 /* current receive descriptor */
479 rxbd
= greth
->rxbd_curr
;
481 /* get status of next received packet */
482 status
= GRETH_REGLOAD(&rxbd
->stat
);
486 /* stop if no more packets received */
487 if (status
& GRETH_BD_EN
) {
491 debug("greth_recv: packet 0x%x, 0x%x, len: %d\n",
492 (unsigned int)rxbd
, status
, status
& GRETH_BD_LEN
);
494 /* Check status for errors.
496 if (status
& GRETH_RXBD_ERR_FT
) {
497 greth
->stats
.rx_length_errors
++;
500 if (status
& (GRETH_RXBD_ERR_AE
| GRETH_RXBD_ERR_OE
)) {
501 greth
->stats
.rx_frame_errors
++;
504 if (status
& GRETH_RXBD_ERR_CRC
) {
505 greth
->stats
.rx_crc_errors
++;
509 greth
->stats
.rx_errors
++;
511 ("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n",
512 greth
->stats
.rx_length_errors
,
513 greth
->stats
.rx_frame_errors
,
514 greth
->stats
.rx_crc_errors
, status
,
515 greth
->stats
.rx_packets
);
516 /* print all rx descriptors */
517 for (i
= 0; i
< GRETH_RXBD_CNT
; i
++) {
518 printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i
,
519 GRETH_REGLOAD(&greth
->rxbd_base
[i
].stat
),
520 GRETH_REGLOAD(&greth
->rxbd_base
[i
].addr
));
523 /* Process the incoming packet. */
524 len
= status
& GRETH_BD_LEN
;
525 d
= (char *)rxbd
->addr
;
528 ("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",
529 len
, d
[0], d
[1], d
[2], d
[3], d
[4], d
[5], d
[6],
532 /* flush all data cache to make sure we're not reading old packet data */
533 sparc_dcache_flush_all();
535 /* pass packet on to network subsystem */
536 NetReceive((void *)d
, len
);
538 /* bump stats counters */
539 greth
->stats
.rx_packets
++;
541 /* bad is now 0 ==> will stop loop */
544 /* reenable descriptor to receive more packet with this descriptor, wrap around if needed */
547 (((unsigned int)greth
->rxbd_curr
>=
548 (unsigned int)greth
->rxbd_max
) ? GRETH_BD_WR
: 0);
553 ((unsigned int)greth
->rxbd_curr
>=
554 (unsigned int)greth
->rxbd_max
) ? greth
->
555 rxbd_base
: (greth
->rxbd_curr
+ 1);
560 GRETH_REGORIN(®s
->control
, GRETH_RXEN
);
563 /* return positive length of packet or 0 if non received */
567 void greth_set_hwaddr(greth_priv
* greth
, unsigned char *mac
)
569 /* save new MAC address */
570 greth
->dev
->enetaddr
[0] = greth
->hwaddr
[0] = mac
[0];
571 greth
->dev
->enetaddr
[1] = greth
->hwaddr
[1] = mac
[1];
572 greth
->dev
->enetaddr
[2] = greth
->hwaddr
[2] = mac
[2];
573 greth
->dev
->enetaddr
[3] = greth
->hwaddr
[3] = mac
[3];
574 greth
->dev
->enetaddr
[4] = greth
->hwaddr
[4] = mac
[4];
575 greth
->dev
->enetaddr
[5] = greth
->hwaddr
[5] = mac
[5];
576 greth
->regs
->esa_msb
= (mac
[0] << 8) | mac
[1];
577 greth
->regs
->esa_lsb
=
578 (mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5];
580 debug("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
581 mac
[0], mac
[1], mac
[2], mac
[3], mac
[4], mac
[5]);
584 int greth_initialize(bd_t
* bis
)
587 ambapp_apbdev apbdev
;
588 struct eth_device
*dev
;
590 char *addr_str
, *end
;
591 unsigned char addr
[6];
593 debug("Scanning for GRETH\n");
595 /* Find Device & IRQ via AMBA Plug&Play information */
596 if (ambapp_apb_first(VENDOR_GAISLER
, GAISLER_ETHMAC
, &apbdev
) != 1) {
597 return -1; /* GRETH not found */
600 greth
= (greth_priv
*) malloc(sizeof(greth_priv
));
601 dev
= (struct eth_device
*)malloc(sizeof(struct eth_device
));
602 memset(dev
, 0, sizeof(struct eth_device
));
603 memset(greth
, 0, sizeof(greth_priv
));
605 greth
->regs
= (greth_regs
*) apbdev
.address
;
606 greth
->irq
= apbdev
.irq
;
607 debug("Found GRETH at %p, irq %d\n", greth
->regs
, greth
->irq
);
608 dev
->priv
= (void *)greth
;
609 dev
->iobase
= (unsigned int)greth
->regs
;
610 dev
->init
= greth_init
;
611 dev
->halt
= greth_halt
;
612 dev
->send
= greth_send
;
613 dev
->recv
= greth_recv
;
617 GRETH_REGSAVE(&greth
->regs
->control
, GRETH_RESET
);
619 /* Wait for core to finish reset cycle */
620 while (GRETH_REGLOAD(&greth
->regs
->control
) & GRETH_RESET
) ;
622 /* Get the phy address which assumed to have been set
623 correctly with the reset value in hardware */
624 greth
->phyaddr
= (GRETH_REGLOAD(&greth
->regs
->mdio
) >> 11) & 0x1F;
626 /* Check if mac is gigabit capable */
627 greth
->gbit_mac
= (GRETH_REGLOAD(&greth
->regs
->control
) >> 27) & 1;
629 /* Make descriptor string */
630 if (greth
->gbit_mac
) {
631 sprintf(dev
->name
, "GRETH_10/100/GB");
633 sprintf(dev
->name
, "GRETH_10/100");
636 /* initiate PHY, select speed/duplex depending on connected PHY */
637 if (greth_init_phy(greth
, bis
)) {
638 /* Failed to init PHY (timedout) */
639 debug("GRETH[%p]: Failed to init PHY\n", greth
->regs
);
643 /* Register Device to EtherNet subsystem */
646 /* Get MAC address */
647 if ((addr_str
= getenv("ethaddr")) != NULL
) {
648 for (i
= 0; i
< 6; i
++) {
650 addr_str
? simple_strtoul(addr_str
, &end
, 16) : 0;
652 addr_str
= (*end
) ? end
+ 1 : end
;
656 /* HW Address not found in environment, Set default HW address */
657 addr
[0] = GRETH_HWADDR_0
; /* MSB */
658 addr
[1] = GRETH_HWADDR_1
;
659 addr
[2] = GRETH_HWADDR_2
;
660 addr
[3] = GRETH_HWADDR_3
;
661 addr
[4] = GRETH_HWADDR_4
;
662 addr
[5] = GRETH_HWADDR_5
; /* LSB */
665 /* set and remember MAC address */
666 greth_set_hwaddr(greth
, addr
);
668 debug("GRETH[%p]: Initialized successfully\n", greth
->regs
);