drivers/net/greth.c

   1 /* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
   2  *
   3  * Driver use polling mode (no Interrupt)
   4  *
   5  * (C) Copyright 2007
   6  * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /* #define DEBUG */
  28
  29 #include <common.h>
  30 #include <command.h>
  31 #include <net.h>
  32 #include <netdev.h>
  33 #include <malloc.h>
  34 #include <asm/processor.h>
  35 #include <ambapp.h>
  36 #include <asm/leon.h>
  37
  38 #include "greth.h"
  39
  40 /* Default to 3s timeout on autonegotiation */
  41 #ifndef GRETH_PHY_TIMEOUT_MS
  42 #define GRETH_PHY_TIMEOUT_MS 3000
  43 #endif
  44
  45 /* ByPass Cache when reading regs */
  46 #define GRETH_REGLOAD(addr)             SPARC_NOCACHE_READ(addr)
  47 /* Write-through cache ==> no bypassing needed on writes */
  48 #define GRETH_REGSAVE(addr,data) (*(volatile unsigned int *)(addr) = (data))
  49 #define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data)
  50 #define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data)
  51
  52 #define GRETH_RXBD_CNT 4
  53 #define GRETH_TXBD_CNT 1
  54
  55 #define GRETH_RXBUF_SIZE 1540
  56 #define GRETH_BUF_ALIGN 4
  57 #define GRETH_RXBUF_EFF_SIZE \
  58         ( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN )
  59
  60 typedef struct {
  61         greth_regs *regs;
  62         int irq;
  63         struct eth_device *dev;
  64
  65         /* Hardware info */
  66         unsigned char phyaddr;
  67         int gbit_mac;
  68
  69         /* Current operating Mode */
  70         int gb;                 /* GigaBit */
  71         int fd;                 /* Full Duplex */
  72         int sp;                 /* 10/100Mbps speed (1=100,0=10) */
  73         int auto_neg;           /* Auto negotiate done */
  74
  75         unsigned char hwaddr[6];        /* MAC Address */
  76
  77         /* Descriptors */
  78         greth_bd *rxbd_base, *rxbd_max;
  79         greth_bd *txbd_base, *txbd_max;
  80
  81         greth_bd *rxbd_curr;
  82
  83         /* rx buffers in rx descriptors */
  84         void *rxbuf_base;       /* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */
  85
  86         /* unused for gbit_mac, temp buffer for sending packets with unligned
  87          * start.
  88          * Pointer to packet allocated with malloc.
  89          */
  90         void *txbuf;
  91
  92         struct {
  93                 /* rx status */
  94                 unsigned int rx_packets,
  95                     rx_crc_errors, rx_frame_errors, rx_length_errors, rx_errors;
  96
  97                 /* tx stats */
  98                 unsigned int tx_packets,
  99                     tx_latecol_errors,
 100                     tx_underrun_errors, tx_limit_errors, tx_errors;
 101         } stats;
 102 } greth_priv;
 103
 104 /* Read MII register 'addr' from core 'regs' */
 105 static int read_mii(int addr, volatile greth_regs * regs)
 106 {
 107         while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
 108         }
 109
 110         GRETH_REGSAVE(&regs->mdio, (0 << 11) | ((addr & 0x1F) << 6) | 2);
 111
 112         while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
 113         }
 114
 115         if (!(GRETH_REGLOAD(&regs->mdio) & GRETH_MII_NVALID)) {
 116                 return (GRETH_REGLOAD(&regs->mdio) >> 16) & 0xFFFF;
 117         } else {
 118                 return -1;
 119         }
 120 }
 121
 122 static void write_mii(int addr, int data, volatile greth_regs * regs)
 123 {
 124         while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
 125         }
 126
 127         GRETH_REGSAVE(&regs->mdio,
 128                       ((data & 0xFFFF) << 16) | (0 << 11) | ((addr & 0x1F) << 6)
 129                       | 1);
 130
 131         while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
 132         }
 133
 134 }
 135
 136 /* init/start hardware and allocate descriptor buffers for rx side
 137  *
 138  */
 139 int greth_init(struct eth_device *dev, bd_t * bis)
 140 {
 141         int i;
 142
 143         greth_priv *greth = dev->priv;
 144         greth_regs *regs = greth->regs;
 145
 146         debug("greth_init\n");
 147
 148         if (!greth->rxbd_base) {
 149
 150                 /* allocate descriptors */
 151                 greth->rxbd_base = (greth_bd *)
 152                     memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
 153                 greth->txbd_base = (greth_bd *)
 154                     memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
 155
 156                 /* allocate buffers to all descriptors  */
 157                 greth->rxbuf_base =
 158                     malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT);
 159         }
 160
 161         /* initate rx decriptors */
 162         for (i = 0; i < GRETH_RXBD_CNT; i++) {
 163                 greth->rxbd_base[i].addr = (unsigned int)
 164                     greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE * i);
 165                 /* enable desciptor & set wrap bit if last descriptor */
 166                 if (i >= (GRETH_RXBD_CNT - 1)) {
 167                         greth->rxbd_base[i].stat = GRETH_BD_EN | GRETH_BD_WR;
 168                 } else {
 169                         greth->rxbd_base[i].stat = GRETH_BD_EN;
 170                 }
 171         }
 172
 173         /* initiate indexes */
 174         greth->rxbd_curr = greth->rxbd_base;
 175         greth->rxbd_max = greth->rxbd_base + (GRETH_RXBD_CNT - 1);
 176         greth->txbd_max = greth->txbd_base + (GRETH_TXBD_CNT - 1);
 177         /*
 178          * greth->txbd_base->addr = 0;
 179          * greth->txbd_base->stat = GRETH_BD_WR;
 180          */
 181
 182         /* initate tx decriptors */
 183         for (i = 0; i < GRETH_TXBD_CNT; i++) {
 184                 greth->txbd_base[i].addr = 0;
 185                 /* enable desciptor & set wrap bit if last descriptor */
 186                 if (i >= (GRETH_RXBD_CNT - 1)) {
 187                         greth->txbd_base[i].stat = GRETH_BD_WR;
 188                 } else {
 189                         greth->txbd_base[i].stat = 0;
 190                 }
 191         }
 192
 193         /**** SET HARDWARE REGS ****/
 194
 195         /* Set pointer to tx/rx descriptor areas */
 196         GRETH_REGSAVE(&regs->rx_desc_p, (unsigned int)&greth->rxbd_base[0]);
 197         GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)&greth->txbd_base[0]);
 198
 199         /* Enable Transmitter, GRETH will now scan descriptors for packets
 200          * to transmitt */
 201         debug("greth_init: enabling receiver\n");
 202         GRETH_REGORIN(&regs->control, GRETH_RXEN);
 203
 204         return 0;
 205 }
 206
 207 /* Initiate PHY to a relevant speed
 208  * return:
 209  *  - 0 = success
 210  *  - 1 = timeout/fail
 211  */
 212 int greth_init_phy(greth_priv * dev, bd_t * bis)
 213 {
 214         greth_regs *regs = dev->regs;
 215         int tmp, tmp1, tmp2, i;
 216         unsigned int start, timeout;
 217
 218         /* X msecs to ticks */
 219         timeout = usec2ticks(GRETH_PHY_TIMEOUT_MS * 1000);
 220
 221         /* Get system timer0 current value
 222          * Total timeout is 5s
 223          */
 224         start = get_timer(0);
 225
 226         /* get phy control register default values */
 227
 228         while ((tmp = read_mii(0, regs)) & 0x8000) {
 229                 if (get_timer(start) > timeout)
 230                         return 1;       /* Fail */
 231         }
 232
 233         /* reset PHY and wait for completion */
 234         write_mii(0, 0x8000 | tmp, regs);
 235
 236         while (((tmp = read_mii(0, regs))) & 0x8000) {
 237                 if (get_timer(start) > timeout)
 238                         return 1;       /* Fail */
 239         }
 240
 241         /* Check if PHY is autoneg capable and then determine operating
 242          * mode, otherwise force it to 10 Mbit halfduplex
 243          */
 244         dev->gb = 0;
 245         dev->fd = 0;
 246         dev->sp = 0;
 247         dev->auto_neg = 0;
 248         if (!((tmp >> 12) & 1)) {
 249                 write_mii(0, 0, regs);
 250         } else {
 251                 /* wait for auto negotiation to complete and then check operating mode */
 252                 dev->auto_neg = 1;
 253                 i = 0;
 254                 while (!(((tmp = read_mii(1, regs)) >> 5) & 1)) {
 255                         if (get_timer(start) > timeout) {
 256                                 printf("Auto negotiation timed out. "
 257                                        "Selecting default config\n");
 258                                 tmp = read_mii(0, regs);
 259                                 dev->gb = ((tmp >> 6) & 1)
 260                                     && !((tmp >> 13) & 1);
 261                                 dev->sp = !((tmp >> 6) & 1)
 262                                     && ((tmp >> 13) & 1);
 263                                 dev->fd = (tmp >> 8) & 1;
 264                                 goto auto_neg_done;
 265                         }
 266                 }
 267                 if ((tmp >> 8) & 1) {
 268                         tmp1 = read_mii(9, regs);
 269                         tmp2 = read_mii(10, regs);
 270                         if ((tmp1 & GRETH_MII_EXTADV_1000FD) &&
 271                             (tmp2 & GRETH_MII_EXTPRT_1000FD)) {
 272                                 dev->gb = 1;
 273                                 dev->fd = 1;
 274                         }
 275                         if ((tmp1 & GRETH_MII_EXTADV_1000HD) &&
 276                             (tmp2 & GRETH_MII_EXTPRT_1000HD)) {
 277                                 dev->gb = 1;
 278                                 dev->fd = 0;
 279                         }
 280                 }
 281                 if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) {
 282                         tmp1 = read_mii(4, regs);
 283                         tmp2 = read_mii(5, regs);
 284                         if ((tmp1 & GRETH_MII_100TXFD) &&
 285                             (tmp2 & GRETH_MII_100TXFD)) {
 286                                 dev->sp = 1;
 287                                 dev->fd = 1;
 288                         }
 289                         if ((tmp1 & GRETH_MII_100TXHD) &&
 290                             (tmp2 & GRETH_MII_100TXHD)) {
 291                                 dev->sp = 1;
 292                                 dev->fd = 0;
 293                         }
 294                         if ((tmp1 & GRETH_MII_10FD) && (tmp2 & GRETH_MII_10FD)) {
 295                                 dev->fd = 1;
 296                         }
 297                         if ((dev->gb == 1) && (dev->gbit_mac == 0)) {
 298                                 dev->gb = 0;
 299                                 dev->fd = 0;
 300                                 write_mii(0, dev->sp << 13, regs);
 301                         }
 302                 }
 303
 304         }
 305       auto_neg_done:
 306         debug("%s GRETH Ethermac at [0x%x] irq %d. Running \
 307                 %d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half");
 308         /* Read out PHY info if extended registers are available */
 309         if (tmp & 1) {
 310                 tmp1 = read_mii(2, regs);
 311                 tmp2 = read_mii(3, regs);
 312                 tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F);
 313                 tmp = tmp2 & 0xF;
 314
 315                 tmp2 = (tmp2 >> 4) & 0x3F;
 316                 debug("PHY: Vendor %x   Device %x    Revision %d\n", tmp1,
 317                        tmp2, tmp);
 318         } else {
 319                 printf("PHY info not available\n");
 320         }
 321
 322         /* set speed and duplex bits in control register */
 323         GRETH_REGORIN(&regs->control,
 324                       (dev->gb << 8) | (dev->sp << 7) | (dev->fd << 4));
 325
 326         return 0;
 327 }
 328
 329 void greth_halt(struct eth_device *dev)
 330 {
 331         greth_priv *greth;
 332         greth_regs *regs;
 333         int i;
 334
 335         debug("greth_halt\n");
 336
 337         if (!dev || !dev->priv)
 338                 return;
 339
 340         greth = dev->priv;
 341         regs = greth->regs;
 342
 343         if (!regs)
 344                 return;
 345
 346         /* disable receiver/transmitter by clearing the enable bits */
 347         GRETH_REGANDIN(&regs->control, ~(GRETH_RXEN | GRETH_TXEN));
 348
 349         /* reset rx/tx descriptors */
 350         if (greth->rxbd_base) {
 351                 for (i = 0; i < GRETH_RXBD_CNT; i++) {
 352                         greth->rxbd_base[i].stat =
 353                             (i >= (GRETH_RXBD_CNT - 1)) ? GRETH_BD_WR : 0;
 354                 }
 355         }
 356
 357         if (greth->txbd_base) {
 358                 for (i = 0; i < GRETH_TXBD_CNT; i++) {
 359                         greth->txbd_base[i].stat =
 360                             (i >= (GRETH_TXBD_CNT - 1)) ? GRETH_BD_WR : 0;
 361                 }
 362         }
 363 }
 364
 365 int greth_send(struct eth_device *dev, volatile void *eth_data, int data_length)
 366 {
 367         greth_priv *greth = dev->priv;
 368         greth_regs *regs = greth->regs;
 369         greth_bd *txbd;
 370         void *txbuf;
 371         unsigned int status;
 372
 373         debug("greth_send\n");
 374
 375         /* send data, wait for data to be sent, then return */
 376         if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1))
 377             && !greth->gbit_mac) {
 378                 /* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer
 379                  * and copy data to before giving it to GRETH.
 380                  */
 381                 if (!greth->txbuf) {
 382                         greth->txbuf = malloc(GRETH_RXBUF_SIZE);
 383                 }
 384
 385                 txbuf = greth->txbuf;
 386
 387                 /* copy data info buffer */
 388                 memcpy((char *)txbuf, (char *)eth_data, data_length);
 389
 390                 /* keep buffer to next time */
 391         } else {
 392                 txbuf = (void *)eth_data;
 393         }
 394         /* get descriptor to use, only 1 supported... hehe easy */
 395         txbd = greth->txbd_base;
 396
 397         /* setup descriptor to wrap around to it self */
 398         txbd->addr = (unsigned int)txbuf;
 399         txbd->stat = GRETH_BD_EN | GRETH_BD_WR | data_length;
 400
 401         /* Remind Core which descriptor to use when sending */
 402         GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)txbd);
 403
 404         /* initate send by enabling transmitter */
 405         GRETH_REGORIN(&regs->control, GRETH_TXEN);
 406
 407         /* Wait for data to be sent */
 408         while ((status = GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN) {
 409                 ;
 410         }
 411
 412         /* was the packet transmitted succesfully? */
 413         if (status & GRETH_TXBD_ERR_AL) {
 414                 greth->stats.tx_limit_errors++;
 415         }
 416
 417         if (status & GRETH_TXBD_ERR_UE) {
 418                 greth->stats.tx_underrun_errors++;
 419         }
 420
 421         if (status & GRETH_TXBD_ERR_LC) {
 422                 greth->stats.tx_latecol_errors++;
 423         }
 424
 425         if (status &
 426             (GRETH_TXBD_ERR_LC | GRETH_TXBD_ERR_UE | GRETH_TXBD_ERR_AL)) {
 427                 /* any error */
 428                 greth->stats.tx_errors++;
 429                 return -1;
 430         }
 431
 432         /* bump tx packet counter */
 433         greth->stats.tx_packets++;
 434
 435         /* return succefully */
 436         return 0;
 437 }
 438
 439 int greth_recv(struct eth_device *dev)
 440 {
 441         greth_priv *greth = dev->priv;
 442         greth_regs *regs = greth->regs;
 443         greth_bd *rxbd;
 444         unsigned int status, len = 0, bad;
 445         unsigned char *d;
 446         int enable = 0;
 447         int i;
 448
 449         /* Receive One packet only, but clear as many error packets as there are
 450          * available.
 451          */
 452         {
 453                 /* current receive descriptor */
 454                 rxbd = greth->rxbd_curr;
 455
 456                 /* get status of next received packet */
 457                 status = GRETH_REGLOAD(&rxbd->stat);
 458
 459                 bad = 0;
 460
 461                 /* stop if no more packets received */
 462                 if (status & GRETH_BD_EN) {
 463                         goto done;
 464                 }
 465
 466                 debug("greth_recv: packet 0x%lx, 0x%lx, len: %d\n",
 467                        (unsigned int)rxbd, status, status & GRETH_BD_LEN);
 468
 469                 /* Check status for errors.
 470                  */
 471                 if (status & GRETH_RXBD_ERR_FT) {
 472                         greth->stats.rx_length_errors++;
 473                         bad = 1;
 474                 }
 475                 if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) {
 476                         greth->stats.rx_frame_errors++;
 477                         bad = 1;
 478                 }
 479                 if (status & GRETH_RXBD_ERR_CRC) {
 480                         greth->stats.rx_crc_errors++;
 481                         bad = 1;
 482                 }
 483                 if (bad) {
 484                         greth->stats.rx_errors++;
 485                         printf
 486                             ("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n",
 487                              greth->stats.rx_length_errors,
 488                              greth->stats.rx_frame_errors,
 489                              greth->stats.rx_crc_errors, status,
 490                              greth->stats.rx_packets);
 491                         /* print all rx descriptors */
 492                         for (i = 0; i < GRETH_RXBD_CNT; i++) {
 493                                 printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i,
 494                                        GRETH_REGLOAD(&greth->rxbd_base[i].stat),
 495                                        GRETH_REGLOAD(&greth->rxbd_base[i].
 496                                                      addr));
 497                         }
 498                 } else {
 499                         /* Process the incoming packet. */
 500                         len = status & GRETH_BD_LEN;
 501                         d = (char *)rxbd->addr;
 502
 503                         debug
 504                             ("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",
 505                              len, d[0], d[1], d[2], d[3], d[4], d[5], d[6],
 506                              d[7]);
 507
 508                         /* flush all data cache to make sure we're not reading old packet data */
 509                         sparc_dcache_flush_all();
 510
 511                         /* pass packet on to network subsystem */
 512                         NetReceive((void *)d, len);
 513
 514                         /* bump stats counters */
 515                         greth->stats.rx_packets++;
 516
 517                         /* bad is now 0 ==> will stop loop */
 518                 }
 519
 520                 /* reenable descriptor to receive more packet with this descriptor, wrap around if needed */
 521                 rxbd->stat =
 522                     GRETH_BD_EN |
 523                     (((unsigned int)greth->rxbd_curr >=
 524                       (unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0);
 525                 enable = 1;
 526
 527                 /* increase index */
 528                 greth->rxbd_curr =
 529                     ((unsigned int)greth->rxbd_curr >=
 530                      (unsigned int)greth->rxbd_max) ? greth->
 531                     rxbd_base : (greth->rxbd_curr + 1);
 532
 533         };
 534
 535         if (enable) {
 536                 GRETH_REGORIN(&regs->control, GRETH_RXEN);
 537         }
 538       done:
 539         /* return positive length of packet or 0 if non recieved */
 540         return len;
 541 }
 542
 543 void greth_set_hwaddr(greth_priv * greth, unsigned char *mac)
 544 {
 545         /* save new MAC address */
 546         greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0];
 547         greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1];
 548         greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2];
 549         greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3];
 550         greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4];
 551         greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5];
 552         greth->regs->esa_msb = (mac[0] << 8) | mac[1];
 553         greth->regs->esa_lsb =
 554             (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
 555
 556         debug("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
 557                mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 558 }
 559
 560 int greth_initialize(bd_t * bis)
 561 {
 562         greth_priv *greth;
 563         ambapp_apbdev apbdev;
 564         struct eth_device *dev;
 565         int i;
 566         char *addr_str, *end;
 567         unsigned char addr[6];
 568
 569         debug("Scanning for GRETH\n");
 570
 571         /* Find Device & IRQ via AMBA Plug&Play information */
 572         if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_ETHMAC, &apbdev) != 1) {
 573                 return -1;      /* GRETH not found */
 574         }
 575
 576         greth = (greth_priv *) malloc(sizeof(greth_priv));
 577         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 578         memset(dev, 0, sizeof(struct eth_device));
 579         memset(greth, 0, sizeof(greth_priv));
 580
 581         greth->regs = (greth_regs *) apbdev.address;
 582         greth->irq = apbdev.irq;
 583         debug("Found GRETH at 0x%lx, irq %d\n", greth->regs, greth->irq);
 584         dev->priv = (void *)greth;
 585         dev->iobase = (unsigned int)greth->regs;
 586         dev->init = greth_init;
 587         dev->halt = greth_halt;
 588         dev->send = greth_send;
 589         dev->recv = greth_recv;
 590         greth->dev = dev;
 591
 592         /* Reset Core */
 593         GRETH_REGSAVE(&greth->regs->control, GRETH_RESET);
 594
 595         /* Wait for core to finish reset cycle */
 596         while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) ;
 597
 598         /* Get the phy address which assumed to have been set
 599            correctly with the reset value in hardware */
 600         greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F;
 601
 602         /* Check if mac is gigabit capable */
 603         greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1;
 604
 605         /* Make descriptor string */
 606         if (greth->gbit_mac) {
 607                 sprintf(dev->name, "GRETH 10/100/GB");
 608         } else {
 609                 sprintf(dev->name, "GRETH 10/100");
 610         }
 611
 612         /* initiate PHY, select speed/duplex depending on connected PHY */
 613         if (greth_init_phy(greth, bis)) {
 614                 /* Failed to init PHY (timedout) */
 615                 return -1;
 616         }
 617
 618         /* Register Device to EtherNet subsystem  */
 619         eth_register(dev);
 620
 621         /* Get MAC address */
 622         if ((addr_str = getenv("ethaddr")) != NULL) {
 623                 for (i = 0; i < 6; i++) {
 624                         addr[i] =
 625                             addr_str ? simple_strtoul(addr_str, &end, 16) : 0;
 626                         if (addr_str) {
 627                                 addr_str = (*end) ? end + 1 : end;
 628                         }
 629                 }
 630         } else {
 631                 /* HW Address not found in environment, Set default HW address */
 632                 addr[0] = GRETH_HWADDR_0;       /* MSB */
 633                 addr[1] = GRETH_HWADDR_1;
 634                 addr[2] = GRETH_HWADDR_2;
 635                 addr[3] = GRETH_HWADDR_3;
 636                 addr[4] = GRETH_HWADDR_4;
 637                 addr[5] = GRETH_HWADDR_5;       /* LSB */
 638         }
 639
 640         /* set and remember MAC address */
 641         greth_set_hwaddr(greth, addr);
 642
 643         return 0;
 644 }