drivers/net/higmacv300.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019, Linaro Limited
   4  */
   5
   6 #include <cpu_func.h>
   7 #include <malloc.h>
   8 #include <asm/io.h>
   9 #include <common.h>
  10 #include <console.h>
  11 #include <linux/bug.h>
  12 #include <linux/mii.h>
  13 #include <miiphy.h>
  14 #include <net.h>
  15 #include <reset.h>
  16 #include <wait_bit.h>
  17
  18 #define STATION_ADDR_LOW                0x0000
  19 #define STATION_ADDR_HIGH               0x0004
  20 #define MAC_DUPLEX_HALF_CTRL            0x0008
  21 #define PORT_MODE                       0x0040
  22 #define PORT_EN                         0x0044
  23 #define BIT_TX_EN                       BIT(2)
  24 #define BIT_RX_EN                       BIT(1)
  25 #define MODE_CHANGE_EN                  0x01b4
  26 #define BIT_MODE_CHANGE_EN              BIT(0)
  27 #define MDIO_SINGLE_CMD                 0x03c0
  28 #define BIT_MDIO_BUSY                   BIT(20)
  29 #define MDIO_READ                       (BIT(17) | BIT_MDIO_BUSY)
  30 #define MDIO_WRITE                      (BIT(16) | BIT_MDIO_BUSY)
  31 #define MDIO_SINGLE_DATA                0x03c4
  32 #define MDIO_RDATA_STATUS               0x03d0
  33 #define BIT_MDIO_RDATA_INVALID          BIT(0)
  34 #define RX_FQ_START_ADDR                0x0500
  35 #define RX_FQ_DEPTH                     0x0504
  36 #define RX_FQ_WR_ADDR                   0x0508
  37 #define RX_FQ_RD_ADDR                   0x050c
  38 #define RX_FQ_REG_EN                    0x0518
  39 #define RX_BQ_START_ADDR                0x0520
  40 #define RX_BQ_DEPTH                     0x0524
  41 #define RX_BQ_WR_ADDR                   0x0528
  42 #define RX_BQ_RD_ADDR                   0x052c
  43 #define RX_BQ_REG_EN                    0x0538
  44 #define TX_BQ_START_ADDR                0x0580
  45 #define TX_BQ_DEPTH                     0x0584
  46 #define TX_BQ_WR_ADDR                   0x0588
  47 #define TX_BQ_RD_ADDR                   0x058c
  48 #define TX_BQ_REG_EN                    0x0598
  49 #define TX_RQ_START_ADDR                0x05a0
  50 #define TX_RQ_DEPTH                     0x05a4
  51 #define TX_RQ_WR_ADDR                   0x05a8
  52 #define TX_RQ_RD_ADDR                   0x05ac
  53 #define TX_RQ_REG_EN                    0x05b8
  54 #define BIT_START_ADDR_EN               BIT(2)
  55 #define BIT_DEPTH_EN                    BIT(1)
  56 #define DESC_WR_RD_ENA                  0x05cc
  57 #define BIT_RX_OUTCFF_WR                BIT(3)
  58 #define BIT_RX_CFF_RD                   BIT(2)
  59 #define BIT_TX_OUTCFF_WR                BIT(1)
  60 #define BIT_TX_CFF_RD                   BIT(0)
  61 #define BITS_DESC_ENA                   (BIT_RX_OUTCFF_WR | BIT_RX_CFF_RD | \
  62                                          BIT_TX_OUTCFF_WR | BIT_TX_CFF_RD)
  63
  64 /* MACIF_CTRL */
  65 #define RGMII_SPEED_1000                0x2c
  66 #define RGMII_SPEED_100                 0x2f
  67 #define RGMII_SPEED_10                  0x2d
  68 #define MII_SPEED_100                   0x0f
  69 #define MII_SPEED_10                    0x0d
  70 #define GMAC_SPEED_1000                 0x05
  71 #define GMAC_SPEED_100                  0x01
  72 #define GMAC_SPEED_10                   0x00
  73 #define GMAC_FULL_DUPLEX                BIT(4)
  74
  75 #define RX_DESC_NUM                     64
  76 #define TX_DESC_NUM                     2
  77 #define DESC_SIZE                       32
  78 #define DESC_WORD_SHIFT                 3
  79 #define DESC_BYTE_SHIFT                 5
  80 #define DESC_CNT(n)                     ((n) >> DESC_BYTE_SHIFT)
  81 #define DESC_BYTE(n)                    ((n) << DESC_BYTE_SHIFT)
  82 #define DESC_VLD_FREE                   0
  83 #define DESC_VLD_BUSY                   1
  84
  85 #define MAC_MAX_FRAME_SIZE              1600
  86
  87 enum higmac_queue {
  88         RX_FQ,
  89         RX_BQ,
  90         TX_BQ,
  91         TX_RQ,
  92 };
  93
  94 struct higmac_desc {
  95         unsigned int buf_addr;
  96         unsigned int buf_len:11;
  97         unsigned int reserve0:5;
  98         unsigned int data_len:11;
  99         unsigned int reserve1:2;
 100         unsigned int fl:2;
 101         unsigned int descvid:1;
 102         unsigned int reserve2[6];
 103 };
 104
 105 struct higmac_priv {
 106         void __iomem *base;
 107         void __iomem *macif_ctrl;
 108         struct reset_ctl rst_phy;
 109         struct higmac_desc *rxfq;
 110         struct higmac_desc *rxbq;
 111         struct higmac_desc *txbq;
 112         struct higmac_desc *txrq;
 113         int rxdesc_in_use;
 114         struct mii_dev *bus;
 115         struct phy_device *phydev;
 116         int phyintf;
 117         int phyaddr;
 118 };
 119
 120 #define flush_desc(d) flush_cache((unsigned long)(d), sizeof(*(d)))
 121 #define invalidate_desc(d) \
 122         invalidate_dcache_range((unsigned long)(d), \
 123                                 (unsigned long)(d) + sizeof(*(d)))
 124
 125 static int higmac_write_hwaddr(struct udevice *dev)
 126 {
 127         struct eth_pdata *pdata = dev_get_platdata(dev);
 128         struct higmac_priv *priv = dev_get_priv(dev);
 129         unsigned char *mac = pdata->enetaddr;
 130         u32 val;
 131
 132         val = mac[1] | (mac[0] << 8);
 133         writel(val, priv->base + STATION_ADDR_HIGH);
 134
 135         val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
 136         writel(val, priv->base + STATION_ADDR_LOW);
 137
 138         return 0;
 139 }
 140
 141 static int higmac_free_pkt(struct udevice *dev, uchar *packet, int length)
 142 {
 143         struct higmac_priv *priv = dev_get_priv(dev);
 144
 145         /* Inform GMAC that the RX descriptor is no longer in use */
 146         writel(DESC_BYTE(priv->rxdesc_in_use), priv->base + RX_BQ_RD_ADDR);
 147
 148         return 0;
 149 }
 150
 151 static int higmac_recv(struct udevice *dev, int flags, uchar **packetp)
 152 {
 153         struct higmac_priv *priv = dev_get_priv(dev);
 154         struct higmac_desc *fqd = priv->rxfq;
 155         struct higmac_desc *bqd = priv->rxbq;
 156         int fqw_pos, fqr_pos, bqw_pos, bqr_pos;
 157         int timeout = 100000;
 158         int len = 0;
 159         int space;
 160         int i;
 161
 162         fqw_pos = DESC_CNT(readl(priv->base + RX_FQ_WR_ADDR));
 163         fqr_pos = DESC_CNT(readl(priv->base + RX_FQ_RD_ADDR));
 164
 165         if (fqw_pos >= fqr_pos)
 166                 space = RX_DESC_NUM - (fqw_pos - fqr_pos);
 167         else
 168                 space = fqr_pos - fqw_pos;
 169
 170         /* Leave one free to distinguish full filled from empty buffer */
 171         for (i = 0; i < space - 1; i++) {
 172                 fqd = priv->rxfq + fqw_pos;
 173                 invalidate_dcache_range(fqd->buf_addr,
 174                                         fqd->buf_addr + MAC_MAX_FRAME_SIZE);
 175
 176                 if (++fqw_pos >= RX_DESC_NUM)
 177                         fqw_pos = 0;
 178
 179                 writel(DESC_BYTE(fqw_pos), priv->base + RX_FQ_WR_ADDR);
 180         }
 181
 182         bqr_pos = DESC_CNT(readl(priv->base + RX_BQ_RD_ADDR));
 183         bqd += bqr_pos;
 184         /* BQ is only ever written by GMAC */
 185         invalidate_desc(bqd);
 186
 187         do {
 188                 bqw_pos = DESC_CNT(readl(priv->base + RX_BQ_WR_ADDR));
 189                 udelay(1);
 190         } while (--timeout && bqw_pos == bqr_pos);
 191
 192         if (!timeout)
 193                 return -ETIMEDOUT;
 194
 195         if (++bqr_pos >= RX_DESC_NUM)
 196                 bqr_pos = 0;
 197
 198         len = bqd->data_len;
 199
 200         /* CPU should not have touched this buffer since we added it to FQ */
 201         invalidate_dcache_range(bqd->buf_addr, bqd->buf_addr + len);
 202         *packetp = (void *)(unsigned long)bqd->buf_addr;
 203
 204         /* Record the RX_BQ descriptor that is holding RX data */
 205         priv->rxdesc_in_use = bqr_pos;
 206
 207         return len;
 208 }
 209
 210 static int higmac_send(struct udevice *dev, void *packet, int length)
 211 {
 212         struct higmac_priv *priv = dev_get_priv(dev);
 213         struct higmac_desc *bqd = priv->txbq;
 214         int bqw_pos, rqw_pos, rqr_pos;
 215         int timeout = 1000;
 216
 217         flush_cache((unsigned long)packet, length);
 218
 219         bqw_pos = DESC_CNT(readl(priv->base + TX_BQ_WR_ADDR));
 220         bqd += bqw_pos;
 221         bqd->buf_addr = (unsigned long)packet;
 222         bqd->descvid = DESC_VLD_BUSY;
 223         bqd->data_len = length;
 224         flush_desc(bqd);
 225
 226         if (++bqw_pos >= TX_DESC_NUM)
 227                 bqw_pos = 0;
 228
 229         writel(DESC_BYTE(bqw_pos), priv->base + TX_BQ_WR_ADDR);
 230
 231         rqr_pos = DESC_CNT(readl(priv->base + TX_RQ_RD_ADDR));
 232         if (++rqr_pos >= TX_DESC_NUM)
 233                 rqr_pos = 0;
 234
 235         do {
 236                 rqw_pos = DESC_CNT(readl(priv->base + TX_RQ_WR_ADDR));
 237                 udelay(1);
 238         } while (--timeout && rqr_pos != rqw_pos);
 239
 240         if (!timeout)
 241                 return -ETIMEDOUT;
 242
 243         writel(DESC_BYTE(rqr_pos), priv->base + TX_RQ_RD_ADDR);
 244
 245         return 0;
 246 }
 247
 248 static int higmac_adjust_link(struct higmac_priv *priv)
 249 {
 250         struct phy_device *phydev = priv->phydev;
 251         int interface = priv->phyintf;
 252         u32 val;
 253
 254         switch (interface) {
 255         case PHY_INTERFACE_MODE_RGMII:
 256                 if (phydev->speed == SPEED_1000)
 257                         val = RGMII_SPEED_1000;
 258                 else if (phydev->speed == SPEED_100)
 259                         val = RGMII_SPEED_100;
 260                 else
 261                         val = RGMII_SPEED_10;
 262                 break;
 263         case PHY_INTERFACE_MODE_MII:
 264                 if (phydev->speed == SPEED_100)
 265                         val = MII_SPEED_100;
 266                 else
 267                         val = MII_SPEED_10;
 268                 break;
 269         default:
 270                 debug("unsupported mode: %d\n", interface);
 271                 return -EINVAL;
 272         }
 273
 274         if (phydev->duplex)
 275                 val |= GMAC_FULL_DUPLEX;
 276
 277         writel(val, priv->macif_ctrl);
 278
 279         if (phydev->speed == SPEED_1000)
 280                 val = GMAC_SPEED_1000;
 281         else if (phydev->speed == SPEED_100)
 282                 val = GMAC_SPEED_100;
 283         else
 284                 val = GMAC_SPEED_10;
 285
 286         writel(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
 287         writel(val, priv->base + PORT_MODE);
 288         writel(0, priv->base + MODE_CHANGE_EN);
 289         writel(phydev->duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
 290
 291         return 0;
 292 }
 293
 294 static int higmac_start(struct udevice *dev)
 295 {
 296         struct higmac_priv *priv = dev_get_priv(dev);
 297         struct phy_device *phydev = priv->phydev;
 298         int ret;
 299
 300         ret = phy_startup(phydev);
 301         if (ret)
 302                 return ret;
 303
 304         if (!phydev->link) {
 305                 debug("%s: link down\n", phydev->dev->name);
 306                 return -ENODEV;
 307         }
 308
 309         ret = higmac_adjust_link(priv);
 310         if (ret)
 311                 return ret;
 312
 313         /* Enable port */
 314         writel(BITS_DESC_ENA, priv->base + DESC_WR_RD_ENA);
 315         writel(BIT_TX_EN | BIT_RX_EN, priv->base + PORT_EN);
 316
 317         return 0;
 318 }
 319
 320 static void higmac_stop(struct udevice *dev)
 321 {
 322         struct higmac_priv *priv = dev_get_priv(dev);
 323
 324         /* Disable port */
 325         writel(0, priv->base + PORT_EN);
 326         writel(0, priv->base + DESC_WR_RD_ENA);
 327 }
 328
 329 static const struct eth_ops higmac_ops = {
 330         .start          = higmac_start,
 331         .send           = higmac_send,
 332         .recv           = higmac_recv,
 333         .free_pkt       = higmac_free_pkt,
 334         .stop           = higmac_stop,
 335         .write_hwaddr   = higmac_write_hwaddr,
 336 };
 337
 338 static int higmac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 339 {
 340         struct higmac_priv *priv = bus->priv;
 341         int ret;
 342
 343         ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
 344                                 false, 1000, false);
 345         if (ret)
 346                 return ret;
 347
 348         writel(MDIO_READ | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
 349
 350         ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
 351                                 false, 1000, false);
 352         if (ret)
 353                 return ret;
 354
 355         if (readl(priv->base + MDIO_RDATA_STATUS) & BIT_MDIO_RDATA_INVALID)
 356                 return -EINVAL;
 357
 358         return readl(priv->base + MDIO_SINGLE_DATA) >> 16;
 359 }
 360
 361 static int higmac_mdio_write(struct mii_dev *bus, int addr, int devad,
 362                              int reg, u16 value)
 363 {
 364         struct higmac_priv *priv = bus->priv;
 365         int ret;
 366
 367         ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
 368                                 false, 1000, false);
 369         if (ret)
 370                 return ret;
 371
 372         writel(value, priv->base + MDIO_SINGLE_DATA);
 373         writel(MDIO_WRITE | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
 374
 375         return 0;
 376 }
 377
 378 static int higmac_init_rx_descs(struct higmac_desc *descs, int num)
 379 {
 380         int i;
 381
 382         for (i = 0; i < num; i++) {
 383                 struct higmac_desc *desc = &descs[i];
 384
 385                 desc->buf_addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 386                                                          MAC_MAX_FRAME_SIZE);
 387                 if (!desc->buf_addr)
 388                         goto free_bufs;
 389
 390                 desc->descvid = DESC_VLD_FREE;
 391                 desc->buf_len = MAC_MAX_FRAME_SIZE - 1;
 392                 flush_desc(desc);
 393         }
 394
 395         return 0;
 396
 397 free_bufs:
 398         while (--i > 0)
 399                 free((void *)(unsigned long)descs[i].buf_addr);
 400         return -ENOMEM;
 401 }
 402
 403 static int higmac_init_hw_queue(struct higmac_priv *priv,
 404                                 enum higmac_queue queue)
 405 {
 406         struct higmac_desc *desc, **pdesc;
 407         u32 regaddr, regen, regdep;
 408         int depth;
 409         int len;
 410
 411         switch (queue) {
 412         case RX_FQ:
 413                 regaddr = RX_FQ_START_ADDR;
 414                 regen = RX_FQ_REG_EN;
 415                 regdep = RX_FQ_DEPTH;
 416                 depth = RX_DESC_NUM;
 417                 pdesc = &priv->rxfq;
 418                 break;
 419         case RX_BQ:
 420                 regaddr = RX_BQ_START_ADDR;
 421                 regen = RX_BQ_REG_EN;
 422                 regdep = RX_BQ_DEPTH;
 423                 depth = RX_DESC_NUM;
 424                 pdesc = &priv->rxbq;
 425                 break;
 426         case TX_BQ:
 427                 regaddr = TX_BQ_START_ADDR;
 428                 regen = TX_BQ_REG_EN;
 429                 regdep = TX_BQ_DEPTH;
 430                 depth = TX_DESC_NUM;
 431                 pdesc = &priv->txbq;
 432                 break;
 433         case TX_RQ:
 434                 regaddr = TX_RQ_START_ADDR;
 435                 regen = TX_RQ_REG_EN;
 436                 regdep = TX_RQ_DEPTH;
 437                 depth = TX_DESC_NUM;
 438                 pdesc = &priv->txrq;
 439                 break;
 440         }
 441
 442         /* Enable depth */
 443         writel(BIT_DEPTH_EN, priv->base + regen);
 444         writel(depth << DESC_WORD_SHIFT, priv->base + regdep);
 445         writel(0, priv->base + regen);
 446
 447         len = depth * sizeof(*desc);
 448         desc = memalign(ARCH_DMA_MINALIGN, len);
 449         if (!desc)
 450                 return -ENOMEM;
 451         memset(desc, 0, len);
 452         flush_cache((unsigned long)desc, len);
 453         *pdesc = desc;
 454
 455         /* Set up RX_FQ descriptors */
 456         if (queue == RX_FQ)
 457                 higmac_init_rx_descs(desc, depth);
 458
 459         /* Enable start address */
 460         writel(BIT_START_ADDR_EN, priv->base + regen);
 461         writel((unsigned long)desc, priv->base + regaddr);
 462         writel(0, priv->base + regen);
 463
 464         return 0;
 465 }
 466
 467 static int higmac_hw_init(struct higmac_priv *priv)
 468 {
 469         int ret;
 470
 471         /* Initialize hardware queues */
 472         ret = higmac_init_hw_queue(priv, RX_FQ);
 473         if (ret)
 474                 return ret;
 475
 476         ret = higmac_init_hw_queue(priv, RX_BQ);
 477         if (ret)
 478                 goto free_rx_fq;
 479
 480         ret = higmac_init_hw_queue(priv, TX_BQ);
 481         if (ret)
 482                 goto free_rx_bq;
 483
 484         ret = higmac_init_hw_queue(priv, TX_RQ);
 485         if (ret)
 486                 goto free_tx_bq;
 487
 488         /* Reset phy */
 489         reset_deassert(&priv->rst_phy);
 490         mdelay(10);
 491         reset_assert(&priv->rst_phy);
 492         mdelay(30);
 493         reset_deassert(&priv->rst_phy);
 494         mdelay(30);
 495
 496         return 0;
 497
 498 free_tx_bq:
 499         free(priv->txbq);
 500 free_rx_bq:
 501         free(priv->rxbq);
 502 free_rx_fq:
 503         free(priv->rxfq);
 504         return ret;
 505 }
 506
 507 static int higmac_probe(struct udevice *dev)
 508 {
 509         struct higmac_priv *priv = dev_get_priv(dev);
 510         struct phy_device *phydev;
 511         struct mii_dev *bus;
 512         int ret;
 513
 514         ret = higmac_hw_init(priv);
 515         if (ret)
 516                 return ret;
 517
 518         bus = mdio_alloc();
 519         if (!bus)
 520                 return -ENOMEM;
 521
 522         bus->read = higmac_mdio_read;
 523         bus->write = higmac_mdio_write;
 524         bus->priv = priv;
 525         priv->bus = bus;
 526
 527         ret = mdio_register_seq(bus, dev->seq);
 528         if (ret)
 529                 return ret;
 530
 531         phydev = phy_connect(bus, priv->phyaddr, dev, priv->phyintf);
 532         if (!phydev)
 533                 return -ENODEV;
 534
 535         phydev->supported &= PHY_GBIT_FEATURES;
 536         phydev->advertising = phydev->supported;
 537         priv->phydev = phydev;
 538
 539         return phy_config(phydev);
 540 }
 541
 542 static int higmac_remove(struct udevice *dev)
 543 {
 544         struct higmac_priv *priv = dev_get_priv(dev);
 545         int i;
 546
 547         mdio_unregister(priv->bus);
 548         mdio_free(priv->bus);
 549
 550         /* Free RX packet buffers */
 551         for (i = 0; i < RX_DESC_NUM; i++)
 552                 free((void *)(unsigned long)priv->rxfq[i].buf_addr);
 553
 554         return 0;
 555 }
 556
 557 static int higmac_ofdata_to_platdata(struct udevice *dev)
 558 {
 559         struct higmac_priv *priv = dev_get_priv(dev);
 560         int phyintf = PHY_INTERFACE_MODE_NONE;
 561         const char *phy_mode;
 562         ofnode phy_node;
 563
 564         priv->base = dev_remap_addr_index(dev, 0);
 565         priv->macif_ctrl = dev_remap_addr_index(dev, 1);
 566
 567         phy_mode = dev_read_string(dev, "phy-mode");
 568         if (phy_mode)
 569                 phyintf = phy_get_interface_by_name(phy_mode);
 570         if (phyintf == PHY_INTERFACE_MODE_NONE)
 571                 return -ENODEV;
 572         priv->phyintf = phyintf;
 573
 574         phy_node = dev_read_subnode(dev, "phy");
 575         if (!ofnode_valid(phy_node)) {
 576                 debug("failed to find phy node\n");
 577                 return -ENODEV;
 578         }
 579         priv->phyaddr = ofnode_read_u32_default(phy_node, "reg", 0);
 580
 581         return reset_get_by_name(dev, "phy", &priv->rst_phy);
 582 }
 583
 584 static const struct udevice_id higmac_ids[] = {
 585         { .compatible = "hisilicon,hi3798cv200-gmac" },
 586         { }
 587 };
 588
 589 U_BOOT_DRIVER(eth_higmac) = {
 590         .name   = "eth_higmac",
 591         .id     = UCLASS_ETH,
 592         .of_match = higmac_ids,
 593         .ofdata_to_platdata = higmac_ofdata_to_platdata,
 594         .probe  = higmac_probe,
 595         .remove = higmac_remove,
 596         .ops    = &higmac_ops,
 597         .priv_auto_alloc_size = sizeof(struct higmac_priv),
 598         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 599 };