]> git.ipfire.org Git - thirdparty/u-boot.git/blob - drivers/net/inca-ip_sw.c
projects / thirdparty / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Add GPL-2.0+ SPDX-License-Identifier to source files
[thirdparty/u-boot.git] / drivers / net / inca-ip_sw.c
1 /*
2 * INCA-IP internal switch ethernet driver.
3 *
4 * (C) Copyright 2003-2004
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10
11 #include <common.h>
12
13 #include <malloc.h>
14 #include <net.h>
15 #include <netdev.h>
16 #include <asm/inca-ip.h>
17 #include <asm/addrspace.h>
18
19
20 #define NUM_RX_DESC PKTBUFSRX
21 #define NUM_TX_DESC 3
22 #define TOUT_LOOP 1000000
23
24
25 #define DELAY udelay(10000)
26 /* Sometimes the store word instruction hangs while writing to one
27 * of the Switch registers. Moving the instruction into a separate
28 * function somehow makes the problem go away.
29 */
30 static void SWORD(volatile u32 * reg, u32 value)
31 {
32 *reg = value;
33 }
34
35 #define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
36 #define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
37 #define SW_WRITE_REG(reg, value) \
38 SWORD(reg, value);\
39 DELAY;\
40 SWORD(reg, value);
41
42 #define SW_READ_REG(reg, value) \
43 value = (u32)*((volatile u32*)reg);\
44 DELAY;\
45 value = (u32)*((volatile u32*)reg);
46
47 #define INCA_DMA_TX_POLLING_TIME 0x07
48 #define INCA_DMA_RX_POLLING_TIME 0x07
49
50 #define INCA_DMA_TX_HOLD 0x80000000
51 #define INCA_DMA_TX_EOP 0x40000000
52 #define INCA_DMA_TX_SOP 0x20000000
53 #define INCA_DMA_TX_ICPT 0x10000000
54 #define INCA_DMA_TX_IEOP 0x08000000
55
56 #define INCA_DMA_RX_C 0x80000000
57 #define INCA_DMA_RX_SOP 0x40000000
58 #define INCA_DMA_RX_EOP 0x20000000
59
60 #define INCA_SWITCH_PHY_SPEED_10H 0x1
61 #define INCA_SWITCH_PHY_SPEED_10F 0x5
62 #define INCA_SWITCH_PHY_SPEED_100H 0x2
63 #define INCA_SWITCH_PHY_SPEED_100F 0x6
64
65 /************************ Auto MDIX settings ************************/
66 #define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR
67 #define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
68 #define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT
69 #define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16
70
71 #define WAIT_SIGNAL_RETRIES 100
72 #define WAIT_LINK_RETRIES 100
73 #define LINK_RETRY_DELAY 2000 /* ms */
74 /********************************************************************/
75
76 typedef struct
77 {
78 union {
79 struct {
80 volatile u32 HOLD :1;
81 volatile u32 ICpt :1;
82 volatile u32 IEop :1;
83 volatile u32 offset :3;
84 volatile u32 reserved0 :4;
85 volatile u32 NFB :22;
86 }field;
87
88 volatile u32 word;
89 }params;
90
91 volatile u32 nextRxDescPtr;
92
93 volatile u32 RxDataPtr;
94
95 union {
96 struct {
97 volatile u32 C :1;
98 volatile u32 Sop :1;
99 volatile u32 Eop :1;
100 volatile u32 reserved3 :12;
101 volatile u32 NBT :17;
102 }field;
103
104 volatile u32 word;
105 }status;
106
107 } inca_rx_descriptor_t;
108
109
110 typedef struct
111 {
112 union {
113 struct {
114 volatile u32 HOLD :1;
115 volatile u32 Eop :1;
116 volatile u32 Sop :1;
117 volatile u32 ICpt :1;
118 volatile u32 IEop :1;
119 volatile u32 reserved0 :5;
120 volatile u32 NBA :22;
121 }field;
122
123 volatile u32 word;
124 }params;
125
126 volatile u32 nextTxDescPtr;
127
128 volatile u32 TxDataPtr;
129
130 volatile u32 C :1;
131 volatile u32 reserved3 :31;
132
133 } inca_tx_descriptor_t;
134
135
136 static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16)));
137 static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
138
139 static int tx_new, rx_new, tx_hold, rx_hold;
140 static int tx_old_hold = -1;
141 static int initialized = 0;
142
143
144 static int inca_switch_init(struct eth_device *dev, bd_t * bis);
145 static int inca_switch_send(struct eth_device *dev, void *packet, int length);
146 static int inca_switch_recv(struct eth_device *dev);
147 static void inca_switch_halt(struct eth_device *dev);
148 static void inca_init_switch_chip(void);
149 static void inca_dma_init(void);
150 static int inca_amdix(void);
151
152
153 int inca_switch_initialize(bd_t * bis)
154 {
155 struct eth_device *dev;
156
157 #if 0
158 printf("Entered inca_switch_initialize()\n");
159 #endif
160
161 if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
162 printf("Failed to allocate memory\n");
163 return 0;
164 }
165 memset(dev, 0, sizeof(*dev));
166
167 inca_dma_init();
168
169 inca_init_switch_chip();
170
171 #if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
172 inca_amdix();
173 #endif
174
175 sprintf(dev->name, "INCA-IP Switch");
176 dev->init = inca_switch_init;
177 dev->halt = inca_switch_halt;
178 dev->send = inca_switch_send;
179 dev->recv = inca_switch_recv;
180
181 eth_register(dev);
182
183 #if 0
184 printf("Leaving inca_switch_initialize()\n");
185 #endif
186
187 return 0;
188 }
189
190
191 static int inca_switch_init(struct eth_device *dev, bd_t * bis)
192 {
193 int i;
194 u32 v, regValue;
195 u16 wTmp;
196
197 #if 0
198 printf("Entering inca_switch_init()\n");
199 #endif
200
201 /* Set MAC address.
202 */
203 wTmp = (u16)dev->enetaddr[0];
204 regValue = (wTmp << 8) | dev->enetaddr[1];
205
206 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue);
207
208 wTmp = (u16)dev->enetaddr[2];
209 regValue = (wTmp << 8) | dev->enetaddr[3];
210 regValue = regValue << 16;
211 wTmp = (u16)dev->enetaddr[4];
212 regValue |= (wTmp<<8) | dev->enetaddr[5];
213
214 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
215
216 /* Initialize the descriptor rings.
217 */
218 for (i = 0; i < NUM_RX_DESC; i++) {
219 inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]);
220 memset(rx_desc, 0, sizeof(rx_ring[i]));
221
222 /* Set maximum size of receive buffer.
223 */
224 rx_desc->params.field.NFB = PKTSIZE_ALIGN;
225
226 /* Set the offset of the receive buffer. Zero means
227 * that the offset mechanism is not used.
228 */
229 rx_desc->params.field.offset = 0;
230
231 /* Check if it is the last descriptor.
232 */
233 if (i == (NUM_RX_DESC - 1)) {
234 /* Let the last descriptor point to the first
235 * one.
236 */
237 rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring);
238 } else {
239 /* Set the address of the next descriptor.
240 */
241 rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]);
242 }
243
244 rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]);
245 }
246
247 #if 0
248 printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]);
249 printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
250 #endif
251
252 for (i = 0; i < NUM_TX_DESC; i++) {
253 inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]);
254
255 memset(tx_desc, 0, sizeof(tx_ring[i]));
256
257 tx_desc->params.word = 0;
258 tx_desc->params.field.HOLD = 1;
259 tx_desc->C = 1;
260
261 /* Check if it is the last descriptor.
262 */
263 if (i == (NUM_TX_DESC - 1)) {
264 /* Let the last descriptor point to the
265 * first one.
266 */
267 tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring);
268 } else {
269 /* Set the address of the next descriptor.
270 */
271 tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]);
272 }
273 }
274
275 /* Initialize RxDMA.
276 */
277 DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
278 debug("RX status = 0x%08X\n", v);
279
280 /* Writing to the FRDA of CHANNEL.
281 */
282 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
283
284 /* Writing to the COMMAND REG.
285 */
286 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT);
287
288 /* Initialize TxDMA.
289 */
290 DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
291 debug("TX status = 0x%08X\n", v);
292
293 /* Writing to the FRDA of CHANNEL.
294 */
295 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
296
297 tx_new = rx_new = 0;
298
299 tx_hold = NUM_TX_DESC - 1;
300 rx_hold = NUM_RX_DESC - 1;
301
302 #if 0
303 rx_ring[rx_hold].params.field.HOLD = 1;
304 #endif
305 /* enable spanning tree forwarding, enable the CPU port */
306 /* ST_PT:
307 * CPS (CPU port status) 0x3 (forwarding)
308 * LPS (LAN port status) 0x3 (forwarding)
309 * PPS (PC port status) 0x3 (forwarding)
310 */
311 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
312
313 #if 0
314 printf("Leaving inca_switch_init()\n");
315 #endif
316
317 return 0;
318 }
319
320
321 static int inca_switch_send(struct eth_device *dev, void *packet, int length)
322 {
323 int i;
324 int res = -1;
325 u32 command;
326 u32 regValue;
327 inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]);
328
329 #if 0
330 printf("Entered inca_switch_send()\n");
331 #endif
332
333 if (length <= 0) {
334 printf ("%s: bad packet size: %d\n", dev->name, length);
335 goto Done;
336 }
337
338 for(i = 0; tx_desc->C == 0; i++) {
339 if (i >= TOUT_LOOP) {
340 printf("%s: tx error buffer not ready\n", dev->name);
341 goto Done;
342 }
343 }
344
345 if (tx_old_hold >= 0) {
346 ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1;
347 }
348 tx_old_hold = tx_hold;
349
350 tx_desc->params.word =
351 (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD);
352
353 tx_desc->C = 0;
354 tx_desc->TxDataPtr = (u32)packet;
355 tx_desc->params.field.NBA = length;
356
357 ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0;
358
359 tx_hold = tx_new;
360 tx_new = (tx_new + 1) % NUM_TX_DESC;
361
362
363 if (! initialized) {
364 command = INCA_IP_DMA_DMA_TXCCR0_INIT;
365 initialized = 1;
366 } else {
367 command = INCA_IP_DMA_DMA_TXCCR0_HR;
368 }
369
370 DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
371 regValue |= command;
372 #if 0
373 printf("regValue = 0x%x\n", regValue);
374 #endif
375 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
376
377 #if 1
378 for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) {
379 if (i >= TOUT_LOOP) {
380 printf("%s: tx buffer not ready\n", dev->name);
381 goto Done;
382 }
383 }
384 #endif
385 res = length;
386 Done:
387 #if 0
388 printf("Leaving inca_switch_send()\n");
389 #endif
390 return res;
391 }
392
393
394 static int inca_switch_recv(struct eth_device *dev)
395 {
396 int length = 0;
397 inca_rx_descriptor_t * rx_desc;
398
399 #if 0
400 printf("Entered inca_switch_recv()\n");
401 #endif
402
403 for (;;) {
404 rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]);
405
406 if (rx_desc->status.field.C == 0) {
407 break;
408 }
409
410 #if 0
411 rx_ring[rx_new].params.field.HOLD = 1;
412 #endif
413
414 if (! rx_desc->status.field.Eop) {
415 printf("Partly received packet!!!\n");
416 break;
417 }
418
419 length = rx_desc->status.field.NBT;
420 rx_desc->status.word &=
421 ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C);
422 #if 0
423 {
424 int i;
425 for (i=0;i<length - 4;i++) {
426 if (i % 16 == 0) printf("\n%04x: ", i);
427 printf("%02X ", NetRxPackets[rx_new][i]);
428 }
429 printf("\n");
430 }
431 #endif
432
433 if (length) {
434 #if 0
435 printf("Received %d bytes\n", length);
436 #endif
437 NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4);
438 } else {
439 #if 1
440 printf("Zero length!!!\n");
441 #endif
442 }
443
444
445 ((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0;
446
447 rx_hold = rx_new;
448
449 rx_new = (rx_new + 1) % NUM_RX_DESC;
450 }
451
452 #if 0
453 printf("Leaving inca_switch_recv()\n");
454 #endif
455
456 return length;
457 }
458
459
460 static void inca_switch_halt(struct eth_device *dev)
461 {
462 #if 0
463 printf("Entered inca_switch_halt()\n");
464 #endif
465
466 #if 1
467 initialized = 0;
468 #endif
469 #if 1
470 /* Disable forwarding to the CPU port.
471 */
472 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
473
474 /* Close RxDMA channel.
475 */
476 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
477
478 /* Close TxDMA channel.
479 */
480 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
481
482
483 #endif
484 #if 0
485 printf("Leaving inca_switch_halt()\n");
486 #endif
487 }
488
489
490 static void inca_init_switch_chip(void)
491 {
492 u32 regValue;
493
494 /* To workaround a problem with collision counter
495 * (see Errata sheet).
496 */
497 SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
498 SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
499
500 #if 1
501 /* init MDIO configuration:
502 * MDS (Poll speed): 0x01 (4ms)
503 * PHY_LAN_ADDR: 0x06
504 * PHY_PC_ADDR: 0x05
505 * UEP (Use External PHY): 0x00 (Internal PHY is used)
506 * PS (Port Select): 0x00 (PT/UMM for LAN)
507 * PT (PHY Test): 0x00 (no test mode)
508 * UMM (Use MDIO Mode): 0x00 (state machine is disabled)
509 */
510 SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
511
512 /* init PHY:
513 * SL (Auto Neg. Speed for LAN)
514 * SP (Auto Neg. Speed for PC)
515 * LL (Link Status for LAN)
516 * LP (Link Status for PC)
517 * DL (Duplex Status for LAN)
518 * DP (Duplex Status for PC)
519 * PL (Auto Neg. Pause Status for LAN)
520 * PP (Auto Neg. Pause Status for PC)
521 */
522 SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
523
524 /* MDIO_ACC:
525 * RA (Request/Ack) 0x01 (Request)
526 * RW (Read/Write) 0x01 (Write)
527 * PHY_ADDR 0x05 (PC)
528 * REG_ADDR 0x00 (PHY_BCR: basic control register)
529 * PHY_DATA 0x8000
530 * Reset - software reset
531 * LB (loop back) - normal
532 * SS (speed select) - 10 Mbit/s
533 * ANE (auto neg. enable) - enable
534 * PD (power down) - normal
535 * ISO (isolate) - normal
536 * RAN (restart auto neg.) - normal
537 * DM (duplex mode) - half duplex
538 * CT (collision test) - enable
539 */
540 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
541
542 /* MDIO_ACC:
543 * RA (Request/Ack) 0x01 (Request)
544 * RW (Read/Write) 0x01 (Write)
545 * PHY_ADDR 0x06 (LAN)
546 * REG_ADDR 0x00 (PHY_BCR: basic control register)
547 * PHY_DATA 0x8000
548 * Reset - software reset
549 * LB (loop back) - normal
550 * SS (speed select) - 10 Mbit/s
551 * ANE (auto neg. enable) - enable
552 * PD (power down) - normal
553 * ISO (isolate) - normal
554 * RAN (restart auto neg.) - normal
555 * DM (duplex mode) - half duplex
556 * CT (collision test) - enable
557 */
558 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
559
560 #endif
561
562 /* Make sure the CPU port is disabled for now. We
563 * don't want packets to get stacked for us until
564 * we enable DMA and are prepared to receive them.
565 */
566 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
567
568 SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
569
570 /* CRC GEN is enabled.
571 */
572 regValue |= 0x00000200;
573 SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
574
575 /* ADD TAG is disabled.
576 */
577 SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
578 regValue &= ~0x00000002;
579 SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
580 }
581
582
583 static void inca_dma_init(void)
584 {
585 /* Switch off all DMA channels.
586 */
587 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
588 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
589
590 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
591 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
592 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
593
594 /* Setup TX channel polling time.
595 */
596 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
597
598 /* Setup RX channel polling time.
599 */
600 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
601
602 /* ERRATA: write reset value into the DMA RX IMR register.
603 */
604 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
605
606 /* Just in case: disable all transmit interrupts also.
607 */
608 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
609
610 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
611 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF);
612 }
613
614 #if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
615 static int inca_amdix(void)
616 {
617 u32 phyReg1 = 0;
618 u32 phyReg4 = 0;
619 u32 phyReg5 = 0;
620 u32 phyReg6 = 0;
621 u32 phyReg31 = 0;
622 u32 regEphy = 0;
623 int mdi_flag;
624 int retries;
625
626 /* Setup GPIO pins.
627 */
628 *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
629 *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
630
631 #if 0
632 /* Wait for signal.
633 */
634 retries = WAIT_SIGNAL_RETRIES;
635 while (--retries) {
636 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
637 (0x1 << 31) | /* RA */
638 (0x0 << 30) | /* Read */
639 (0x6 << 21) | /* LAN */
640 (17 << 16)); /* PHY_MCSR */
641 do {
642 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
643 } while (phyReg1 & (1 << 31));
644
645 if (phyReg1 & (1 << 1)) {
646 /* Signal detected */
647 break;
648 }
649 }
650
651 if (!retries)
652 goto Fail;
653 #endif
654
655 /* Set MDI mode.
656 */
657 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
658 mdi_flag = 1;
659
660 /* Wait for link.
661 */
662 retries = WAIT_LINK_RETRIES;
663 while (--retries) {
664 udelay(LINK_RETRY_DELAY * 1000);
665 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
666 (0x1 << 31) | /* RA */
667 (0x0 << 30) | /* Read */
668 (0x6 << 21) | /* LAN */
669 (1 << 16)); /* PHY_BSR */
670 do {
671 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
672 } while (phyReg1 & (1 << 31));
673
674 if (phyReg1 & (1 << 2)) {
675 /* Link is up */
676 break;
677 } else if (mdi_flag) {
678 /* Set MDIX mode */
679 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
680 mdi_flag = 0;
681 } else {
682 /* Set MDI mode */
683 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
684 mdi_flag = 1;
685 }
686 }
687
688 if (!retries) {
689 goto Fail;
690 } else {
691 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
692 (0x1 << 31) | /* RA */
693 (0x0 << 30) | /* Read */
694 (0x6 << 21) | /* LAN */
695 (1 << 16)); /* PHY_BSR */
696 do {
697 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
698 } while (phyReg1 & (1 << 31));
699
700 /* Auto-negotiation / Parallel detection complete
701 */
702 if (phyReg1 & (1 << 5)) {
703 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
704 (0x1 << 31) | /* RA */
705 (0x0 << 30) | /* Read */
706 (0x6 << 21) | /* LAN */
707 (31 << 16)); /* PHY_SCSR */
708 do {
709 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31);
710 } while (phyReg31 & (1 << 31));
711
712 switch ((phyReg31 >> 2) & 0x7) {
713 case INCA_SWITCH_PHY_SPEED_10H:
714 /* 10Base-T Half-duplex */
715 regEphy = 0;
716 break;
717 case INCA_SWITCH_PHY_SPEED_10F:
718 /* 10Base-T Full-duplex */
719 regEphy = INCA_IP_Switch_EPHY_DL;
720 break;
721 case INCA_SWITCH_PHY_SPEED_100H:
722 /* 100Base-TX Half-duplex */
723 regEphy = INCA_IP_Switch_EPHY_SL;
724 break;
725 case INCA_SWITCH_PHY_SPEED_100F:
726 /* 100Base-TX Full-duplex */
727 regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL;
728 break;
729 }
730
731 /* In case of Auto-negotiation,
732 * update the negotiated PAUSE support status
733 */
734 if (phyReg1 & (1 << 3)) {
735 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
736 (0x1 << 31) | /* RA */
737 (0x0 << 30) | /* Read */
738 (0x6 << 21) | /* LAN */
739 (6 << 16)); /* MII_EXPANSION */
740 do {
741 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
742 } while (phyReg6 & (1 << 31));
743
744 /* We are Autoneg-able.
745 * Is Link partner also able to autoneg?
746 */
747 if (phyReg6 & (1 << 0)) {
748 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
749 (0x1 << 31) | /* RA */
750 (0x0 << 30) | /* Read */
751 (0x6 << 21) | /* LAN */
752 (4 << 16)); /* MII_ADVERTISE */
753 do {
754 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
755 } while (phyReg4 & (1 << 31));
756
757 /* We advertise PAUSE capab.
758 * Does link partner also advertise it?
759 */
760 if (phyReg4 & (1 << 10)) {
761 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
762 (0x1 << 31) | /* RA */
763 (0x0 << 30) | /* Read */
764 (0x6 << 21) | /* LAN */
765 (5 << 16)); /* MII_LPA */
766 do {
767 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
768 } while (phyReg5 & (1 << 31));
769
770 /* Link partner is PAUSE capab.
771 */
772 if (phyReg5 & (1 << 10)) {
773 regEphy |= INCA_IP_Switch_EPHY_PL;
774 }
775 }
776 }
777
778 }
779
780 /* Link is up */
781 regEphy |= INCA_IP_Switch_EPHY_LL;
782
783 SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy);
784 }
785 }
786
787 return 0;
788
789 Fail:
790 printf("No Link on LAN port\n");
791 return -1;
792 }
793 #endif /* CONFIG_INCA_IP_SWITCH_AMDIX */
"Das U-Boot" Source Tree