1 /*********************************************************************
3 * Filename: w83977af_ir.c
5 * Description: FIR driver for the Winbond W83977AF Super I/O chip
6 * Status: Experimental.
7 * Author: Paul VanderSpek
8 * Created at: Wed Nov 4 11:46:16 1998
9 * Modified at: Fri Jan 28 12:10:59 2000
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
12 * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
13 * Copyright (c) 1998-1999 Rebel.com
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * Neither Paul VanderSpek nor Rebel.com admit liability nor provide
21 * warranty for any of this software. This material is provided "AS-IS"
24 * If you find bugs in this file, its very likely that the same bug
25 * will also be in pc87108.c since the implementations are quite
28 * Notice that all functions that needs to access the chip in _any_
29 * way, must save BSR register on entry, and restore it on exit.
30 * It is _very_ important to follow this policy!
34 * bank = inb( iobase+BSR);
36 * do_your_stuff_here();
38 * outb( bank, iobase+BSR);
40 ********************************************************************/
42 #include <linux/module.h>
43 #include <linux/kernel.h>
44 #include <linux/types.h>
45 #include <linux/skbuff.h>
46 #include <linux/netdevice.h>
47 #include <linux/ioport.h>
48 #include <linux/delay.h>
49 #include <linux/init.h>
50 #include <linux/rtnetlink.h>
51 #include <linux/dma-mapping.h>
52 #include <linux/gfp.h>
56 #include <asm/byteorder.h>
58 #include <net/irda/irda.h>
59 #include <net/irda/wrapper.h>
60 #include <net/irda/irda_device.h>
62 #include "w83977af_ir.h"
64 #ifdef CONFIG_ARCH_NETWINDER /* Adjust to NetWinder differences */
65 #undef CONFIG_NETWINDER_TX_DMA_PROBLEMS /* Not needed */
66 #define CONFIG_NETWINDER_RX_DMA_PROBLEMS /* Must have this one! */
68 #define CONFIG_USE_W977_PNP /* Currently needed */
69 #define PIO_MAX_SPEED 115200
71 static char *driver_name
= "w83977af_ir";
72 static int qos_mtt_bits
= 0x07; /* 1 ms or more */
74 #define CHIP_IO_EXTENT 8
76 static unsigned int io
[] = { 0x180, ~0, ~0, ~0 };
77 #ifdef CONFIG_ARCH_NETWINDER /* Adjust to NetWinder differences */
78 static unsigned int irq
[] = { 6, 0, 0, 0 };
80 static unsigned int irq
[] = { 11, 0, 0, 0 };
82 static unsigned int dma
[] = { 1, 0, 0, 0 };
83 static unsigned int efbase
[] = { W977_EFIO_BASE
, W977_EFIO2_BASE
};
84 static unsigned int efio
= W977_EFIO_BASE
;
86 static struct w83977af_ir
*dev_self
[] = { NULL
, NULL
, NULL
, NULL
};
89 static int w83977af_open(int i
, unsigned int iobase
, unsigned int irq
,
91 static int w83977af_close(struct w83977af_ir
*self
);
92 static int w83977af_probe(int iobase
, int irq
, int dma
);
93 static int w83977af_dma_receive(struct w83977af_ir
*self
);
94 static int w83977af_dma_receive_complete(struct w83977af_ir
*self
);
95 static netdev_tx_t
w83977af_hard_xmit(struct sk_buff
*skb
,
96 struct net_device
*dev
);
97 static int w83977af_pio_write(int iobase
, __u8
*buf
, int len
, int fifo_size
);
98 static void w83977af_dma_write(struct w83977af_ir
*self
, int iobase
);
99 static void w83977af_change_speed(struct w83977af_ir
*self
, __u32 speed
);
100 static int w83977af_is_receiving(struct w83977af_ir
*self
);
102 static int w83977af_net_open(struct net_device
*dev
);
103 static int w83977af_net_close(struct net_device
*dev
);
104 static int w83977af_net_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
107 * Function w83977af_init ()
109 * Initialize chip. Just try to find out how many chips we are dealing with
112 static int __init
w83977af_init(void)
116 IRDA_DEBUG(0, "%s()\n", __func__
);
118 for (i
=0; i
< ARRAY_SIZE(dev_self
) && io
[i
] < 2000; i
++) {
119 if (w83977af_open(i
, io
[i
], irq
[i
], dma
[i
]) == 0)
126 * Function w83977af_cleanup ()
128 * Close all configured chips
131 static void __exit
w83977af_cleanup(void)
135 IRDA_DEBUG(4, "%s()\n", __func__
);
137 for (i
=0; i
< ARRAY_SIZE(dev_self
); i
++) {
139 w83977af_close(dev_self
[i
]);
143 static const struct net_device_ops w83977_netdev_ops
= {
144 .ndo_open
= w83977af_net_open
,
145 .ndo_stop
= w83977af_net_close
,
146 .ndo_start_xmit
= w83977af_hard_xmit
,
147 .ndo_do_ioctl
= w83977af_net_ioctl
,
151 * Function w83977af_open (iobase, irq)
153 * Open driver instance
156 static int w83977af_open(int i
, unsigned int iobase
, unsigned int irq
,
159 struct net_device
*dev
;
160 struct w83977af_ir
*self
;
163 IRDA_DEBUG(0, "%s()\n", __func__
);
165 /* Lock the port that we need */
166 if (!request_region(iobase
, CHIP_IO_EXTENT
, driver_name
)) {
167 IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n",
172 if (w83977af_probe(iobase
, irq
, dma
) == -1) {
177 * Allocate new instance of the driver
179 dev
= alloc_irdadev(sizeof(struct w83977af_ir
));
181 printk( KERN_ERR
"IrDA: Can't allocate memory for "
182 "IrDA control block!\n");
187 self
= netdev_priv(dev
);
188 spin_lock_init(&self
->lock
);
192 self
->io
.fir_base
= iobase
;
194 self
->io
.fir_ext
= CHIP_IO_EXTENT
;
196 self
->io
.fifo_size
= 32;
198 /* Initialize QoS for this device */
199 irda_init_max_qos_capabilies(&self
->qos
);
201 /* The only value we must override it the baudrate */
203 /* FIXME: The HP HDLS-1100 does not support 1152000! */
204 self
->qos
.baud_rate
.bits
= IR_9600
|IR_19200
|IR_38400
|IR_57600
|
205 IR_115200
|IR_576000
|IR_1152000
|(IR_4000000
<< 8);
207 /* The HP HDLS-1100 needs 1 ms according to the specs */
208 self
->qos
.min_turn_time
.bits
= qos_mtt_bits
;
209 irda_qos_bits_to_value(&self
->qos
);
211 /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
212 self
->rx_buff
.truesize
= 14384;
213 self
->tx_buff
.truesize
= 4000;
215 /* Allocate memory if needed */
217 dma_alloc_coherent(NULL
, self
->rx_buff
.truesize
,
218 &self
->rx_buff_dma
, GFP_KERNEL
);
219 if (self
->rx_buff
.head
== NULL
) {
224 memset(self
->rx_buff
.head
, 0, self
->rx_buff
.truesize
);
227 dma_alloc_coherent(NULL
, self
->tx_buff
.truesize
,
228 &self
->tx_buff_dma
, GFP_KERNEL
);
229 if (self
->tx_buff
.head
== NULL
) {
233 memset(self
->tx_buff
.head
, 0, self
->tx_buff
.truesize
);
235 self
->rx_buff
.in_frame
= FALSE
;
236 self
->rx_buff
.state
= OUTSIDE_FRAME
;
237 self
->tx_buff
.data
= self
->tx_buff
.head
;
238 self
->rx_buff
.data
= self
->rx_buff
.head
;
241 dev
->netdev_ops
= &w83977_netdev_ops
;
243 err
= register_netdev(dev
);
245 IRDA_ERROR("%s(), register_netdevice() failed!\n", __func__
);
248 IRDA_MESSAGE("IrDA: Registered device %s\n", dev
->name
);
250 /* Need to store self somewhere */
255 dma_free_coherent(NULL
, self
->tx_buff
.truesize
,
256 self
->tx_buff
.head
, self
->tx_buff_dma
);
258 dma_free_coherent(NULL
, self
->rx_buff
.truesize
,
259 self
->rx_buff
.head
, self
->rx_buff_dma
);
263 release_region(iobase
, CHIP_IO_EXTENT
);
268 * Function w83977af_close (self)
270 * Close driver instance
273 static int w83977af_close(struct w83977af_ir
*self
)
277 IRDA_DEBUG(0, "%s()\n", __func__
);
279 iobase
= self
->io
.fir_base
;
281 #ifdef CONFIG_USE_W977_PNP
282 /* enter PnP configuration mode */
283 w977_efm_enter(efio
);
285 w977_select_device(W977_DEVICE_IR
, efio
);
287 /* Deactivate device */
288 w977_write_reg(0x30, 0x00, efio
);
291 #endif /* CONFIG_USE_W977_PNP */
293 /* Remove netdevice */
294 unregister_netdev(self
->netdev
);
296 /* Release the PORT that this driver is using */
297 IRDA_DEBUG(0 , "%s(), Releasing Region %03x\n",
298 __func__
, self
->io
.fir_base
);
299 release_region(self
->io
.fir_base
, self
->io
.fir_ext
);
301 if (self
->tx_buff
.head
)
302 dma_free_coherent(NULL
, self
->tx_buff
.truesize
,
303 self
->tx_buff
.head
, self
->tx_buff_dma
);
305 if (self
->rx_buff
.head
)
306 dma_free_coherent(NULL
, self
->rx_buff
.truesize
,
307 self
->rx_buff
.head
, self
->rx_buff_dma
);
309 free_netdev(self
->netdev
);
314 static int w83977af_probe(int iobase
, int irq
, int dma
)
319 for (i
=0; i
< 2; i
++) {
320 IRDA_DEBUG( 0, "%s()\n", __func__
);
321 #ifdef CONFIG_USE_W977_PNP
322 /* Enter PnP configuration mode */
323 w977_efm_enter(efbase
[i
]);
325 w977_select_device(W977_DEVICE_IR
, efbase
[i
]);
327 /* Configure PnP port, IRQ, and DMA channel */
328 w977_write_reg(0x60, (iobase
>> 8) & 0xff, efbase
[i
]);
329 w977_write_reg(0x61, (iobase
) & 0xff, efbase
[i
]);
331 w977_write_reg(0x70, irq
, efbase
[i
]);
332 #ifdef CONFIG_ARCH_NETWINDER
333 /* Netwinder uses 1 higher than Linux */
334 w977_write_reg(0x74, dma
+1, efbase
[i
]);
336 w977_write_reg(0x74, dma
, efbase
[i
]);
337 #endif /*CONFIG_ARCH_NETWINDER */
338 w977_write_reg(0x75, 0x04, efbase
[i
]); /* Disable Tx DMA */
340 /* Set append hardware CRC, enable IR bank selection */
341 w977_write_reg(0xf0, APEDCRC
|ENBNKSEL
, efbase
[i
]);
343 /* Activate device */
344 w977_write_reg(0x30, 0x01, efbase
[i
]);
346 w977_efm_exit(efbase
[i
]);
347 #endif /* CONFIG_USE_W977_PNP */
348 /* Disable Advanced mode */
349 switch_bank(iobase
, SET2
);
350 outb(iobase
+2, 0x00);
352 /* Turn on UART (global) interrupts */
353 switch_bank(iobase
, SET0
);
354 outb(HCR_EN_IRQ
, iobase
+HCR
);
356 /* Switch to advanced mode */
357 switch_bank(iobase
, SET2
);
358 outb(inb(iobase
+ADCR1
) | ADCR1_ADV_SL
, iobase
+ADCR1
);
360 /* Set default IR-mode */
361 switch_bank(iobase
, SET0
);
362 outb(HCR_SIR
, iobase
+HCR
);
364 /* Read the Advanced IR ID */
365 switch_bank(iobase
, SET3
);
366 version
= inb(iobase
+AUID
);
369 if (0x10 == (version
& 0xf0)) {
372 /* Set FIFO size to 32 */
373 switch_bank(iobase
, SET2
);
374 outb(ADCR2_RXFS32
|ADCR2_TXFS32
, iobase
+ADCR2
);
376 /* Set FIFO threshold to TX17, RX16 */
377 switch_bank(iobase
, SET0
);
378 outb(UFR_RXTL
|UFR_TXTL
|UFR_TXF_RST
|UFR_RXF_RST
|
379 UFR_EN_FIFO
,iobase
+UFR
);
381 /* Receiver frame length */
382 switch_bank(iobase
, SET4
);
383 outb(2048 & 0xff, iobase
+6);
384 outb((2048 >> 8) & 0x1f, iobase
+7);
387 * Init HP HSDL-1100 transceiver.
389 * Set IRX_MSL since we have 2 * receive paths IRRX,
390 * and IRRXH. Clear IRSL0D since we want IRSL0 * to
391 * be a input pin used for IRRXH
393 * IRRX pin 37 connected to receiver
394 * IRTX pin 38 connected to transmitter
395 * FIRRX pin 39 connected to receiver (IRSL0)
396 * CIRRX pin 40 connected to pin 37
398 switch_bank(iobase
, SET7
);
399 outb(0x40, iobase
+7);
401 IRDA_MESSAGE("W83977AF (IR) driver loaded. "
402 "Version: 0x%02x\n", version
);
406 /* Try next extented function register address */
407 IRDA_DEBUG( 0, "%s(), Wrong chip version", __func__
);
413 static void w83977af_change_speed(struct w83977af_ir
*self
, __u32 speed
)
415 int ir_mode
= HCR_SIR
;
419 iobase
= self
->io
.fir_base
;
421 /* Update accounting for new speed */
422 self
->io
.speed
= speed
;
424 /* Save current bank */
425 set
= inb(iobase
+SSR
);
427 /* Disable interrupts */
428 switch_bank(iobase
, SET0
);
432 switch_bank(iobase
, SET2
);
433 outb(0x00, iobase
+ABHL
);
436 case 9600: outb(0x0c, iobase
+ABLL
); break;
437 case 19200: outb(0x06, iobase
+ABLL
); break;
438 case 38400: outb(0x03, iobase
+ABLL
); break;
439 case 57600: outb(0x02, iobase
+ABLL
); break;
440 case 115200: outb(0x01, iobase
+ABLL
); break;
442 ir_mode
= HCR_MIR_576
;
443 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__
);
446 ir_mode
= HCR_MIR_1152
;
447 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", __func__
);
451 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", __func__
);
455 IRDA_DEBUG(0, "%s(), unknown baud rate of %d\n", __func__
, speed
);
460 switch_bank(iobase
, SET0
);
461 outb(ir_mode
, iobase
+HCR
);
463 /* set FIFO size to 32 */
464 switch_bank(iobase
, SET2
);
465 outb(ADCR2_RXFS32
|ADCR2_TXFS32
, iobase
+ADCR2
);
467 /* set FIFO threshold to TX17, RX16 */
468 switch_bank(iobase
, SET0
);
469 outb(0x00, iobase
+UFR
); /* Reset */
470 outb(UFR_EN_FIFO
, iobase
+UFR
); /* First we must enable FIFO */
471 outb(0xa7, iobase
+UFR
);
473 netif_wake_queue(self
->netdev
);
475 /* Enable some interrupts so we can receive frames */
476 switch_bank(iobase
, SET0
);
477 if (speed
> PIO_MAX_SPEED
) {
478 outb(ICR_EFSFI
, iobase
+ICR
);
479 w83977af_dma_receive(self
);
481 outb(ICR_ERBRI
, iobase
+ICR
);
484 outb(set
, iobase
+SSR
);
488 * Function w83977af_hard_xmit (skb, dev)
490 * Sets up a DMA transfer to send the current frame.
493 static netdev_tx_t
w83977af_hard_xmit(struct sk_buff
*skb
,
494 struct net_device
*dev
)
496 struct w83977af_ir
*self
;
502 self
= netdev_priv(dev
);
504 iobase
= self
->io
.fir_base
;
506 IRDA_DEBUG(4, "%s(%ld), skb->len=%d\n", __func__
, jiffies
,
509 /* Lock transmit buffer */
510 netif_stop_queue(dev
);
512 /* Check if we need to change the speed */
513 speed
= irda_get_next_speed(skb
);
514 if ((speed
!= self
->io
.speed
) && (speed
!= -1)) {
515 /* Check for empty frame */
517 w83977af_change_speed(self
, speed
);
518 dev
->trans_start
= jiffies
;
522 self
->new_speed
= speed
;
525 /* Save current set */
526 set
= inb(iobase
+SSR
);
528 /* Decide if we should use PIO or DMA transfer */
529 if (self
->io
.speed
> PIO_MAX_SPEED
) {
530 self
->tx_buff
.data
= self
->tx_buff
.head
;
531 skb_copy_from_linear_data(skb
, self
->tx_buff
.data
, skb
->len
);
532 self
->tx_buff
.len
= skb
->len
;
534 mtt
= irda_get_mtt(skb
);
535 IRDA_DEBUG(4, "%s(%ld), mtt=%d\n", __func__
, jiffies
, mtt
);
539 /* Enable DMA interrupt */
540 switch_bank(iobase
, SET0
);
541 outb(ICR_EDMAI
, iobase
+ICR
);
542 w83977af_dma_write(self
, iobase
);
544 self
->tx_buff
.data
= self
->tx_buff
.head
;
545 self
->tx_buff
.len
= async_wrap_skb(skb
, self
->tx_buff
.data
,
546 self
->tx_buff
.truesize
);
548 /* Add interrupt on tx low level (will fire immediately) */
549 switch_bank(iobase
, SET0
);
550 outb(ICR_ETXTHI
, iobase
+ICR
);
552 dev
->trans_start
= jiffies
;
555 /* Restore set register */
556 outb(set
, iobase
+SSR
);
562 * Function w83977af_dma_write (self, iobase)
564 * Send frame using DMA
567 static void w83977af_dma_write(struct w83977af_ir
*self
, int iobase
)
570 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
574 IRDA_DEBUG(4, "%s(), len=%d\n", __func__
, self
->tx_buff
.len
);
576 /* Save current set */
577 set
= inb(iobase
+SSR
);
580 switch_bank(iobase
, SET0
);
581 outb(inb(iobase
+HCR
) & ~HCR_EN_DMA
, iobase
+HCR
);
583 /* Choose transmit DMA channel */
584 switch_bank(iobase
, SET2
);
585 outb(ADCR1_D_CHSW
|/*ADCR1_DMA_F|*/ADCR1_ADV_SL
, iobase
+ADCR1
);
586 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
587 spin_lock_irqsave(&self
->lock
, flags
);
589 disable_dma(self
->io
.dma
);
590 clear_dma_ff(self
->io
.dma
);
591 set_dma_mode(self
->io
.dma
, DMA_MODE_READ
);
592 set_dma_addr(self
->io
.dma
, self
->tx_buff_dma
);
593 set_dma_count(self
->io
.dma
, self
->tx_buff
.len
);
595 irda_setup_dma(self
->io
.dma
, self
->tx_buff_dma
, self
->tx_buff
.len
,
598 self
->io
.direction
= IO_XMIT
;
601 switch_bank(iobase
, SET0
);
602 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
603 hcr
= inb(iobase
+HCR
);
604 outb(hcr
| HCR_EN_DMA
, iobase
+HCR
);
605 enable_dma(self
->io
.dma
);
606 spin_unlock_irqrestore(&self
->lock
, flags
);
608 outb(inb(iobase
+HCR
) | HCR_EN_DMA
| HCR_TX_WT
, iobase
+HCR
);
611 /* Restore set register */
612 outb(set
, iobase
+SSR
);
616 * Function w83977af_pio_write (iobase, buf, len, fifo_size)
621 static int w83977af_pio_write(int iobase
, __u8
*buf
, int len
, int fifo_size
)
626 IRDA_DEBUG(4, "%s()\n", __func__
);
628 /* Save current bank */
629 set
= inb(iobase
+SSR
);
631 switch_bank(iobase
, SET0
);
632 if (!(inb_p(iobase
+USR
) & USR_TSRE
)) {
634 "%s(), warning, FIFO not empty yet!\n", __func__
);
637 IRDA_DEBUG(4, "%s(), %d bytes left in tx fifo\n",
638 __func__
, fifo_size
);
641 /* Fill FIFO with current frame */
642 while ((fifo_size
-- > 0) && (actual
< len
)) {
643 /* Transmit next byte */
644 outb(buf
[actual
++], iobase
+TBR
);
647 IRDA_DEBUG(4, "%s(), fifo_size %d ; %d sent of %d\n",
648 __func__
, fifo_size
, actual
, len
);
651 outb(set
, iobase
+SSR
);
657 * Function w83977af_dma_xmit_complete (self)
659 * The transfer of a frame in finished. So do the necessary things
663 static void w83977af_dma_xmit_complete(struct w83977af_ir
*self
)
668 IRDA_DEBUG(4, "%s(%ld)\n", __func__
, jiffies
);
670 IRDA_ASSERT(self
!= NULL
, return;);
672 iobase
= self
->io
.fir_base
;
674 /* Save current set */
675 set
= inb(iobase
+SSR
);
678 switch_bank(iobase
, SET0
);
679 outb(inb(iobase
+HCR
) & ~HCR_EN_DMA
, iobase
+HCR
);
681 /* Check for underrrun! */
682 if (inb(iobase
+AUDR
) & AUDR_UNDR
) {
683 IRDA_DEBUG(0, "%s(), Transmit underrun!\n", __func__
);
685 self
->netdev
->stats
.tx_errors
++;
686 self
->netdev
->stats
.tx_fifo_errors
++;
688 /* Clear bit, by writing 1 to it */
689 outb(AUDR_UNDR
, iobase
+AUDR
);
691 self
->netdev
->stats
.tx_packets
++;
694 if (self
->new_speed
) {
695 w83977af_change_speed(self
, self
->new_speed
);
699 /* Unlock tx_buff and request another frame */
700 /* Tell the network layer, that we want more frames */
701 netif_wake_queue(self
->netdev
);
704 outb(set
, iobase
+SSR
);
708 * Function w83977af_dma_receive (self)
710 * Get ready for receiving a frame. The device will initiate a DMA
711 * if it starts to receive a frame.
714 static int w83977af_dma_receive(struct w83977af_ir
*self
)
718 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
722 IRDA_ASSERT(self
!= NULL
, return -1;);
724 IRDA_DEBUG(4, "%s\n", __func__
);
726 iobase
= self
->io
.fir_base
;
728 /* Save current set */
729 set
= inb(iobase
+SSR
);
732 switch_bank(iobase
, SET0
);
733 outb(inb(iobase
+HCR
) & ~HCR_EN_DMA
, iobase
+HCR
);
735 /* Choose DMA Rx, DMA Fairness, and Advanced mode */
736 switch_bank(iobase
, SET2
);
737 outb((inb(iobase
+ADCR1
) & ~ADCR1_D_CHSW
)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL
,
740 self
->io
.direction
= IO_RECV
;
741 self
->rx_buff
.data
= self
->rx_buff
.head
;
743 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
744 spin_lock_irqsave(&self
->lock
, flags
);
746 disable_dma(self
->io
.dma
);
747 clear_dma_ff(self
->io
.dma
);
748 set_dma_mode(self
->io
.dma
, DMA_MODE_READ
);
749 set_dma_addr(self
->io
.dma
, self
->rx_buff_dma
);
750 set_dma_count(self
->io
.dma
, self
->rx_buff
.truesize
);
752 irda_setup_dma(self
->io
.dma
, self
->rx_buff_dma
, self
->rx_buff
.truesize
,
756 * Reset Rx FIFO. This will also flush the ST_FIFO, it's very
757 * important that we don't reset the Tx FIFO since it might not
758 * be finished transmitting yet
760 switch_bank(iobase
, SET0
);
761 outb(UFR_RXTL
|UFR_TXTL
|UFR_RXF_RST
|UFR_EN_FIFO
, iobase
+UFR
);
762 self
->st_fifo
.len
= self
->st_fifo
.tail
= self
->st_fifo
.head
= 0;
765 switch_bank(iobase
, SET0
);
766 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
767 hcr
= inb(iobase
+HCR
);
768 outb(hcr
| HCR_EN_DMA
, iobase
+HCR
);
769 enable_dma(self
->io
.dma
);
770 spin_unlock_irqrestore(&self
->lock
, flags
);
772 outb(inb(iobase
+HCR
) | HCR_EN_DMA
, iobase
+HCR
);
775 outb(set
, iobase
+SSR
);
781 * Function w83977af_receive_complete (self)
783 * Finished with receiving a frame
786 static int w83977af_dma_receive_complete(struct w83977af_ir
*self
)
789 struct st_fifo
*st_fifo
;
795 IRDA_DEBUG(4, "%s\n", __func__
);
797 st_fifo
= &self
->st_fifo
;
799 iobase
= self
->io
.fir_base
;
801 /* Save current set */
802 set
= inb(iobase
+SSR
);
804 iobase
= self
->io
.fir_base
;
806 /* Read status FIFO */
807 switch_bank(iobase
, SET5
);
808 while ((status
= inb(iobase
+FS_FO
)) & FS_FO_FSFDR
) {
809 st_fifo
->entries
[st_fifo
->tail
].status
= status
;
811 st_fifo
->entries
[st_fifo
->tail
].len
= inb(iobase
+RFLFL
);
812 st_fifo
->entries
[st_fifo
->tail
].len
|= inb(iobase
+RFLFH
) << 8;
818 while (st_fifo
->len
) {
819 /* Get first entry */
820 status
= st_fifo
->entries
[st_fifo
->head
].status
;
821 len
= st_fifo
->entries
[st_fifo
->head
].len
;
825 /* Check for errors */
826 if (status
& FS_FO_ERR_MSK
) {
827 if (status
& FS_FO_LST_FR
) {
828 /* Add number of lost frames to stats */
829 self
->netdev
->stats
.rx_errors
+= len
;
832 self
->netdev
->stats
.rx_errors
++;
834 self
->rx_buff
.data
+= len
;
836 if (status
& FS_FO_MX_LEX
)
837 self
->netdev
->stats
.rx_length_errors
++;
839 if (status
& FS_FO_PHY_ERR
)
840 self
->netdev
->stats
.rx_frame_errors
++;
842 if (status
& FS_FO_CRC_ERR
)
843 self
->netdev
->stats
.rx_crc_errors
++;
845 /* The errors below can be reported in both cases */
846 if (status
& FS_FO_RX_OV
)
847 self
->netdev
->stats
.rx_fifo_errors
++;
849 if (status
& FS_FO_FSF_OV
)
850 self
->netdev
->stats
.rx_fifo_errors
++;
853 /* Check if we have transferred all data to memory */
854 switch_bank(iobase
, SET0
);
855 if (inb(iobase
+USR
) & USR_RDR
) {
856 udelay(80); /* Should be enough!? */
859 skb
= dev_alloc_skb(len
+1);
862 "%s(), memory squeeze, dropping frame.\n", __func__
);
863 /* Restore set register */
864 outb(set
, iobase
+SSR
);
869 /* Align to 20 bytes */
872 /* Copy frame without CRC */
873 if (self
->io
.speed
< 4000000) {
875 skb_copy_to_linear_data(skb
,
880 skb_copy_to_linear_data(skb
,
885 /* Move to next frame */
886 self
->rx_buff
.data
+= len
;
887 self
->netdev
->stats
.rx_packets
++;
889 skb
->dev
= self
->netdev
;
890 skb_reset_mac_header(skb
);
891 skb
->protocol
= htons(ETH_P_IRDA
);
895 /* Restore set register */
896 outb(set
, iobase
+SSR
);
902 * Function pc87108_pio_receive (self)
904 * Receive all data in receiver FIFO
907 static void w83977af_pio_receive(struct w83977af_ir
*self
)
912 IRDA_DEBUG(4, "%s()\n", __func__
);
914 IRDA_ASSERT(self
!= NULL
, return;);
916 iobase
= self
->io
.fir_base
;
918 /* Receive all characters in Rx FIFO */
920 byte
= inb(iobase
+RBR
);
921 async_unwrap_char(self
->netdev
, &self
->netdev
->stats
, &self
->rx_buff
,
923 } while (inb(iobase
+USR
) & USR_RDR
); /* Data available */
927 * Function w83977af_sir_interrupt (self, eir)
929 * Handle SIR interrupt
932 static __u8
w83977af_sir_interrupt(struct w83977af_ir
*self
, int isr
)
939 IRDA_DEBUG(4, "%s(), isr=%#x\n", __func__
, isr
);
941 iobase
= self
->io
.fir_base
;
942 /* Transmit FIFO low on data */
943 if (isr
& ISR_TXTH_I
) {
944 /* Write data left in transmit buffer */
945 actual
= w83977af_pio_write(self
->io
.fir_base
,
950 self
->tx_buff
.data
+= actual
;
951 self
->tx_buff
.len
-= actual
;
953 self
->io
.direction
= IO_XMIT
;
955 /* Check if finished */
956 if (self
->tx_buff
.len
> 0) {
957 new_icr
|= ICR_ETXTHI
;
959 set
= inb(iobase
+SSR
);
960 switch_bank(iobase
, SET0
);
961 outb(AUDR_SFEND
, iobase
+AUDR
);
962 outb(set
, iobase
+SSR
);
964 self
->netdev
->stats
.tx_packets
++;
966 /* Feed me more packets */
967 netif_wake_queue(self
->netdev
);
968 new_icr
|= ICR_ETBREI
;
971 /* Check if transmission has completed */
972 if (isr
& ISR_TXEMP_I
) {
973 /* Check if we need to change the speed? */
974 if (self
->new_speed
) {
976 "%s(), Changing speed!\n", __func__
);
977 w83977af_change_speed(self
, self
->new_speed
);
981 /* Turn around and get ready to receive some data */
982 self
->io
.direction
= IO_RECV
;
983 new_icr
|= ICR_ERBRI
;
986 /* Rx FIFO threshold or timeout */
987 if (isr
& ISR_RXTH_I
) {
988 w83977af_pio_receive(self
);
991 new_icr
|= ICR_ERBRI
;
997 * Function pc87108_fir_interrupt (self, eir)
999 * Handle MIR/FIR interrupt
1002 static __u8
w83977af_fir_interrupt(struct w83977af_ir
*self
, int isr
)
1008 iobase
= self
->io
.fir_base
;
1009 set
= inb(iobase
+SSR
);
1011 /* End of frame detected in FIFO */
1012 if (isr
& (ISR_FEND_I
|ISR_FSF_I
)) {
1013 if (w83977af_dma_receive_complete(self
)) {
1015 /* Wait for next status FIFO interrupt */
1016 new_icr
|= ICR_EFSFI
;
1018 /* DMA not finished yet */
1020 /* Set timer value, resolution 1 ms */
1021 switch_bank(iobase
, SET4
);
1022 outb(0x01, iobase
+TMRL
); /* 1 ms */
1023 outb(0x00, iobase
+TMRH
);
1026 outb(IR_MSL_EN_TMR
, iobase
+IR_MSL
);
1028 new_icr
|= ICR_ETMRI
;
1031 /* Timer finished */
1032 if (isr
& ISR_TMR_I
) {
1034 switch_bank(iobase
, SET4
);
1035 outb(0, iobase
+IR_MSL
);
1037 /* Clear timer event */
1038 /* switch_bank(iobase, SET0); */
1039 /* outb(ASCR_CTE, iobase+ASCR); */
1041 /* Check if this is a TX timer interrupt */
1042 if (self
->io
.direction
== IO_XMIT
) {
1043 w83977af_dma_write(self
, iobase
);
1045 new_icr
|= ICR_EDMAI
;
1047 /* Check if DMA has now finished */
1048 w83977af_dma_receive_complete(self
);
1050 new_icr
|= ICR_EFSFI
;
1053 /* Finished with DMA */
1054 if (isr
& ISR_DMA_I
) {
1055 w83977af_dma_xmit_complete(self
);
1057 /* Check if there are more frames to be transmitted */
1058 /* if (irda_device_txqueue_empty(self)) { */
1060 /* Prepare for receive
1062 * ** Netwinder Tx DMA likes that we do this anyway **
1064 w83977af_dma_receive(self
);
1065 new_icr
= ICR_EFSFI
;
1070 outb(set
, iobase
+SSR
);
1076 * Function w83977af_interrupt (irq, dev_id, regs)
1078 * An interrupt from the chip has arrived. Time to do some work
1081 static irqreturn_t
w83977af_interrupt(int irq
, void *dev_id
)
1083 struct net_device
*dev
= dev_id
;
1084 struct w83977af_ir
*self
;
1088 self
= netdev_priv(dev
);
1090 iobase
= self
->io
.fir_base
;
1092 /* Save current bank */
1093 set
= inb(iobase
+SSR
);
1094 switch_bank(iobase
, SET0
);
1096 icr
= inb(iobase
+ICR
);
1097 isr
= inb(iobase
+ISR
) & icr
; /* Mask out the interesting ones */
1099 outb(0, iobase
+ICR
); /* Disable interrupts */
1102 /* Dispatch interrupt handler for the current speed */
1103 if (self
->io
.speed
> PIO_MAX_SPEED
)
1104 icr
= w83977af_fir_interrupt(self
, isr
);
1106 icr
= w83977af_sir_interrupt(self
, isr
);
1109 outb(icr
, iobase
+ICR
); /* Restore (new) interrupts */
1110 outb(set
, iobase
+SSR
); /* Restore bank register */
1111 return IRQ_RETVAL(isr
);
1115 * Function w83977af_is_receiving (self)
1117 * Return TRUE is we are currently receiving a frame
1120 static int w83977af_is_receiving(struct w83977af_ir
*self
)
1126 IRDA_ASSERT(self
!= NULL
, return FALSE
;);
1128 if (self
->io
.speed
> 115200) {
1129 iobase
= self
->io
.fir_base
;
1131 /* Check if rx FIFO is not empty */
1132 set
= inb(iobase
+SSR
);
1133 switch_bank(iobase
, SET2
);
1134 if ((inb(iobase
+RXFDTH
) & 0x3f) != 0) {
1135 /* We are receiving something */
1138 outb(set
, iobase
+SSR
);
1140 status
= (self
->rx_buff
.state
!= OUTSIDE_FRAME
);
1146 * Function w83977af_net_open (dev)
1151 static int w83977af_net_open(struct net_device
*dev
)
1153 struct w83977af_ir
*self
;
1158 IRDA_DEBUG(0, "%s()\n", __func__
);
1160 IRDA_ASSERT(dev
!= NULL
, return -1;);
1161 self
= netdev_priv(dev
);
1163 IRDA_ASSERT(self
!= NULL
, return 0;);
1165 iobase
= self
->io
.fir_base
;
1167 if (request_irq(self
->io
.irq
, w83977af_interrupt
, 0, dev
->name
,
1172 * Always allocate the DMA channel after the IRQ,
1173 * and clean up on failure.
1175 if (request_dma(self
->io
.dma
, dev
->name
)) {
1176 free_irq(self
->io
.irq
, self
);
1180 /* Save current set */
1181 set
= inb(iobase
+SSR
);
1183 /* Enable some interrupts so we can receive frames again */
1184 switch_bank(iobase
, SET0
);
1185 if (self
->io
.speed
> 115200) {
1186 outb(ICR_EFSFI
, iobase
+ICR
);
1187 w83977af_dma_receive(self
);
1189 outb(ICR_ERBRI
, iobase
+ICR
);
1191 /* Restore bank register */
1192 outb(set
, iobase
+SSR
);
1194 /* Ready to play! */
1195 netif_start_queue(dev
);
1197 /* Give self a hardware name */
1198 sprintf(hwname
, "w83977af @ 0x%03x", self
->io
.fir_base
);
1201 * Open new IrLAP layer instance, now that everything should be
1202 * initialized properly
1204 self
->irlap
= irlap_open(dev
, &self
->qos
, hwname
);
1210 * Function w83977af_net_close (dev)
1215 static int w83977af_net_close(struct net_device
*dev
)
1217 struct w83977af_ir
*self
;
1221 IRDA_DEBUG(0, "%s()\n", __func__
);
1223 IRDA_ASSERT(dev
!= NULL
, return -1;);
1225 self
= netdev_priv(dev
);
1227 IRDA_ASSERT(self
!= NULL
, return 0;);
1229 iobase
= self
->io
.fir_base
;
1232 netif_stop_queue(dev
);
1234 /* Stop and remove instance of IrLAP */
1236 irlap_close(self
->irlap
);
1239 disable_dma(self
->io
.dma
);
1241 /* Save current set */
1242 set
= inb(iobase
+SSR
);
1244 /* Disable interrupts */
1245 switch_bank(iobase
, SET0
);
1246 outb(0, iobase
+ICR
);
1248 free_irq(self
->io
.irq
, dev
);
1249 free_dma(self
->io
.dma
);
1251 /* Restore bank register */
1252 outb(set
, iobase
+SSR
);
1258 * Function w83977af_net_ioctl (dev, rq, cmd)
1260 * Process IOCTL commands for this device
1263 static int w83977af_net_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
1265 struct if_irda_req
*irq
= (struct if_irda_req
*) rq
;
1266 struct w83977af_ir
*self
;
1267 unsigned long flags
;
1270 IRDA_ASSERT(dev
!= NULL
, return -1;);
1272 self
= netdev_priv(dev
);
1274 IRDA_ASSERT(self
!= NULL
, return -1;);
1276 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__
, dev
->name
, cmd
);
1278 spin_lock_irqsave(&self
->lock
, flags
);
1281 case SIOCSBANDWIDTH
: /* Set bandwidth */
1282 if (!capable(CAP_NET_ADMIN
)) {
1286 w83977af_change_speed(self
, irq
->ifr_baudrate
);
1288 case SIOCSMEDIABUSY
: /* Set media busy */
1289 if (!capable(CAP_NET_ADMIN
)) {
1293 irda_device_set_media_busy(self
->netdev
, TRUE
);
1295 case SIOCGRECEIVING
: /* Check if we are receiving right now */
1296 irq
->ifr_receiving
= w83977af_is_receiving(self
);
1302 spin_unlock_irqrestore(&self
->lock
, flags
);
1306 MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>");
1307 MODULE_DESCRIPTION("Winbond W83977AF IrDA Device Driver");
1308 MODULE_LICENSE("GPL");
1311 module_param(qos_mtt_bits
, int, 0);
1312 MODULE_PARM_DESC(qos_mtt_bits
, "Mimimum Turn Time");
1313 module_param_array(io
, int, NULL
, 0);
1314 MODULE_PARM_DESC(io
, "Base I/O addresses");
1315 module_param_array(irq
, int, NULL
, 0);
1316 MODULE_PARM_DESC(irq
, "IRQ lines");
1319 * Function init_module (void)
1324 module_init(w83977af_init
);
1327 * Function cleanup_module (void)
1332 module_exit(w83977af_cleanup
);