2 * Ethernet driver for TI K2HK EVM.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
21 #include <asm/ti-common/keystone_nav.h>
22 #include <asm/ti-common/keystone_net.h>
23 #include <asm/ti-common/keystone_serdes.h>
24 #include <asm/arch/psc_defs.h>
26 DECLARE_GLOBAL_DATA_PTR
;
29 unsigned int emac_open
;
30 static struct mii_dev
*mdio_bus
;
31 static unsigned int sys_has_mdio
= 1;
34 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
35 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
37 #define emac_gigabit_enable(x) /* no gigabit to enable */
40 #define RX_BUFF_NUMS 24
41 #define RX_BUFF_LEN 1520
42 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
43 #define SGMII_ANEG_TIMEOUT 4000
45 static u8 rx_buffs
[RX_BUFF_NUMS
* RX_BUFF_LEN
] __aligned(16);
48 struct rx_buff_desc net_rx_buffs
= {
50 .num_buffs
= RX_BUFF_NUMS
,
51 .buff_len
= RX_BUFF_LEN
,
59 LINK_TYPE_MAC_TO_MAC_AUTO
= 0,
60 LINK_TYPE_MAC_TO_PHY_MODE
= 1,
61 LINK_TYPE_MAC_TO_MAC_FORCED_MODE
= 2,
62 LINK_TYPE_MAC_TO_FIBRE_MODE
= 3,
63 LINK_TYPE_MAC_TO_PHY_NO_MDIO_MODE
= 4,
64 LINK_TYPE_10G_MAC_TO_PHY_MODE
= 10,
65 LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE
= 11,
68 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
69 ((mac)[2] << 16) | ((mac)[3] << 24))
70 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
72 #ifdef CONFIG_KSNET_NETCP_V1_0
74 #define EMAC_EMACSW_BASE_OFS 0x90800
75 #define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
77 /* CPSW Switch slave registers */
78 #define CPGMACSL_REG_SA_LO 0x10
79 #define CPGMACSL_REG_SA_HI 0x14
81 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
84 #elif defined CONFIG_KSNET_NETCP_V1_5
86 #define EMAC_EMACSW_PORT_BASE_OFS 0x222000
88 /* CPSW Switch slave registers */
89 #define CPGMACSL_REG_SA_LO 0x308
90 #define CPGMACSL_REG_SA_HI 0x30c
92 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
100 struct phy_device
*phydev
;
101 struct mii_dev
*mdio_bus
;
103 phy_interface_t phy_if
;
106 struct rx_buff_desc net_rx_buffs
;
107 struct pktdma_cfg
*netcp_pktdma
;
110 enum link_type link_type
;
118 static int keystone2_mdio_reset(struct mii_dev
*bus
)
121 struct mdio_regs
*adap_mdio
= bus
->priv
;
123 clkdiv
= (EMAC_MDIO_BUS_FREQ
/ EMAC_MDIO_CLOCK_FREQ
) - 1;
125 writel((clkdiv
& 0xffff) | MDIO_CONTROL_ENABLE
|
126 MDIO_CONTROL_FAULT
| MDIO_CONTROL_FAULT_ENABLE
,
127 &adap_mdio
->control
);
129 while (readl(&adap_mdio
->control
) & MDIO_CONTROL_IDLE
)
136 * keystone2_mdio_read - read a PHY register via MDIO interface.
137 * Blocks until operation is complete.
139 static int keystone2_mdio_read(struct mii_dev
*bus
,
140 int addr
, int devad
, int reg
)
143 struct mdio_regs
*adap_mdio
= bus
->priv
;
145 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
148 writel(MDIO_USERACCESS0_GO
| MDIO_USERACCESS0_WRITE_READ
|
149 ((reg
& 0x1f) << 21) | ((addr
& 0x1f) << 16),
150 &adap_mdio
->useraccess0
);
152 /* Wait for command to complete */
153 while ((tmp
= readl(&adap_mdio
->useraccess0
)) & MDIO_USERACCESS0_GO
)
156 if (tmp
& MDIO_USERACCESS0_ACK
)
163 * keystone2_mdio_write - write to a PHY register via MDIO interface.
164 * Blocks until operation is complete.
166 static int keystone2_mdio_write(struct mii_dev
*bus
,
167 int addr
, int devad
, int reg
, u16 val
)
169 struct mdio_regs
*adap_mdio
= bus
->priv
;
171 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
174 writel(MDIO_USERACCESS0_GO
| MDIO_USERACCESS0_WRITE_WRITE
|
175 ((reg
& 0x1f) << 21) | ((addr
& 0x1f) << 16) |
176 (val
& 0xffff), &adap_mdio
->useraccess0
);
178 /* Wait for command to complete */
179 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
185 #ifndef CONFIG_DM_ETH
186 static void __attribute__((unused
))
187 keystone2_eth_gigabit_enable(struct eth_device
*dev
)
190 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
193 data
= keystone2_mdio_read(mdio_bus
, eth_priv
->phy_addr
,
195 /* speed selection MSB */
196 if (!(data
& (1 << 6)))
201 * Check if link detected is giga-bit
202 * If Gigabit mode detected, enable gigbit in MAC
204 writel(readl(DEVICE_EMACSL_BASE(eth_priv
->slave_port
- 1) +
206 EMAC_MACCONTROL_GIGFORCE
| EMAC_MACCONTROL_GIGABIT_ENABLE
,
207 DEVICE_EMACSL_BASE(eth_priv
->slave_port
- 1) + CPGMACSL_REG_CTL
);
210 static void __attribute__((unused
))
211 keystone2_eth_gigabit_enable(struct udevice
*dev
)
213 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
216 if (priv
->has_mdio
) {
217 data
= keystone2_mdio_read(priv
->mdio_bus
, priv
->phy_addr
,
219 /* speed selection MSB */
220 if (!(data
& (1 << 6)))
225 * Check if link detected is giga-bit
226 * If Gigabit mode detected, enable gigbit in MAC
228 writel(readl(DEVICE_EMACSL_BASE(priv
->slave_port
- 1) +
230 EMAC_MACCONTROL_GIGFORCE
| EMAC_MACCONTROL_GIGABIT_ENABLE
,
231 DEVICE_EMACSL_BASE(priv
->slave_port
- 1) + CPGMACSL_REG_CTL
);
235 #ifdef CONFIG_SOC_K2G
236 int keystone_rgmii_config(struct phy_device
*phy_dev
)
238 unsigned int i
, status
;
242 if (i
> SGMII_ANEG_TIMEOUT
) {
243 puts(" TIMEOUT !\n");
249 puts("user interrupt!\n");
254 if ((i
++ % 500) == 0)
257 udelay(1000); /* 1 ms */
258 status
= readl(RGMII_STATUS_REG
);
259 } while (!(status
& RGMII_REG_STATUS_LINK
));
266 int keystone_sgmii_config(struct phy_device
*phy_dev
, int port
, int interface
)
268 unsigned int i
, status
, mask
;
269 unsigned int mr_adv_ability
, control
;
272 case SGMII_LINK_MAC_MAC_AUTONEG
:
273 mr_adv_ability
= (SGMII_REG_MR_ADV_ENABLE
|
274 SGMII_REG_MR_ADV_LINK
|
275 SGMII_REG_MR_ADV_FULL_DUPLEX
|
276 SGMII_REG_MR_ADV_GIG_MODE
);
277 control
= (SGMII_REG_CONTROL_MASTER
|
278 SGMII_REG_CONTROL_AUTONEG
);
281 case SGMII_LINK_MAC_PHY
:
282 case SGMII_LINK_MAC_PHY_FORCED
:
283 mr_adv_ability
= SGMII_REG_MR_ADV_ENABLE
;
284 control
= SGMII_REG_CONTROL_AUTONEG
;
287 case SGMII_LINK_MAC_MAC_FORCED
:
288 mr_adv_ability
= (SGMII_REG_MR_ADV_ENABLE
|
289 SGMII_REG_MR_ADV_LINK
|
290 SGMII_REG_MR_ADV_FULL_DUPLEX
|
291 SGMII_REG_MR_ADV_GIG_MODE
);
292 control
= SGMII_REG_CONTROL_MASTER
;
295 case SGMII_LINK_MAC_FIBER
:
296 mr_adv_ability
= 0x20;
297 control
= SGMII_REG_CONTROL_AUTONEG
;
301 mr_adv_ability
= SGMII_REG_MR_ADV_ENABLE
;
302 control
= SGMII_REG_CONTROL_AUTONEG
;
305 __raw_writel(0, SGMII_CTL_REG(port
));
308 * Wait for the SerDes pll to lock,
309 * but don't trap if lock is never read
311 for (i
= 0; i
< 1000; i
++) {
313 status
= __raw_readl(SGMII_STATUS_REG(port
));
314 if ((status
& SGMII_REG_STATUS_LOCK
) != 0)
318 __raw_writel(mr_adv_ability
, SGMII_MRADV_REG(port
));
319 __raw_writel(control
, SGMII_CTL_REG(port
));
322 mask
= SGMII_REG_STATUS_LINK
;
324 if (control
& SGMII_REG_CONTROL_AUTONEG
)
325 mask
|= SGMII_REG_STATUS_AUTONEG
;
327 status
= __raw_readl(SGMII_STATUS_REG(port
));
328 if ((status
& mask
) == mask
)
331 printf("\n%s Waiting for SGMII auto negotiation to complete",
333 while ((status
& mask
) != mask
) {
337 if (i
> SGMII_ANEG_TIMEOUT
) {
338 puts(" TIMEOUT !\n");
344 puts("user interrupt!\n");
349 if ((i
++ % 500) == 0)
352 udelay(1000); /* 1 ms */
353 status
= __raw_readl(SGMII_STATUS_REG(port
));
361 int mac_sl_reset(u32 port
)
365 if (port
>= DEVICE_N_GMACSL_PORTS
)
366 return GMACSL_RET_INVALID_PORT
;
368 /* Set the soft reset bit */
369 writel(CPGMAC_REG_RESET_VAL_RESET
,
370 DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
372 /* Wait for the bit to clear */
373 for (i
= 0; i
< DEVICE_EMACSL_RESET_POLL_COUNT
; i
++) {
374 v
= readl(DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
375 if ((v
& CPGMAC_REG_RESET_VAL_RESET_MASK
) !=
376 CPGMAC_REG_RESET_VAL_RESET
)
377 return GMACSL_RET_OK
;
380 /* Timeout on the reset */
381 return GMACSL_RET_WARN_RESET_INCOMPLETE
;
384 int mac_sl_config(u_int16_t port
, struct mac_sl_cfg
*cfg
)
387 int ret
= GMACSL_RET_OK
;
389 if (port
>= DEVICE_N_GMACSL_PORTS
)
390 return GMACSL_RET_INVALID_PORT
;
392 if (cfg
->max_rx_len
> CPGMAC_REG_MAXLEN_LEN
) {
393 cfg
->max_rx_len
= CPGMAC_REG_MAXLEN_LEN
;
394 ret
= GMACSL_RET_WARN_MAXLEN_TOO_BIG
;
397 /* Must wait if the device is undergoing reset */
398 for (i
= 0; i
< DEVICE_EMACSL_RESET_POLL_COUNT
; i
++) {
399 v
= readl(DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
400 if ((v
& CPGMAC_REG_RESET_VAL_RESET_MASK
) !=
401 CPGMAC_REG_RESET_VAL_RESET
)
405 if (i
== DEVICE_EMACSL_RESET_POLL_COUNT
)
406 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE
;
408 writel(cfg
->max_rx_len
, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_MAXLEN
);
409 writel(cfg
->ctl
, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_CTL
);
411 #ifndef CONFIG_SOC_K2HK
412 /* Map RX packet flow priority to 0 */
413 writel(0, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RX_PRI_MAP
);
419 int ethss_config(u32 ctl
, u32 max_pkt_size
)
423 /* Max length register */
424 writel(max_pkt_size
, DEVICE_CPSW_BASE
+ CPSW_REG_MAXLEN
);
426 /* Control register */
427 writel(ctl
, DEVICE_CPSW_BASE
+ CPSW_REG_CTL
);
429 /* All statistics enabled by default */
430 writel(CPSW_REG_VAL_STAT_ENABLE_ALL
,
431 DEVICE_CPSW_BASE
+ CPSW_REG_STAT_PORT_EN
);
433 /* Reset and enable the ALE */
434 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE
|
435 CPSW_REG_VAL_ALE_CTL_BYPASS
,
436 DEVICE_CPSW_BASE
+ CPSW_REG_ALE_CONTROL
);
438 /* All ports put into forward mode */
439 for (i
= 0; i
< DEVICE_CPSW_NUM_PORTS
; i
++)
440 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE
,
441 DEVICE_CPSW_BASE
+ CPSW_REG_ALE_PORTCTL(i
));
446 int ethss_start(void)
449 struct mac_sl_cfg cfg
;
451 cfg
.max_rx_len
= MAX_SIZE_STREAM_BUFFER
;
452 cfg
.ctl
= GMACSL_ENABLE
| GMACSL_RX_ENABLE_EXT_CTL
;
454 for (i
= 0; i
< DEVICE_N_GMACSL_PORTS
; i
++) {
456 mac_sl_config(i
, &cfg
);
466 for (i
= 0; i
< DEVICE_N_GMACSL_PORTS
; i
++)
472 struct ks2_serdes ks2_serdes_sgmii_156p25mhz
= {
473 .clk
= SERDES_CLOCK_156P25M
,
474 .rate
= SERDES_RATE_5G
,
475 .rate_mode
= SERDES_QUARTER_RATE
,
476 .intf
= SERDES_PHY_SGMII
,
480 #ifndef CONFIG_SOC_K2G
481 static void keystone2_net_serdes_setup(void)
483 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE
,
484 &ks2_serdes_sgmii_156p25mhz
,
485 CONFIG_KSNET_SERDES_LANES_PER_SGMII
);
487 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
488 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE
,
489 &ks2_serdes_sgmii_156p25mhz
,
490 CONFIG_KSNET_SERDES_LANES_PER_SGMII
);
493 /* wait till setup */
498 #ifndef CONFIG_DM_ETH
500 int keystone2_eth_read_mac_addr(struct eth_device
*dev
)
502 struct eth_priv_t
*eth_priv
;
506 eth_priv
= (struct eth_priv_t
*)dev
->priv
;
508 /* Read the e-fuse mac address */
509 if (eth_priv
->slave_port
== 1) {
510 maca
= __raw_readl(MAC_ID_BASE_ADDR
);
511 macb
= __raw_readl(MAC_ID_BASE_ADDR
+ 4);
514 dev
->enetaddr
[0] = (macb
>> 8) & 0xff;
515 dev
->enetaddr
[1] = (macb
>> 0) & 0xff;
516 dev
->enetaddr
[2] = (maca
>> 24) & 0xff;
517 dev
->enetaddr
[3] = (maca
>> 16) & 0xff;
518 dev
->enetaddr
[4] = (maca
>> 8) & 0xff;
519 dev
->enetaddr
[5] = (maca
>> 0) & 0xff;
524 int32_t cpmac_drv_send(u32
*buffer
, int num_bytes
, int slave_port_num
)
526 if (num_bytes
< EMAC_MIN_ETHERNET_PKT_SIZE
)
527 num_bytes
= EMAC_MIN_ETHERNET_PKT_SIZE
;
529 return ksnav_send(&netcp_pktdma
, buffer
,
530 num_bytes
, (slave_port_num
) << 16);
533 /* Eth device open */
534 static int keystone2_eth_open(struct eth_device
*dev
, bd_t
*bis
)
536 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
537 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
539 debug("+ emac_open\n");
541 net_rx_buffs
.rx_flow
= eth_priv
->rx_flow
;
544 (eth_priv
->sgmii_link_type
== SGMII_LINK_MAC_PHY
) ? 1 : 0;
547 keystone2_mdio_reset(mdio_bus
);
549 #ifdef CONFIG_SOC_K2G
550 keystone_rgmii_config(phy_dev
);
552 keystone_sgmii_config(phy_dev
, eth_priv
->slave_port
- 1,
553 eth_priv
->sgmii_link_type
);
558 /* On chip switch configuration */
559 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE
);
561 /* TODO: add error handling code */
563 printf("ERROR: qm_init()\n");
566 if (ksnav_init(&netcp_pktdma
, &net_rx_buffs
)) {
568 printf("ERROR: netcp_init()\n");
573 * Streaming switch configuration. If not present this
574 * statement is defined to void in target.h.
575 * If present this is usually defined to a series of register writes
577 hw_config_streaming_switch();
580 keystone2_mdio_reset(mdio_bus
);
582 phy_startup(phy_dev
);
583 if (phy_dev
->link
== 0) {
584 ksnav_close(&netcp_pktdma
);
590 emac_gigabit_enable(dev
);
594 debug("- emac_open\n");
601 /* Eth device close */
602 void keystone2_eth_close(struct eth_device
*dev
)
604 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
605 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
607 debug("+ emac_close\n");
614 ksnav_close(&netcp_pktdma
);
616 phy_shutdown(phy_dev
);
620 debug("- emac_close\n");
624 * This function sends a single packet on the network and returns
625 * positive number (number of bytes transmitted) or negative for error
627 static int keystone2_eth_send_packet(struct eth_device
*dev
,
628 void *packet
, int length
)
631 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
632 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
634 genphy_update_link(phy_dev
);
635 if (phy_dev
->link
== 0)
638 if (cpmac_drv_send((u32
*)packet
, length
, eth_priv
->slave_port
) != 0)
645 * This function handles receipt of a packet from the network
647 static int keystone2_eth_rcv_packet(struct eth_device
*dev
)
653 hd
= ksnav_recv(&netcp_pktdma
, &pkt
, &pkt_size
);
657 net_process_received_packet((uchar
*)pkt
, pkt_size
);
659 ksnav_release_rxhd(&netcp_pktdma
, hd
);
664 #ifdef CONFIG_MCAST_TFTP
665 static int keystone2_eth_bcast_addr(struct eth_device
*dev
, u32 ip
, u8 set
)
672 * This function initializes the EMAC hardware.
674 int keystone2_emac_initialize(struct eth_priv_t
*eth_priv
)
677 struct eth_device
*dev
;
678 struct phy_device
*phy_dev
;
679 struct mdio_regs
*adap_mdio
= (struct mdio_regs
*)EMAC_MDIO_BASE_ADDR
;
681 dev
= malloc(sizeof(struct eth_device
));
685 memset(dev
, 0, sizeof(struct eth_device
));
687 strcpy(dev
->name
, eth_priv
->int_name
);
688 dev
->priv
= eth_priv
;
690 keystone2_eth_read_mac_addr(dev
);
693 dev
->init
= keystone2_eth_open
;
694 dev
->halt
= keystone2_eth_close
;
695 dev
->send
= keystone2_eth_send_packet
;
696 dev
->recv
= keystone2_eth_rcv_packet
;
697 #ifdef CONFIG_MCAST_TFTP
698 dev
->mcast
= keystone2_eth_bcast_addr
;
703 /* Register MDIO bus if it's not registered yet */
705 mdio_bus
= mdio_alloc();
706 mdio_bus
->read
= keystone2_mdio_read
;
707 mdio_bus
->write
= keystone2_mdio_write
;
708 mdio_bus
->reset
= keystone2_mdio_reset
;
709 mdio_bus
->priv
= (void *)EMAC_MDIO_BASE_ADDR
;
710 strcpy(mdio_bus
->name
, "ethernet-mdio");
712 res
= mdio_register(mdio_bus
);
717 #ifndef CONFIG_SOC_K2G
718 keystone2_net_serdes_setup();
721 /* Create phy device and bind it with driver */
722 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
723 phy_dev
= phy_connect(mdio_bus
, eth_priv
->phy_addr
,
724 dev
, eth_priv
->phy_if
);
727 phy_dev
= phy_find_by_mask(mdio_bus
, 1 << eth_priv
->phy_addr
,
731 eth_priv
->phy_dev
= phy_dev
;
738 static int ks2_eth_start(struct udevice
*dev
)
740 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
742 #ifdef CONFIG_SOC_K2G
743 keystone_rgmii_config(priv
->phydev
);
745 keystone_sgmii_config(priv
->phydev
, priv
->slave_port
- 1,
746 priv
->sgmii_link_type
);
751 /* On chip switch configuration */
752 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE
);
756 if (ksnav_init(priv
->netcp_pktdma
, &priv
->net_rx_buffs
)) {
757 error("ksnav_init failed\n");
762 * Streaming switch configuration. If not present this
763 * statement is defined to void in target.h.
764 * If present this is usually defined to a series of register writes
766 hw_config_streaming_switch();
768 if (priv
->has_mdio
) {
769 keystone2_mdio_reset(priv
->mdio_bus
);
771 phy_startup(priv
->phydev
);
772 if (priv
->phydev
->link
== 0) {
773 error("phy startup failed\n");
778 emac_gigabit_enable(dev
);
782 priv
->emac_open
= true;
787 ksnav_close(priv
->netcp_pktdma
);
794 static int ks2_eth_send(struct udevice
*dev
, void *packet
, int length
)
796 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
798 genphy_update_link(priv
->phydev
);
799 if (priv
->phydev
->link
== 0)
802 if (length
< EMAC_MIN_ETHERNET_PKT_SIZE
)
803 length
= EMAC_MIN_ETHERNET_PKT_SIZE
;
805 return ksnav_send(priv
->netcp_pktdma
, (u32
*)packet
,
806 length
, (priv
->slave_port
) << 16);
809 static int ks2_eth_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
811 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
815 priv
->hd
= ksnav_recv(priv
->netcp_pktdma
, &pkt
, &pkt_size
);
816 if (priv
->hd
== NULL
)
819 *packetp
= (uchar
*)pkt
;
824 static int ks2_eth_free_pkt(struct udevice
*dev
, uchar
*packet
,
827 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
829 ksnav_release_rxhd(priv
->netcp_pktdma
, priv
->hd
);
834 static void ks2_eth_stop(struct udevice
*dev
)
836 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
838 if (!priv
->emac_open
)
842 ksnav_close(priv
->netcp_pktdma
);
844 phy_shutdown(priv
->phydev
);
845 priv
->emac_open
= false;
848 int ks2_eth_read_rom_hwaddr(struct udevice
*dev
)
850 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
851 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
855 /* Read the e-fuse mac address */
856 if (priv
->slave_port
== 1) {
857 maca
= __raw_readl(MAC_ID_BASE_ADDR
);
858 macb
= __raw_readl(MAC_ID_BASE_ADDR
+ 4);
861 pdata
->enetaddr
[0] = (macb
>> 8) & 0xff;
862 pdata
->enetaddr
[1] = (macb
>> 0) & 0xff;
863 pdata
->enetaddr
[2] = (maca
>> 24) & 0xff;
864 pdata
->enetaddr
[3] = (maca
>> 16) & 0xff;
865 pdata
->enetaddr
[4] = (maca
>> 8) & 0xff;
866 pdata
->enetaddr
[5] = (maca
>> 0) & 0xff;
871 int ks2_eth_write_hwaddr(struct udevice
*dev
)
873 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
874 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
876 writel(mac_hi(pdata
->enetaddr
),
877 DEVICE_EMACSW_BASE(pdata
->iobase
, priv
->slave_port
- 1) +
879 writel(mac_lo(pdata
->enetaddr
),
880 DEVICE_EMACSW_BASE(pdata
->iobase
, priv
->slave_port
- 1) +
886 static int ks2_eth_probe(struct udevice
*dev
)
888 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
889 struct mii_dev
*mdio_bus
;
894 /* These clock enables has to be moved to common location */
896 writel(KS2_ETHERNET_RGMII
, KS2_ETHERNET_CFG
);
898 /* By default, select PA PLL clock as PA clock source */
899 #ifndef CONFIG_SOC_K2G
900 if (psc_enable_module(KS2_LPSC_PA
))
903 if (psc_enable_module(KS2_LPSC_CPGMAC
))
905 if (psc_enable_module(KS2_LPSC_CRYPTO
))
908 if (cpu_is_k2e() || cpu_is_k2l())
912 priv
->net_rx_buffs
.buff_ptr
= rx_buffs
;
913 priv
->net_rx_buffs
.num_buffs
= RX_BUFF_NUMS
;
914 priv
->net_rx_buffs
.buff_len
= RX_BUFF_LEN
;
916 if (priv
->slave_port
== 1) {
918 * Register MDIO bus for slave 0 only, other slave have
921 mdio_bus
= mdio_alloc();
923 error("MDIO alloc failed\n");
926 priv
->mdio_bus
= mdio_bus
;
927 mdio_bus
->read
= keystone2_mdio_read
;
928 mdio_bus
->write
= keystone2_mdio_write
;
929 mdio_bus
->reset
= keystone2_mdio_reset
;
930 mdio_bus
->priv
= priv
->mdio_base
;
931 sprintf(mdio_bus
->name
, "ethernet-mdio");
933 ret
= mdio_register(mdio_bus
);
935 error("MDIO bus register failed\n");
939 /* Get the MDIO bus from slave 0 device */
940 struct ks2_eth_priv
*parent_priv
;
942 parent_priv
= dev_get_priv(dev
->parent
);
943 priv
->mdio_bus
= parent_priv
->mdio_bus
;
946 #ifndef CONFIG_SOC_K2G
947 keystone2_net_serdes_setup();
950 priv
->netcp_pktdma
= &netcp_pktdma
;
952 if (priv
->has_mdio
) {
953 priv
->phydev
= phy_connect(priv
->mdio_bus
, priv
->phy_addr
,
955 phy_config(priv
->phydev
);
961 int ks2_eth_remove(struct udevice
*dev
)
963 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
966 mdio_unregister(priv
->mdio_bus
);
967 mdio_free(priv
->mdio_bus
);
972 static const struct eth_ops ks2_eth_ops
= {
973 .start
= ks2_eth_start
,
974 .send
= ks2_eth_send
,
975 .recv
= ks2_eth_recv
,
976 .free_pkt
= ks2_eth_free_pkt
,
977 .stop
= ks2_eth_stop
,
978 .read_rom_hwaddr
= ks2_eth_read_rom_hwaddr
,
979 .write_hwaddr
= ks2_eth_write_hwaddr
,
982 static int ks2_eth_bind_slaves(struct udevice
*dev
, int gbe
, int *gbe_0
)
984 const void *fdt
= gd
->fdt_blob
;
985 struct udevice
*sl_dev
;
992 interfaces
= fdt_subnode_offset(fdt
, gbe
, "interfaces");
993 fdt_for_each_subnode(slave
, fdt
, interfaces
) {
996 slave_no
= fdtdec_get_int(fdt
, slave
, "slave-port", -ENOENT
);
997 if (slave_no
== -ENOENT
)
1000 if (slave_no
== 0) {
1001 /* This is the current eth device */
1004 /* Slave devices to be registered */
1005 slave_name
= malloc(20);
1006 snprintf(slave_name
, 20, "netcp@slave-%d", slave_no
);
1007 ret
= device_bind_driver_to_node(dev
, "eth_ks2_sl",
1011 error("ks2_net - not able to bind slave interfaces\n");
1017 sec_slave
= fdt_subnode_offset(fdt
, gbe
, "secondary-slave-ports");
1018 fdt_for_each_subnode(slave
, fdt
, sec_slave
) {
1021 slave_no
= fdtdec_get_int(fdt
, slave
, "slave-port", -ENOENT
);
1022 if (slave_no
== -ENOENT
)
1025 /* Slave devices to be registered */
1026 slave_name
= malloc(20);
1027 snprintf(slave_name
, 20, "netcp@slave-%d", slave_no
);
1028 ret
= device_bind_driver_to_node(dev
, "eth_ks2_sl", slave_name
,
1031 error("ks2_net - not able to bind slave interfaces\n");
1039 static int ks2_eth_parse_slave_interface(int netcp
, int slave
,
1040 struct ks2_eth_priv
*priv
,
1041 struct eth_pdata
*pdata
)
1043 const void *fdt
= gd
->fdt_blob
;
1049 priv
->slave_port
= fdtdec_get_int(fdt
, slave
, "slave-port", -1);
1050 priv
->net_rx_buffs
.rx_flow
= priv
->slave_port
* 8;
1052 /* U-Boot slave port number starts with 1 instead of 0 */
1053 priv
->slave_port
+= 1;
1055 dma_count
= fdtdec_get_int_array_count(fdt
, netcp
,
1056 "ti,navigator-dmas",
1059 if (dma_count
> (2 * priv
->slave_port
)) {
1062 dma_idx
= priv
->slave_port
* 2 - 1;
1063 priv
->net_rx_buffs
.rx_flow
= dma_channel
[dma_idx
];
1066 priv
->link_type
= fdtdec_get_int(fdt
, slave
, "link-interface", -1);
1068 phy
= fdtdec_lookup_phandle(fdt
, slave
, "phy-handle");
1070 priv
->phy_addr
= fdtdec_get_int(fdt
, phy
, "reg", -1);
1072 mdio
= fdt_parent_offset(fdt
, phy
);
1074 error("mdio dt not found\n");
1077 priv
->mdio_base
= (void *)fdtdec_get_addr(fdt
, mdio
, "reg");
1080 if (priv
->link_type
== LINK_TYPE_MAC_TO_PHY_MODE
) {
1081 priv
->phy_if
= PHY_INTERFACE_MODE_SGMII
;
1082 pdata
->phy_interface
= priv
->phy_if
;
1083 priv
->sgmii_link_type
= SGMII_LINK_MAC_PHY
;
1084 priv
->has_mdio
= true;
1090 static int ks2_sl_eth_ofdata_to_platdata(struct udevice
*dev
)
1092 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
1093 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
1094 const void *fdt
= gd
->fdt_blob
;
1095 int slave
= dev
->of_offset
;
1101 interfaces
= fdt_parent_offset(fdt
, slave
);
1102 gbe
= fdt_parent_offset(fdt
, interfaces
);
1103 netcp_devices
= fdt_parent_offset(fdt
, gbe
);
1104 netcp
= fdt_parent_offset(fdt
, netcp_devices
);
1106 ks2_eth_parse_slave_interface(netcp
, slave
, priv
, pdata
);
1108 pdata
->iobase
= fdtdec_get_addr(fdt
, netcp
, "reg");
1113 static int ks2_eth_ofdata_to_platdata(struct udevice
*dev
)
1115 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
1116 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
1117 const void *fdt
= gd
->fdt_blob
;
1118 int gbe_0
= -ENODEV
;
1122 netcp_devices
= fdt_subnode_offset(fdt
, dev
->of_offset
,
1124 gbe
= fdt_subnode_offset(fdt
, netcp_devices
, "gbe");
1126 ks2_eth_bind_slaves(dev
, gbe
, &gbe_0
);
1128 ks2_eth_parse_slave_interface(dev
->of_offset
, gbe_0
, priv
, pdata
);
1130 pdata
->iobase
= dev_get_addr(dev
);
1135 static const struct udevice_id ks2_eth_ids
[] = {
1136 { .compatible
= "ti,netcp-1.0" },
1140 U_BOOT_DRIVER(eth_ks2_slave
) = {
1141 .name
= "eth_ks2_sl",
1143 .ofdata_to_platdata
= ks2_sl_eth_ofdata_to_platdata
,
1144 .probe
= ks2_eth_probe
,
1145 .remove
= ks2_eth_remove
,
1146 .ops
= &ks2_eth_ops
,
1147 .priv_auto_alloc_size
= sizeof(struct ks2_eth_priv
),
1148 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
1149 .flags
= DM_FLAG_ALLOC_PRIV_DMA
,
1152 U_BOOT_DRIVER(eth_ks2
) = {
1155 .of_match
= ks2_eth_ids
,
1156 .ofdata_to_platdata
= ks2_eth_ofdata_to_platdata
,
1157 .probe
= ks2_eth_probe
,
1158 .remove
= ks2_eth_remove
,
1159 .ops
= &ks2_eth_ops
,
1160 .priv_auto_alloc_size
= sizeof(struct ks2_eth_priv
),
1161 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
1162 .flags
= DM_FLAG_ALLOC_PRIV_DMA
,