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Merge git://www.denx.de/git/u-boot-ppc4xx
[people/ms/u-boot.git] / drivers / net / keystone_net.c
1 /*
2 * Ethernet driver for TI K2HK EVM.
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9 #include <common.h>
10 #include <command.h>
11 #include <console.h>
12
13 #include <dm.h>
14 #include <dm/lists.h>
15
16 #include <net.h>
17 #include <phy.h>
18 #include <errno.h>
19 #include <miiphy.h>
20 #include <malloc.h>
21 #include <asm/ti-common/keystone_nav.h>
22 #include <asm/ti-common/keystone_net.h>
23 #include <asm/ti-common/keystone_serdes.h>
24 #include <asm/arch/psc_defs.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #ifndef CONFIG_DM_ETH
29 unsigned int emac_open;
30 static struct mii_dev *mdio_bus;
31 static unsigned int sys_has_mdio = 1;
32 #endif
33
34 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
35 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
36 #else
37 #define emac_gigabit_enable(x) /* no gigabit to enable */
38 #endif
39
40 #define RX_BUFF_NUMS 24
41 #define RX_BUFF_LEN 1520
42 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
43 #define SGMII_ANEG_TIMEOUT 4000
44
45 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
46
47 #ifndef CONFIG_DM_ETH
48 struct rx_buff_desc net_rx_buffs = {
49 .buff_ptr = rx_buffs,
50 .num_buffs = RX_BUFF_NUMS,
51 .buff_len = RX_BUFF_LEN,
52 .rx_flow = 22,
53 };
54 #endif
55
56 #ifdef CONFIG_DM_ETH
57
58 enum link_type {
59 LINK_TYPE_MAC_TO_MAC_AUTO = 0,
60 LINK_TYPE_MAC_TO_PHY_MODE = 1,
61 LINK_TYPE_MAC_TO_MAC_FORCED_MODE = 2,
62 LINK_TYPE_MAC_TO_FIBRE_MODE = 3,
63 LINK_TYPE_MAC_TO_PHY_NO_MDIO_MODE = 4,
64 LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
65 LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
66 };
67
68 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
69 ((mac)[2] << 16) | ((mac)[3] << 24))
70 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
71
72 #ifdef CONFIG_KSNET_NETCP_V1_0
73
74 #define EMAC_EMACSW_BASE_OFS 0x90800
75 #define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
76
77 /* CPSW Switch slave registers */
78 #define CPGMACSL_REG_SA_LO 0x10
79 #define CPGMACSL_REG_SA_HI 0x14
80
81 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
82 (x) * 0x30)
83
84 #elif defined CONFIG_KSNET_NETCP_V1_5
85
86 #define EMAC_EMACSW_PORT_BASE_OFS 0x222000
87
88 /* CPSW Switch slave registers */
89 #define CPGMACSL_REG_SA_LO 0x308
90 #define CPGMACSL_REG_SA_HI 0x30c
91
92 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
93 (x) * 0x1000)
94
95 #endif
96
97
98 struct ks2_eth_priv {
99 struct udevice *dev;
100 struct phy_device *phydev;
101 struct mii_dev *mdio_bus;
102 int phy_addr;
103 phy_interface_t phy_if;
104 int sgmii_link_type;
105 void *mdio_base;
106 struct rx_buff_desc net_rx_buffs;
107 struct pktdma_cfg *netcp_pktdma;
108 void *hd;
109 int slave_port;
110 enum link_type link_type;
111 bool emac_open;
112 bool has_mdio;
113 };
114 #endif
115
116 /* MDIO */
117
118 static int keystone2_mdio_reset(struct mii_dev *bus)
119 {
120 u_int32_t clkdiv;
121 struct mdio_regs *adap_mdio = bus->priv;
122
123 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
124
125 writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
126 MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
127 &adap_mdio->control);
128
129 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
130 ;
131
132 return 0;
133 }
134
135 /**
136 * keystone2_mdio_read - read a PHY register via MDIO interface.
137 * Blocks until operation is complete.
138 */
139 static int keystone2_mdio_read(struct mii_dev *bus,
140 int addr, int devad, int reg)
141 {
142 int tmp;
143 struct mdio_regs *adap_mdio = bus->priv;
144
145 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
146 ;
147
148 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
149 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
150 &adap_mdio->useraccess0);
151
152 /* Wait for command to complete */
153 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
154 ;
155
156 if (tmp & MDIO_USERACCESS0_ACK)
157 return tmp & 0xffff;
158
159 return -1;
160 }
161
162 /**
163 * keystone2_mdio_write - write to a PHY register via MDIO interface.
164 * Blocks until operation is complete.
165 */
166 static int keystone2_mdio_write(struct mii_dev *bus,
167 int addr, int devad, int reg, u16 val)
168 {
169 struct mdio_regs *adap_mdio = bus->priv;
170
171 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
172 ;
173
174 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
175 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
176 (val & 0xffff), &adap_mdio->useraccess0);
177
178 /* Wait for command to complete */
179 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
180 ;
181
182 return 0;
183 }
184
185 #ifndef CONFIG_DM_ETH
186 static void __attribute__((unused))
187 keystone2_eth_gigabit_enable(struct eth_device *dev)
188 {
189 u_int16_t data;
190 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
191
192 if (sys_has_mdio) {
193 data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
194 MDIO_DEVAD_NONE, 0);
195 /* speed selection MSB */
196 if (!(data & (1 << 6)))
197 return;
198 }
199
200 /*
201 * Check if link detected is giga-bit
202 * If Gigabit mode detected, enable gigbit in MAC
203 */
204 writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
205 CPGMACSL_REG_CTL) |
206 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
207 DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
208 }
209 #else
210 static void __attribute__((unused))
211 keystone2_eth_gigabit_enable(struct udevice *dev)
212 {
213 struct ks2_eth_priv *priv = dev_get_priv(dev);
214 u_int16_t data;
215
216 if (priv->has_mdio) {
217 data = keystone2_mdio_read(priv->mdio_bus, priv->phy_addr,
218 MDIO_DEVAD_NONE, 0);
219 /* speed selection MSB */
220 if (!(data & (1 << 6)))
221 return;
222 }
223
224 /*
225 * Check if link detected is giga-bit
226 * If Gigabit mode detected, enable gigbit in MAC
227 */
228 writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) +
229 CPGMACSL_REG_CTL) |
230 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
231 DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL);
232 }
233 #endif
234
235 #ifdef CONFIG_SOC_K2G
236 int keystone_rgmii_config(struct phy_device *phy_dev)
237 {
238 unsigned int i, status;
239
240 i = 0;
241 do {
242 if (i > SGMII_ANEG_TIMEOUT) {
243 puts(" TIMEOUT !\n");
244 phy_dev->link = 0;
245 return 0;
246 }
247
248 if (ctrlc()) {
249 puts("user interrupt!\n");
250 phy_dev->link = 0;
251 return -EINTR;
252 }
253
254 if ((i++ % 500) == 0)
255 printf(".");
256
257 udelay(1000); /* 1 ms */
258 status = readl(RGMII_STATUS_REG);
259 } while (!(status & RGMII_REG_STATUS_LINK));
260
261 puts(" done\n");
262
263 return 0;
264 }
265 #else
266 int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
267 {
268 unsigned int i, status, mask;
269 unsigned int mr_adv_ability, control;
270
271 switch (interface) {
272 case SGMII_LINK_MAC_MAC_AUTONEG:
273 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
274 SGMII_REG_MR_ADV_LINK |
275 SGMII_REG_MR_ADV_FULL_DUPLEX |
276 SGMII_REG_MR_ADV_GIG_MODE);
277 control = (SGMII_REG_CONTROL_MASTER |
278 SGMII_REG_CONTROL_AUTONEG);
279
280 break;
281 case SGMII_LINK_MAC_PHY:
282 case SGMII_LINK_MAC_PHY_FORCED:
283 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
284 control = SGMII_REG_CONTROL_AUTONEG;
285
286 break;
287 case SGMII_LINK_MAC_MAC_FORCED:
288 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
289 SGMII_REG_MR_ADV_LINK |
290 SGMII_REG_MR_ADV_FULL_DUPLEX |
291 SGMII_REG_MR_ADV_GIG_MODE);
292 control = SGMII_REG_CONTROL_MASTER;
293
294 break;
295 case SGMII_LINK_MAC_FIBER:
296 mr_adv_ability = 0x20;
297 control = SGMII_REG_CONTROL_AUTONEG;
298
299 break;
300 default:
301 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
302 control = SGMII_REG_CONTROL_AUTONEG;
303 }
304
305 __raw_writel(0, SGMII_CTL_REG(port));
306
307 /*
308 * Wait for the SerDes pll to lock,
309 * but don't trap if lock is never read
310 */
311 for (i = 0; i < 1000; i++) {
312 udelay(2000);
313 status = __raw_readl(SGMII_STATUS_REG(port));
314 if ((status & SGMII_REG_STATUS_LOCK) != 0)
315 break;
316 }
317
318 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
319 __raw_writel(control, SGMII_CTL_REG(port));
320
321
322 mask = SGMII_REG_STATUS_LINK;
323
324 if (control & SGMII_REG_CONTROL_AUTONEG)
325 mask |= SGMII_REG_STATUS_AUTONEG;
326
327 status = __raw_readl(SGMII_STATUS_REG(port));
328 if ((status & mask) == mask)
329 return 0;
330
331 printf("\n%s Waiting for SGMII auto negotiation to complete",
332 phy_dev->dev->name);
333 while ((status & mask) != mask) {
334 /*
335 * Timeout reached ?
336 */
337 if (i > SGMII_ANEG_TIMEOUT) {
338 puts(" TIMEOUT !\n");
339 phy_dev->link = 0;
340 return 0;
341 }
342
343 if (ctrlc()) {
344 puts("user interrupt!\n");
345 phy_dev->link = 0;
346 return -EINTR;
347 }
348
349 if ((i++ % 500) == 0)
350 printf(".");
351
352 udelay(1000); /* 1 ms */
353 status = __raw_readl(SGMII_STATUS_REG(port));
354 }
355 puts(" done\n");
356
357 return 0;
358 }
359 #endif
360
361 int mac_sl_reset(u32 port)
362 {
363 u32 i, v;
364
365 if (port >= DEVICE_N_GMACSL_PORTS)
366 return GMACSL_RET_INVALID_PORT;
367
368 /* Set the soft reset bit */
369 writel(CPGMAC_REG_RESET_VAL_RESET,
370 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
371
372 /* Wait for the bit to clear */
373 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
374 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
375 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
376 CPGMAC_REG_RESET_VAL_RESET)
377 return GMACSL_RET_OK;
378 }
379
380 /* Timeout on the reset */
381 return GMACSL_RET_WARN_RESET_INCOMPLETE;
382 }
383
384 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
385 {
386 u32 v, i;
387 int ret = GMACSL_RET_OK;
388
389 if (port >= DEVICE_N_GMACSL_PORTS)
390 return GMACSL_RET_INVALID_PORT;
391
392 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
393 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
394 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
395 }
396
397 /* Must wait if the device is undergoing reset */
398 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
399 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
400 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
401 CPGMAC_REG_RESET_VAL_RESET)
402 break;
403 }
404
405 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
406 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
407
408 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
409 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
410
411 #ifndef CONFIG_SOC_K2HK
412 /* Map RX packet flow priority to 0 */
413 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
414 #endif
415
416 return ret;
417 }
418
419 int ethss_config(u32 ctl, u32 max_pkt_size)
420 {
421 u32 i;
422
423 /* Max length register */
424 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
425
426 /* Control register */
427 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
428
429 /* All statistics enabled by default */
430 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
431 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
432
433 /* Reset and enable the ALE */
434 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
435 CPSW_REG_VAL_ALE_CTL_BYPASS,
436 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
437
438 /* All ports put into forward mode */
439 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
440 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
441 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
442
443 return 0;
444 }
445
446 int ethss_start(void)
447 {
448 int i;
449 struct mac_sl_cfg cfg;
450
451 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
452 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
453
454 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
455 mac_sl_reset(i);
456 mac_sl_config(i, &cfg);
457 }
458
459 return 0;
460 }
461
462 int ethss_stop(void)
463 {
464 int i;
465
466 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
467 mac_sl_reset(i);
468
469 return 0;
470 }
471
472 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
473 .clk = SERDES_CLOCK_156P25M,
474 .rate = SERDES_RATE_5G,
475 .rate_mode = SERDES_QUARTER_RATE,
476 .intf = SERDES_PHY_SGMII,
477 .loopback = 0,
478 };
479
480 #ifndef CONFIG_SOC_K2G
481 static void keystone2_net_serdes_setup(void)
482 {
483 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
484 &ks2_serdes_sgmii_156p25mhz,
485 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
486
487 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
488 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
489 &ks2_serdes_sgmii_156p25mhz,
490 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
491 #endif
492
493 /* wait till setup */
494 udelay(5000);
495 }
496 #endif
497
498 #ifndef CONFIG_DM_ETH
499
500 int keystone2_eth_read_mac_addr(struct eth_device *dev)
501 {
502 struct eth_priv_t *eth_priv;
503 u32 maca = 0;
504 u32 macb = 0;
505
506 eth_priv = (struct eth_priv_t *)dev->priv;
507
508 /* Read the e-fuse mac address */
509 if (eth_priv->slave_port == 1) {
510 maca = __raw_readl(MAC_ID_BASE_ADDR);
511 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
512 }
513
514 dev->enetaddr[0] = (macb >> 8) & 0xff;
515 dev->enetaddr[1] = (macb >> 0) & 0xff;
516 dev->enetaddr[2] = (maca >> 24) & 0xff;
517 dev->enetaddr[3] = (maca >> 16) & 0xff;
518 dev->enetaddr[4] = (maca >> 8) & 0xff;
519 dev->enetaddr[5] = (maca >> 0) & 0xff;
520
521 return 0;
522 }
523
524 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
525 {
526 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
527 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
528
529 return ksnav_send(&netcp_pktdma, buffer,
530 num_bytes, (slave_port_num) << 16);
531 }
532
533 /* Eth device open */
534 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
535 {
536 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
537 struct phy_device *phy_dev = eth_priv->phy_dev;
538
539 debug("+ emac_open\n");
540
541 net_rx_buffs.rx_flow = eth_priv->rx_flow;
542
543 sys_has_mdio =
544 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
545
546 if (sys_has_mdio)
547 keystone2_mdio_reset(mdio_bus);
548
549 #ifdef CONFIG_SOC_K2G
550 keystone_rgmii_config(phy_dev);
551 #else
552 keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
553 eth_priv->sgmii_link_type);
554 #endif
555
556 udelay(10000);
557
558 /* On chip switch configuration */
559 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
560
561 /* TODO: add error handling code */
562 if (qm_init()) {
563 printf("ERROR: qm_init()\n");
564 return -1;
565 }
566 if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
567 qm_close();
568 printf("ERROR: netcp_init()\n");
569 return -1;
570 }
571
572 /*
573 * Streaming switch configuration. If not present this
574 * statement is defined to void in target.h.
575 * If present this is usually defined to a series of register writes
576 */
577 hw_config_streaming_switch();
578
579 if (sys_has_mdio) {
580 keystone2_mdio_reset(mdio_bus);
581
582 phy_startup(phy_dev);
583 if (phy_dev->link == 0) {
584 ksnav_close(&netcp_pktdma);
585 qm_close();
586 return -1;
587 }
588 }
589
590 emac_gigabit_enable(dev);
591
592 ethss_start();
593
594 debug("- emac_open\n");
595
596 emac_open = 1;
597
598 return 0;
599 }
600
601 /* Eth device close */
602 void keystone2_eth_close(struct eth_device *dev)
603 {
604 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
605 struct phy_device *phy_dev = eth_priv->phy_dev;
606
607 debug("+ emac_close\n");
608
609 if (!emac_open)
610 return;
611
612 ethss_stop();
613
614 ksnav_close(&netcp_pktdma);
615 qm_close();
616 phy_shutdown(phy_dev);
617
618 emac_open = 0;
619
620 debug("- emac_close\n");
621 }
622
623 /*
624 * This function sends a single packet on the network and returns
625 * positive number (number of bytes transmitted) or negative for error
626 */
627 static int keystone2_eth_send_packet(struct eth_device *dev,
628 void *packet, int length)
629 {
630 int ret_status = -1;
631 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
632 struct phy_device *phy_dev = eth_priv->phy_dev;
633
634 genphy_update_link(phy_dev);
635 if (phy_dev->link == 0)
636 return -1;
637
638 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
639 return ret_status;
640
641 return length;
642 }
643
644 /*
645 * This function handles receipt of a packet from the network
646 */
647 static int keystone2_eth_rcv_packet(struct eth_device *dev)
648 {
649 void *hd;
650 int pkt_size;
651 u32 *pkt;
652
653 hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
654 if (hd == NULL)
655 return 0;
656
657 net_process_received_packet((uchar *)pkt, pkt_size);
658
659 ksnav_release_rxhd(&netcp_pktdma, hd);
660
661 return pkt_size;
662 }
663
664 #ifdef CONFIG_MCAST_TFTP
665 static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set)
666 {
667 return 0;
668 }
669 #endif
670
671 /*
672 * This function initializes the EMAC hardware.
673 */
674 int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
675 {
676 int res;
677 struct eth_device *dev;
678 struct phy_device *phy_dev;
679 struct mdio_regs *adap_mdio = (struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
680
681 dev = malloc(sizeof(struct eth_device));
682 if (dev == NULL)
683 return -1;
684
685 memset(dev, 0, sizeof(struct eth_device));
686
687 strcpy(dev->name, eth_priv->int_name);
688 dev->priv = eth_priv;
689
690 keystone2_eth_read_mac_addr(dev);
691
692 dev->iobase = 0;
693 dev->init = keystone2_eth_open;
694 dev->halt = keystone2_eth_close;
695 dev->send = keystone2_eth_send_packet;
696 dev->recv = keystone2_eth_rcv_packet;
697 #ifdef CONFIG_MCAST_TFTP
698 dev->mcast = keystone2_eth_bcast_addr;
699 #endif
700
701 eth_register(dev);
702
703 /* Register MDIO bus if it's not registered yet */
704 if (!mdio_bus) {
705 mdio_bus = mdio_alloc();
706 mdio_bus->read = keystone2_mdio_read;
707 mdio_bus->write = keystone2_mdio_write;
708 mdio_bus->reset = keystone2_mdio_reset;
709 mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
710 strcpy(mdio_bus->name, "ethernet-mdio");
711
712 res = mdio_register(mdio_bus);
713 if (res)
714 return res;
715 }
716
717 #ifndef CONFIG_SOC_K2G
718 keystone2_net_serdes_setup();
719 #endif
720
721 /* Create phy device and bind it with driver */
722 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
723 phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
724 dev, eth_priv->phy_if);
725 phy_config(phy_dev);
726 #else
727 phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
728 eth_priv->phy_if);
729 phy_dev->dev = dev;
730 #endif
731 eth_priv->phy_dev = phy_dev;
732
733 return 0;
734 }
735
736 #else
737
738 static int ks2_eth_start(struct udevice *dev)
739 {
740 struct ks2_eth_priv *priv = dev_get_priv(dev);
741
742 #ifdef CONFIG_SOC_K2G
743 keystone_rgmii_config(priv->phydev);
744 #else
745 keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
746 priv->sgmii_link_type);
747 #endif
748
749 udelay(10000);
750
751 /* On chip switch configuration */
752 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
753
754 qm_init();
755
756 if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) {
757 error("ksnav_init failed\n");
758 goto err_knav_init;
759 }
760
761 /*
762 * Streaming switch configuration. If not present this
763 * statement is defined to void in target.h.
764 * If present this is usually defined to a series of register writes
765 */
766 hw_config_streaming_switch();
767
768 if (priv->has_mdio) {
769 keystone2_mdio_reset(priv->mdio_bus);
770
771 phy_startup(priv->phydev);
772 if (priv->phydev->link == 0) {
773 error("phy startup failed\n");
774 goto err_phy_start;
775 }
776 }
777
778 emac_gigabit_enable(dev);
779
780 ethss_start();
781
782 priv->emac_open = true;
783
784 return 0;
785
786 err_phy_start:
787 ksnav_close(priv->netcp_pktdma);
788 err_knav_init:
789 qm_close();
790
791 return -EFAULT;
792 }
793
794 static int ks2_eth_send(struct udevice *dev, void *packet, int length)
795 {
796 struct ks2_eth_priv *priv = dev_get_priv(dev);
797
798 genphy_update_link(priv->phydev);
799 if (priv->phydev->link == 0)
800 return -1;
801
802 if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
803 length = EMAC_MIN_ETHERNET_PKT_SIZE;
804
805 return ksnav_send(priv->netcp_pktdma, (u32 *)packet,
806 length, (priv->slave_port) << 16);
807 }
808
809 static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp)
810 {
811 struct ks2_eth_priv *priv = dev_get_priv(dev);
812 int pkt_size;
813 u32 *pkt = NULL;
814
815 priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size);
816 if (priv->hd == NULL)
817 return -EAGAIN;
818
819 *packetp = (uchar *)pkt;
820
821 return pkt_size;
822 }
823
824 static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet,
825 int length)
826 {
827 struct ks2_eth_priv *priv = dev_get_priv(dev);
828
829 ksnav_release_rxhd(priv->netcp_pktdma, priv->hd);
830
831 return 0;
832 }
833
834 static void ks2_eth_stop(struct udevice *dev)
835 {
836 struct ks2_eth_priv *priv = dev_get_priv(dev);
837
838 if (!priv->emac_open)
839 return;
840 ethss_stop();
841
842 ksnav_close(priv->netcp_pktdma);
843 qm_close();
844 phy_shutdown(priv->phydev);
845 priv->emac_open = false;
846 }
847
848 int ks2_eth_read_rom_hwaddr(struct udevice *dev)
849 {
850 struct ks2_eth_priv *priv = dev_get_priv(dev);
851 struct eth_pdata *pdata = dev_get_platdata(dev);
852 u32 maca = 0;
853 u32 macb = 0;
854
855 /* Read the e-fuse mac address */
856 if (priv->slave_port == 1) {
857 maca = __raw_readl(MAC_ID_BASE_ADDR);
858 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
859 }
860
861 pdata->enetaddr[0] = (macb >> 8) & 0xff;
862 pdata->enetaddr[1] = (macb >> 0) & 0xff;
863 pdata->enetaddr[2] = (maca >> 24) & 0xff;
864 pdata->enetaddr[3] = (maca >> 16) & 0xff;
865 pdata->enetaddr[4] = (maca >> 8) & 0xff;
866 pdata->enetaddr[5] = (maca >> 0) & 0xff;
867
868 return 0;
869 }
870
871 int ks2_eth_write_hwaddr(struct udevice *dev)
872 {
873 struct ks2_eth_priv *priv = dev_get_priv(dev);
874 struct eth_pdata *pdata = dev_get_platdata(dev);
875
876 writel(mac_hi(pdata->enetaddr),
877 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
878 CPGMACSL_REG_SA_HI);
879 writel(mac_lo(pdata->enetaddr),
880 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
881 CPGMACSL_REG_SA_LO);
882
883 return 0;
884 }
885
886 static int ks2_eth_probe(struct udevice *dev)
887 {
888 struct ks2_eth_priv *priv = dev_get_priv(dev);
889 struct mii_dev *mdio_bus;
890 int ret;
891
892 priv->dev = dev;
893
894 /* These clock enables has to be moved to common location */
895 if (cpu_is_k2g())
896 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
897
898 /* By default, select PA PLL clock as PA clock source */
899 #ifndef CONFIG_SOC_K2G
900 if (psc_enable_module(KS2_LPSC_PA))
901 return -EACCES;
902 #endif
903 if (psc_enable_module(KS2_LPSC_CPGMAC))
904 return -EACCES;
905 if (psc_enable_module(KS2_LPSC_CRYPTO))
906 return -EACCES;
907
908 if (cpu_is_k2e() || cpu_is_k2l())
909 pll_pa_clk_sel();
910
911
912 priv->net_rx_buffs.buff_ptr = rx_buffs;
913 priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
914 priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
915
916 if (priv->slave_port == 1) {
917 /*
918 * Register MDIO bus for slave 0 only, other slave have
919 * to re-use the same
920 */
921 mdio_bus = mdio_alloc();
922 if (!mdio_bus) {
923 error("MDIO alloc failed\n");
924 return -ENOMEM;
925 }
926 priv->mdio_bus = mdio_bus;
927 mdio_bus->read = keystone2_mdio_read;
928 mdio_bus->write = keystone2_mdio_write;
929 mdio_bus->reset = keystone2_mdio_reset;
930 mdio_bus->priv = priv->mdio_base;
931 sprintf(mdio_bus->name, "ethernet-mdio");
932
933 ret = mdio_register(mdio_bus);
934 if (ret) {
935 error("MDIO bus register failed\n");
936 return ret;
937 }
938 } else {
939 /* Get the MDIO bus from slave 0 device */
940 struct ks2_eth_priv *parent_priv;
941
942 parent_priv = dev_get_priv(dev->parent);
943 priv->mdio_bus = parent_priv->mdio_bus;
944 }
945
946 #ifndef CONFIG_SOC_K2G
947 keystone2_net_serdes_setup();
948 #endif
949
950 priv->netcp_pktdma = &netcp_pktdma;
951
952 if (priv->has_mdio) {
953 priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
954 dev, priv->phy_if);
955 phy_config(priv->phydev);
956 }
957
958 return 0;
959 }
960
961 int ks2_eth_remove(struct udevice *dev)
962 {
963 struct ks2_eth_priv *priv = dev_get_priv(dev);
964
965 free(priv->phydev);
966 mdio_unregister(priv->mdio_bus);
967 mdio_free(priv->mdio_bus);
968
969 return 0;
970 }
971
972 static const struct eth_ops ks2_eth_ops = {
973 .start = ks2_eth_start,
974 .send = ks2_eth_send,
975 .recv = ks2_eth_recv,
976 .free_pkt = ks2_eth_free_pkt,
977 .stop = ks2_eth_stop,
978 .read_rom_hwaddr = ks2_eth_read_rom_hwaddr,
979 .write_hwaddr = ks2_eth_write_hwaddr,
980 };
981
982 static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0)
983 {
984 const void *fdt = gd->fdt_blob;
985 struct udevice *sl_dev;
986 int interfaces;
987 int sec_slave;
988 int slave;
989 int ret;
990 char *slave_name;
991
992 interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
993 fdt_for_each_subnode(fdt, slave, interfaces) {
994 int slave_no;
995
996 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
997 if (slave_no == -ENOENT)
998 continue;
999
1000 if (slave_no == 0) {
1001 /* This is the current eth device */
1002 *gbe_0 = slave;
1003 } else {
1004 /* Slave devices to be registered */
1005 slave_name = malloc(20);
1006 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
1007 ret = device_bind_driver_to_node(dev, "eth_ks2_sl",
1008 slave_name, slave,
1009 &sl_dev);
1010 if (ret) {
1011 error("ks2_net - not able to bind slave interfaces\n");
1012 return ret;
1013 }
1014 }
1015 }
1016
1017 sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports");
1018 fdt_for_each_subnode(fdt, slave, sec_slave) {
1019 int slave_no;
1020
1021 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
1022 if (slave_no == -ENOENT)
1023 continue;
1024
1025 /* Slave devices to be registered */
1026 slave_name = malloc(20);
1027 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
1028 ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name,
1029 slave, &sl_dev);
1030 if (ret) {
1031 error("ks2_net - not able to bind slave interfaces\n");
1032 return ret;
1033 }
1034 }
1035
1036 return 0;
1037 }
1038
1039 static int ks2_eth_parse_slave_interface(int netcp, int slave,
1040 struct ks2_eth_priv *priv,
1041 struct eth_pdata *pdata)
1042 {
1043 const void *fdt = gd->fdt_blob;
1044 int mdio;
1045 int phy;
1046 int dma_count;
1047 u32 dma_channel[8];
1048
1049 priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1);
1050 priv->net_rx_buffs.rx_flow = priv->slave_port * 8;
1051
1052 /* U-Boot slave port number starts with 1 instead of 0 */
1053 priv->slave_port += 1;
1054
1055 dma_count = fdtdec_get_int_array_count(fdt, netcp,
1056 "ti,navigator-dmas",
1057 dma_channel, 8);
1058
1059 if (dma_count > (2 * priv->slave_port)) {
1060 int dma_idx;
1061
1062 dma_idx = priv->slave_port * 2 - 1;
1063 priv->net_rx_buffs.rx_flow = dma_channel[dma_idx];
1064 }
1065
1066 priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1);
1067
1068 phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle");
1069 if (phy >= 0) {
1070 priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1);
1071
1072 mdio = fdt_parent_offset(fdt, phy);
1073 if (mdio < 0) {
1074 error("mdio dt not found\n");
1075 return -ENODEV;
1076 }
1077 priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
1078 }
1079
1080 if (priv->link_type == LINK_TYPE_MAC_TO_PHY_MODE) {
1081 priv->phy_if = PHY_INTERFACE_MODE_SGMII;
1082 pdata->phy_interface = priv->phy_if;
1083 priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
1084 priv->has_mdio = true;
1085 }
1086
1087 return 0;
1088 }
1089
1090 static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev)
1091 {
1092 struct ks2_eth_priv *priv = dev_get_priv(dev);
1093 struct eth_pdata *pdata = dev_get_platdata(dev);
1094 const void *fdt = gd->fdt_blob;
1095 int slave = dev->of_offset;
1096 int interfaces;
1097 int gbe;
1098 int netcp_devices;
1099 int netcp;
1100
1101 interfaces = fdt_parent_offset(fdt, slave);
1102 gbe = fdt_parent_offset(fdt, interfaces);
1103 netcp_devices = fdt_parent_offset(fdt, gbe);
1104 netcp = fdt_parent_offset(fdt, netcp_devices);
1105
1106 ks2_eth_parse_slave_interface(netcp, slave, priv, pdata);
1107
1108 pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg");
1109
1110 return 0;
1111 }
1112
1113 static int ks2_eth_ofdata_to_platdata(struct udevice *dev)
1114 {
1115 struct ks2_eth_priv *priv = dev_get_priv(dev);
1116 struct eth_pdata *pdata = dev_get_platdata(dev);
1117 const void *fdt = gd->fdt_blob;
1118 int gbe_0 = -ENODEV;
1119 int netcp_devices;
1120 int gbe;
1121
1122 netcp_devices = fdt_subnode_offset(fdt, dev->of_offset,
1123 "netcp-devices");
1124 gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
1125
1126 ks2_eth_bind_slaves(dev, gbe, &gbe_0);
1127
1128 ks2_eth_parse_slave_interface(dev->of_offset, gbe_0, priv, pdata);
1129
1130 pdata->iobase = dev_get_addr(dev);
1131
1132 return 0;
1133 }
1134
1135 static const struct udevice_id ks2_eth_ids[] = {
1136 { .compatible = "ti,netcp-1.0" },
1137 { }
1138 };
1139
1140 U_BOOT_DRIVER(eth_ks2_slave) = {
1141 .name = "eth_ks2_sl",
1142 .id = UCLASS_ETH,
1143 .ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata,
1144 .probe = ks2_eth_probe,
1145 .remove = ks2_eth_remove,
1146 .ops = &ks2_eth_ops,
1147 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
1148 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1149 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1150 };
1151
1152 U_BOOT_DRIVER(eth_ks2) = {
1153 .name = "eth_ks2",
1154 .id = UCLASS_ETH,
1155 .of_match = ks2_eth_ids,
1156 .ofdata_to_platdata = ks2_eth_ofdata_to_platdata,
1157 .probe = ks2_eth_probe,
1158 .remove = ks2_eth_remove,
1159 .ops = &ks2_eth_ops,
1160 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
1161 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1162 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1163 };
1164 #endif
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