2 * Ethernet driver for TI K2HK EVM.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
21 #include <asm/ti-common/keystone_nav.h>
22 #include <asm/ti-common/keystone_net.h>
23 #include <asm/ti-common/keystone_serdes.h>
24 #include <asm/arch/psc_defs.h>
26 DECLARE_GLOBAL_DATA_PTR
;
29 unsigned int emac_open
;
30 static struct mii_dev
*mdio_bus
;
31 static unsigned int sys_has_mdio
= 1;
34 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
35 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
37 #define emac_gigabit_enable(x) /* no gigabit to enable */
40 #define RX_BUFF_NUMS 24
41 #define RX_BUFF_LEN 1520
42 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
43 #define SGMII_ANEG_TIMEOUT 4000
45 static u8 rx_buffs
[RX_BUFF_NUMS
* RX_BUFF_LEN
] __aligned(16);
48 struct rx_buff_desc net_rx_buffs
= {
50 .num_buffs
= RX_BUFF_NUMS
,
51 .buff_len
= RX_BUFF_LEN
,
59 LINK_TYPE_SGMII_MAC_TO_MAC_AUTO
= 0,
60 LINK_TYPE_SGMII_MAC_TO_PHY_MODE
= 1,
61 LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE
= 2,
62 LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE
= 3,
63 LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE
= 4,
64 LINK_TYPE_RGMII_LINK_MAC_PHY
= 5,
65 LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED
= 6,
66 LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO
= 7,
67 LINK_TYPE_10G_MAC_TO_PHY_MODE
= 10,
68 LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE
= 11,
71 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
72 ((mac)[2] << 16) | ((mac)[3] << 24))
73 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
75 #ifdef CONFIG_KSNET_NETCP_V1_0
77 #define EMAC_EMACSW_BASE_OFS 0x90800
78 #define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
80 /* CPSW Switch slave registers */
81 #define CPGMACSL_REG_SA_LO 0x10
82 #define CPGMACSL_REG_SA_HI 0x14
84 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
87 #elif defined CONFIG_KSNET_NETCP_V1_5
89 #define EMAC_EMACSW_PORT_BASE_OFS 0x222000
91 /* CPSW Switch slave registers */
92 #define CPGMACSL_REG_SA_LO 0x308
93 #define CPGMACSL_REG_SA_HI 0x30c
95 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
101 struct ks2_eth_priv
{
103 struct phy_device
*phydev
;
104 struct mii_dev
*mdio_bus
;
106 phy_interface_t phy_if
;
109 struct rx_buff_desc net_rx_buffs
;
110 struct pktdma_cfg
*netcp_pktdma
;
113 enum link_type link_type
;
121 static int keystone2_mdio_reset(struct mii_dev
*bus
)
124 struct mdio_regs
*adap_mdio
= bus
->priv
;
126 clkdiv
= (EMAC_MDIO_BUS_FREQ
/ EMAC_MDIO_CLOCK_FREQ
) - 1;
128 writel((clkdiv
& 0xffff) | MDIO_CONTROL_ENABLE
|
129 MDIO_CONTROL_FAULT
| MDIO_CONTROL_FAULT_ENABLE
,
130 &adap_mdio
->control
);
132 while (readl(&adap_mdio
->control
) & MDIO_CONTROL_IDLE
)
139 * keystone2_mdio_read - read a PHY register via MDIO interface.
140 * Blocks until operation is complete.
142 static int keystone2_mdio_read(struct mii_dev
*bus
,
143 int addr
, int devad
, int reg
)
146 struct mdio_regs
*adap_mdio
= bus
->priv
;
148 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
151 writel(MDIO_USERACCESS0_GO
| MDIO_USERACCESS0_WRITE_READ
|
152 ((reg
& 0x1f) << 21) | ((addr
& 0x1f) << 16),
153 &adap_mdio
->useraccess0
);
155 /* Wait for command to complete */
156 while ((tmp
= readl(&adap_mdio
->useraccess0
)) & MDIO_USERACCESS0_GO
)
159 if (tmp
& MDIO_USERACCESS0_ACK
)
166 * keystone2_mdio_write - write to a PHY register via MDIO interface.
167 * Blocks until operation is complete.
169 static int keystone2_mdio_write(struct mii_dev
*bus
,
170 int addr
, int devad
, int reg
, u16 val
)
172 struct mdio_regs
*adap_mdio
= bus
->priv
;
174 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
177 writel(MDIO_USERACCESS0_GO
| MDIO_USERACCESS0_WRITE_WRITE
|
178 ((reg
& 0x1f) << 21) | ((addr
& 0x1f) << 16) |
179 (val
& 0xffff), &adap_mdio
->useraccess0
);
181 /* Wait for command to complete */
182 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
188 #ifndef CONFIG_DM_ETH
189 static void __attribute__((unused
))
190 keystone2_eth_gigabit_enable(struct eth_device
*dev
)
193 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
196 data
= keystone2_mdio_read(mdio_bus
, eth_priv
->phy_addr
,
198 /* speed selection MSB */
199 if (!(data
& (1 << 6)))
204 * Check if link detected is giga-bit
205 * If Gigabit mode detected, enable gigbit in MAC
207 writel(readl(DEVICE_EMACSL_BASE(eth_priv
->slave_port
- 1) +
209 EMAC_MACCONTROL_GIGFORCE
| EMAC_MACCONTROL_GIGABIT_ENABLE
,
210 DEVICE_EMACSL_BASE(eth_priv
->slave_port
- 1) + CPGMACSL_REG_CTL
);
213 static void __attribute__((unused
))
214 keystone2_eth_gigabit_enable(struct udevice
*dev
)
216 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
219 if (priv
->has_mdio
) {
220 data
= keystone2_mdio_read(priv
->mdio_bus
, priv
->phy_addr
,
222 /* speed selection MSB */
223 if (!(data
& (1 << 6)))
228 * Check if link detected is giga-bit
229 * If Gigabit mode detected, enable gigbit in MAC
231 writel(readl(DEVICE_EMACSL_BASE(priv
->slave_port
- 1) +
233 EMAC_MACCONTROL_GIGFORCE
| EMAC_MACCONTROL_GIGABIT_ENABLE
,
234 DEVICE_EMACSL_BASE(priv
->slave_port
- 1) + CPGMACSL_REG_CTL
);
238 #ifdef CONFIG_SOC_K2G
239 int keystone_rgmii_config(struct phy_device
*phy_dev
)
241 unsigned int i
, status
;
245 if (i
> SGMII_ANEG_TIMEOUT
) {
246 puts(" TIMEOUT !\n");
252 puts("user interrupt!\n");
257 if ((i
++ % 500) == 0)
260 udelay(1000); /* 1 ms */
261 status
= readl(RGMII_STATUS_REG
);
262 } while (!(status
& RGMII_REG_STATUS_LINK
));
269 int keystone_sgmii_config(struct phy_device
*phy_dev
, int port
, int interface
)
271 unsigned int i
, status
, mask
;
272 unsigned int mr_adv_ability
, control
;
275 case SGMII_LINK_MAC_MAC_AUTONEG
:
276 mr_adv_ability
= (SGMII_REG_MR_ADV_ENABLE
|
277 SGMII_REG_MR_ADV_LINK
|
278 SGMII_REG_MR_ADV_FULL_DUPLEX
|
279 SGMII_REG_MR_ADV_GIG_MODE
);
280 control
= (SGMII_REG_CONTROL_MASTER
|
281 SGMII_REG_CONTROL_AUTONEG
);
284 case SGMII_LINK_MAC_PHY
:
285 case SGMII_LINK_MAC_PHY_FORCED
:
286 mr_adv_ability
= SGMII_REG_MR_ADV_ENABLE
;
287 control
= SGMII_REG_CONTROL_AUTONEG
;
290 case SGMII_LINK_MAC_MAC_FORCED
:
291 mr_adv_ability
= (SGMII_REG_MR_ADV_ENABLE
|
292 SGMII_REG_MR_ADV_LINK
|
293 SGMII_REG_MR_ADV_FULL_DUPLEX
|
294 SGMII_REG_MR_ADV_GIG_MODE
);
295 control
= SGMII_REG_CONTROL_MASTER
;
298 case SGMII_LINK_MAC_FIBER
:
299 mr_adv_ability
= 0x20;
300 control
= SGMII_REG_CONTROL_AUTONEG
;
304 mr_adv_ability
= SGMII_REG_MR_ADV_ENABLE
;
305 control
= SGMII_REG_CONTROL_AUTONEG
;
308 __raw_writel(0, SGMII_CTL_REG(port
));
311 * Wait for the SerDes pll to lock,
312 * but don't trap if lock is never read
314 for (i
= 0; i
< 1000; i
++) {
316 status
= __raw_readl(SGMII_STATUS_REG(port
));
317 if ((status
& SGMII_REG_STATUS_LOCK
) != 0)
321 __raw_writel(mr_adv_ability
, SGMII_MRADV_REG(port
));
322 __raw_writel(control
, SGMII_CTL_REG(port
));
325 mask
= SGMII_REG_STATUS_LINK
;
327 if (control
& SGMII_REG_CONTROL_AUTONEG
)
328 mask
|= SGMII_REG_STATUS_AUTONEG
;
330 status
= __raw_readl(SGMII_STATUS_REG(port
));
331 if ((status
& mask
) == mask
)
334 printf("\n%s Waiting for SGMII auto negotiation to complete",
336 while ((status
& mask
) != mask
) {
340 if (i
> SGMII_ANEG_TIMEOUT
) {
341 puts(" TIMEOUT !\n");
347 puts("user interrupt!\n");
352 if ((i
++ % 500) == 0)
355 udelay(1000); /* 1 ms */
356 status
= __raw_readl(SGMII_STATUS_REG(port
));
364 int mac_sl_reset(u32 port
)
368 if (port
>= DEVICE_N_GMACSL_PORTS
)
369 return GMACSL_RET_INVALID_PORT
;
371 /* Set the soft reset bit */
372 writel(CPGMAC_REG_RESET_VAL_RESET
,
373 DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
375 /* Wait for the bit to clear */
376 for (i
= 0; i
< DEVICE_EMACSL_RESET_POLL_COUNT
; i
++) {
377 v
= readl(DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
378 if ((v
& CPGMAC_REG_RESET_VAL_RESET_MASK
) !=
379 CPGMAC_REG_RESET_VAL_RESET
)
380 return GMACSL_RET_OK
;
383 /* Timeout on the reset */
384 return GMACSL_RET_WARN_RESET_INCOMPLETE
;
387 int mac_sl_config(u_int16_t port
, struct mac_sl_cfg
*cfg
)
390 int ret
= GMACSL_RET_OK
;
392 if (port
>= DEVICE_N_GMACSL_PORTS
)
393 return GMACSL_RET_INVALID_PORT
;
395 if (cfg
->max_rx_len
> CPGMAC_REG_MAXLEN_LEN
) {
396 cfg
->max_rx_len
= CPGMAC_REG_MAXLEN_LEN
;
397 ret
= GMACSL_RET_WARN_MAXLEN_TOO_BIG
;
400 /* Must wait if the device is undergoing reset */
401 for (i
= 0; i
< DEVICE_EMACSL_RESET_POLL_COUNT
; i
++) {
402 v
= readl(DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
403 if ((v
& CPGMAC_REG_RESET_VAL_RESET_MASK
) !=
404 CPGMAC_REG_RESET_VAL_RESET
)
408 if (i
== DEVICE_EMACSL_RESET_POLL_COUNT
)
409 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE
;
411 writel(cfg
->max_rx_len
, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_MAXLEN
);
412 writel(cfg
->ctl
, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_CTL
);
414 #ifndef CONFIG_SOC_K2HK
415 /* Map RX packet flow priority to 0 */
416 writel(0, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RX_PRI_MAP
);
422 int ethss_config(u32 ctl
, u32 max_pkt_size
)
426 /* Max length register */
427 writel(max_pkt_size
, DEVICE_CPSW_BASE
+ CPSW_REG_MAXLEN
);
429 /* Control register */
430 writel(ctl
, DEVICE_CPSW_BASE
+ CPSW_REG_CTL
);
432 /* All statistics enabled by default */
433 writel(CPSW_REG_VAL_STAT_ENABLE_ALL
,
434 DEVICE_CPSW_BASE
+ CPSW_REG_STAT_PORT_EN
);
436 /* Reset and enable the ALE */
437 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE
|
438 CPSW_REG_VAL_ALE_CTL_BYPASS
,
439 DEVICE_CPSW_BASE
+ CPSW_REG_ALE_CONTROL
);
441 /* All ports put into forward mode */
442 for (i
= 0; i
< DEVICE_CPSW_NUM_PORTS
; i
++)
443 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE
,
444 DEVICE_CPSW_BASE
+ CPSW_REG_ALE_PORTCTL(i
));
449 int ethss_start(void)
452 struct mac_sl_cfg cfg
;
454 cfg
.max_rx_len
= MAX_SIZE_STREAM_BUFFER
;
455 cfg
.ctl
= GMACSL_ENABLE
| GMACSL_RX_ENABLE_EXT_CTL
;
457 for (i
= 0; i
< DEVICE_N_GMACSL_PORTS
; i
++) {
459 mac_sl_config(i
, &cfg
);
469 for (i
= 0; i
< DEVICE_N_GMACSL_PORTS
; i
++)
475 struct ks2_serdes ks2_serdes_sgmii_156p25mhz
= {
476 .clk
= SERDES_CLOCK_156P25M
,
477 .rate
= SERDES_RATE_5G
,
478 .rate_mode
= SERDES_QUARTER_RATE
,
479 .intf
= SERDES_PHY_SGMII
,
483 #ifndef CONFIG_SOC_K2G
484 static void keystone2_net_serdes_setup(void)
486 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE
,
487 &ks2_serdes_sgmii_156p25mhz
,
488 CONFIG_KSNET_SERDES_LANES_PER_SGMII
);
490 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
491 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE
,
492 &ks2_serdes_sgmii_156p25mhz
,
493 CONFIG_KSNET_SERDES_LANES_PER_SGMII
);
496 /* wait till setup */
501 #ifndef CONFIG_DM_ETH
503 int keystone2_eth_read_mac_addr(struct eth_device
*dev
)
505 struct eth_priv_t
*eth_priv
;
509 eth_priv
= (struct eth_priv_t
*)dev
->priv
;
511 /* Read the e-fuse mac address */
512 if (eth_priv
->slave_port
== 1) {
513 maca
= __raw_readl(MAC_ID_BASE_ADDR
);
514 macb
= __raw_readl(MAC_ID_BASE_ADDR
+ 4);
517 dev
->enetaddr
[0] = (macb
>> 8) & 0xff;
518 dev
->enetaddr
[1] = (macb
>> 0) & 0xff;
519 dev
->enetaddr
[2] = (maca
>> 24) & 0xff;
520 dev
->enetaddr
[3] = (maca
>> 16) & 0xff;
521 dev
->enetaddr
[4] = (maca
>> 8) & 0xff;
522 dev
->enetaddr
[5] = (maca
>> 0) & 0xff;
527 int32_t cpmac_drv_send(u32
*buffer
, int num_bytes
, int slave_port_num
)
529 if (num_bytes
< EMAC_MIN_ETHERNET_PKT_SIZE
)
530 num_bytes
= EMAC_MIN_ETHERNET_PKT_SIZE
;
532 return ksnav_send(&netcp_pktdma
, buffer
,
533 num_bytes
, (slave_port_num
) << 16);
536 /* Eth device open */
537 static int keystone2_eth_open(struct eth_device
*dev
, bd_t
*bis
)
539 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
540 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
542 debug("+ emac_open\n");
544 net_rx_buffs
.rx_flow
= eth_priv
->rx_flow
;
547 (eth_priv
->sgmii_link_type
== SGMII_LINK_MAC_PHY
) ? 1 : 0;
550 keystone2_mdio_reset(mdio_bus
);
552 #ifdef CONFIG_SOC_K2G
553 keystone_rgmii_config(phy_dev
);
555 keystone_sgmii_config(phy_dev
, eth_priv
->slave_port
- 1,
556 eth_priv
->sgmii_link_type
);
561 /* On chip switch configuration */
562 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE
);
564 /* TODO: add error handling code */
566 printf("ERROR: qm_init()\n");
569 if (ksnav_init(&netcp_pktdma
, &net_rx_buffs
)) {
571 printf("ERROR: netcp_init()\n");
576 * Streaming switch configuration. If not present this
577 * statement is defined to void in target.h.
578 * If present this is usually defined to a series of register writes
580 hw_config_streaming_switch();
583 keystone2_mdio_reset(mdio_bus
);
585 phy_startup(phy_dev
);
586 if (phy_dev
->link
== 0) {
587 ksnav_close(&netcp_pktdma
);
593 emac_gigabit_enable(dev
);
597 debug("- emac_open\n");
604 /* Eth device close */
605 void keystone2_eth_close(struct eth_device
*dev
)
607 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
608 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
610 debug("+ emac_close\n");
617 ksnav_close(&netcp_pktdma
);
619 phy_shutdown(phy_dev
);
623 debug("- emac_close\n");
627 * This function sends a single packet on the network and returns
628 * positive number (number of bytes transmitted) or negative for error
630 static int keystone2_eth_send_packet(struct eth_device
*dev
,
631 void *packet
, int length
)
634 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
635 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
637 genphy_update_link(phy_dev
);
638 if (phy_dev
->link
== 0)
641 if (cpmac_drv_send((u32
*)packet
, length
, eth_priv
->slave_port
) != 0)
648 * This function handles receipt of a packet from the network
650 static int keystone2_eth_rcv_packet(struct eth_device
*dev
)
656 hd
= ksnav_recv(&netcp_pktdma
, &pkt
, &pkt_size
);
660 net_process_received_packet((uchar
*)pkt
, pkt_size
);
662 ksnav_release_rxhd(&netcp_pktdma
, hd
);
667 #ifdef CONFIG_MCAST_TFTP
668 static int keystone2_eth_bcast_addr(struct eth_device
*dev
, u32 ip
, u8 set
)
675 * This function initializes the EMAC hardware.
677 int keystone2_emac_initialize(struct eth_priv_t
*eth_priv
)
680 struct eth_device
*dev
;
681 struct phy_device
*phy_dev
;
682 struct mdio_regs
*adap_mdio
= (struct mdio_regs
*)EMAC_MDIO_BASE_ADDR
;
684 dev
= malloc(sizeof(struct eth_device
));
688 memset(dev
, 0, sizeof(struct eth_device
));
690 strcpy(dev
->name
, eth_priv
->int_name
);
691 dev
->priv
= eth_priv
;
693 keystone2_eth_read_mac_addr(dev
);
696 dev
->init
= keystone2_eth_open
;
697 dev
->halt
= keystone2_eth_close
;
698 dev
->send
= keystone2_eth_send_packet
;
699 dev
->recv
= keystone2_eth_rcv_packet
;
700 #ifdef CONFIG_MCAST_TFTP
701 dev
->mcast
= keystone2_eth_bcast_addr
;
706 /* Register MDIO bus if it's not registered yet */
708 mdio_bus
= mdio_alloc();
709 mdio_bus
->read
= keystone2_mdio_read
;
710 mdio_bus
->write
= keystone2_mdio_write
;
711 mdio_bus
->reset
= keystone2_mdio_reset
;
712 mdio_bus
->priv
= (void *)EMAC_MDIO_BASE_ADDR
;
713 strcpy(mdio_bus
->name
, "ethernet-mdio");
715 res
= mdio_register(mdio_bus
);
720 #ifndef CONFIG_SOC_K2G
721 keystone2_net_serdes_setup();
724 /* Create phy device and bind it with driver */
725 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
726 phy_dev
= phy_connect(mdio_bus
, eth_priv
->phy_addr
,
727 dev
, eth_priv
->phy_if
);
730 phy_dev
= phy_find_by_mask(mdio_bus
, 1 << eth_priv
->phy_addr
,
734 eth_priv
->phy_dev
= phy_dev
;
741 static int ks2_eth_start(struct udevice
*dev
)
743 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
745 #ifdef CONFIG_SOC_K2G
746 keystone_rgmii_config(priv
->phydev
);
748 keystone_sgmii_config(priv
->phydev
, priv
->slave_port
- 1,
749 priv
->sgmii_link_type
);
754 /* On chip switch configuration */
755 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE
);
759 if (ksnav_init(priv
->netcp_pktdma
, &priv
->net_rx_buffs
)) {
760 error("ksnav_init failed\n");
765 * Streaming switch configuration. If not present this
766 * statement is defined to void in target.h.
767 * If present this is usually defined to a series of register writes
769 hw_config_streaming_switch();
771 if (priv
->has_mdio
) {
772 keystone2_mdio_reset(priv
->mdio_bus
);
774 phy_startup(priv
->phydev
);
775 if (priv
->phydev
->link
== 0) {
776 error("phy startup failed\n");
781 emac_gigabit_enable(dev
);
785 priv
->emac_open
= true;
790 ksnav_close(priv
->netcp_pktdma
);
797 static int ks2_eth_send(struct udevice
*dev
, void *packet
, int length
)
799 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
801 genphy_update_link(priv
->phydev
);
802 if (priv
->phydev
->link
== 0)
805 if (length
< EMAC_MIN_ETHERNET_PKT_SIZE
)
806 length
= EMAC_MIN_ETHERNET_PKT_SIZE
;
808 return ksnav_send(priv
->netcp_pktdma
, (u32
*)packet
,
809 length
, (priv
->slave_port
) << 16);
812 static int ks2_eth_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
814 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
818 priv
->hd
= ksnav_recv(priv
->netcp_pktdma
, &pkt
, &pkt_size
);
819 if (priv
->hd
== NULL
)
822 *packetp
= (uchar
*)pkt
;
827 static int ks2_eth_free_pkt(struct udevice
*dev
, uchar
*packet
,
830 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
832 ksnav_release_rxhd(priv
->netcp_pktdma
, priv
->hd
);
837 static void ks2_eth_stop(struct udevice
*dev
)
839 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
841 if (!priv
->emac_open
)
845 ksnav_close(priv
->netcp_pktdma
);
847 phy_shutdown(priv
->phydev
);
848 priv
->emac_open
= false;
851 int ks2_eth_read_rom_hwaddr(struct udevice
*dev
)
853 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
854 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
858 /* Read the e-fuse mac address */
859 if (priv
->slave_port
== 1) {
860 maca
= __raw_readl(MAC_ID_BASE_ADDR
);
861 macb
= __raw_readl(MAC_ID_BASE_ADDR
+ 4);
864 pdata
->enetaddr
[0] = (macb
>> 8) & 0xff;
865 pdata
->enetaddr
[1] = (macb
>> 0) & 0xff;
866 pdata
->enetaddr
[2] = (maca
>> 24) & 0xff;
867 pdata
->enetaddr
[3] = (maca
>> 16) & 0xff;
868 pdata
->enetaddr
[4] = (maca
>> 8) & 0xff;
869 pdata
->enetaddr
[5] = (maca
>> 0) & 0xff;
874 int ks2_eth_write_hwaddr(struct udevice
*dev
)
876 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
877 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
879 writel(mac_hi(pdata
->enetaddr
),
880 DEVICE_EMACSW_BASE(pdata
->iobase
, priv
->slave_port
- 1) +
882 writel(mac_lo(pdata
->enetaddr
),
883 DEVICE_EMACSW_BASE(pdata
->iobase
, priv
->slave_port
- 1) +
889 static int ks2_eth_probe(struct udevice
*dev
)
891 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
892 struct mii_dev
*mdio_bus
;
897 /* These clock enables has to be moved to common location */
899 writel(KS2_ETHERNET_RGMII
, KS2_ETHERNET_CFG
);
901 /* By default, select PA PLL clock as PA clock source */
902 #ifndef CONFIG_SOC_K2G
903 if (psc_enable_module(KS2_LPSC_PA
))
906 if (psc_enable_module(KS2_LPSC_CPGMAC
))
908 if (psc_enable_module(KS2_LPSC_CRYPTO
))
911 if (cpu_is_k2e() || cpu_is_k2l())
915 priv
->net_rx_buffs
.buff_ptr
= rx_buffs
;
916 priv
->net_rx_buffs
.num_buffs
= RX_BUFF_NUMS
;
917 priv
->net_rx_buffs
.buff_len
= RX_BUFF_LEN
;
919 if (priv
->slave_port
== 1) {
921 * Register MDIO bus for slave 0 only, other slave have
924 mdio_bus
= mdio_alloc();
926 error("MDIO alloc failed\n");
929 priv
->mdio_bus
= mdio_bus
;
930 mdio_bus
->read
= keystone2_mdio_read
;
931 mdio_bus
->write
= keystone2_mdio_write
;
932 mdio_bus
->reset
= keystone2_mdio_reset
;
933 mdio_bus
->priv
= priv
->mdio_base
;
934 sprintf(mdio_bus
->name
, "ethernet-mdio");
936 ret
= mdio_register(mdio_bus
);
938 error("MDIO bus register failed\n");
942 /* Get the MDIO bus from slave 0 device */
943 struct ks2_eth_priv
*parent_priv
;
945 parent_priv
= dev_get_priv(dev
->parent
);
946 priv
->mdio_bus
= parent_priv
->mdio_bus
;
949 #ifndef CONFIG_SOC_K2G
950 keystone2_net_serdes_setup();
953 priv
->netcp_pktdma
= &netcp_pktdma
;
955 if (priv
->has_mdio
) {
956 priv
->phydev
= phy_connect(priv
->mdio_bus
, priv
->phy_addr
,
958 phy_config(priv
->phydev
);
964 int ks2_eth_remove(struct udevice
*dev
)
966 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
969 mdio_unregister(priv
->mdio_bus
);
970 mdio_free(priv
->mdio_bus
);
975 static const struct eth_ops ks2_eth_ops
= {
976 .start
= ks2_eth_start
,
977 .send
= ks2_eth_send
,
978 .recv
= ks2_eth_recv
,
979 .free_pkt
= ks2_eth_free_pkt
,
980 .stop
= ks2_eth_stop
,
981 .read_rom_hwaddr
= ks2_eth_read_rom_hwaddr
,
982 .write_hwaddr
= ks2_eth_write_hwaddr
,
985 static int ks2_eth_bind_slaves(struct udevice
*dev
, int gbe
, int *gbe_0
)
987 const void *fdt
= gd
->fdt_blob
;
988 struct udevice
*sl_dev
;
995 interfaces
= fdt_subnode_offset(fdt
, gbe
, "interfaces");
996 fdt_for_each_subnode(slave
, fdt
, interfaces
) {
999 slave_no
= fdtdec_get_int(fdt
, slave
, "slave-port", -ENOENT
);
1000 if (slave_no
== -ENOENT
)
1003 if (slave_no
== 0) {
1004 /* This is the current eth device */
1007 /* Slave devices to be registered */
1008 slave_name
= malloc(20);
1009 snprintf(slave_name
, 20, "netcp@slave-%d", slave_no
);
1010 ret
= device_bind_driver_to_node(dev
, "eth_ks2_sl",
1011 slave_name
, offset_to_ofnode(slave
),
1014 error("ks2_net - not able to bind slave interfaces\n");
1020 sec_slave
= fdt_subnode_offset(fdt
, gbe
, "secondary-slave-ports");
1021 fdt_for_each_subnode(slave
, fdt
, sec_slave
) {
1024 slave_no
= fdtdec_get_int(fdt
, slave
, "slave-port", -ENOENT
);
1025 if (slave_no
== -ENOENT
)
1028 /* Slave devices to be registered */
1029 slave_name
= malloc(20);
1030 snprintf(slave_name
, 20, "netcp@slave-%d", slave_no
);
1031 ret
= device_bind_driver_to_node(dev
, "eth_ks2_sl", slave_name
,
1032 offset_to_ofnode(slave
), &sl_dev
);
1034 error("ks2_net - not able to bind slave interfaces\n");
1042 static int ks2_eth_parse_slave_interface(int netcp
, int slave
,
1043 struct ks2_eth_priv
*priv
,
1044 struct eth_pdata
*pdata
)
1046 const void *fdt
= gd
->fdt_blob
;
1052 priv
->slave_port
= fdtdec_get_int(fdt
, slave
, "slave-port", -1);
1053 priv
->net_rx_buffs
.rx_flow
= priv
->slave_port
* 8;
1055 /* U-Boot slave port number starts with 1 instead of 0 */
1056 priv
->slave_port
+= 1;
1058 dma_count
= fdtdec_get_int_array_count(fdt
, netcp
,
1059 "ti,navigator-dmas",
1062 if (dma_count
> (2 * priv
->slave_port
)) {
1065 dma_idx
= priv
->slave_port
* 2 - 1;
1066 priv
->net_rx_buffs
.rx_flow
= dma_channel
[dma_idx
];
1069 priv
->link_type
= fdtdec_get_int(fdt
, slave
, "link-interface", -1);
1071 phy
= fdtdec_lookup_phandle(fdt
, slave
, "phy-handle");
1073 priv
->phy_addr
= fdtdec_get_int(fdt
, phy
, "reg", -1);
1075 mdio
= fdt_parent_offset(fdt
, phy
);
1077 error("mdio dt not found\n");
1080 priv
->mdio_base
= (void *)fdtdec_get_addr(fdt
, mdio
, "reg");
1083 if (priv
->link_type
== LINK_TYPE_SGMII_MAC_TO_PHY_MODE
) {
1084 priv
->phy_if
= PHY_INTERFACE_MODE_SGMII
;
1085 pdata
->phy_interface
= priv
->phy_if
;
1086 priv
->sgmii_link_type
= SGMII_LINK_MAC_PHY
;
1087 priv
->has_mdio
= true;
1088 } else if (priv
->link_type
== LINK_TYPE_RGMII_LINK_MAC_PHY
) {
1089 priv
->phy_if
= PHY_INTERFACE_MODE_RGMII
;
1090 pdata
->phy_interface
= priv
->phy_if
;
1091 priv
->has_mdio
= true;
1097 static int ks2_sl_eth_ofdata_to_platdata(struct udevice
*dev
)
1099 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
1100 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
1101 const void *fdt
= gd
->fdt_blob
;
1102 int slave
= dev_of_offset(dev
);
1108 interfaces
= fdt_parent_offset(fdt
, slave
);
1109 gbe
= fdt_parent_offset(fdt
, interfaces
);
1110 netcp_devices
= fdt_parent_offset(fdt
, gbe
);
1111 netcp
= fdt_parent_offset(fdt
, netcp_devices
);
1113 ks2_eth_parse_slave_interface(netcp
, slave
, priv
, pdata
);
1115 pdata
->iobase
= fdtdec_get_addr(fdt
, netcp
, "reg");
1120 static int ks2_eth_ofdata_to_platdata(struct udevice
*dev
)
1122 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
1123 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
1124 const void *fdt
= gd
->fdt_blob
;
1125 int gbe_0
= -ENODEV
;
1129 netcp_devices
= fdt_subnode_offset(fdt
, dev_of_offset(dev
),
1131 gbe
= fdt_subnode_offset(fdt
, netcp_devices
, "gbe");
1133 ks2_eth_bind_slaves(dev
, gbe
, &gbe_0
);
1135 ks2_eth_parse_slave_interface(dev_of_offset(dev
), gbe_0
, priv
, pdata
);
1137 pdata
->iobase
= devfdt_get_addr(dev
);
1142 static const struct udevice_id ks2_eth_ids
[] = {
1143 { .compatible
= "ti,netcp-1.0" },
1147 U_BOOT_DRIVER(eth_ks2_slave
) = {
1148 .name
= "eth_ks2_sl",
1150 .ofdata_to_platdata
= ks2_sl_eth_ofdata_to_platdata
,
1151 .probe
= ks2_eth_probe
,
1152 .remove
= ks2_eth_remove
,
1153 .ops
= &ks2_eth_ops
,
1154 .priv_auto_alloc_size
= sizeof(struct ks2_eth_priv
),
1155 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
1156 .flags
= DM_FLAG_ALLOC_PRIV_DMA
,
1159 U_BOOT_DRIVER(eth_ks2
) = {
1162 .of_match
= ks2_eth_ids
,
1163 .ofdata_to_platdata
= ks2_eth_ofdata_to_platdata
,
1164 .probe
= ks2_eth_probe
,
1165 .remove
= ks2_eth_remove
,
1166 .ops
= &ks2_eth_ops
,
1167 .priv_auto_alloc_size
= sizeof(struct ks2_eth_priv
),
1168 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
1169 .flags
= DM_FLAG_ALLOC_PRIV_DMA
,