2 * Ethernet driver for TI K2HK EVM.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/ti-common/keystone_nav.h>
18 #include <asm/ti-common/keystone_net.h>
19 #include <asm/ti-common/keystone_serdes.h>
21 unsigned int emac_open
;
22 static struct mii_dev
*mdio_bus
;
23 static unsigned int sys_has_mdio
= 1;
25 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
26 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
28 #define emac_gigabit_enable(x) /* no gigabit to enable */
31 #define RX_BUFF_NUMS 24
32 #define RX_BUFF_LEN 1520
33 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
34 #define SGMII_ANEG_TIMEOUT 4000
36 static u8 rx_buffs
[RX_BUFF_NUMS
* RX_BUFF_LEN
] __aligned(16);
38 struct rx_buff_desc net_rx_buffs
= {
40 .num_buffs
= RX_BUFF_NUMS
,
41 .buff_len
= RX_BUFF_LEN
,
45 static void keystone2_net_serdes_setup(void);
47 int keystone2_eth_read_mac_addr(struct eth_device
*dev
)
49 struct eth_priv_t
*eth_priv
;
53 eth_priv
= (struct eth_priv_t
*)dev
->priv
;
55 /* Read the e-fuse mac address */
56 if (eth_priv
->slave_port
== 1) {
57 maca
= __raw_readl(MAC_ID_BASE_ADDR
);
58 macb
= __raw_readl(MAC_ID_BASE_ADDR
+ 4);
61 dev
->enetaddr
[0] = (macb
>> 8) & 0xff;
62 dev
->enetaddr
[1] = (macb
>> 0) & 0xff;
63 dev
->enetaddr
[2] = (maca
>> 24) & 0xff;
64 dev
->enetaddr
[3] = (maca
>> 16) & 0xff;
65 dev
->enetaddr
[4] = (maca
>> 8) & 0xff;
66 dev
->enetaddr
[5] = (maca
>> 0) & 0xff;
73 static int keystone2_mdio_reset(struct mii_dev
*bus
)
76 struct mdio_regs
*adap_mdio
= bus
->priv
;
78 clkdiv
= (EMAC_MDIO_BUS_FREQ
/ EMAC_MDIO_CLOCK_FREQ
) - 1;
80 writel((clkdiv
& 0xffff) | MDIO_CONTROL_ENABLE
|
81 MDIO_CONTROL_FAULT
| MDIO_CONTROL_FAULT_ENABLE
,
84 while (readl(&adap_mdio
->control
) & MDIO_CONTROL_IDLE
)
91 * keystone2_mdio_read - read a PHY register via MDIO interface.
92 * Blocks until operation is complete.
94 static int keystone2_mdio_read(struct mii_dev
*bus
,
95 int addr
, int devad
, int reg
)
98 struct mdio_regs
*adap_mdio
= bus
->priv
;
100 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
103 writel(MDIO_USERACCESS0_GO
| MDIO_USERACCESS0_WRITE_READ
|
104 ((reg
& 0x1f) << 21) | ((addr
& 0x1f) << 16),
105 &adap_mdio
->useraccess0
);
107 /* Wait for command to complete */
108 while ((tmp
= readl(&adap_mdio
->useraccess0
)) & MDIO_USERACCESS0_GO
)
111 if (tmp
& MDIO_USERACCESS0_ACK
)
118 * keystone2_mdio_write - write to a PHY register via MDIO interface.
119 * Blocks until operation is complete.
121 static int keystone2_mdio_write(struct mii_dev
*bus
,
122 int addr
, int devad
, int reg
, u16 val
)
124 struct mdio_regs
*adap_mdio
= bus
->priv
;
126 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
129 writel(MDIO_USERACCESS0_GO
| MDIO_USERACCESS0_WRITE_WRITE
|
130 ((reg
& 0x1f) << 21) | ((addr
& 0x1f) << 16) |
131 (val
& 0xffff), &adap_mdio
->useraccess0
);
133 /* Wait for command to complete */
134 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
140 static void __attribute__((unused
))
141 keystone2_eth_gigabit_enable(struct eth_device
*dev
)
144 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
147 data
= keystone2_mdio_read(mdio_bus
, eth_priv
->phy_addr
,
149 /* speed selection MSB */
150 if (!(data
& (1 << 6)))
155 * Check if link detected is giga-bit
156 * If Gigabit mode detected, enable gigbit in MAC
158 writel(readl(DEVICE_EMACSL_BASE(eth_priv
->slave_port
- 1) +
160 EMAC_MACCONTROL_GIGFORCE
| EMAC_MACCONTROL_GIGABIT_ENABLE
,
161 DEVICE_EMACSL_BASE(eth_priv
->slave_port
- 1) + CPGMACSL_REG_CTL
);
164 int keystone_sgmii_link_status(int port
)
168 status
= __raw_readl(SGMII_STATUS_REG(port
));
170 return (status
& SGMII_REG_STATUS_LOCK
) &&
171 (status
& SGMII_REG_STATUS_LINK
);
174 int keystone_sgmii_config(struct phy_device
*phy_dev
, int port
, int interface
)
176 unsigned int i
, status
, mask
;
177 unsigned int mr_adv_ability
, control
;
180 case SGMII_LINK_MAC_MAC_AUTONEG
:
181 mr_adv_ability
= (SGMII_REG_MR_ADV_ENABLE
|
182 SGMII_REG_MR_ADV_LINK
|
183 SGMII_REG_MR_ADV_FULL_DUPLEX
|
184 SGMII_REG_MR_ADV_GIG_MODE
);
185 control
= (SGMII_REG_CONTROL_MASTER
|
186 SGMII_REG_CONTROL_AUTONEG
);
189 case SGMII_LINK_MAC_PHY
:
190 case SGMII_LINK_MAC_PHY_FORCED
:
191 mr_adv_ability
= SGMII_REG_MR_ADV_ENABLE
;
192 control
= SGMII_REG_CONTROL_AUTONEG
;
195 case SGMII_LINK_MAC_MAC_FORCED
:
196 mr_adv_ability
= (SGMII_REG_MR_ADV_ENABLE
|
197 SGMII_REG_MR_ADV_LINK
|
198 SGMII_REG_MR_ADV_FULL_DUPLEX
|
199 SGMII_REG_MR_ADV_GIG_MODE
);
200 control
= SGMII_REG_CONTROL_MASTER
;
203 case SGMII_LINK_MAC_FIBER
:
204 mr_adv_ability
= 0x20;
205 control
= SGMII_REG_CONTROL_AUTONEG
;
209 mr_adv_ability
= SGMII_REG_MR_ADV_ENABLE
;
210 control
= SGMII_REG_CONTROL_AUTONEG
;
213 __raw_writel(0, SGMII_CTL_REG(port
));
216 * Wait for the SerDes pll to lock,
217 * but don't trap if lock is never read
219 for (i
= 0; i
< 1000; i
++) {
221 status
= __raw_readl(SGMII_STATUS_REG(port
));
222 if ((status
& SGMII_REG_STATUS_LOCK
) != 0)
226 __raw_writel(mr_adv_ability
, SGMII_MRADV_REG(port
));
227 __raw_writel(control
, SGMII_CTL_REG(port
));
230 mask
= SGMII_REG_STATUS_LINK
;
232 if (control
& SGMII_REG_CONTROL_AUTONEG
)
233 mask
|= SGMII_REG_STATUS_AUTONEG
;
235 status
= __raw_readl(SGMII_STATUS_REG(port
));
236 if ((status
& mask
) == mask
)
239 printf("\n%s Waiting for SGMII auto negotiation to complete",
241 while ((status
& mask
) != mask
) {
245 if (i
> SGMII_ANEG_TIMEOUT
) {
246 puts(" TIMEOUT !\n");
252 puts("user interrupt!\n");
257 if ((i
++ % 500) == 0)
260 udelay(1000); /* 1 ms */
261 status
= __raw_readl(SGMII_STATUS_REG(port
));
268 int mac_sl_reset(u32 port
)
272 if (port
>= DEVICE_N_GMACSL_PORTS
)
273 return GMACSL_RET_INVALID_PORT
;
275 /* Set the soft reset bit */
276 writel(CPGMAC_REG_RESET_VAL_RESET
,
277 DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
279 /* Wait for the bit to clear */
280 for (i
= 0; i
< DEVICE_EMACSL_RESET_POLL_COUNT
; i
++) {
281 v
= readl(DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
282 if ((v
& CPGMAC_REG_RESET_VAL_RESET_MASK
) !=
283 CPGMAC_REG_RESET_VAL_RESET
)
284 return GMACSL_RET_OK
;
287 /* Timeout on the reset */
288 return GMACSL_RET_WARN_RESET_INCOMPLETE
;
291 int mac_sl_config(u_int16_t port
, struct mac_sl_cfg
*cfg
)
294 int ret
= GMACSL_RET_OK
;
296 if (port
>= DEVICE_N_GMACSL_PORTS
)
297 return GMACSL_RET_INVALID_PORT
;
299 if (cfg
->max_rx_len
> CPGMAC_REG_MAXLEN_LEN
) {
300 cfg
->max_rx_len
= CPGMAC_REG_MAXLEN_LEN
;
301 ret
= GMACSL_RET_WARN_MAXLEN_TOO_BIG
;
304 /* Must wait if the device is undergoing reset */
305 for (i
= 0; i
< DEVICE_EMACSL_RESET_POLL_COUNT
; i
++) {
306 v
= readl(DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
307 if ((v
& CPGMAC_REG_RESET_VAL_RESET_MASK
) !=
308 CPGMAC_REG_RESET_VAL_RESET
)
312 if (i
== DEVICE_EMACSL_RESET_POLL_COUNT
)
313 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE
;
315 writel(cfg
->max_rx_len
, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_MAXLEN
);
316 writel(cfg
->ctl
, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_CTL
);
318 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
319 /* Map RX packet flow priority to 0 */
320 writel(0, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RX_PRI_MAP
);
326 int ethss_config(u32 ctl
, u32 max_pkt_size
)
330 /* Max length register */
331 writel(max_pkt_size
, DEVICE_CPSW_BASE
+ CPSW_REG_MAXLEN
);
333 /* Control register */
334 writel(ctl
, DEVICE_CPSW_BASE
+ CPSW_REG_CTL
);
336 /* All statistics enabled by default */
337 writel(CPSW_REG_VAL_STAT_ENABLE_ALL
,
338 DEVICE_CPSW_BASE
+ CPSW_REG_STAT_PORT_EN
);
340 /* Reset and enable the ALE */
341 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE
|
342 CPSW_REG_VAL_ALE_CTL_BYPASS
,
343 DEVICE_CPSW_BASE
+ CPSW_REG_ALE_CONTROL
);
345 /* All ports put into forward mode */
346 for (i
= 0; i
< DEVICE_CPSW_NUM_PORTS
; i
++)
347 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE
,
348 DEVICE_CPSW_BASE
+ CPSW_REG_ALE_PORTCTL(i
));
353 int ethss_start(void)
356 struct mac_sl_cfg cfg
;
358 cfg
.max_rx_len
= MAX_SIZE_STREAM_BUFFER
;
359 cfg
.ctl
= GMACSL_ENABLE
| GMACSL_RX_ENABLE_EXT_CTL
;
361 for (i
= 0; i
< DEVICE_N_GMACSL_PORTS
; i
++) {
363 mac_sl_config(i
, &cfg
);
373 for (i
= 0; i
< DEVICE_N_GMACSL_PORTS
; i
++)
379 int32_t cpmac_drv_send(u32
*buffer
, int num_bytes
, int slave_port_num
)
381 if (num_bytes
< EMAC_MIN_ETHERNET_PKT_SIZE
)
382 num_bytes
= EMAC_MIN_ETHERNET_PKT_SIZE
;
384 return ksnav_send(&netcp_pktdma
, buffer
,
385 num_bytes
, (slave_port_num
) << 16);
388 /* Eth device open */
389 static int keystone2_eth_open(struct eth_device
*dev
, bd_t
*bis
)
391 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
392 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
394 debug("+ emac_open\n");
396 net_rx_buffs
.rx_flow
= eth_priv
->rx_flow
;
399 (eth_priv
->sgmii_link_type
== SGMII_LINK_MAC_PHY
) ? 1 : 0;
402 keystone2_mdio_reset(mdio_bus
);
404 keystone_sgmii_config(phy_dev
, eth_priv
->slave_port
- 1,
405 eth_priv
->sgmii_link_type
);
409 /* On chip switch configuration */
410 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE
);
412 /* TODO: add error handling code */
414 printf("ERROR: qm_init()\n");
417 if (ksnav_init(&netcp_pktdma
, &net_rx_buffs
)) {
419 printf("ERROR: netcp_init()\n");
424 * Streaming switch configuration. If not present this
425 * statement is defined to void in target.h.
426 * If present this is usually defined to a series of register writes
428 hw_config_streaming_switch();
431 keystone2_mdio_reset(mdio_bus
);
433 phy_startup(phy_dev
);
434 if (phy_dev
->link
== 0) {
435 ksnav_close(&netcp_pktdma
);
441 emac_gigabit_enable(dev
);
445 debug("- emac_open\n");
452 /* Eth device close */
453 void keystone2_eth_close(struct eth_device
*dev
)
455 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
456 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
458 debug("+ emac_close\n");
465 ksnav_close(&netcp_pktdma
);
467 phy_shutdown(phy_dev
);
471 debug("- emac_close\n");
475 * This function sends a single packet on the network and returns
476 * positive number (number of bytes transmitted) or negative for error
478 static int keystone2_eth_send_packet(struct eth_device
*dev
,
479 void *packet
, int length
)
482 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
483 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
485 genphy_update_link(phy_dev
);
486 if (phy_dev
->link
== 0)
489 if (cpmac_drv_send((u32
*)packet
, length
, eth_priv
->slave_port
) != 0)
496 * This function handles receipt of a packet from the network
498 static int keystone2_eth_rcv_packet(struct eth_device
*dev
)
504 hd
= ksnav_recv(&netcp_pktdma
, &pkt
, &pkt_size
);
508 net_process_received_packet((uchar
*)pkt
, pkt_size
);
510 ksnav_release_rxhd(&netcp_pktdma
, hd
);
515 #ifdef CONFIG_MCAST_TFTP
516 static int keystone2_eth_bcast_addr(struct eth_device
*dev
, u32 ip
, u8 set
)
523 * This function initializes the EMAC hardware.
525 int keystone2_emac_initialize(struct eth_priv_t
*eth_priv
)
528 struct eth_device
*dev
;
529 struct phy_device
*phy_dev
;
531 dev
= malloc(sizeof(struct eth_device
));
535 memset(dev
, 0, sizeof(struct eth_device
));
537 strcpy(dev
->name
, eth_priv
->int_name
);
538 dev
->priv
= eth_priv
;
540 keystone2_eth_read_mac_addr(dev
);
543 dev
->init
= keystone2_eth_open
;
544 dev
->halt
= keystone2_eth_close
;
545 dev
->send
= keystone2_eth_send_packet
;
546 dev
->recv
= keystone2_eth_rcv_packet
;
547 #ifdef CONFIG_MCAST_TFTP
548 dev
->mcast
= keystone2_eth_bcast_addr
;
553 /* Register MDIO bus if it's not registered yet */
555 mdio_bus
= mdio_alloc();
556 mdio_bus
->read
= keystone2_mdio_read
;
557 mdio_bus
->write
= keystone2_mdio_write
;
558 mdio_bus
->reset
= keystone2_mdio_reset
;
559 mdio_bus
->priv
= (void *)EMAC_MDIO_BASE_ADDR
;
560 sprintf(mdio_bus
->name
, "ethernet-mdio");
562 res
= mdio_register(mdio_bus
);
567 keystone2_net_serdes_setup();
569 /* Create phy device and bind it with driver */
570 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
571 phy_dev
= phy_connect(mdio_bus
, eth_priv
->phy_addr
,
572 dev
, PHY_INTERFACE_MODE_SGMII
);
575 phy_dev
= phy_find_by_mask(mdio_bus
, 1 << eth_priv
->phy_addr
,
576 PHY_INTERFACE_MODE_SGMII
);
579 eth_priv
->phy_dev
= phy_dev
;
584 struct ks2_serdes ks2_serdes_sgmii_156p25mhz
= {
585 .clk
= SERDES_CLOCK_156P25M
,
586 .rate
= SERDES_RATE_5G
,
587 .rate_mode
= SERDES_QUARTER_RATE
,
588 .intf
= SERDES_PHY_SGMII
,
592 static void keystone2_net_serdes_setup(void)
594 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE
,
595 &ks2_serdes_sgmii_156p25mhz
,
596 CONFIG_KSNET_SERDES_LANES_PER_SGMII
);
598 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
599 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE
,
600 &ks2_serdes_sgmii_156p25mhz
,
601 CONFIG_KSNET_SERDES_LANES_PER_SGMII
);
604 /* wait till setup */