2 * Ethernet driver for TI K2HK EVM.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm/ti-common/keystone_nav.h>
21 #include <asm/ti-common/keystone_net.h>
22 #include <asm/ti-common/keystone_serdes.h>
23 #include <asm/arch/psc_defs.h>
25 DECLARE_GLOBAL_DATA_PTR
;
28 unsigned int emac_open
;
29 static struct mii_dev
*mdio_bus
;
30 static unsigned int sys_has_mdio
= 1;
33 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
34 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
36 #define emac_gigabit_enable(x) /* no gigabit to enable */
39 #define RX_BUFF_NUMS 24
40 #define RX_BUFF_LEN 1520
41 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
42 #define SGMII_ANEG_TIMEOUT 4000
44 static u8 rx_buffs
[RX_BUFF_NUMS
* RX_BUFF_LEN
] __aligned(16);
47 struct rx_buff_desc net_rx_buffs
= {
49 .num_buffs
= RX_BUFF_NUMS
,
50 .buff_len
= RX_BUFF_LEN
,
58 LINK_TYPE_MAC_TO_MAC_AUTO
= 0,
59 LINK_TYPE_MAC_TO_PHY_MODE
= 1,
60 LINK_TYPE_MAC_TO_MAC_FORCED_MODE
= 2,
61 LINK_TYPE_MAC_TO_FIBRE_MODE
= 3,
62 LINK_TYPE_MAC_TO_PHY_NO_MDIO_MODE
= 4,
63 LINK_TYPE_10G_MAC_TO_PHY_MODE
= 10,
64 LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE
= 11,
67 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
68 ((mac)[2] << 16) | ((mac)[3] << 24))
69 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
71 #ifdef CONFIG_KSNET_NETCP_V1_0
73 #define EMAC_EMACSW_BASE_OFS 0x90800
74 #define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
76 /* CPSW Switch slave registers */
77 #define CPGMACSL_REG_SA_LO 0x10
78 #define CPGMACSL_REG_SA_HI 0x14
80 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
83 #elif defined CONFIG_KSNET_NETCP_V1_5
85 #define EMAC_EMACSW_PORT_BASE_OFS 0x222000
87 /* CPSW Switch slave registers */
88 #define CPGMACSL_REG_SA_LO 0x308
89 #define CPGMACSL_REG_SA_HI 0x30c
91 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
99 struct phy_device
*phydev
;
100 struct mii_dev
*mdio_bus
;
102 phy_interface_t phy_if
;
105 struct rx_buff_desc net_rx_buffs
;
106 struct pktdma_cfg
*netcp_pktdma
;
109 enum link_type link_type
;
117 static int keystone2_mdio_reset(struct mii_dev
*bus
)
120 struct mdio_regs
*adap_mdio
= bus
->priv
;
122 clkdiv
= (EMAC_MDIO_BUS_FREQ
/ EMAC_MDIO_CLOCK_FREQ
) - 1;
124 writel((clkdiv
& 0xffff) | MDIO_CONTROL_ENABLE
|
125 MDIO_CONTROL_FAULT
| MDIO_CONTROL_FAULT_ENABLE
,
126 &adap_mdio
->control
);
128 while (readl(&adap_mdio
->control
) & MDIO_CONTROL_IDLE
)
135 * keystone2_mdio_read - read a PHY register via MDIO interface.
136 * Blocks until operation is complete.
138 static int keystone2_mdio_read(struct mii_dev
*bus
,
139 int addr
, int devad
, int reg
)
142 struct mdio_regs
*adap_mdio
= bus
->priv
;
144 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
147 writel(MDIO_USERACCESS0_GO
| MDIO_USERACCESS0_WRITE_READ
|
148 ((reg
& 0x1f) << 21) | ((addr
& 0x1f) << 16),
149 &adap_mdio
->useraccess0
);
151 /* Wait for command to complete */
152 while ((tmp
= readl(&adap_mdio
->useraccess0
)) & MDIO_USERACCESS0_GO
)
155 if (tmp
& MDIO_USERACCESS0_ACK
)
162 * keystone2_mdio_write - write to a PHY register via MDIO interface.
163 * Blocks until operation is complete.
165 static int keystone2_mdio_write(struct mii_dev
*bus
,
166 int addr
, int devad
, int reg
, u16 val
)
168 struct mdio_regs
*adap_mdio
= bus
->priv
;
170 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
173 writel(MDIO_USERACCESS0_GO
| MDIO_USERACCESS0_WRITE_WRITE
|
174 ((reg
& 0x1f) << 21) | ((addr
& 0x1f) << 16) |
175 (val
& 0xffff), &adap_mdio
->useraccess0
);
177 /* Wait for command to complete */
178 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
184 #ifndef CONFIG_DM_ETH
185 static void __attribute__((unused
))
186 keystone2_eth_gigabit_enable(struct eth_device
*dev
)
189 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
192 data
= keystone2_mdio_read(mdio_bus
, eth_priv
->phy_addr
,
194 /* speed selection MSB */
195 if (!(data
& (1 << 6)))
200 * Check if link detected is giga-bit
201 * If Gigabit mode detected, enable gigbit in MAC
203 writel(readl(DEVICE_EMACSL_BASE(eth_priv
->slave_port
- 1) +
205 EMAC_MACCONTROL_GIGFORCE
| EMAC_MACCONTROL_GIGABIT_ENABLE
,
206 DEVICE_EMACSL_BASE(eth_priv
->slave_port
- 1) + CPGMACSL_REG_CTL
);
209 static void __attribute__((unused
))
210 keystone2_eth_gigabit_enable(struct udevice
*dev
)
212 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
215 if (priv
->has_mdio
) {
216 data
= keystone2_mdio_read(priv
->mdio_bus
, priv
->phy_addr
,
218 /* speed selection MSB */
219 if (!(data
& (1 << 6)))
224 * Check if link detected is giga-bit
225 * If Gigabit mode detected, enable gigbit in MAC
227 writel(readl(DEVICE_EMACSL_BASE(priv
->slave_port
- 1) +
229 EMAC_MACCONTROL_GIGFORCE
| EMAC_MACCONTROL_GIGABIT_ENABLE
,
230 DEVICE_EMACSL_BASE(priv
->slave_port
- 1) + CPGMACSL_REG_CTL
);
234 #ifdef CONFIG_SOC_K2G
235 int keystone_rgmii_config(struct phy_device
*phy_dev
)
237 unsigned int i
, status
;
241 if (i
> SGMII_ANEG_TIMEOUT
) {
242 puts(" TIMEOUT !\n");
248 puts("user interrupt!\n");
253 if ((i
++ % 500) == 0)
256 udelay(1000); /* 1 ms */
257 status
= readl(RGMII_STATUS_REG
);
258 } while (!(status
& RGMII_REG_STATUS_LINK
));
265 int keystone_sgmii_config(struct phy_device
*phy_dev
, int port
, int interface
)
267 unsigned int i
, status
, mask
;
268 unsigned int mr_adv_ability
, control
;
271 case SGMII_LINK_MAC_MAC_AUTONEG
:
272 mr_adv_ability
= (SGMII_REG_MR_ADV_ENABLE
|
273 SGMII_REG_MR_ADV_LINK
|
274 SGMII_REG_MR_ADV_FULL_DUPLEX
|
275 SGMII_REG_MR_ADV_GIG_MODE
);
276 control
= (SGMII_REG_CONTROL_MASTER
|
277 SGMII_REG_CONTROL_AUTONEG
);
280 case SGMII_LINK_MAC_PHY
:
281 case SGMII_LINK_MAC_PHY_FORCED
:
282 mr_adv_ability
= SGMII_REG_MR_ADV_ENABLE
;
283 control
= SGMII_REG_CONTROL_AUTONEG
;
286 case SGMII_LINK_MAC_MAC_FORCED
:
287 mr_adv_ability
= (SGMII_REG_MR_ADV_ENABLE
|
288 SGMII_REG_MR_ADV_LINK
|
289 SGMII_REG_MR_ADV_FULL_DUPLEX
|
290 SGMII_REG_MR_ADV_GIG_MODE
);
291 control
= SGMII_REG_CONTROL_MASTER
;
294 case SGMII_LINK_MAC_FIBER
:
295 mr_adv_ability
= 0x20;
296 control
= SGMII_REG_CONTROL_AUTONEG
;
300 mr_adv_ability
= SGMII_REG_MR_ADV_ENABLE
;
301 control
= SGMII_REG_CONTROL_AUTONEG
;
304 __raw_writel(0, SGMII_CTL_REG(port
));
307 * Wait for the SerDes pll to lock,
308 * but don't trap if lock is never read
310 for (i
= 0; i
< 1000; i
++) {
312 status
= __raw_readl(SGMII_STATUS_REG(port
));
313 if ((status
& SGMII_REG_STATUS_LOCK
) != 0)
317 __raw_writel(mr_adv_ability
, SGMII_MRADV_REG(port
));
318 __raw_writel(control
, SGMII_CTL_REG(port
));
321 mask
= SGMII_REG_STATUS_LINK
;
323 if (control
& SGMII_REG_CONTROL_AUTONEG
)
324 mask
|= SGMII_REG_STATUS_AUTONEG
;
326 status
= __raw_readl(SGMII_STATUS_REG(port
));
327 if ((status
& mask
) == mask
)
330 printf("\n%s Waiting for SGMII auto negotiation to complete",
332 while ((status
& mask
) != mask
) {
336 if (i
> SGMII_ANEG_TIMEOUT
) {
337 puts(" TIMEOUT !\n");
343 puts("user interrupt!\n");
348 if ((i
++ % 500) == 0)
351 udelay(1000); /* 1 ms */
352 status
= __raw_readl(SGMII_STATUS_REG(port
));
360 int mac_sl_reset(u32 port
)
364 if (port
>= DEVICE_N_GMACSL_PORTS
)
365 return GMACSL_RET_INVALID_PORT
;
367 /* Set the soft reset bit */
368 writel(CPGMAC_REG_RESET_VAL_RESET
,
369 DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
371 /* Wait for the bit to clear */
372 for (i
= 0; i
< DEVICE_EMACSL_RESET_POLL_COUNT
; i
++) {
373 v
= readl(DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
374 if ((v
& CPGMAC_REG_RESET_VAL_RESET_MASK
) !=
375 CPGMAC_REG_RESET_VAL_RESET
)
376 return GMACSL_RET_OK
;
379 /* Timeout on the reset */
380 return GMACSL_RET_WARN_RESET_INCOMPLETE
;
383 int mac_sl_config(u_int16_t port
, struct mac_sl_cfg
*cfg
)
386 int ret
= GMACSL_RET_OK
;
388 if (port
>= DEVICE_N_GMACSL_PORTS
)
389 return GMACSL_RET_INVALID_PORT
;
391 if (cfg
->max_rx_len
> CPGMAC_REG_MAXLEN_LEN
) {
392 cfg
->max_rx_len
= CPGMAC_REG_MAXLEN_LEN
;
393 ret
= GMACSL_RET_WARN_MAXLEN_TOO_BIG
;
396 /* Must wait if the device is undergoing reset */
397 for (i
= 0; i
< DEVICE_EMACSL_RESET_POLL_COUNT
; i
++) {
398 v
= readl(DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
399 if ((v
& CPGMAC_REG_RESET_VAL_RESET_MASK
) !=
400 CPGMAC_REG_RESET_VAL_RESET
)
404 if (i
== DEVICE_EMACSL_RESET_POLL_COUNT
)
405 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE
;
407 writel(cfg
->max_rx_len
, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_MAXLEN
);
408 writel(cfg
->ctl
, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_CTL
);
410 #ifndef CONFIG_SOC_K2HK
411 /* Map RX packet flow priority to 0 */
412 writel(0, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RX_PRI_MAP
);
418 int ethss_config(u32 ctl
, u32 max_pkt_size
)
422 /* Max length register */
423 writel(max_pkt_size
, DEVICE_CPSW_BASE
+ CPSW_REG_MAXLEN
);
425 /* Control register */
426 writel(ctl
, DEVICE_CPSW_BASE
+ CPSW_REG_CTL
);
428 /* All statistics enabled by default */
429 writel(CPSW_REG_VAL_STAT_ENABLE_ALL
,
430 DEVICE_CPSW_BASE
+ CPSW_REG_STAT_PORT_EN
);
432 /* Reset and enable the ALE */
433 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE
|
434 CPSW_REG_VAL_ALE_CTL_BYPASS
,
435 DEVICE_CPSW_BASE
+ CPSW_REG_ALE_CONTROL
);
437 /* All ports put into forward mode */
438 for (i
= 0; i
< DEVICE_CPSW_NUM_PORTS
; i
++)
439 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE
,
440 DEVICE_CPSW_BASE
+ CPSW_REG_ALE_PORTCTL(i
));
445 int ethss_start(void)
448 struct mac_sl_cfg cfg
;
450 cfg
.max_rx_len
= MAX_SIZE_STREAM_BUFFER
;
451 cfg
.ctl
= GMACSL_ENABLE
| GMACSL_RX_ENABLE_EXT_CTL
;
453 for (i
= 0; i
< DEVICE_N_GMACSL_PORTS
; i
++) {
455 mac_sl_config(i
, &cfg
);
465 for (i
= 0; i
< DEVICE_N_GMACSL_PORTS
; i
++)
471 struct ks2_serdes ks2_serdes_sgmii_156p25mhz
= {
472 .clk
= SERDES_CLOCK_156P25M
,
473 .rate
= SERDES_RATE_5G
,
474 .rate_mode
= SERDES_QUARTER_RATE
,
475 .intf
= SERDES_PHY_SGMII
,
479 #ifndef CONFIG_SOC_K2G
480 static void keystone2_net_serdes_setup(void)
482 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE
,
483 &ks2_serdes_sgmii_156p25mhz
,
484 CONFIG_KSNET_SERDES_LANES_PER_SGMII
);
486 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
487 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE
,
488 &ks2_serdes_sgmii_156p25mhz
,
489 CONFIG_KSNET_SERDES_LANES_PER_SGMII
);
492 /* wait till setup */
497 #ifndef CONFIG_DM_ETH
499 int keystone2_eth_read_mac_addr(struct eth_device
*dev
)
501 struct eth_priv_t
*eth_priv
;
505 eth_priv
= (struct eth_priv_t
*)dev
->priv
;
507 /* Read the e-fuse mac address */
508 if (eth_priv
->slave_port
== 1) {
509 maca
= __raw_readl(MAC_ID_BASE_ADDR
);
510 macb
= __raw_readl(MAC_ID_BASE_ADDR
+ 4);
513 dev
->enetaddr
[0] = (macb
>> 8) & 0xff;
514 dev
->enetaddr
[1] = (macb
>> 0) & 0xff;
515 dev
->enetaddr
[2] = (maca
>> 24) & 0xff;
516 dev
->enetaddr
[3] = (maca
>> 16) & 0xff;
517 dev
->enetaddr
[4] = (maca
>> 8) & 0xff;
518 dev
->enetaddr
[5] = (maca
>> 0) & 0xff;
523 int32_t cpmac_drv_send(u32
*buffer
, int num_bytes
, int slave_port_num
)
525 if (num_bytes
< EMAC_MIN_ETHERNET_PKT_SIZE
)
526 num_bytes
= EMAC_MIN_ETHERNET_PKT_SIZE
;
528 return ksnav_send(&netcp_pktdma
, buffer
,
529 num_bytes
, (slave_port_num
) << 16);
532 /* Eth device open */
533 static int keystone2_eth_open(struct eth_device
*dev
, bd_t
*bis
)
535 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
536 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
538 debug("+ emac_open\n");
540 net_rx_buffs
.rx_flow
= eth_priv
->rx_flow
;
543 (eth_priv
->sgmii_link_type
== SGMII_LINK_MAC_PHY
) ? 1 : 0;
546 keystone2_mdio_reset(mdio_bus
);
548 #ifdef CONFIG_SOC_K2G
549 keystone_rgmii_config(phy_dev
);
551 keystone_sgmii_config(phy_dev
, eth_priv
->slave_port
- 1,
552 eth_priv
->sgmii_link_type
);
557 /* On chip switch configuration */
558 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE
);
560 /* TODO: add error handling code */
562 printf("ERROR: qm_init()\n");
565 if (ksnav_init(&netcp_pktdma
, &net_rx_buffs
)) {
567 printf("ERROR: netcp_init()\n");
572 * Streaming switch configuration. If not present this
573 * statement is defined to void in target.h.
574 * If present this is usually defined to a series of register writes
576 hw_config_streaming_switch();
579 keystone2_mdio_reset(mdio_bus
);
581 phy_startup(phy_dev
);
582 if (phy_dev
->link
== 0) {
583 ksnav_close(&netcp_pktdma
);
589 emac_gigabit_enable(dev
);
593 debug("- emac_open\n");
600 /* Eth device close */
601 void keystone2_eth_close(struct eth_device
*dev
)
603 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
604 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
606 debug("+ emac_close\n");
613 ksnav_close(&netcp_pktdma
);
615 phy_shutdown(phy_dev
);
619 debug("- emac_close\n");
623 * This function sends a single packet on the network and returns
624 * positive number (number of bytes transmitted) or negative for error
626 static int keystone2_eth_send_packet(struct eth_device
*dev
,
627 void *packet
, int length
)
630 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
631 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
633 genphy_update_link(phy_dev
);
634 if (phy_dev
->link
== 0)
637 if (cpmac_drv_send((u32
*)packet
, length
, eth_priv
->slave_port
) != 0)
644 * This function handles receipt of a packet from the network
646 static int keystone2_eth_rcv_packet(struct eth_device
*dev
)
652 hd
= ksnav_recv(&netcp_pktdma
, &pkt
, &pkt_size
);
656 net_process_received_packet((uchar
*)pkt
, pkt_size
);
658 ksnav_release_rxhd(&netcp_pktdma
, hd
);
663 #ifdef CONFIG_MCAST_TFTP
664 static int keystone2_eth_bcast_addr(struct eth_device
*dev
, u32 ip
, u8 set
)
671 * This function initializes the EMAC hardware.
673 int keystone2_emac_initialize(struct eth_priv_t
*eth_priv
)
676 struct eth_device
*dev
;
677 struct phy_device
*phy_dev
;
678 struct mdio_regs
*adap_mdio
= (struct mdio_regs
*)EMAC_MDIO_BASE_ADDR
;
680 dev
= malloc(sizeof(struct eth_device
));
684 memset(dev
, 0, sizeof(struct eth_device
));
686 strcpy(dev
->name
, eth_priv
->int_name
);
687 dev
->priv
= eth_priv
;
689 keystone2_eth_read_mac_addr(dev
);
692 dev
->init
= keystone2_eth_open
;
693 dev
->halt
= keystone2_eth_close
;
694 dev
->send
= keystone2_eth_send_packet
;
695 dev
->recv
= keystone2_eth_rcv_packet
;
696 #ifdef CONFIG_MCAST_TFTP
697 dev
->mcast
= keystone2_eth_bcast_addr
;
702 /* Register MDIO bus if it's not registered yet */
704 mdio_bus
= mdio_alloc();
705 mdio_bus
->read
= keystone2_mdio_read
;
706 mdio_bus
->write
= keystone2_mdio_write
;
707 mdio_bus
->reset
= keystone2_mdio_reset
;
708 mdio_bus
->priv
= (void *)EMAC_MDIO_BASE_ADDR
;
709 strcpy(mdio_bus
->name
, "ethernet-mdio");
711 res
= mdio_register(mdio_bus
);
716 #ifndef CONFIG_SOC_K2G
717 keystone2_net_serdes_setup();
720 /* Create phy device and bind it with driver */
721 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
722 phy_dev
= phy_connect(mdio_bus
, eth_priv
->phy_addr
,
723 dev
, eth_priv
->phy_if
);
726 phy_dev
= phy_find_by_mask(mdio_bus
, 1 << eth_priv
->phy_addr
,
730 eth_priv
->phy_dev
= phy_dev
;
737 static int ks2_eth_start(struct udevice
*dev
)
739 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
741 #ifdef CONFIG_SOC_K2G
742 keystone_rgmii_config(priv
->phydev
);
744 keystone_sgmii_config(priv
->phydev
, priv
->slave_port
- 1,
745 priv
->sgmii_link_type
);
750 /* On chip switch configuration */
751 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE
);
755 if (ksnav_init(priv
->netcp_pktdma
, &priv
->net_rx_buffs
)) {
756 error("ksnav_init failed\n");
761 * Streaming switch configuration. If not present this
762 * statement is defined to void in target.h.
763 * If present this is usually defined to a series of register writes
765 hw_config_streaming_switch();
767 if (priv
->has_mdio
) {
768 phy_startup(priv
->phydev
);
769 if (priv
->phydev
->link
== 0) {
770 error("phy startup failed\n");
775 emac_gigabit_enable(dev
);
779 priv
->emac_open
= true;
784 ksnav_close(priv
->netcp_pktdma
);
791 static int ks2_eth_send(struct udevice
*dev
, void *packet
, int length
)
793 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
795 genphy_update_link(priv
->phydev
);
796 if (priv
->phydev
->link
== 0)
799 if (length
< EMAC_MIN_ETHERNET_PKT_SIZE
)
800 length
= EMAC_MIN_ETHERNET_PKT_SIZE
;
802 return ksnav_send(priv
->netcp_pktdma
, (u32
*)packet
,
803 length
, (priv
->slave_port
) << 16);
806 static int ks2_eth_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
808 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
812 priv
->hd
= ksnav_recv(priv
->netcp_pktdma
, &pkt
, &pkt_size
);
813 if (priv
->hd
== NULL
)
816 *packetp
= (uchar
*)pkt
;
821 static int ks2_eth_free_pkt(struct udevice
*dev
, uchar
*packet
,
824 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
826 ksnav_release_rxhd(priv
->netcp_pktdma
, priv
->hd
);
831 static void ks2_eth_stop(struct udevice
*dev
)
833 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
835 if (!priv
->emac_open
)
839 ksnav_close(priv
->netcp_pktdma
);
841 phy_shutdown(priv
->phydev
);
842 priv
->emac_open
= false;
845 int ks2_eth_read_rom_hwaddr(struct udevice
*dev
)
847 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
848 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
852 /* Read the e-fuse mac address */
853 if (priv
->slave_port
== 1) {
854 maca
= __raw_readl(MAC_ID_BASE_ADDR
);
855 macb
= __raw_readl(MAC_ID_BASE_ADDR
+ 4);
858 pdata
->enetaddr
[0] = (macb
>> 8) & 0xff;
859 pdata
->enetaddr
[1] = (macb
>> 0) & 0xff;
860 pdata
->enetaddr
[2] = (maca
>> 24) & 0xff;
861 pdata
->enetaddr
[3] = (maca
>> 16) & 0xff;
862 pdata
->enetaddr
[4] = (maca
>> 8) & 0xff;
863 pdata
->enetaddr
[5] = (maca
>> 0) & 0xff;
868 int ks2_eth_write_hwaddr(struct udevice
*dev
)
870 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
871 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
873 writel(mac_hi(pdata
->enetaddr
),
874 DEVICE_EMACSW_BASE(pdata
->iobase
, priv
->slave_port
- 1) +
876 writel(mac_lo(pdata
->enetaddr
),
877 DEVICE_EMACSW_BASE(pdata
->iobase
, priv
->slave_port
- 1) +
883 static int ks2_eth_probe(struct udevice
*dev
)
885 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
886 struct mii_dev
*mdio_bus
;
891 /* These clock enables has to be moved to common location */
893 writel(KS2_ETHERNET_RGMII
, KS2_ETHERNET_CFG
);
895 /* By default, select PA PLL clock as PA clock source */
896 #ifndef CONFIG_SOC_K2G
897 if (psc_enable_module(KS2_LPSC_PA
))
900 if (psc_enable_module(KS2_LPSC_CPGMAC
))
902 if (psc_enable_module(KS2_LPSC_CRYPTO
))
905 if (cpu_is_k2e() || cpu_is_k2l())
909 priv
->net_rx_buffs
.buff_ptr
= rx_buffs
,
910 priv
->net_rx_buffs
.num_buffs
= RX_BUFF_NUMS
,
911 priv
->net_rx_buffs
.buff_len
= RX_BUFF_LEN
,
913 /* Register MDIO bus */
914 mdio_bus
= mdio_alloc();
916 error("MDIO alloc failed\n");
919 priv
->mdio_bus
= mdio_bus
;
920 mdio_bus
->read
= keystone2_mdio_read
;
921 mdio_bus
->write
= keystone2_mdio_write
;
922 mdio_bus
->reset
= keystone2_mdio_reset
;
923 mdio_bus
->priv
= priv
->mdio_base
;
924 sprintf(mdio_bus
->name
, "ethernet-mdio");
926 ret
= mdio_register(mdio_bus
);
928 error("MDIO bus register failed\n");
932 #ifndef CONFIG_SOC_K2G
933 keystone2_net_serdes_setup();
936 priv
->netcp_pktdma
= &netcp_pktdma
;
938 priv
->phydev
= phy_connect(mdio_bus
, priv
->phy_addr
, dev
, priv
->phy_if
);
939 phy_config(priv
->phydev
);
944 int ks2_eth_remove(struct udevice
*dev
)
946 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
949 mdio_unregister(priv
->mdio_bus
);
950 mdio_free(priv
->mdio_bus
);
955 static const struct eth_ops ks2_eth_ops
= {
956 .start
= ks2_eth_start
,
957 .send
= ks2_eth_send
,
958 .recv
= ks2_eth_recv
,
959 .free_pkt
= ks2_eth_free_pkt
,
960 .stop
= ks2_eth_stop
,
961 .read_rom_hwaddr
= ks2_eth_read_rom_hwaddr
,
962 .write_hwaddr
= ks2_eth_write_hwaddr
,
966 static int ks2_eth_ofdata_to_platdata(struct udevice
*dev
)
968 struct ks2_eth_priv
*priv
= dev_get_priv(dev
);
969 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
970 const void *fdt
= gd
->fdt_blob
;
978 interfaces
= fdt_subnode_offset(fdt
, dev
->of_offset
,
980 interface_0
= fdt_subnode_offset(fdt
, interfaces
, "interface-0");
982 netcp_gbe_0
= fdtdec_lookup_phandle(fdt
, interface_0
, "netcp-gbe");
983 priv
->link_type
= fdtdec_get_int(fdt
, netcp_gbe_0
,
984 "link-interface", -1);
985 priv
->slave_port
= fdtdec_get_int(fdt
, netcp_gbe_0
, "slave-port", -1);
986 /* U-Boot slave port number starts with 1 instead of 0 */
987 priv
->slave_port
+= 1;
989 phy
= fdtdec_lookup_phandle(fdt
, netcp_gbe_0
, "phy-handle");
990 priv
->phy_addr
= fdtdec_get_int(fdt
, phy
, "reg", -1);
992 mdio
= fdt_parent_offset(fdt
, phy
);
994 error("mdio dt not found\n");
997 priv
->mdio_base
= (void *)fdtdec_get_addr(fdt
, mdio
, "reg");
999 if (priv
->link_type
== LINK_TYPE_MAC_TO_PHY_MODE
) {
1000 priv
->phy_if
= PHY_INTERFACE_MODE_SGMII
;
1001 pdata
->phy_interface
= priv
->phy_if
;
1002 priv
->sgmii_link_type
= SGMII_LINK_MAC_PHY
;
1003 priv
->has_mdio
= true;
1005 pdata
->iobase
= dev_get_addr(dev
);
1007 fdtdec_get_int_array(fdt
, dev
->of_offset
, "ti,navigator-dmas",
1009 priv
->net_rx_buffs
.rx_flow
= dma_channel
[1];
1014 static const struct udevice_id ks2_eth_ids
[] = {
1015 { .compatible
= "ti,netcp-1.0" },
1020 U_BOOT_DRIVER(eth_ks2
) = {
1023 .of_match
= ks2_eth_ids
,
1024 .ofdata_to_platdata
= ks2_eth_ofdata_to_platdata
,
1025 .probe
= ks2_eth_probe
,
1026 .remove
= ks2_eth_remove
,
1027 .ops
= &ks2_eth_ops
,
1028 .priv_auto_alloc_size
= sizeof(struct ks2_eth_priv
),
1029 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
1030 .flags
= DM_FLAG_ALLOC_PRIV_DMA
,