2 * Ethernet driver for TI K2HK EVM.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/emac_defs.h>
16 #include <asm/arch/psc_defs.h>
17 #include <asm/arch/keystone_nav.h>
19 unsigned int emac_dbg
;
21 unsigned int emac_open
;
22 static unsigned int sys_has_mdio
= 1;
24 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
25 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
27 #define emac_gigabit_enable(x) /* no gigabit to enable */
30 #define RX_BUFF_NUMS 24
31 #define RX_BUFF_LEN 1520
32 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
34 static u8 rx_buffs
[RX_BUFF_NUMS
* RX_BUFF_LEN
] __aligned(16);
36 struct rx_buff_desc net_rx_buffs
= {
38 .num_buffs
= RX_BUFF_NUMS
,
39 .buff_len
= RX_BUFF_LEN
,
43 static void keystone2_eth_mdio_enable(void);
45 static int gen_get_link_speed(int phy_addr
);
48 static volatile struct emac_regs
*adap_emac
=
49 (struct emac_regs
*)EMAC_EMACSL_BASE_ADDR
;
50 static volatile struct mdio_regs
*adap_mdio
=
51 (struct mdio_regs
*)EMAC_MDIO_BASE_ADDR
;
53 int keystone2_eth_read_mac_addr(struct eth_device
*dev
)
55 struct eth_priv_t
*eth_priv
;
59 eth_priv
= (struct eth_priv_t
*)dev
->priv
;
61 /* Read the e-fuse mac address */
62 if (eth_priv
->slave_port
== 1) {
63 maca
= __raw_readl(MAC_ID_BASE_ADDR
);
64 macb
= __raw_readl(MAC_ID_BASE_ADDR
+ 4);
67 dev
->enetaddr
[0] = (macb
>> 8) & 0xff;
68 dev
->enetaddr
[1] = (macb
>> 0) & 0xff;
69 dev
->enetaddr
[2] = (maca
>> 24) & 0xff;
70 dev
->enetaddr
[3] = (maca
>> 16) & 0xff;
71 dev
->enetaddr
[4] = (maca
>> 8) & 0xff;
72 dev
->enetaddr
[5] = (maca
>> 0) & 0xff;
77 static void keystone2_eth_mdio_enable(void)
81 clkdiv
= (EMAC_MDIO_BUS_FREQ
/ EMAC_MDIO_CLOCK_FREQ
) - 1;
83 writel((clkdiv
& 0xffff) |
86 MDIO_CONTROL_FAULT_ENABLE
,
89 while (readl(&adap_mdio
->control
) & MDIO_CONTROL_IDLE
)
93 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
94 int keystone2_eth_phy_read(u_int8_t phy_addr
, u_int8_t reg_num
, u_int16_t
*data
)
98 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
101 writel(MDIO_USERACCESS0_GO
|
102 MDIO_USERACCESS0_WRITE_READ
|
103 ((reg_num
& 0x1f) << 21) |
104 ((phy_addr
& 0x1f) << 16),
105 &adap_mdio
->useraccess0
);
107 /* Wait for command to complete */
108 while ((tmp
= readl(&adap_mdio
->useraccess0
)) & MDIO_USERACCESS0_GO
)
111 if (tmp
& MDIO_USERACCESS0_ACK
) {
112 *data
= tmp
& 0xffff;
121 * Write to a PHY register via MDIO inteface.
122 * Blocks until operation is complete.
124 int keystone2_eth_phy_write(u_int8_t phy_addr
, u_int8_t reg_num
, u_int16_t data
)
126 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
129 writel(MDIO_USERACCESS0_GO
|
130 MDIO_USERACCESS0_WRITE_WRITE
|
131 ((reg_num
& 0x1f) << 21) |
132 ((phy_addr
& 0x1f) << 16) |
134 &adap_mdio
->useraccess0
);
136 /* Wait for command to complete */
137 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
143 /* PHY functions for a generic PHY */
144 static int gen_get_link_speed(int phy_addr
)
148 if ((!keystone2_eth_phy_read(phy_addr
, MII_STATUS_REG
, &tmp
)) &&
156 static void __attribute__((unused
))
157 keystone2_eth_gigabit_enable(struct eth_device
*dev
)
160 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
163 if (keystone2_eth_phy_read(eth_priv
->phy_addr
, 0, &data
) ||
164 !(data
& (1 << 6))) /* speed selection MSB */
169 * Check if link detected is giga-bit
170 * If Gigabit mode detected, enable gigbit in MAC
172 writel(readl(&(adap_emac
[eth_priv
->slave_port
- 1].maccontrol
)) |
173 EMAC_MACCONTROL_GIGFORCE
| EMAC_MACCONTROL_GIGABIT_ENABLE
,
174 &(adap_emac
[eth_priv
->slave_port
- 1].maccontrol
))
178 int keystone_sgmii_link_status(int port
)
182 status
= __raw_readl(SGMII_STATUS_REG(port
));
184 return status
& SGMII_REG_STATUS_LINK
;
188 int keystone_get_link_status(struct eth_device
*dev
)
190 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
193 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
196 for (j
= 0; (j
< CONFIG_GET_LINK_STATUS_ATTEMPTS
) && (link_state
== 0);
200 keystone_sgmii_link_status(eth_priv
->slave_port
- 1);
205 if (eth_priv
->sgmii_link_type
== SGMII_LINK_MAC_PHY
)
206 if (gen_get_link_speed(eth_priv
->phy_addr
))
209 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
215 int keystone_sgmii_config(int port
, int interface
)
217 unsigned int i
, status
, mask
;
218 unsigned int mr_adv_ability
, control
;
221 case SGMII_LINK_MAC_MAC_AUTONEG
:
222 mr_adv_ability
= (SGMII_REG_MR_ADV_ENABLE
|
223 SGMII_REG_MR_ADV_LINK
|
224 SGMII_REG_MR_ADV_FULL_DUPLEX
|
225 SGMII_REG_MR_ADV_GIG_MODE
);
226 control
= (SGMII_REG_CONTROL_MASTER
|
227 SGMII_REG_CONTROL_AUTONEG
);
230 case SGMII_LINK_MAC_PHY
:
231 case SGMII_LINK_MAC_PHY_FORCED
:
232 mr_adv_ability
= SGMII_REG_MR_ADV_ENABLE
;
233 control
= SGMII_REG_CONTROL_AUTONEG
;
236 case SGMII_LINK_MAC_MAC_FORCED
:
237 mr_adv_ability
= (SGMII_REG_MR_ADV_ENABLE
|
238 SGMII_REG_MR_ADV_LINK
|
239 SGMII_REG_MR_ADV_FULL_DUPLEX
|
240 SGMII_REG_MR_ADV_GIG_MODE
);
241 control
= SGMII_REG_CONTROL_MASTER
;
244 case SGMII_LINK_MAC_FIBER
:
245 mr_adv_ability
= 0x20;
246 control
= SGMII_REG_CONTROL_AUTONEG
;
250 mr_adv_ability
= SGMII_REG_MR_ADV_ENABLE
;
251 control
= SGMII_REG_CONTROL_AUTONEG
;
254 __raw_writel(0, SGMII_CTL_REG(port
));
257 * Wait for the SerDes pll to lock,
258 * but don't trap if lock is never read
260 for (i
= 0; i
< 1000; i
++) {
262 status
= __raw_readl(SGMII_STATUS_REG(port
));
263 if ((status
& SGMII_REG_STATUS_LOCK
) != 0)
267 __raw_writel(mr_adv_ability
, SGMII_MRADV_REG(port
));
268 __raw_writel(control
, SGMII_CTL_REG(port
));
271 mask
= SGMII_REG_STATUS_LINK
;
273 if (control
& SGMII_REG_CONTROL_AUTONEG
)
274 mask
|= SGMII_REG_STATUS_AUTONEG
;
276 for (i
= 0; i
< 1000; i
++) {
277 status
= __raw_readl(SGMII_STATUS_REG(port
));
278 if ((status
& mask
) == mask
)
285 int mac_sl_reset(u32 port
)
289 if (port
>= DEVICE_N_GMACSL_PORTS
)
290 return GMACSL_RET_INVALID_PORT
;
292 /* Set the soft reset bit */
293 writel(CPGMAC_REG_RESET_VAL_RESET
,
294 DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
296 /* Wait for the bit to clear */
297 for (i
= 0; i
< DEVICE_EMACSL_RESET_POLL_COUNT
; i
++) {
298 v
= readl(DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
299 if ((v
& CPGMAC_REG_RESET_VAL_RESET_MASK
) !=
300 CPGMAC_REG_RESET_VAL_RESET
)
301 return GMACSL_RET_OK
;
304 /* Timeout on the reset */
305 return GMACSL_RET_WARN_RESET_INCOMPLETE
;
308 int mac_sl_config(u_int16_t port
, struct mac_sl_cfg
*cfg
)
311 int ret
= GMACSL_RET_OK
;
313 if (port
>= DEVICE_N_GMACSL_PORTS
)
314 return GMACSL_RET_INVALID_PORT
;
316 if (cfg
->max_rx_len
> CPGMAC_REG_MAXLEN_LEN
) {
317 cfg
->max_rx_len
= CPGMAC_REG_MAXLEN_LEN
;
318 ret
= GMACSL_RET_WARN_MAXLEN_TOO_BIG
;
321 /* Must wait if the device is undergoing reset */
322 for (i
= 0; i
< DEVICE_EMACSL_RESET_POLL_COUNT
; i
++) {
323 v
= readl(DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
324 if ((v
& CPGMAC_REG_RESET_VAL_RESET_MASK
) !=
325 CPGMAC_REG_RESET_VAL_RESET
)
329 if (i
== DEVICE_EMACSL_RESET_POLL_COUNT
)
330 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE
;
332 writel(cfg
->max_rx_len
, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_MAXLEN
);
333 writel(cfg
->ctl
, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_CTL
);
338 int ethss_config(u32 ctl
, u32 max_pkt_size
)
342 /* Max length register */
343 writel(max_pkt_size
, DEVICE_CPSW_BASE
+ CPSW_REG_MAXLEN
);
345 /* Control register */
346 writel(ctl
, DEVICE_CPSW_BASE
+ CPSW_REG_CTL
);
348 /* All statistics enabled by default */
349 writel(CPSW_REG_VAL_STAT_ENABLE_ALL
,
350 DEVICE_CPSW_BASE
+ CPSW_REG_STAT_PORT_EN
);
352 /* Reset and enable the ALE */
353 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE
|
354 CPSW_REG_VAL_ALE_CTL_BYPASS
,
355 DEVICE_CPSW_BASE
+ CPSW_REG_ALE_CONTROL
);
357 /* All ports put into forward mode */
358 for (i
= 0; i
< DEVICE_CPSW_NUM_PORTS
; i
++)
359 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE
,
360 DEVICE_CPSW_BASE
+ CPSW_REG_ALE_PORTCTL(i
));
365 int ethss_start(void)
368 struct mac_sl_cfg cfg
;
370 cfg
.max_rx_len
= MAX_SIZE_STREAM_BUFFER
;
371 cfg
.ctl
= GMACSL_ENABLE
| GMACSL_RX_ENABLE_EXT_CTL
;
373 for (i
= 0; i
< DEVICE_N_GMACSL_PORTS
; i
++) {
375 mac_sl_config(i
, &cfg
);
385 for (i
= 0; i
< DEVICE_N_GMACSL_PORTS
; i
++)
391 int32_t cpmac_drv_send(u32
*buffer
, int num_bytes
, int slave_port_num
)
393 if (num_bytes
< EMAC_MIN_ETHERNET_PKT_SIZE
)
394 num_bytes
= EMAC_MIN_ETHERNET_PKT_SIZE
;
396 return netcp_send(buffer
, num_bytes
, (slave_port_num
) << 16);
399 /* Eth device open */
400 static int keystone2_eth_open(struct eth_device
*dev
, bd_t
*bis
)
404 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
406 debug("+ emac_open\n");
408 net_rx_buffs
.rx_flow
= eth_priv
->rx_flow
;
411 (eth_priv
->sgmii_link_type
== SGMII_LINK_MAC_PHY
) ? 1 : 0;
413 psc_enable_module(KS2_LPSC_PA
);
414 psc_enable_module(KS2_LPSC_CPGMAC
);
416 sgmii_serdes_setup_156p25mhz();
419 keystone2_eth_mdio_enable();
421 keystone_sgmii_config(eth_priv
->slave_port
- 1,
422 eth_priv
->sgmii_link_type
);
426 /* On chip switch configuration */
427 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE
);
429 /* TODO: add error handling code */
431 printf("ERROR: qm_init()\n");
434 if (netcp_init(&net_rx_buffs
)) {
436 printf("ERROR: netcp_init()\n");
441 * Streaming switch configuration. If not present this
442 * statement is defined to void in target.h.
443 * If present this is usually defined to a series of register writes
445 hw_config_streaming_switch();
448 /* Init MDIO & get link state */
449 clkdiv
= (EMAC_MDIO_BUS_FREQ
/ EMAC_MDIO_CLOCK_FREQ
) - 1;
450 writel((clkdiv
& 0xff) | MDIO_CONTROL_ENABLE
|
451 MDIO_CONTROL_FAULT
, &adap_mdio
->control
)
454 /* We need to wait for MDIO to start */
457 link
= keystone_get_link_status(dev
);
465 emac_gigabit_enable(dev
);
469 debug("- emac_open\n");
476 /* Eth device close */
477 void keystone2_eth_close(struct eth_device
*dev
)
479 debug("+ emac_close\n");
491 debug("- emac_close\n");
494 static int tx_send_loop
;
497 * This function sends a single packet on the network and returns
498 * positive number (number of bytes transmitted) or negative for error
500 static int keystone2_eth_send_packet(struct eth_device
*dev
,
501 void *packet
, int length
)
504 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
508 if (keystone_get_link_status(dev
) == 0)
511 emac_gigabit_enable(dev
);
513 if (cpmac_drv_send((u32
*)packet
, length
, eth_priv
->slave_port
) != 0)
516 if (keystone_get_link_status(dev
) == 0)
519 emac_gigabit_enable(dev
);
525 * This function handles receipt of a packet from the network
527 static int keystone2_eth_rcv_packet(struct eth_device
*dev
)
533 hd
= netcp_recv(&pkt
, &pkt_size
);
537 NetReceive((uchar
*)pkt
, pkt_size
);
539 netcp_release_rxhd(hd
);
545 * This function initializes the EMAC hardware.
547 int keystone2_emac_initialize(struct eth_priv_t
*eth_priv
)
549 struct eth_device
*dev
;
551 dev
= malloc(sizeof(struct eth_device
));
555 memset(dev
, 0, sizeof(struct eth_device
));
557 strcpy(dev
->name
, eth_priv
->int_name
);
558 dev
->priv
= eth_priv
;
560 keystone2_eth_read_mac_addr(dev
);
563 dev
->init
= keystone2_eth_open
;
564 dev
->halt
= keystone2_eth_close
;
565 dev
->send
= keystone2_eth_send_packet
;
566 dev
->recv
= keystone2_eth_rcv_packet
;
573 void sgmii_serdes_setup_156p25mhz(void)
578 * configure Serializer/Deserializer (SerDes) hardware. SerDes IP
579 * hardware vendor published only register addresses and their values
580 * to be used for configuring SerDes. So had to use hardcoded values
583 clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000);
584 clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282);
585 clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438);
586 clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700);
587 clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000);
589 clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080);
590 clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000);
591 clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000);
592 clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000);
593 clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8);
594 clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4);
595 clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400);
596 clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800);
597 clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082);
598 clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385);
600 clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080);
601 clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000);
602 clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000);
603 clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000);
604 clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8);
605 clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4);
606 clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400);
607 clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800);
608 clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082);
609 clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385);
611 clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080);
612 clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000);
613 clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000);
614 clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000);
615 clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8);
616 clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4);
617 clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400);
618 clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800);
619 clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082);
620 clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385);
622 clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080);
623 clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000);
624 clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000);
625 clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000);
626 clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8);
627 clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4);
628 clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400);
629 clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800);
630 clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082);
631 clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385);
633 clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800);
634 clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000);
635 clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00);
636 clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600);
637 clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000);
638 clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000);
639 clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000);
640 clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b);
641 clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000);
642 clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e);
643 clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003);
644 clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f);
646 clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00);
647 clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72);
648 clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100);
649 clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060);
650 clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000);
651 clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220);
652 clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602);
653 clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1);
654 clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989);
655 clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001);
656 clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000);
657 clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000);
658 clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d);
660 /*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/
661 clrbits_le32(0x0232a010, 1 << 28);
663 /* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */
664 clrbits_le32(0x0232a228, 1 << 29);
665 writel(0xF800F8C0, 0x0232bfe0);
666 clrbits_le32(0x0232a428, 1 << 29);
667 writel(0xF800F8C0, 0x0232bfe4);
668 clrbits_le32(0x0232a628, 1 << 29);
669 writel(0xF800F8C0, 0x0232bfe8);
670 clrbits_le32(0x0232a828, 1 << 29);
671 writel(0xF800F8C0, 0x0232bfec);
673 /*Enable pll via the pll_ctrl 0x0014*/
674 writel(0xe0000000, 0x0232bff4)
677 /*Waiting for SGMII Serdes PLL lock.*/
678 for (cnt
= 10000; cnt
> 0 && ((readl(0x02090114) & 0x10) == 0); cnt
--)
681 for (cnt
= 10000; cnt
> 0 && ((readl(0x02090214) & 0x10) == 0); cnt
--)
684 for (cnt
= 10000; cnt
> 0 && ((readl(0x02090414) & 0x10) == 0); cnt
--)
687 for (cnt
= 10000; cnt
> 0 && ((readl(0x02090514) & 0x10) == 0); cnt
--)
693 void sgmii_serdes_shutdown(void)
696 * shutdown SerDes hardware. SerDes hardware vendor published only
697 * register addresses and their values. So had to use hardcoded
700 clrbits_le32(0x0232bfe0, 3 << 29 | 3 << 13);
701 setbits_le32(0x02320228, 1 << 29);
702 clrbits_le32(0x0232bfe4, 3 << 29 | 3 << 13);
703 setbits_le32(0x02320428, 1 << 29);
704 clrbits_le32(0x0232bfe8, 3 << 29 | 3 << 13);
705 setbits_le32(0x02320628, 1 << 29);
706 clrbits_le32(0x0232bfec, 3 << 29 | 3 << 13);
707 setbits_le32(0x02320828, 1 << 29);
709 clrbits_le32(0x02320034, 3 << 29);
710 setbits_le32(0x02320010, 1 << 28);