2 * Copyright (C) 2005-2006 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
11 * The u-boot networking stack is a little weird. It seems like the
12 * networking core allocates receive buffers up front without any
13 * regard to the hardware that's supposed to actually receive those
16 * The MACB receives packets into 128-byte receive buffers, so the
17 * buffers allocated by the core isn't very practical to use. We'll
18 * allocate our own, but we need one such buffer in case a packet
19 * wraps around the DMA ring so that we have to copy it.
21 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
22 * configuration header. This way, the core allocates one RX buffer
23 * and one TX buffer, each of which can hold a ethernet packet of
26 * For some reason, the networking core unconditionally specifies a
27 * 32-byte packet "alignment" (which really should be called
28 * "padding"). MACB shouldn't need that, but we'll refrain from any
29 * core modifications here...
39 #include <linux/mii.h>
41 #include <asm/dma-mapping.h>
42 #include <asm/arch/clk.h>
43 #include <linux/errno.h>
47 DECLARE_GLOBAL_DATA_PTR
;
49 #define MACB_RX_BUFFER_SIZE 4096
50 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
51 #define MACB_TX_RING_SIZE 16
52 #define MACB_TX_TIMEOUT 1000
53 #define MACB_AUTONEG_TIMEOUT 5000000
55 struct macb_dma_desc
{
60 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
61 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
62 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
63 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
65 #define RXADDR_USED 0x00000001
66 #define RXADDR_WRAP 0x00000002
68 #define RXBUF_FRMLEN_MASK 0x00000fff
69 #define RXBUF_FRAME_START 0x00004000
70 #define RXBUF_FRAME_END 0x00008000
71 #define RXBUF_TYPEID_MATCH 0x00400000
72 #define RXBUF_ADDR4_MATCH 0x00800000
73 #define RXBUF_ADDR3_MATCH 0x01000000
74 #define RXBUF_ADDR2_MATCH 0x02000000
75 #define RXBUF_ADDR1_MATCH 0x04000000
76 #define RXBUF_BROADCAST 0x80000000
78 #define TXBUF_FRMLEN_MASK 0x000007ff
79 #define TXBUF_FRAME_END 0x00008000
80 #define TXBUF_NOCRC 0x00010000
81 #define TXBUF_EXHAUSTED 0x08000000
82 #define TXBUF_UNDERRUN 0x10000000
83 #define TXBUF_MAXRETRY 0x20000000
84 #define TXBUF_WRAP 0x40000000
85 #define TXBUF_USED 0x80000000
93 unsigned int next_rx_tail
;
98 struct macb_dma_desc
*rx_ring
;
99 struct macb_dma_desc
*tx_ring
;
101 unsigned long rx_buffer_dma
;
102 unsigned long rx_ring_dma
;
103 unsigned long tx_ring_dma
;
105 struct macb_dma_desc
*dummy_desc
;
106 unsigned long dummy_desc_dma
;
108 const struct device
*dev
;
109 #ifndef CONFIG_DM_ETH
110 struct eth_device netdev
;
112 unsigned short phy_addr
;
115 struct phy_device
*phydev
;
120 unsigned long pclk_rate
;
122 phy_interface_t phy_interface
;
125 #ifndef CONFIG_DM_ETH
126 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
129 static int macb_is_gem(struct macb_device
*macb
)
131 return MACB_BFEXT(IDNUM
, macb_readl(macb
, MID
)) == 0x2;
134 #ifndef cpu_is_sama5d2
135 #define cpu_is_sama5d2() 0
138 #ifndef cpu_is_sama5d4
139 #define cpu_is_sama5d4() 0
142 static int gem_is_gigabit_capable(struct macb_device
*macb
)
145 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
146 * configured to support only 10/100.
148 return macb_is_gem(macb
) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
151 static void macb_mdio_write(struct macb_device
*macb
, u8 reg
, u16 value
)
153 unsigned long netctl
;
154 unsigned long netstat
;
157 netctl
= macb_readl(macb
, NCR
);
158 netctl
|= MACB_BIT(MPE
);
159 macb_writel(macb
, NCR
, netctl
);
161 frame
= (MACB_BF(SOF
, 1)
163 | MACB_BF(PHYA
, macb
->phy_addr
)
166 | MACB_BF(DATA
, value
));
167 macb_writel(macb
, MAN
, frame
);
170 netstat
= macb_readl(macb
, NSR
);
171 } while (!(netstat
& MACB_BIT(IDLE
)));
173 netctl
= macb_readl(macb
, NCR
);
174 netctl
&= ~MACB_BIT(MPE
);
175 macb_writel(macb
, NCR
, netctl
);
178 static u16
macb_mdio_read(struct macb_device
*macb
, u8 reg
)
180 unsigned long netctl
;
181 unsigned long netstat
;
184 netctl
= macb_readl(macb
, NCR
);
185 netctl
|= MACB_BIT(MPE
);
186 macb_writel(macb
, NCR
, netctl
);
188 frame
= (MACB_BF(SOF
, 1)
190 | MACB_BF(PHYA
, macb
->phy_addr
)
193 macb_writel(macb
, MAN
, frame
);
196 netstat
= macb_readl(macb
, NSR
);
197 } while (!(netstat
& MACB_BIT(IDLE
)));
199 frame
= macb_readl(macb
, MAN
);
201 netctl
= macb_readl(macb
, NCR
);
202 netctl
&= ~MACB_BIT(MPE
);
203 macb_writel(macb
, NCR
, netctl
);
205 return MACB_BFEXT(DATA
, frame
);
208 void __weak
arch_get_mdio_control(const char *name
)
213 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
215 int macb_miiphy_read(struct mii_dev
*bus
, int phy_adr
, int devad
, int reg
)
219 struct udevice
*dev
= eth_get_dev_by_name(bus
->name
);
220 struct macb_device
*macb
= dev_get_priv(dev
);
222 struct eth_device
*dev
= eth_get_dev_by_name(bus
->name
);
223 struct macb_device
*macb
= to_macb(dev
);
226 if (macb
->phy_addr
!= phy_adr
)
229 arch_get_mdio_control(bus
->name
);
230 value
= macb_mdio_read(macb
, reg
);
235 int macb_miiphy_write(struct mii_dev
*bus
, int phy_adr
, int devad
, int reg
,
239 struct udevice
*dev
= eth_get_dev_by_name(bus
->name
);
240 struct macb_device
*macb
= dev_get_priv(dev
);
242 struct eth_device
*dev
= eth_get_dev_by_name(bus
->name
);
243 struct macb_device
*macb
= to_macb(dev
);
246 if (macb
->phy_addr
!= phy_adr
)
249 arch_get_mdio_control(bus
->name
);
250 macb_mdio_write(macb
, reg
, value
);
258 static inline void macb_invalidate_ring_desc(struct macb_device
*macb
, bool rx
)
261 invalidate_dcache_range(macb
->rx_ring_dma
,
262 ALIGN(macb
->rx_ring_dma
+ MACB_RX_DMA_DESC_SIZE
,
265 invalidate_dcache_range(macb
->tx_ring_dma
,
266 ALIGN(macb
->tx_ring_dma
+ MACB_TX_DMA_DESC_SIZE
,
270 static inline void macb_flush_ring_desc(struct macb_device
*macb
, bool rx
)
273 flush_dcache_range(macb
->rx_ring_dma
, macb
->rx_ring_dma
+
274 ALIGN(MACB_RX_DMA_DESC_SIZE
, PKTALIGN
));
276 flush_dcache_range(macb
->tx_ring_dma
, macb
->tx_ring_dma
+
277 ALIGN(MACB_TX_DMA_DESC_SIZE
, PKTALIGN
));
280 static inline void macb_flush_rx_buffer(struct macb_device
*macb
)
282 flush_dcache_range(macb
->rx_buffer_dma
, macb
->rx_buffer_dma
+
283 ALIGN(MACB_RX_BUFFER_SIZE
, PKTALIGN
));
286 static inline void macb_invalidate_rx_buffer(struct macb_device
*macb
)
288 invalidate_dcache_range(macb
->rx_buffer_dma
, macb
->rx_buffer_dma
+
289 ALIGN(MACB_RX_BUFFER_SIZE
, PKTALIGN
));
292 #if defined(CONFIG_CMD_NET)
294 static int _macb_send(struct macb_device
*macb
, const char *name
, void *packet
,
297 unsigned long paddr
, ctrl
;
298 unsigned int tx_head
= macb
->tx_head
;
301 paddr
= dma_map_single(packet
, length
, DMA_TO_DEVICE
);
303 ctrl
= length
& TXBUF_FRMLEN_MASK
;
304 ctrl
|= TXBUF_FRAME_END
;
305 if (tx_head
== (MACB_TX_RING_SIZE
- 1)) {
312 macb
->tx_ring
[tx_head
].ctrl
= ctrl
;
313 macb
->tx_ring
[tx_head
].addr
= paddr
;
315 macb_flush_ring_desc(macb
, TX
);
316 /* Do we need check paddr and length is dcache line aligned? */
317 flush_dcache_range(paddr
, paddr
+ ALIGN(length
, ARCH_DMA_MINALIGN
));
318 macb_writel(macb
, NCR
, MACB_BIT(TE
) | MACB_BIT(RE
) | MACB_BIT(TSTART
));
321 * I guess this is necessary because the networking core may
322 * re-use the transmit buffer as soon as we return...
324 for (i
= 0; i
<= MACB_TX_TIMEOUT
; i
++) {
326 macb_invalidate_ring_desc(macb
, TX
);
327 ctrl
= macb
->tx_ring
[tx_head
].ctrl
;
328 if (ctrl
& TXBUF_USED
)
333 dma_unmap_single(packet
, length
, paddr
);
335 if (i
<= MACB_TX_TIMEOUT
) {
336 if (ctrl
& TXBUF_UNDERRUN
)
337 printf("%s: TX underrun\n", name
);
338 if (ctrl
& TXBUF_EXHAUSTED
)
339 printf("%s: TX buffers exhausted in mid frame\n", name
);
341 printf("%s: TX timeout\n", name
);
344 /* No one cares anyway */
348 static void reclaim_rx_buffers(struct macb_device
*macb
,
349 unsigned int new_tail
)
355 macb_invalidate_ring_desc(macb
, RX
);
356 while (i
> new_tail
) {
357 macb
->rx_ring
[i
].addr
&= ~RXADDR_USED
;
359 if (i
> MACB_RX_RING_SIZE
)
363 while (i
< new_tail
) {
364 macb
->rx_ring
[i
].addr
&= ~RXADDR_USED
;
369 macb_flush_ring_desc(macb
, RX
);
370 macb
->rx_tail
= new_tail
;
373 static int _macb_recv(struct macb_device
*macb
, uchar
**packetp
)
375 unsigned int next_rx_tail
= macb
->next_rx_tail
;
380 macb
->wrapped
= false;
382 macb_invalidate_ring_desc(macb
, RX
);
384 if (!(macb
->rx_ring
[next_rx_tail
].addr
& RXADDR_USED
))
387 status
= macb
->rx_ring
[next_rx_tail
].ctrl
;
388 if (status
& RXBUF_FRAME_START
) {
389 if (next_rx_tail
!= macb
->rx_tail
)
390 reclaim_rx_buffers(macb
, next_rx_tail
);
391 macb
->wrapped
= false;
394 if (status
& RXBUF_FRAME_END
) {
395 buffer
= macb
->rx_buffer
+ 128 * macb
->rx_tail
;
396 length
= status
& RXBUF_FRMLEN_MASK
;
398 macb_invalidate_rx_buffer(macb
);
400 unsigned int headlen
, taillen
;
402 headlen
= 128 * (MACB_RX_RING_SIZE
404 taillen
= length
- headlen
;
405 memcpy((void *)net_rx_packets
[0],
407 memcpy((void *)net_rx_packets
[0] + headlen
,
408 macb
->rx_buffer
, taillen
);
409 *packetp
= (void *)net_rx_packets
[0];
414 if (++next_rx_tail
>= MACB_RX_RING_SIZE
)
416 macb
->next_rx_tail
= next_rx_tail
;
419 if (++next_rx_tail
>= MACB_RX_RING_SIZE
) {
420 macb
->wrapped
= true;
428 static void macb_phy_reset(struct macb_device
*macb
, const char *name
)
433 adv
= ADVERTISE_CSMA
| ADVERTISE_ALL
;
434 macb_mdio_write(macb
, MII_ADVERTISE
, adv
);
435 printf("%s: Starting autonegotiation...\n", name
);
436 macb_mdio_write(macb
, MII_BMCR
, (BMCR_ANENABLE
439 for (i
= 0; i
< MACB_AUTONEG_TIMEOUT
/ 100; i
++) {
440 status
= macb_mdio_read(macb
, MII_BMSR
);
441 if (status
& BMSR_ANEGCOMPLETE
)
446 if (status
& BMSR_ANEGCOMPLETE
)
447 printf("%s: Autonegotiation complete\n", name
);
449 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
453 static int macb_phy_find(struct macb_device
*macb
, const char *name
)
458 /* Search for PHY... */
459 for (i
= 0; i
< 32; i
++) {
461 phy_id
= macb_mdio_read(macb
, MII_PHYSID1
);
462 if (phy_id
!= 0xffff) {
463 printf("%s: PHY present at %d\n", name
, i
);
468 /* PHY isn't up to snuff */
469 printf("%s: PHY not found\n", name
);
475 static int macb_phy_init(struct udevice
*dev
, const char *name
)
477 static int macb_phy_init(struct macb_device
*macb
, const char *name
)
481 struct macb_device
*macb
= dev_get_priv(dev
);
484 u16 phy_id
, status
, adv
, lpa
;
485 int media
, speed
, duplex
;
488 arch_get_mdio_control(name
);
489 /* Auto-detect phy_addr */
490 if (!macb_phy_find(macb
, name
))
493 /* Check if the PHY is up to snuff... */
494 phy_id
= macb_mdio_read(macb
, MII_PHYSID1
);
495 if (phy_id
== 0xffff) {
496 printf("%s: No PHY present\n", name
);
502 macb
->phydev
= phy_connect(macb
->bus
, macb
->phy_addr
, dev
,
503 macb
->phy_interface
);
505 /* need to consider other phy interface mode */
506 macb
->phydev
= phy_connect(macb
->bus
, macb
->phy_addr
, &macb
->netdev
,
507 PHY_INTERFACE_MODE_RGMII
);
510 printf("phy_connect failed\n");
514 phy_config(macb
->phydev
);
517 status
= macb_mdio_read(macb
, MII_BMSR
);
518 if (!(status
& BMSR_LSTATUS
)) {
519 /* Try to re-negotiate if we don't have link already. */
520 macb_phy_reset(macb
, name
);
522 for (i
= 0; i
< MACB_AUTONEG_TIMEOUT
/ 100; i
++) {
523 status
= macb_mdio_read(macb
, MII_BMSR
);
524 if (status
& BMSR_LSTATUS
)
530 if (!(status
& BMSR_LSTATUS
)) {
531 printf("%s: link down (status: 0x%04x)\n",
536 /* First check for GMAC and that it is GiB capable */
537 if (gem_is_gigabit_capable(macb
)) {
538 lpa
= macb_mdio_read(macb
, MII_STAT1000
);
540 if (lpa
& (LPA_1000FULL
| LPA_1000HALF
)) {
541 duplex
= ((lpa
& LPA_1000FULL
) ? 1 : 0);
543 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
545 duplex
? "full" : "half",
548 ncfgr
= macb_readl(macb
, NCFGR
);
549 ncfgr
&= ~(MACB_BIT(SPD
) | MACB_BIT(FD
));
550 ncfgr
|= GEM_BIT(GBE
);
553 ncfgr
|= MACB_BIT(FD
);
555 macb_writel(macb
, NCFGR
, ncfgr
);
561 /* fall back for EMAC checking */
562 adv
= macb_mdio_read(macb
, MII_ADVERTISE
);
563 lpa
= macb_mdio_read(macb
, MII_LPA
);
564 media
= mii_nway_result(lpa
& adv
);
565 speed
= (media
& (ADVERTISE_100FULL
| ADVERTISE_100HALF
)
567 duplex
= (media
& ADVERTISE_FULL
) ? 1 : 0;
568 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
570 speed
? "100" : "10",
571 duplex
? "full" : "half",
574 ncfgr
= macb_readl(macb
, NCFGR
);
575 ncfgr
&= ~(MACB_BIT(SPD
) | MACB_BIT(FD
) | GEM_BIT(GBE
));
577 ncfgr
|= MACB_BIT(SPD
);
579 ncfgr
|= MACB_BIT(FD
);
580 macb_writel(macb
, NCFGR
, ncfgr
);
585 static int gmac_init_multi_queues(struct macb_device
*macb
)
587 int i
, num_queues
= 1;
590 /* bit 0 is never set but queue 0 always exists */
591 queue_mask
= gem_readl(macb
, DCFG6
) & 0xff;
594 for (i
= 1; i
< MACB_MAX_QUEUES
; i
++)
595 if (queue_mask
& (1 << i
))
598 macb
->dummy_desc
->ctrl
= TXBUF_USED
;
599 macb
->dummy_desc
->addr
= 0;
600 flush_dcache_range(macb
->dummy_desc_dma
, macb
->dummy_desc_dma
+
601 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE
, PKTALIGN
));
603 for (i
= 1; i
< num_queues
; i
++)
604 gem_writel_queue_TBQP(macb
, macb
->dummy_desc_dma
, i
- 1);
610 static int _macb_init(struct udevice
*dev
, const char *name
)
612 static int _macb_init(struct macb_device
*macb
, const char *name
)
616 struct macb_device
*macb
= dev_get_priv(dev
);
622 * macb_halt should have been called at some point before now,
623 * so we'll assume the controller is idle.
626 /* initialize DMA descriptors */
627 paddr
= macb
->rx_buffer_dma
;
628 for (i
= 0; i
< MACB_RX_RING_SIZE
; i
++) {
629 if (i
== (MACB_RX_RING_SIZE
- 1))
630 paddr
|= RXADDR_WRAP
;
631 macb
->rx_ring
[i
].addr
= paddr
;
632 macb
->rx_ring
[i
].ctrl
= 0;
635 macb_flush_ring_desc(macb
, RX
);
636 macb_flush_rx_buffer(macb
);
638 for (i
= 0; i
< MACB_TX_RING_SIZE
; i
++) {
639 macb
->tx_ring
[i
].addr
= 0;
640 if (i
== (MACB_TX_RING_SIZE
- 1))
641 macb
->tx_ring
[i
].ctrl
= TXBUF_USED
| TXBUF_WRAP
;
643 macb
->tx_ring
[i
].ctrl
= TXBUF_USED
;
645 macb_flush_ring_desc(macb
, TX
);
650 macb
->next_rx_tail
= 0;
652 macb_writel(macb
, RBQP
, macb
->rx_ring_dma
);
653 macb_writel(macb
, TBQP
, macb
->tx_ring_dma
);
655 if (macb_is_gem(macb
)) {
656 /* Check the multi queue and initialize the queue for tx */
657 gmac_init_multi_queues(macb
);
660 * When the GMAC IP with GE feature, this bit is used to
661 * select interface between RGMII and GMII.
662 * When the GMAC IP without GE feature, this bit is used
663 * to select interface between RMII and MII.
666 if ((macb
->phy_interface
== PHY_INTERFACE_MODE_RMII
) ||
667 (macb
->phy_interface
== PHY_INTERFACE_MODE_RGMII
))
668 gem_writel(macb
, UR
, GEM_BIT(RGMII
));
670 gem_writel(macb
, UR
, 0);
672 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
673 gem_writel(macb
, UR
, GEM_BIT(RGMII
));
675 gem_writel(macb
, UR
, 0);
679 /* choose RMII or MII mode. This depends on the board */
681 #ifdef CONFIG_AT91FAMILY
682 if (macb
->phy_interface
== PHY_INTERFACE_MODE_RMII
) {
683 macb_writel(macb
, USRIO
,
684 MACB_BIT(RMII
) | MACB_BIT(CLKEN
));
686 macb_writel(macb
, USRIO
, MACB_BIT(CLKEN
));
689 if (macb
->phy_interface
== PHY_INTERFACE_MODE_RMII
)
690 macb_writel(macb
, USRIO
, 0);
692 macb_writel(macb
, USRIO
, MACB_BIT(MII
));
696 #ifdef CONFIG_AT91FAMILY
697 macb_writel(macb
, USRIO
, MACB_BIT(RMII
) | MACB_BIT(CLKEN
));
699 macb_writel(macb
, USRIO
, 0);
702 #ifdef CONFIG_AT91FAMILY
703 macb_writel(macb
, USRIO
, MACB_BIT(CLKEN
));
705 macb_writel(macb
, USRIO
, MACB_BIT(MII
));
707 #endif /* CONFIG_RMII */
712 if (!macb_phy_init(dev
, name
))
714 if (!macb_phy_init(macb
, name
))
718 /* Enable TX and RX */
719 macb_writel(macb
, NCR
, MACB_BIT(TE
) | MACB_BIT(RE
));
724 static void _macb_halt(struct macb_device
*macb
)
728 /* Halt the controller and wait for any ongoing transmission to end. */
729 ncr
= macb_readl(macb
, NCR
);
730 ncr
|= MACB_BIT(THALT
);
731 macb_writel(macb
, NCR
, ncr
);
734 tsr
= macb_readl(macb
, TSR
);
735 } while (tsr
& MACB_BIT(TGO
));
737 /* Disable TX and RX, and clear statistics */
738 macb_writel(macb
, NCR
, MACB_BIT(CLRSTAT
));
741 static int _macb_write_hwaddr(struct macb_device
*macb
, unsigned char *enetaddr
)
746 /* set hardware address */
747 hwaddr_bottom
= enetaddr
[0] | enetaddr
[1] << 8 |
748 enetaddr
[2] << 16 | enetaddr
[3] << 24;
749 macb_writel(macb
, SA1B
, hwaddr_bottom
);
750 hwaddr_top
= enetaddr
[4] | enetaddr
[5] << 8;
751 macb_writel(macb
, SA1T
, hwaddr_top
);
755 static u32
macb_mdc_clk_div(int id
, struct macb_device
*macb
)
758 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
759 unsigned long macb_hz
= macb
->pclk_rate
;
761 unsigned long macb_hz
= get_macb_pclk_rate(id
);
764 if (macb_hz
< 20000000)
765 config
= MACB_BF(CLK
, MACB_CLK_DIV8
);
766 else if (macb_hz
< 40000000)
767 config
= MACB_BF(CLK
, MACB_CLK_DIV16
);
768 else if (macb_hz
< 80000000)
769 config
= MACB_BF(CLK
, MACB_CLK_DIV32
);
771 config
= MACB_BF(CLK
, MACB_CLK_DIV64
);
776 static u32
gem_mdc_clk_div(int id
, struct macb_device
*macb
)
780 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
781 unsigned long macb_hz
= macb
->pclk_rate
;
783 unsigned long macb_hz
= get_macb_pclk_rate(id
);
786 if (macb_hz
< 20000000)
787 config
= GEM_BF(CLK
, GEM_CLK_DIV8
);
788 else if (macb_hz
< 40000000)
789 config
= GEM_BF(CLK
, GEM_CLK_DIV16
);
790 else if (macb_hz
< 80000000)
791 config
= GEM_BF(CLK
, GEM_CLK_DIV32
);
792 else if (macb_hz
< 120000000)
793 config
= GEM_BF(CLK
, GEM_CLK_DIV48
);
794 else if (macb_hz
< 160000000)
795 config
= GEM_BF(CLK
, GEM_CLK_DIV64
);
797 config
= GEM_BF(CLK
, GEM_CLK_DIV96
);
803 * Get the DMA bus width field of the network configuration register that we
804 * should program. We find the width from decoding the design configuration
805 * register to find the maximum supported data bus width.
807 static u32
macb_dbw(struct macb_device
*macb
)
809 switch (GEM_BFEXT(DBWDEF
, gem_readl(macb
, DCFG1
))) {
811 return GEM_BF(DBW
, GEM_DBW128
);
813 return GEM_BF(DBW
, GEM_DBW64
);
816 return GEM_BF(DBW
, GEM_DBW32
);
820 static void _macb_eth_initialize(struct macb_device
*macb
)
822 int id
= 0; /* This is not used by functions we call */
825 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
826 macb
->rx_buffer
= dma_alloc_coherent(MACB_RX_BUFFER_SIZE
,
827 &macb
->rx_buffer_dma
);
828 macb
->rx_ring
= dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE
,
830 macb
->tx_ring
= dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE
,
832 macb
->dummy_desc
= dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE
,
833 &macb
->dummy_desc_dma
);
836 * Do some basic initialization so that we at least can talk
839 if (macb_is_gem(macb
)) {
840 ncfgr
= gem_mdc_clk_div(id
, macb
);
841 ncfgr
|= macb_dbw(macb
);
843 ncfgr
= macb_mdc_clk_div(id
, macb
);
846 macb_writel(macb
, NCFGR
, ncfgr
);
849 #ifndef CONFIG_DM_ETH
850 static int macb_send(struct eth_device
*netdev
, void *packet
, int length
)
852 struct macb_device
*macb
= to_macb(netdev
);
854 return _macb_send(macb
, netdev
->name
, packet
, length
);
857 static int macb_recv(struct eth_device
*netdev
)
859 struct macb_device
*macb
= to_macb(netdev
);
863 macb
->wrapped
= false;
865 macb
->next_rx_tail
= macb
->rx_tail
;
866 length
= _macb_recv(macb
, &packet
);
868 net_process_received_packet(packet
, length
);
869 reclaim_rx_buffers(macb
, macb
->next_rx_tail
);
870 } else if (length
< 0) {
876 static int macb_init(struct eth_device
*netdev
, bd_t
*bd
)
878 struct macb_device
*macb
= to_macb(netdev
);
880 return _macb_init(macb
, netdev
->name
);
883 static void macb_halt(struct eth_device
*netdev
)
885 struct macb_device
*macb
= to_macb(netdev
);
887 return _macb_halt(macb
);
890 static int macb_write_hwaddr(struct eth_device
*netdev
)
892 struct macb_device
*macb
= to_macb(netdev
);
894 return _macb_write_hwaddr(macb
, netdev
->enetaddr
);
897 int macb_eth_initialize(int id
, void *regs
, unsigned int phy_addr
)
899 struct macb_device
*macb
;
900 struct eth_device
*netdev
;
902 macb
= malloc(sizeof(struct macb_device
));
904 printf("Error: Failed to allocate memory for MACB%d\n", id
);
907 memset(macb
, 0, sizeof(struct macb_device
));
909 netdev
= &macb
->netdev
;
912 macb
->phy_addr
= phy_addr
;
914 if (macb_is_gem(macb
))
915 sprintf(netdev
->name
, "gmac%d", id
);
917 sprintf(netdev
->name
, "macb%d", id
);
919 netdev
->init
= macb_init
;
920 netdev
->halt
= macb_halt
;
921 netdev
->send
= macb_send
;
922 netdev
->recv
= macb_recv
;
923 netdev
->write_hwaddr
= macb_write_hwaddr
;
925 _macb_eth_initialize(macb
);
927 eth_register(netdev
);
929 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
931 struct mii_dev
*mdiodev
= mdio_alloc();
934 strncpy(mdiodev
->name
, netdev
->name
, MDIO_NAME_LEN
);
935 mdiodev
->read
= macb_miiphy_read
;
936 mdiodev
->write
= macb_miiphy_write
;
938 retval
= mdio_register(mdiodev
);
941 macb
->bus
= miiphy_get_dev_by_name(netdev
->name
);
945 #endif /* !CONFIG_DM_ETH */
949 static int macb_start(struct udevice
*dev
)
951 return _macb_init(dev
, dev
->name
);
954 static int macb_send(struct udevice
*dev
, void *packet
, int length
)
956 struct macb_device
*macb
= dev_get_priv(dev
);
958 return _macb_send(macb
, dev
->name
, packet
, length
);
961 static int macb_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
963 struct macb_device
*macb
= dev_get_priv(dev
);
965 macb
->next_rx_tail
= macb
->rx_tail
;
966 macb
->wrapped
= false;
968 return _macb_recv(macb
, packetp
);
971 static int macb_free_pkt(struct udevice
*dev
, uchar
*packet
, int length
)
973 struct macb_device
*macb
= dev_get_priv(dev
);
975 reclaim_rx_buffers(macb
, macb
->next_rx_tail
);
980 static void macb_stop(struct udevice
*dev
)
982 struct macb_device
*macb
= dev_get_priv(dev
);
987 static int macb_write_hwaddr(struct udevice
*dev
)
989 struct eth_pdata
*plat
= dev_get_platdata(dev
);
990 struct macb_device
*macb
= dev_get_priv(dev
);
992 return _macb_write_hwaddr(macb
, plat
->enetaddr
);
995 static const struct eth_ops macb_eth_ops
= {
1000 .free_pkt
= macb_free_pkt
,
1001 .write_hwaddr
= macb_write_hwaddr
,
1005 static int macb_enable_clk(struct udevice
*dev
)
1007 struct macb_device
*macb
= dev_get_priv(dev
);
1012 ret
= clk_get_by_index(dev
, 0, &clk
);
1016 ret
= clk_enable(&clk
);
1020 clk_rate
= clk_get_rate(&clk
);
1024 macb
->pclk_rate
= clk_rate
;
1030 static int macb_eth_probe(struct udevice
*dev
)
1032 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
1033 struct macb_device
*macb
= dev_get_priv(dev
);
1034 const char *phy_mode
;
1035 __maybe_unused
int ret
;
1037 phy_mode
= fdt_getprop(gd
->fdt_blob
, dev_of_offset(dev
), "phy-mode",
1040 macb
->phy_interface
= phy_get_interface_by_name(phy_mode
);
1041 if (macb
->phy_interface
== -1) {
1042 debug("%s: Invalid PHY interface '%s'\n", __func__
, phy_mode
);
1046 macb
->regs
= (void *)pdata
->iobase
;
1049 ret
= macb_enable_clk(dev
);
1054 _macb_eth_initialize(macb
);
1056 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1057 macb
->bus
= mdio_alloc();
1060 strncpy(macb
->bus
->name
, dev
->name
, MDIO_NAME_LEN
);
1061 macb
->bus
->read
= macb_miiphy_read
;
1062 macb
->bus
->write
= macb_miiphy_write
;
1064 ret
= mdio_register(macb
->bus
);
1067 macb
->bus
= miiphy_get_dev_by_name(dev
->name
);
1073 static int macb_eth_remove(struct udevice
*dev
)
1075 struct macb_device
*macb
= dev_get_priv(dev
);
1077 #ifdef CONFIG_PHYLIB
1080 mdio_unregister(macb
->bus
);
1081 mdio_free(macb
->bus
);
1086 static int macb_eth_ofdata_to_platdata(struct udevice
*dev
)
1088 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
1090 pdata
->iobase
= devfdt_get_addr(dev
);
1094 static const struct udevice_id macb_eth_ids
[] = {
1095 { .compatible
= "cdns,macb" },
1096 { .compatible
= "cdns,at91sam9260-macb" },
1097 { .compatible
= "atmel,sama5d2-gem" },
1098 { .compatible
= "atmel,sama5d3-gem" },
1099 { .compatible
= "atmel,sama5d4-gem" },
1103 U_BOOT_DRIVER(eth_macb
) = {
1106 .of_match
= macb_eth_ids
,
1107 .ofdata_to_platdata
= macb_eth_ofdata_to_platdata
,
1108 .probe
= macb_eth_probe
,
1109 .remove
= macb_eth_remove
,
1110 .ops
= &macb_eth_ops
,
1111 .priv_auto_alloc_size
= sizeof(struct macb_device
),
1112 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),