]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/net/mcffec.c
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/immap.h>
41 /* Ethernet Transmit and Receive Buffers */
42 #define DBUF_LENGTH 1520
44 #define PKT_MAXBUF_SIZE 1518
45 #define PKT_MINBUF_SIZE 64
46 #define PKT_MAXBLR_SIZE 1520
47 #define LAST_PKTBUFSRX PKTBUFSRX - 1
48 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
49 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
51 DECLARE_GLOBAL_DATA_PTR
;
53 struct fec_info_s fec_info
[] = {
54 #ifdef CFG_FEC0_IOBASE
57 CFG_FEC0_IOBASE
, /* io base */
58 CFG_FEC0_PINMUX
, /* gpio pin muxing */
59 CFG_FEC0_MIIBASE
, /* mii base */
61 0, /* duplex and speed */
69 0, /* initialized flag */
70 (struct fec_info_s
*)-1,
73 #ifdef CFG_FEC1_IOBASE
76 CFG_FEC1_IOBASE
, /* io base */
77 CFG_FEC1_PINMUX
, /* gpio pin muxing */
78 CFG_FEC1_MIIBASE
, /* mii base */
80 0, /* duplex and speed */
82 0, /* phy name init */
83 #ifdef CFG_FEC_BUF_USE_SRAM
84 (cbd_t
*)DBUF_LENGTH
, /* RX BD */
92 0, /* initialized flag */
93 (struct fec_info_s
*)-1,
98 int fec_send(struct eth_device
*dev
, volatile void *packet
, int length
);
99 int fec_recv(struct eth_device
*dev
);
100 int fec_init(struct eth_device
*dev
, bd_t
* bd
);
101 void fec_halt(struct eth_device
*dev
);
102 void fec_reset(struct eth_device
*dev
);
104 extern int fecpin_setclear(struct eth_device
*dev
, int setclear
);
106 #ifdef CFG_DISCOVER_PHY
107 extern void __mii_init(void);
108 extern uint
mii_send(uint mii_cmd
);
109 extern int mii_discover_phy(struct eth_device
*dev
);
110 extern int mcffec_miiphy_read(char *devname
, unsigned char addr
,
111 unsigned char reg
, unsigned short *value
);
112 extern int mcffec_miiphy_write(char *devname
, unsigned char addr
,
113 unsigned char reg
, unsigned short value
);
116 void setFecDuplexSpeed(volatile fec_t
* fecp
, bd_t
* bd
, int dup_spd
)
118 if ((dup_spd
>> 16) == FULL
) {
119 /* Set maximum frame length */
120 fecp
->rcr
= FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE
) | FEC_RCR_MII_MODE
|
121 FEC_RCR_PROM
| 0x100;
122 fecp
->tcr
= FEC_TCR_FDEN
;
124 /* Half duplex mode */
125 fecp
->rcr
= FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE
) |
126 FEC_RCR_MII_MODE
| FEC_RCR_DRT
;
127 fecp
->tcr
&= ~FEC_TCR_FDEN
;
130 if ((dup_spd
& 0xFFFF) == _100BASET
) {
131 #ifdef CONFIG_MCF5445x
132 fecp
->rcr
&= ~0x200; /* disabled 10T base */
137 bd
->bi_ethspeed
= 100;
139 #ifdef CONFIG_MCF5445x
140 fecp
->rcr
|= 0x200; /* enabled 10T base */
145 bd
->bi_ethspeed
= 10;
149 int fec_send(struct eth_device
*dev
, volatile void *packet
, int length
)
151 struct fec_info_s
*info
= dev
->priv
;
152 volatile fec_t
*fecp
= (fec_t
*) (info
->iobase
);
156 miiphy_read(dev
->name
, info
->phy_addr
, PHY_BMSR
, &phyStatus
);
162 while ((info
->txbd
[info
->txIdx
].cbd_sc
& BD_ENET_TX_READY
) &&
163 (j
< MCFFEC_TOUT_LOOP
)) {
167 if (j
>= MCFFEC_TOUT_LOOP
) {
168 printf("TX not ready\n");
171 info
->txbd
[info
->txIdx
].cbd_bufaddr
= (uint
) packet
;
172 info
->txbd
[info
->txIdx
].cbd_datlen
= length
;
173 info
->txbd
[info
->txIdx
].cbd_sc
|= BD_ENET_TX_RDY_LST
;
175 /* Activate transmit Buffer Descriptor polling */
176 fecp
->tdar
= 0x01000000; /* Descriptor polling active */
178 #ifndef CFG_FEC_BUF_USE_SRAM
180 * FEC unable to initial transmit data packet.
181 * A nop will ensure the descriptor polling active completed.
182 * CF Internal RAM has shorter cycle access than DRAM. If use
183 * DRAM as Buffer descriptor and data, a nop is a must.
184 * Affect only V2 and V3.
190 #ifdef CFG_UNIFY_CACHE
195 while ((info
->txbd
[info
->txIdx
].cbd_sc
& BD_ENET_TX_READY
) &&
196 (j
< MCFFEC_TOUT_LOOP
)) {
200 if (j
>= MCFFEC_TOUT_LOOP
) {
201 printf("TX timeout\n");
205 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
206 __FILE__
, __LINE__
, __FUNCTION__
, j
,
207 info
->txbd
[info
->txIdx
].cbd_sc
,
208 (info
->txbd
[info
->txIdx
].cbd_sc
& 0x003C) >> 2);
211 /* return only status bits */
212 rc
= (info
->txbd
[info
->txIdx
].cbd_sc
& BD_ENET_TX_STATS
);
213 info
->txIdx
= (info
->txIdx
+ 1) % TX_BUF_CNT
;
218 int fec_recv(struct eth_device
*dev
)
220 struct fec_info_s
*info
= dev
->priv
;
221 volatile fec_t
*fecp
= (fec_t
*) (info
->iobase
);
225 #ifndef CFG_FEC_BUF_USE_SRAM
227 #ifdef CFG_UNIFY_CACHE
230 /* section 16.9.23.2 */
231 if (info
->rxbd
[info
->rxIdx
].cbd_sc
& BD_ENET_RX_EMPTY
) {
233 break; /* nothing received - leave for() loop */
236 length
= info
->rxbd
[info
->rxIdx
].cbd_datlen
;
238 if (info
->rxbd
[info
->rxIdx
].cbd_sc
& 0x003f) {
239 printf("%s[%d] err: %x\n",
240 __FUNCTION__
, __LINE__
,
241 info
->rxbd
[info
->rxIdx
].cbd_sc
);
243 printf("%s[%d] err: %x\n",
244 __FUNCTION__
, __LINE__
,
245 info
->rxbd
[info
->rxIdx
].cbd_sc
);
250 /* Pass the packet up to the protocol layers. */
251 NetReceive(NetRxPackets
[info
->rxIdx
], length
);
253 fecp
->eir
|= FEC_EIR_RXF
;
256 /* Give the buffer back to the FEC. */
257 info
->rxbd
[info
->rxIdx
].cbd_datlen
= 0;
259 /* wrap around buffer index when necessary */
260 if (info
->rxIdx
== LAST_PKTBUFSRX
) {
261 info
->rxbd
[PKTBUFSRX
- 1].cbd_sc
= BD_ENET_RX_W_E
;
264 info
->rxbd
[info
->rxIdx
].cbd_sc
= BD_ENET_RX_EMPTY
;
268 /* Try to fill Buffer Descriptors */
269 fecp
->rdar
= 0x01000000; /* Descriptor polling active */
276 void dbgFecRegs(struct eth_device
*dev
)
278 struct fec_info_s
*info
= dev
->priv
;
279 volatile fec_t
*fecp
= (fec_t
*) (info
->iobase
);
282 printf("ievent %x - %x\n", (int)&fecp
->eir
, fecp
->eir
);
283 printf("imask %x - %x\n", (int)&fecp
->eimr
, fecp
->eimr
);
284 printf("r_des_active %x - %x\n", (int)&fecp
->rdar
, fecp
->rdar
);
285 printf("x_des_active %x - %x\n", (int)&fecp
->tdar
, fecp
->tdar
);
286 printf("ecntrl %x - %x\n", (int)&fecp
->ecr
, fecp
->ecr
);
287 printf("mii_mframe %x - %x\n", (int)&fecp
->mmfr
, fecp
->mmfr
);
288 printf("mii_speed %x - %x\n", (int)&fecp
->mscr
, fecp
->mscr
);
289 printf("mii_ctrlstat %x - %x\n", (int)&fecp
->mibc
, fecp
->mibc
);
290 printf("r_cntrl %x - %x\n", (int)&fecp
->rcr
, fecp
->rcr
);
291 printf("x_cntrl %x - %x\n", (int)&fecp
->tcr
, fecp
->tcr
);
292 printf("padr_l %x - %x\n", (int)&fecp
->palr
, fecp
->palr
);
293 printf("padr_u %x - %x\n", (int)&fecp
->paur
, fecp
->paur
);
294 printf("op_pause %x - %x\n", (int)&fecp
->opd
, fecp
->opd
);
295 printf("iadr_u %x - %x\n", (int)&fecp
->iaur
, fecp
->iaur
);
296 printf("iadr_l %x - %x\n", (int)&fecp
->ialr
, fecp
->ialr
);
297 printf("gadr_u %x - %x\n", (int)&fecp
->gaur
, fecp
->gaur
);
298 printf("gadr_l %x - %x\n", (int)&fecp
->galr
, fecp
->galr
);
299 printf("x_wmrk %x - %x\n", (int)&fecp
->tfwr
, fecp
->tfwr
);
300 printf("r_bound %x - %x\n", (int)&fecp
->frbr
, fecp
->frbr
);
301 printf("r_fstart %x - %x\n", (int)&fecp
->frsr
, fecp
->frsr
);
302 printf("r_drng %x - %x\n", (int)&fecp
->erdsr
, fecp
->erdsr
);
303 printf("x_drng %x - %x\n", (int)&fecp
->etdsr
, fecp
->etdsr
);
304 printf("r_bufsz %x - %x\n", (int)&fecp
->emrbr
, fecp
->emrbr
);
307 printf("rmon_t_drop %x - %x\n", (int)&fecp
->rmon_t_drop
,
309 printf("rmon_t_packets %x - %x\n", (int)&fecp
->rmon_t_packets
,
310 fecp
->rmon_t_packets
);
311 printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp
->rmon_t_bc_pkt
,
312 fecp
->rmon_t_bc_pkt
);
313 printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp
->rmon_t_mc_pkt
,
314 fecp
->rmon_t_mc_pkt
);
315 printf("rmon_t_crc_align %x - %x\n", (int)&fecp
->rmon_t_crc_align
,
316 fecp
->rmon_t_crc_align
);
317 printf("rmon_t_undersize %x - %x\n", (int)&fecp
->rmon_t_undersize
,
318 fecp
->rmon_t_undersize
);
319 printf("rmon_t_oversize %x - %x\n", (int)&fecp
->rmon_t_oversize
,
320 fecp
->rmon_t_oversize
);
321 printf("rmon_t_frag %x - %x\n", (int)&fecp
->rmon_t_frag
,
323 printf("rmon_t_jab %x - %x\n", (int)&fecp
->rmon_t_jab
,
325 printf("rmon_t_col %x - %x\n", (int)&fecp
->rmon_t_col
,
327 printf("rmon_t_p64 %x - %x\n", (int)&fecp
->rmon_t_p64
,
329 printf("rmon_t_p65to127 %x - %x\n", (int)&fecp
->rmon_t_p65to127
,
330 fecp
->rmon_t_p65to127
);
331 printf("rmon_t_p128to255 %x - %x\n", (int)&fecp
->rmon_t_p128to255
,
332 fecp
->rmon_t_p128to255
);
333 printf("rmon_t_p256to511 %x - %x\n", (int)&fecp
->rmon_t_p256to511
,
334 fecp
->rmon_t_p256to511
);
335 printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp
->rmon_t_p512to1023
,
336 fecp
->rmon_t_p512to1023
);
337 printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp
->rmon_t_p1024to2047
,
338 fecp
->rmon_t_p1024to2047
);
339 printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp
->rmon_t_p_gte2048
,
340 fecp
->rmon_t_p_gte2048
);
341 printf("rmon_t_octets %x - %x\n", (int)&fecp
->rmon_t_octets
,
342 fecp
->rmon_t_octets
);
345 printf("ieee_t_drop %x - %x\n", (int)&fecp
->ieee_t_drop
,
347 printf("ieee_t_frame_ok %x - %x\n", (int)&fecp
->ieee_t_frame_ok
,
348 fecp
->ieee_t_frame_ok
);
349 printf("ieee_t_1col %x - %x\n", (int)&fecp
->ieee_t_1col
,
351 printf("ieee_t_mcol %x - %x\n", (int)&fecp
->ieee_t_mcol
,
353 printf("ieee_t_def %x - %x\n", (int)&fecp
->ieee_t_def
,
355 printf("ieee_t_lcol %x - %x\n", (int)&fecp
->ieee_t_lcol
,
357 printf("ieee_t_excol %x - %x\n", (int)&fecp
->ieee_t_excol
,
359 printf("ieee_t_macerr %x - %x\n", (int)&fecp
->ieee_t_macerr
,
360 fecp
->ieee_t_macerr
);
361 printf("ieee_t_cserr %x - %x\n", (int)&fecp
->ieee_t_cserr
,
363 printf("ieee_t_sqe %x - %x\n", (int)&fecp
->ieee_t_sqe
,
365 printf("ieee_t_fdxfc %x - %x\n", (int)&fecp
->ieee_t_fdxfc
,
367 printf("ieee_t_octets_ok %x - %x\n", (int)&fecp
->ieee_t_octets_ok
,
368 fecp
->ieee_t_octets_ok
);
371 printf("rmon_r_drop %x - %x\n", (int)&fecp
->rmon_r_drop
,
373 printf("rmon_r_packets %x - %x\n", (int)&fecp
->rmon_r_packets
,
374 fecp
->rmon_r_packets
);
375 printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp
->rmon_r_bc_pkt
,
376 fecp
->rmon_r_bc_pkt
);
377 printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp
->rmon_r_mc_pkt
,
378 fecp
->rmon_r_mc_pkt
);
379 printf("rmon_r_crc_align %x - %x\n", (int)&fecp
->rmon_r_crc_align
,
380 fecp
->rmon_r_crc_align
);
381 printf("rmon_r_undersize %x - %x\n", (int)&fecp
->rmon_r_undersize
,
382 fecp
->rmon_r_undersize
);
383 printf("rmon_r_oversize %x - %x\n", (int)&fecp
->rmon_r_oversize
,
384 fecp
->rmon_r_oversize
);
385 printf("rmon_r_frag %x - %x\n", (int)&fecp
->rmon_r_frag
,
387 printf("rmon_r_jab %x - %x\n", (int)&fecp
->rmon_r_jab
,
389 printf("rmon_r_p64 %x - %x\n", (int)&fecp
->rmon_r_p64
,
391 printf("rmon_r_p65to127 %x - %x\n", (int)&fecp
->rmon_r_p65to127
,
392 fecp
->rmon_r_p65to127
);
393 printf("rmon_r_p128to255 %x - %x\n", (int)&fecp
->rmon_r_p128to255
,
394 fecp
->rmon_r_p128to255
);
395 printf("rmon_r_p256to511 %x - %x\n", (int)&fecp
->rmon_r_p256to511
,
396 fecp
->rmon_r_p256to511
);
397 printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp
->rmon_r_p512to1023
,
398 fecp
->rmon_r_p512to1023
);
399 printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp
->rmon_r_p1024to2047
,
400 fecp
->rmon_r_p1024to2047
);
401 printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp
->rmon_r_p_gte2048
,
402 fecp
->rmon_r_p_gte2048
);
403 printf("rmon_r_octets %x - %x\n", (int)&fecp
->rmon_r_octets
,
404 fecp
->rmon_r_octets
);
407 printf("ieee_r_drop %x - %x\n", (int)&fecp
->ieee_r_drop
,
409 printf("ieee_r_frame_ok %x - %x\n", (int)&fecp
->ieee_r_frame_ok
,
410 fecp
->ieee_r_frame_ok
);
411 printf("ieee_r_crc %x - %x\n", (int)&fecp
->ieee_r_crc
,
413 printf("ieee_r_align %x - %x\n", (int)&fecp
->ieee_r_align
,
415 printf("ieee_r_macerr %x - %x\n", (int)&fecp
->ieee_r_macerr
,
416 fecp
->ieee_r_macerr
);
417 printf("ieee_r_fdxfc %x - %x\n", (int)&fecp
->ieee_r_fdxfc
,
419 printf("ieee_r_octets_ok %x - %x\n", (int)&fecp
->ieee_r_octets_ok
,
420 fecp
->ieee_r_octets_ok
);
426 int fec_init(struct eth_device
*dev
, bd_t
* bd
)
428 struct fec_info_s
*info
= dev
->priv
;
429 volatile fec_t
*fecp
= (fec_t
*) (info
->iobase
);
433 fecpin_setclear(dev
, 1);
437 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
438 defined (CFG_DISCOVER_PHY)
442 setFecDuplexSpeed(fecp
, bd
, info
->dup_spd
);
444 #ifndef CFG_DISCOVER_PHY
445 setFecDuplexSpeed(fecp
, bd
, (FECDUPLEX
<< 16) | FECSPEED
);
446 #endif /* ifndef CFG_DISCOVER_PHY */
447 #endif /* CONFIG_CMD_MII || CONFIG_MII */
449 /* We use strictly polling mode only */
452 /* Clear any pending interrupt */
453 fecp
->eir
= 0xffffffff;
455 /* Set station address */
456 if ((u32
) fecp
== CFG_FEC0_IOBASE
) {
457 #ifdef CFG_FEC1_IOBASE
458 volatile fec_t
*fecp1
= (fec_t
*) (CFG_FEC1_IOBASE
);
459 ea
= &bd
->bi_enet1addr
[0];
461 (ea
[0] << 24) | (ea
[1] << 16) | (ea
[2] << 8) | (ea
[3]);
462 fecp1
->paur
= (ea
[4] << 24) | (ea
[5] << 16);
464 ea
= &bd
->bi_enetaddr
[0];
466 (ea
[0] << 24) | (ea
[1] << 16) | (ea
[2] << 8) | (ea
[3]);
467 fecp
->paur
= (ea
[4] << 24) | (ea
[5] << 16);
469 #ifdef CFG_FEC0_IOBASE
470 volatile fec_t
*fecp0
= (fec_t
*) (CFG_FEC0_IOBASE
);
471 ea
= &bd
->bi_enetaddr
[0];
473 (ea
[0] << 24) | (ea
[1] << 16) | (ea
[2] << 8) | (ea
[3]);
474 fecp0
->paur
= (ea
[4] << 24) | (ea
[5] << 16);
476 #ifdef CFG_FEC1_IOBASE
477 ea
= &bd
->bi_enet1addr
[0];
479 (ea
[0] << 24) | (ea
[1] << 16) | (ea
[2] << 8) | (ea
[3]);
480 fecp
->paur
= (ea
[4] << 24) | (ea
[5] << 16);
484 /* Clear unicast address hash table */
488 /* Clear multicast address hash table */
492 /* Set maximum receive buffer size. */
493 fecp
->emrbr
= PKT_MAXBLR_SIZE
;
496 * Setup Buffers and Buffer Desriptors
502 * Setup Receiver Buffer Descriptors (13.14.24.18)
506 for (i
= 0; i
< PKTBUFSRX
; i
++) {
507 info
->rxbd
[i
].cbd_sc
= BD_ENET_RX_EMPTY
;
508 info
->rxbd
[i
].cbd_datlen
= 0; /* Reset */
509 info
->rxbd
[i
].cbd_bufaddr
= (uint
) NetRxPackets
[i
];
511 info
->rxbd
[PKTBUFSRX
- 1].cbd_sc
|= BD_ENET_RX_WRAP
;
514 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
518 for (i
= 0; i
< TX_BUF_CNT
; i
++) {
519 info
->txbd
[i
].cbd_sc
= BD_ENET_TX_LAST
| BD_ENET_TX_TC
;
520 info
->txbd
[i
].cbd_datlen
= 0; /* Reset */
521 info
->txbd
[i
].cbd_bufaddr
= (uint
) (&info
->txbuf
[0]);
523 info
->txbd
[TX_BUF_CNT
- 1].cbd_sc
|= BD_ENET_TX_WRAP
;
525 /* Set receive and transmit descriptor base */
526 fecp
->erdsr
= (unsigned int)(&info
->rxbd
[0]);
527 fecp
->etdsr
= (unsigned int)(&info
->txbd
[0]);
529 /* Now enable the transmit and receive processing */
530 fecp
->ecr
|= FEC_ECR_ETHER_EN
;
532 /* And last, try to fill Rx Buffer Descriptors */
533 fecp
->rdar
= 0x01000000; /* Descriptor polling active */
538 void fec_reset(struct eth_device
*dev
)
540 struct fec_info_s
*info
= dev
->priv
;
541 volatile fec_t
*fecp
= (fec_t
*) (info
->iobase
);
544 fecp
->ecr
= FEC_ECR_RESET
;
545 for (i
= 0; (fecp
->ecr
& FEC_ECR_RESET
) && (i
< FEC_RESET_DELAY
); ++i
) {
548 if (i
== FEC_RESET_DELAY
) {
549 printf("FEC_RESET_DELAY timeout\n");
553 void fec_halt(struct eth_device
*dev
)
555 struct fec_info_s
*info
= dev
->priv
;
559 fecpin_setclear(dev
, 0);
561 info
->rxIdx
= info
->txIdx
= 0;
562 memset(info
->rxbd
, 0, PKTBUFSRX
* sizeof(cbd_t
));
563 memset(info
->txbd
, 0, TX_BUF_CNT
* sizeof(cbd_t
));
564 memset(info
->txbuf
, 0, DBUF_LENGTH
);
567 int mcffec_initialize(bd_t
* bis
)
569 struct eth_device
*dev
;
571 #ifdef CFG_FEC_BUF_USE_SRAM
572 u32 tmp
= CFG_INIT_RAM_ADDR
+ 0x1000;
575 for (i
= 0; i
< sizeof(fec_info
) / sizeof(fec_info
[0]); i
++) {
578 (struct eth_device
*)memalign(CFG_CACHELINE_SIZE
,
583 memset(dev
, 0, sizeof(*dev
));
585 sprintf(dev
->name
, "FEC%d", fec_info
[i
].index
);
587 dev
->priv
= &fec_info
[i
];
588 dev
->init
= fec_init
;
589 dev
->halt
= fec_halt
;
590 dev
->send
= fec_send
;
591 dev
->recv
= fec_recv
;
593 /* setup Receive and Transmit buffer descriptor */
594 #ifdef CFG_FEC_BUF_USE_SRAM
595 fec_info
[i
].rxbd
= (cbd_t
*)((u32
)fec_info
[i
].rxbd
+ tmp
);
596 tmp
= (u32
)fec_info
[i
].rxbd
;
598 (cbd_t
*)((u32
)fec_info
[i
].txbd
+ tmp
+
599 (PKTBUFSRX
* sizeof(cbd_t
)));
600 tmp
= (u32
)fec_info
[i
].txbd
;
602 (char *)((u32
)fec_info
[i
].txbuf
+ tmp
+
603 (CFG_TX_ETH_BUFFER
* sizeof(cbd_t
)));
604 tmp
= (u32
)fec_info
[i
].txbuf
;
607 (cbd_t
*) memalign(CFG_CACHELINE_SIZE
,
608 (PKTBUFSRX
* sizeof(cbd_t
)));
610 (cbd_t
*) memalign(CFG_CACHELINE_SIZE
,
611 (TX_BUF_CNT
* sizeof(cbd_t
)));
613 (char *)memalign(CFG_CACHELINE_SIZE
, DBUF_LENGTH
);
617 printf("rxbd %x txbd %x\n",
618 (int)fec_info
[i
].rxbd
, (int)fec_info
[i
].txbd
);
621 fec_info
[i
].phy_name
= (char *)memalign(CFG_CACHELINE_SIZE
, 32);
625 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
626 miiphy_register(dev
->name
,
627 mcffec_miiphy_read
, mcffec_miiphy_write
);
630 fec_info
[i
- 1].next
= &fec_info
[i
];
632 fec_info
[i
- 1].next
= &fec_info
[0];
635 bis
->bi_ethspeed
= 10;