drivers/net/mpc512x_fec.h

   1 /*
   2  * (C) Copyright 2003 - 2009
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Derived from the MPC8xx driver's header file.
   6  */
   7
   8 #ifndef __MPC512X_FEC_H
   9 #define __MPC512X_FEC_H
  10
  11 #include <common.h>
  12
  13 /* Receive & Transmit Buffer Descriptor definitions */
  14 typedef struct BufferDescriptor {
  15         u16 status;
  16         u16 dataLength;
  17         u32 dataPointer;
  18 } FEC_RBD;
  19
  20 typedef struct {
  21         u16 status;
  22         u16 dataLength;
  23         u32 dataPointer;
  24 } FEC_TBD;
  25
  26 /* private structure */
  27 typedef enum {
  28         SEVENWIRE,                      /* 7-wire       */
  29         MII10,                          /* MII 10Mbps   */
  30         MII100                          /* MII 100Mbps  */
  31 } xceiver_type;
  32
  33 /* BD Numer definitions */
  34 #define FEC_TBD_NUM             48      /* The user can adjust this value */
  35 #define FEC_RBD_NUM             32      /* The user can adjust this value */
  36
  37 /* packet size limit */
  38 #define FEC_MAX_FRAME_LEN       1522    /* recommended default value */
  39
  40 /* Buffer size must be evenly divisible by 16 */
  41 #define FEC_BUFFER_SIZE         ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
  42
  43 typedef struct {
  44         u8 frame[FEC_BUFFER_SIZE];
  45 } mpc512x_frame;
  46
  47 typedef struct {
  48         FEC_RBD rbd[FEC_RBD_NUM];                       /* RBD ring */
  49         FEC_TBD tbd[FEC_TBD_NUM];                       /* TBD ring */
  50         mpc512x_frame recv_frames[FEC_RBD_NUM];         /* receive buff */
  51 } mpc512x_buff_descs;
  52
  53 typedef struct {
  54         volatile fec512x_t *eth;
  55         xceiver_type xcv_type;          /* transceiver type */
  56         mpc512x_buff_descs *bdBase;     /* BD rings and recv buffer */
  57         u16 rbdIndex;                   /* next receive BD to read */
  58         u16 tbdIndex;                   /* next transmit BD to send */
  59         u16 usedTbdIndex;               /* next transmit BD to clean */
  60         u16 cleanTbdNum;                /* the number of available transmit BDs */
  61 } mpc512x_fec_priv;
  62
  63 /* RBD bits definitions */
  64 #define FEC_RBD_EMPTY           0x8000  /* Buffer is empty */
  65 #define FEC_RBD_WRAP            0x2000  /* Last BD in ring */
  66 #define FEC_RBD_LAST            0x0800  /* Buffer is last in frame(useless) */
  67 #define FEC_RBD_MISS            0x0100  /* Miss bit for prom mode */
  68 #define FEC_RBD_BC              0x0080  /* The received frame is broadcast frame */
  69 #define FEC_RBD_MC              0x0040  /* The received frame is multicast frame */
  70 #define FEC_RBD_LG              0x0020  /* Frame length violation */
  71 #define FEC_RBD_NO              0x0010  /* Nonoctet align frame */
  72 #define FEC_RBD_SH              0x0008  /* Short frame */
  73 #define FEC_RBD_CR              0x0004  /* CRC error */
  74 #define FEC_RBD_OV              0x0002  /* Receive FIFO overrun */
  75 #define FEC_RBD_TR              0x0001  /* Frame is truncated */
  76 #define FEC_RBD_ERR             (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
  77                                 FEC_RBD_OV | FEC_RBD_TR)
  78
  79 /* TBD bits definitions */
  80 #define FEC_TBD_READY           0x8000  /* Buffer is ready */
  81 #define FEC_TBD_WRAP            0x2000  /* Last BD in ring */
  82 #define FEC_TBD_LAST            0x0800  /* Buffer is last in frame */
  83 #define FEC_TBD_TC              0x0400  /* Transmit the CRC */
  84 #define FEC_TBD_ABC             0x0200  /* Append bad CRC */
  85
  86 /* MII-related definitios */
  87 #define FEC_MII_DATA_ST         0x40000000      /* Start of frame delimiter */
  88 #define FEC_MII_DATA_OP_RD      0x20000000      /* Perform a read operation */
  89 #define FEC_MII_DATA_OP_WR      0x10000000      /* Perform a write operation */
  90 #define FEC_MII_DATA_PA_MSK     0x0f800000      /* PHY Address field mask */
  91 #define FEC_MII_DATA_RA_MSK     0x007c0000      /* PHY Register field mask */
  92 #define FEC_MII_DATA_TA         0x00020000      /* Turnaround */
  93 #define FEC_MII_DATA_DATAMSK    0x0000ffff      /* PHY data field */
  94
  95 #define FEC_MII_DATA_RA_SHIFT   18      /* MII Register address bits */
  96 #define FEC_MII_DATA_PA_SHIFT   23      /* MII PHY address bits */
  97
  98 #endif  /* __MPC512X_FEC_H */